1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R-Car PWM Timer driver 4 * 5 * Copyright (C) 2015 Renesas Electronics Corporation 6 * 7 * Limitations: 8 * - The hardware cannot generate a 0% duty cycle. 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/log2.h> 16 #include <linux/math64.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/pwm.h> 22 #include <linux/slab.h> 23 24 #define RCAR_PWM_MAX_DIVISION 24 25 #define RCAR_PWM_MAX_CYCLE 1023 26 27 #define RCAR_PWMCR 0x00 28 #define RCAR_PWMCR_CC0_MASK 0x000f0000 29 #define RCAR_PWMCR_CC0_SHIFT 16 30 #define RCAR_PWMCR_CCMD BIT(15) 31 #define RCAR_PWMCR_SYNC BIT(11) 32 #define RCAR_PWMCR_SS0 BIT(4) 33 #define RCAR_PWMCR_EN0 BIT(0) 34 35 #define RCAR_PWMCNT 0x04 36 #define RCAR_PWMCNT_CYC0_MASK 0x03ff0000 37 #define RCAR_PWMCNT_CYC0_SHIFT 16 38 #define RCAR_PWMCNT_PH0_MASK 0x000003ff 39 #define RCAR_PWMCNT_PH0_SHIFT 0 40 41 struct rcar_pwm_chip { 42 void __iomem *base; 43 struct clk *clk; 44 }; 45 46 static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip) 47 { 48 return pwmchip_get_drvdata(chip); 49 } 50 51 static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data, 52 unsigned int offset) 53 { 54 writel(data, rp->base + offset); 55 } 56 57 static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset) 58 { 59 return readl(rp->base + offset); 60 } 61 62 static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data, 63 unsigned int offset) 64 { 65 u32 value; 66 67 value = rcar_pwm_read(rp, offset); 68 value &= ~mask; 69 value |= data & mask; 70 rcar_pwm_write(rp, value, offset); 71 } 72 73 static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns) 74 { 75 unsigned long clk_rate = clk_get_rate(rp->clk); 76 u64 div, tmp; 77 78 if (clk_rate == 0) 79 return -EINVAL; 80 81 div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE; 82 tmp = (u64)period_ns * clk_rate + div - 1; 83 tmp = div64_u64(tmp, div); 84 div = ilog2(tmp - 1) + 1; 85 86 return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE; 87 } 88 89 static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp, 90 unsigned int div) 91 { 92 u32 value; 93 94 value = rcar_pwm_read(rp, RCAR_PWMCR); 95 value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK); 96 97 if (div & 1) 98 value |= RCAR_PWMCR_CCMD; 99 100 div >>= 1; 101 102 value |= div << RCAR_PWMCR_CC0_SHIFT; 103 rcar_pwm_write(rp, value, RCAR_PWMCR); 104 } 105 106 static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, u64 duty_ns, 107 u64 period_ns) 108 { 109 unsigned long long tmp; 110 unsigned long clk_rate = clk_get_rate(rp->clk); 111 u32 cyc, ph; 112 113 /* div <= 24 == RCAR_PWM_MAX_DIVISION, so the shift doesn't overflow. */ 114 tmp = mul_u64_u64_div_u64(period_ns, clk_rate, (u64)NSEC_PER_SEC << div); 115 if (tmp > FIELD_MAX(RCAR_PWMCNT_CYC0_MASK)) 116 tmp = FIELD_MAX(RCAR_PWMCNT_CYC0_MASK); 117 118 cyc = FIELD_PREP(RCAR_PWMCNT_CYC0_MASK, tmp); 119 120 tmp = mul_u64_u64_div_u64(duty_ns, clk_rate, (u64)NSEC_PER_SEC << div); 121 if (tmp > FIELD_MAX(RCAR_PWMCNT_PH0_MASK)) 122 tmp = FIELD_MAX(RCAR_PWMCNT_PH0_MASK); 123 ph = FIELD_PREP(RCAR_PWMCNT_PH0_MASK, tmp); 124 125 /* Avoid prohibited setting */ 126 if (cyc == 0 || ph == 0) 127 return -EINVAL; 128 129 rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT); 130 131 return 0; 132 } 133 134 static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 135 { 136 return pm_runtime_get_sync(pwmchip_parent(chip)); 137 } 138 139 static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 140 { 141 pm_runtime_put(pwmchip_parent(chip)); 142 } 143 144 static int rcar_pwm_enable(struct rcar_pwm_chip *rp) 145 { 146 u32 value; 147 148 /* Don't enable the PWM device if CYC0 or PH0 is 0 */ 149 value = rcar_pwm_read(rp, RCAR_PWMCNT); 150 if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 || 151 (value & RCAR_PWMCNT_PH0_MASK) == 0) 152 return -EINVAL; 153 154 rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR); 155 156 return 0; 157 } 158 159 static void rcar_pwm_disable(struct rcar_pwm_chip *rp) 160 { 161 rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR); 162 } 163 164 static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 165 const struct pwm_state *state) 166 { 167 struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip); 168 int div, ret; 169 170 /* This HW/driver only supports normal polarity */ 171 if (state->polarity != PWM_POLARITY_NORMAL) 172 return -EINVAL; 173 174 if (!state->enabled) { 175 rcar_pwm_disable(rp); 176 return 0; 177 } 178 179 div = rcar_pwm_get_clock_division(rp, state->period); 180 if (div < 0) 181 return div; 182 183 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR); 184 185 ret = rcar_pwm_set_counter(rp, div, state->duty_cycle, state->period); 186 if (!ret) 187 rcar_pwm_set_clock_control(rp, div); 188 189 /* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */ 190 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR); 191 192 if (!ret) 193 ret = rcar_pwm_enable(rp); 194 195 return ret; 196 } 197 198 static const struct pwm_ops rcar_pwm_ops = { 199 .request = rcar_pwm_request, 200 .free = rcar_pwm_free, 201 .apply = rcar_pwm_apply, 202 }; 203 204 static int rcar_pwm_probe(struct platform_device *pdev) 205 { 206 struct pwm_chip *chip; 207 struct rcar_pwm_chip *rcar_pwm; 208 int ret; 209 210 chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*rcar_pwm)); 211 if (IS_ERR(chip)) 212 return PTR_ERR(chip); 213 rcar_pwm = to_rcar_pwm_chip(chip); 214 215 rcar_pwm->base = devm_platform_ioremap_resource(pdev, 0); 216 if (IS_ERR(rcar_pwm->base)) 217 return PTR_ERR(rcar_pwm->base); 218 219 rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL); 220 if (IS_ERR(rcar_pwm->clk)) { 221 dev_err(&pdev->dev, "cannot get clock\n"); 222 return PTR_ERR(rcar_pwm->clk); 223 } 224 225 chip->ops = &rcar_pwm_ops; 226 227 platform_set_drvdata(pdev, chip); 228 229 pm_runtime_enable(&pdev->dev); 230 231 ret = pwmchip_add(chip); 232 if (ret < 0) { 233 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret); 234 pm_runtime_disable(&pdev->dev); 235 return ret; 236 } 237 238 return 0; 239 } 240 241 static void rcar_pwm_remove(struct platform_device *pdev) 242 { 243 struct pwm_chip *chip = platform_get_drvdata(pdev); 244 245 pwmchip_remove(chip); 246 247 pm_runtime_disable(&pdev->dev); 248 } 249 250 static const struct of_device_id rcar_pwm_of_table[] = { 251 { .compatible = "renesas,pwm-rcar", }, 252 { }, 253 }; 254 MODULE_DEVICE_TABLE(of, rcar_pwm_of_table); 255 256 static struct platform_driver rcar_pwm_driver = { 257 .probe = rcar_pwm_probe, 258 .remove = rcar_pwm_remove, 259 .driver = { 260 .name = "pwm-rcar", 261 .of_match_table = rcar_pwm_of_table, 262 } 263 }; 264 module_platform_driver(rcar_pwm_driver); 265 266 MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>"); 267 MODULE_DESCRIPTION("Renesas PWM Timer Driver"); 268 MODULE_LICENSE("GPL v2"); 269 MODULE_ALIAS("platform:pwm-rcar"); 270