1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip Generic power domain support. 4 * 5 * Copyright (c) 2015 Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <linux/arm-smccc.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/err.h> 12 #include <linux/mutex.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_clock.h> 15 #include <linux/pm_domain.h> 16 #include <linux/property.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/of_clk.h> 20 #include <linux/clk.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/mfd/syscon.h> 24 #include <soc/rockchip/pm_domains.h> 25 #include <soc/rockchip/rockchip_sip.h> 26 #include <dt-bindings/power/px30-power.h> 27 #include <dt-bindings/power/rockchip,rv1126-power.h> 28 #include <dt-bindings/power/rk3036-power.h> 29 #include <dt-bindings/power/rk3066-power.h> 30 #include <dt-bindings/power/rk3128-power.h> 31 #include <dt-bindings/power/rk3188-power.h> 32 #include <dt-bindings/power/rk3228-power.h> 33 #include <dt-bindings/power/rk3288-power.h> 34 #include <dt-bindings/power/rk3328-power.h> 35 #include <dt-bindings/power/rk3366-power.h> 36 #include <dt-bindings/power/rk3368-power.h> 37 #include <dt-bindings/power/rk3399-power.h> 38 #include <dt-bindings/power/rockchip,rk3562-power.h> 39 #include <dt-bindings/power/rk3568-power.h> 40 #include <dt-bindings/power/rockchip,rk3576-power.h> 41 #include <dt-bindings/power/rk3588-power.h> 42 43 struct rockchip_domain_info { 44 const char *name; 45 int pwr_mask; 46 int status_mask; 47 int req_mask; 48 int idle_mask; 49 int ack_mask; 50 bool active_wakeup; 51 bool need_regulator; 52 int pwr_w_mask; 53 int req_w_mask; 54 int clk_ungate_mask; 55 int mem_status_mask; 56 int repair_status_mask; 57 u32 pwr_offset; 58 u32 mem_offset; 59 u32 req_offset; 60 }; 61 62 struct rockchip_pmu_info { 63 u32 pwr_offset; 64 u32 status_offset; 65 u32 req_offset; 66 u32 idle_offset; 67 u32 ack_offset; 68 u32 mem_pwr_offset; 69 u32 chain_status_offset; 70 u32 mem_status_offset; 71 u32 repair_status_offset; 72 u32 clk_ungate_offset; 73 74 u32 core_pwrcnt_offset; 75 u32 gpu_pwrcnt_offset; 76 77 unsigned int core_power_transition_time; 78 unsigned int gpu_power_transition_time; 79 80 int num_domains; 81 const struct rockchip_domain_info *domain_info; 82 }; 83 84 #define MAX_QOS_REGS_NUM 5 85 #define QOS_PRIORITY 0x08 86 #define QOS_MODE 0x0c 87 #define QOS_BANDWIDTH 0x10 88 #define QOS_SATURATION 0x14 89 #define QOS_EXTCONTROL 0x18 90 91 struct rockchip_pm_domain { 92 struct generic_pm_domain genpd; 93 const struct rockchip_domain_info *info; 94 struct rockchip_pmu *pmu; 95 int num_qos; 96 struct regmap **qos_regmap; 97 u32 *qos_save_regs[MAX_QOS_REGS_NUM]; 98 int num_clks; 99 struct clk_bulk_data *clks; 100 struct device_node *node; 101 struct regulator *supply; 102 }; 103 104 struct rockchip_pmu { 105 struct device *dev; 106 struct regmap *regmap; 107 const struct rockchip_pmu_info *info; 108 struct mutex mutex; /* mutex lock for pmu */ 109 struct genpd_onecell_data genpd_data; 110 struct generic_pm_domain *domains[]; 111 }; 112 113 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) 114 115 #define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ 116 { \ 117 .name = _name, \ 118 .pwr_mask = (pwr), \ 119 .status_mask = (status), \ 120 .req_mask = (req), \ 121 .idle_mask = (idle), \ 122 .ack_mask = (ack), \ 123 .active_wakeup = (wakeup), \ 124 } 125 126 #define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ 127 { \ 128 .name = _name, \ 129 .pwr_w_mask = (pwr) << 16, \ 130 .pwr_mask = (pwr), \ 131 .status_mask = (status), \ 132 .req_w_mask = (req) << 16, \ 133 .req_mask = (req), \ 134 .idle_mask = (idle), \ 135 .ack_mask = (ack), \ 136 .active_wakeup = wakeup, \ 137 } 138 139 #define DOMAIN_M_G_SD(_name, pwr, status, req, idle, ack, g_mask, mem, wakeup, keepon) \ 140 { \ 141 .name = _name, \ 142 .pwr_w_mask = (pwr) << 16, \ 143 .pwr_mask = (pwr), \ 144 .status_mask = (status), \ 145 .req_w_mask = (req) << 16, \ 146 .req_mask = (req), \ 147 .idle_mask = (idle), \ 148 .ack_mask = (ack), \ 149 .clk_ungate_mask = (g_mask), \ 150 .active_wakeup = wakeup, \ 151 } 152 153 #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup, regulator) \ 154 { \ 155 .name = _name, \ 156 .pwr_offset = p_offset, \ 157 .pwr_w_mask = (pwr) << 16, \ 158 .pwr_mask = (pwr), \ 159 .status_mask = (status), \ 160 .mem_offset = m_offset, \ 161 .mem_status_mask = (m_status), \ 162 .repair_status_mask = (r_status), \ 163 .req_offset = r_offset, \ 164 .req_w_mask = (req) << 16, \ 165 .req_mask = (req), \ 166 .idle_mask = (idle), \ 167 .ack_mask = (ack), \ 168 .active_wakeup = wakeup, \ 169 .need_regulator = regulator, \ 170 } 171 172 #define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup) \ 173 { \ 174 .name = _name, \ 175 .pwr_offset = p_offset, \ 176 .pwr_w_mask = (pwr) << 16, \ 177 .pwr_mask = (pwr), \ 178 .status_mask = (status), \ 179 .mem_offset = m_offset, \ 180 .mem_status_mask = (m_status), \ 181 .repair_status_mask = (r_status), \ 182 .req_offset = r_offset, \ 183 .req_w_mask = (req) << 16, \ 184 .req_mask = (req), \ 185 .idle_mask = (idle), \ 186 .clk_ungate_mask = (g_mask), \ 187 .ack_mask = (ack), \ 188 .active_wakeup = wakeup, \ 189 } 190 191 #define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ 192 { \ 193 .name = _name, \ 194 .req_mask = (req), \ 195 .req_w_mask = (req) << 16, \ 196 .ack_mask = (ack), \ 197 .idle_mask = (idle), \ 198 .active_wakeup = wakeup, \ 199 } 200 201 #define DOMAIN_PX30(name, pwr, status, req, wakeup) \ 202 DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup) 203 204 #define DOMAIN_RV1126(name, pwr, req, idle, wakeup) \ 205 DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup) 206 207 #define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ 208 DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) 209 210 #define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ 211 DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) 212 213 #define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ 214 DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) 215 216 #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ 217 DOMAIN(name, pwr, status, req, req, req, wakeup) 218 219 #define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) \ 220 DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false) 221 222 #define DOMAIN_RK3568(name, pwr, req, wakeup) \ 223 DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) 224 225 #define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \ 226 DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup) 227 228 /* 229 * Dynamic Memory Controller may need to coordinate with us -- see 230 * rockchip_pmu_block(). 231 * 232 * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to 233 * block() while we're initializing the PMU. 234 */ 235 static DEFINE_MUTEX(dmc_pmu_mutex); 236 static struct rockchip_pmu *dmc_pmu; 237 238 /* 239 * Block PMU transitions and make sure they don't interfere with ARM Trusted 240 * Firmware operations. There are two conflicts, noted in the comments below. 241 * 242 * Caller must unblock PMU transitions via rockchip_pmu_unblock(). 243 */ 244 int rockchip_pmu_block(void) 245 { 246 struct rockchip_pmu *pmu; 247 struct generic_pm_domain *genpd; 248 struct rockchip_pm_domain *pd; 249 int i, ret; 250 251 mutex_lock(&dmc_pmu_mutex); 252 253 /* No PMU (yet)? Then we just block rockchip_pmu_probe(). */ 254 if (!dmc_pmu) 255 return 0; 256 pmu = dmc_pmu; 257 258 /* 259 * mutex blocks all idle transitions: we can't touch the 260 * PMU_BUS_IDLE_REQ (our ".idle_offset") register while ARM Trusted 261 * Firmware might be using it. 262 */ 263 mutex_lock(&pmu->mutex); 264 265 /* 266 * Power domain clocks: Per Rockchip, we *must* keep certain clocks 267 * enabled for the duration of power-domain transitions. Most 268 * transitions are handled by this driver, but some cases (in 269 * particular, DRAM DVFS / memory-controller idle) must be handled by 270 * firmware. Firmware can handle most clock management via a special 271 * "ungate" register (PMU_CRU_GATEDIS_CON0), but unfortunately, this 272 * doesn't handle PLLs. We can assist this transition by doing the 273 * clock management on behalf of firmware. 274 */ 275 for (i = 0; i < pmu->genpd_data.num_domains; i++) { 276 genpd = pmu->genpd_data.domains[i]; 277 if (genpd) { 278 pd = to_rockchip_pd(genpd); 279 ret = clk_bulk_enable(pd->num_clks, pd->clks); 280 if (ret < 0) { 281 dev_err(pmu->dev, 282 "failed to enable clks for domain '%s': %d\n", 283 genpd->name, ret); 284 goto err; 285 } 286 } 287 } 288 289 return 0; 290 291 err: 292 for (i = i - 1; i >= 0; i--) { 293 genpd = pmu->genpd_data.domains[i]; 294 if (genpd) { 295 pd = to_rockchip_pd(genpd); 296 clk_bulk_disable(pd->num_clks, pd->clks); 297 } 298 } 299 mutex_unlock(&pmu->mutex); 300 mutex_unlock(&dmc_pmu_mutex); 301 302 return ret; 303 } 304 EXPORT_SYMBOL_GPL(rockchip_pmu_block); 305 306 /* Unblock PMU transitions. */ 307 void rockchip_pmu_unblock(void) 308 { 309 struct rockchip_pmu *pmu; 310 struct generic_pm_domain *genpd; 311 struct rockchip_pm_domain *pd; 312 int i; 313 314 if (dmc_pmu) { 315 pmu = dmc_pmu; 316 for (i = 0; i < pmu->genpd_data.num_domains; i++) { 317 genpd = pmu->genpd_data.domains[i]; 318 if (genpd) { 319 pd = to_rockchip_pd(genpd); 320 clk_bulk_disable(pd->num_clks, pd->clks); 321 } 322 } 323 324 mutex_unlock(&pmu->mutex); 325 } 326 327 mutex_unlock(&dmc_pmu_mutex); 328 } 329 EXPORT_SYMBOL_GPL(rockchip_pmu_unblock); 330 331 #define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup, regulator) \ 332 DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup, regulator) 333 334 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) 335 { 336 struct rockchip_pmu *pmu = pd->pmu; 337 const struct rockchip_domain_info *pd_info = pd->info; 338 unsigned int val; 339 340 regmap_read(pmu->regmap, pmu->info->idle_offset, &val); 341 return (val & pd_info->idle_mask) == pd_info->idle_mask; 342 } 343 344 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu) 345 { 346 unsigned int val; 347 348 regmap_read(pmu->regmap, pmu->info->ack_offset, &val); 349 return val; 350 } 351 352 static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ungate) 353 { 354 const struct rockchip_domain_info *pd_info = pd->info; 355 struct rockchip_pmu *pmu = pd->pmu; 356 unsigned int val; 357 int clk_ungate_w_mask = pd_info->clk_ungate_mask << 16; 358 359 if (!pd_info->clk_ungate_mask) 360 return 0; 361 362 if (!pmu->info->clk_ungate_offset) 363 return 0; 364 365 val = ungate ? (pd_info->clk_ungate_mask | clk_ungate_w_mask) : 366 clk_ungate_w_mask; 367 regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val); 368 369 return 0; 370 } 371 372 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, 373 bool idle) 374 { 375 const struct rockchip_domain_info *pd_info = pd->info; 376 struct generic_pm_domain *genpd = &pd->genpd; 377 struct rockchip_pmu *pmu = pd->pmu; 378 u32 pd_req_offset = pd_info->req_offset; 379 unsigned int target_ack; 380 unsigned int val; 381 bool is_idle; 382 int ret; 383 384 if (pd_info->req_mask == 0) 385 return 0; 386 else if (pd_info->req_w_mask) 387 regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset, 388 idle ? (pd_info->req_mask | pd_info->req_w_mask) : 389 pd_info->req_w_mask); 390 else 391 regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset, 392 pd_info->req_mask, idle ? -1U : 0); 393 394 wmb(); 395 396 /* Wait util idle_ack = 1 */ 397 target_ack = idle ? pd_info->ack_mask : 0; 398 ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val, 399 (val & pd_info->ack_mask) == target_ack, 400 0, 10000); 401 if (ret) { 402 dev_err(pmu->dev, 403 "failed to get ack on domain '%s', val=0x%x\n", 404 genpd->name, val); 405 return ret; 406 } 407 408 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd, 409 is_idle, is_idle == idle, 0, 10000); 410 if (ret) { 411 dev_err(pmu->dev, 412 "failed to set idle on domain '%s', val=%d\n", 413 genpd->name, is_idle); 414 return ret; 415 } 416 417 return 0; 418 } 419 420 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd) 421 { 422 int i; 423 424 for (i = 0; i < pd->num_qos; i++) { 425 regmap_read(pd->qos_regmap[i], 426 QOS_PRIORITY, 427 &pd->qos_save_regs[0][i]); 428 regmap_read(pd->qos_regmap[i], 429 QOS_MODE, 430 &pd->qos_save_regs[1][i]); 431 regmap_read(pd->qos_regmap[i], 432 QOS_BANDWIDTH, 433 &pd->qos_save_regs[2][i]); 434 regmap_read(pd->qos_regmap[i], 435 QOS_SATURATION, 436 &pd->qos_save_regs[3][i]); 437 regmap_read(pd->qos_regmap[i], 438 QOS_EXTCONTROL, 439 &pd->qos_save_regs[4][i]); 440 } 441 return 0; 442 } 443 444 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd) 445 { 446 int i; 447 448 for (i = 0; i < pd->num_qos; i++) { 449 regmap_write(pd->qos_regmap[i], 450 QOS_PRIORITY, 451 pd->qos_save_regs[0][i]); 452 regmap_write(pd->qos_regmap[i], 453 QOS_MODE, 454 pd->qos_save_regs[1][i]); 455 regmap_write(pd->qos_regmap[i], 456 QOS_BANDWIDTH, 457 pd->qos_save_regs[2][i]); 458 regmap_write(pd->qos_regmap[i], 459 QOS_SATURATION, 460 pd->qos_save_regs[3][i]); 461 regmap_write(pd->qos_regmap[i], 462 QOS_EXTCONTROL, 463 pd->qos_save_regs[4][i]); 464 } 465 466 return 0; 467 } 468 469 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd) 470 { 471 struct rockchip_pmu *pmu = pd->pmu; 472 unsigned int val; 473 474 if (pd->info->repair_status_mask) { 475 regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val); 476 /* 1'b1: power on, 1'b0: power off */ 477 return val & pd->info->repair_status_mask; 478 } 479 480 /* check idle status for idle-only domains */ 481 if (pd->info->status_mask == 0) 482 return !rockchip_pmu_domain_is_idle(pd); 483 484 regmap_read(pmu->regmap, pmu->info->status_offset, &val); 485 486 /* 1'b0: power on, 1'b1: power off */ 487 return !(val & pd->info->status_mask); 488 } 489 490 static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd) 491 { 492 struct rockchip_pmu *pmu = pd->pmu; 493 unsigned int val; 494 495 regmap_read(pmu->regmap, 496 pmu->info->mem_status_offset + pd->info->mem_offset, &val); 497 498 /* 1'b0: power on, 1'b1: power off */ 499 return !(val & pd->info->mem_status_mask); 500 } 501 502 static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd) 503 { 504 struct rockchip_pmu *pmu = pd->pmu; 505 unsigned int val; 506 507 regmap_read(pmu->regmap, 508 pmu->info->chain_status_offset + pd->info->mem_offset, &val); 509 510 /* 1'b1: power on, 1'b0: power off */ 511 return val & pd->info->mem_status_mask; 512 } 513 514 static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd) 515 { 516 struct rockchip_pmu *pmu = pd->pmu; 517 struct generic_pm_domain *genpd = &pd->genpd; 518 bool is_on; 519 int ret = 0; 520 521 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on, 522 is_on == true, 0, 10000); 523 if (ret) { 524 dev_err(pmu->dev, 525 "failed to get chain status '%s', target_on=1, val=%d\n", 526 genpd->name, is_on); 527 goto error; 528 } 529 530 udelay(20); 531 532 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, 533 (pd->info->pwr_mask | pd->info->pwr_w_mask)); 534 wmb(); 535 536 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on, 537 is_on == false, 0, 10000); 538 if (ret) { 539 dev_err(pmu->dev, 540 "failed to get mem status '%s', target_on=0, val=%d\n", 541 genpd->name, is_on); 542 goto error; 543 } 544 545 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, 546 pd->info->pwr_w_mask); 547 wmb(); 548 549 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on, 550 is_on == true, 0, 10000); 551 if (ret) { 552 dev_err(pmu->dev, 553 "failed to get mem status '%s', target_on=1, val=%d\n", 554 genpd->name, is_on); 555 } 556 557 error: 558 return ret; 559 } 560 561 static int rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, 562 bool on) 563 { 564 struct rockchip_pmu *pmu = pd->pmu; 565 struct generic_pm_domain *genpd = &pd->genpd; 566 u32 pd_pwr_offset = pd->info->pwr_offset; 567 bool is_on, is_mem_on = false; 568 struct arm_smccc_res res; 569 int ret; 570 571 if (pd->info->pwr_mask == 0) 572 return 0; 573 574 if (on && pd->info->mem_status_mask) 575 is_mem_on = rockchip_pmu_domain_is_mem_on(pd); 576 577 if (pd->info->pwr_w_mask) 578 regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, 579 on ? pd->info->pwr_w_mask : 580 (pd->info->pwr_mask | pd->info->pwr_w_mask)); 581 else 582 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, 583 pd->info->pwr_mask, on ? 0 : -1U); 584 585 wmb(); 586 587 if (is_mem_on) { 588 ret = rockchip_pmu_domain_mem_reset(pd); 589 if (ret) 590 return ret; 591 } 592 593 594 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on, 595 is_on == on, 0, 10000); 596 if (ret) { 597 dev_err(pmu->dev, "failed to set domain '%s' %s, val=%d\n", 598 genpd->name, on ? "on" : "off", is_on); 599 return ret; 600 } 601 602 /* Inform firmware to keep this pd on or off */ 603 if (arm_smccc_1_1_get_conduit() != SMCCC_CONDUIT_NONE) 604 arm_smccc_smc(ROCKCHIP_SIP_SUSPEND_MODE, ROCKCHIP_SLEEP_PD_CONFIG, 605 pmu->info->pwr_offset + pd_pwr_offset, 606 pd->info->pwr_mask, on, 0, 0, 0, &res); 607 608 return 0; 609 } 610 611 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on) 612 { 613 struct rockchip_pmu *pmu = pd->pmu; 614 int ret; 615 616 guard(mutex)(&pmu->mutex); 617 618 if (rockchip_pmu_domain_is_on(pd) == power_on) 619 return 0; 620 621 ret = clk_bulk_enable(pd->num_clks, pd->clks); 622 if (ret < 0) { 623 dev_err(pmu->dev, "failed to enable clocks\n"); 624 return ret; 625 } 626 627 rockchip_pmu_ungate_clk(pd, true); 628 629 if (!power_on) { 630 rockchip_pmu_save_qos(pd); 631 632 /* if powering down, idle request to NIU first */ 633 ret = rockchip_pmu_set_idle_request(pd, true); 634 if (ret < 0) 635 goto out; 636 } 637 638 ret = rockchip_do_pmu_set_power_domain(pd, power_on); 639 if (ret < 0) 640 goto out; 641 642 if (power_on) { 643 /* if powering up, leave idle mode */ 644 ret = rockchip_pmu_set_idle_request(pd, false); 645 if (ret < 0) 646 goto out; 647 648 rockchip_pmu_restore_qos(pd); 649 } 650 651 out: 652 rockchip_pmu_ungate_clk(pd, false); 653 clk_bulk_disable(pd->num_clks, pd->clks); 654 655 return ret; 656 } 657 658 static int rockchip_pd_regulator_disable(struct rockchip_pm_domain *pd) 659 { 660 return IS_ERR_OR_NULL(pd->supply) ? 0 : regulator_disable(pd->supply); 661 } 662 663 static int rockchip_pd_regulator_enable(struct rockchip_pm_domain *pd) 664 { 665 struct rockchip_pmu *pmu = pd->pmu; 666 667 if (!pd->info->need_regulator) 668 return 0; 669 670 if (IS_ERR_OR_NULL(pd->supply)) { 671 pd->supply = devm_of_regulator_get(pmu->dev, pd->node, "domain"); 672 673 if (IS_ERR(pd->supply)) 674 return PTR_ERR(pd->supply); 675 } 676 677 return regulator_enable(pd->supply); 678 } 679 680 static int rockchip_pd_power_on(struct generic_pm_domain *domain) 681 { 682 struct rockchip_pm_domain *pd = to_rockchip_pd(domain); 683 int ret; 684 685 ret = rockchip_pd_regulator_enable(pd); 686 if (ret) { 687 dev_err(pd->pmu->dev, "Failed to enable supply: %d\n", ret); 688 return ret; 689 } 690 691 ret = rockchip_pd_power(pd, true); 692 if (ret) 693 rockchip_pd_regulator_disable(pd); 694 695 return ret; 696 } 697 698 static int rockchip_pd_power_off(struct generic_pm_domain *domain) 699 { 700 struct rockchip_pm_domain *pd = to_rockchip_pd(domain); 701 int ret; 702 703 ret = rockchip_pd_power(pd, false); 704 if (ret) 705 return ret; 706 707 rockchip_pd_regulator_disable(pd); 708 return ret; 709 } 710 711 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd, 712 struct device *dev) 713 { 714 struct clk *clk; 715 int i; 716 int error; 717 718 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name); 719 720 error = pm_clk_create(dev); 721 if (error) { 722 dev_err(dev, "pm_clk_create failed %d\n", error); 723 return error; 724 } 725 726 i = 0; 727 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) { 728 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk); 729 error = pm_clk_add_clk(dev, clk); 730 if (error) { 731 dev_err(dev, "pm_clk_add_clk failed %d\n", error); 732 clk_put(clk); 733 pm_clk_destroy(dev); 734 return error; 735 } 736 } 737 738 return 0; 739 } 740 741 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd, 742 struct device *dev) 743 { 744 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name); 745 746 pm_clk_destroy(dev); 747 } 748 749 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, 750 struct device_node *node) 751 { 752 const struct rockchip_domain_info *pd_info; 753 struct rockchip_pm_domain *pd; 754 struct device_node *qos_node; 755 int i, j; 756 u32 id; 757 int error; 758 759 error = of_property_read_u32(node, "reg", &id); 760 if (error) { 761 dev_err(pmu->dev, 762 "%pOFn: failed to retrieve domain id (reg): %d\n", 763 node, error); 764 return -EINVAL; 765 } 766 767 if (id >= pmu->info->num_domains) { 768 dev_err(pmu->dev, "%pOFn: invalid domain id %d\n", 769 node, id); 770 return -EINVAL; 771 } 772 /* RK3588 has domains with two parents (RKVDEC0/RKVDEC1) */ 773 if (pmu->genpd_data.domains[id]) 774 return 0; 775 776 pd_info = &pmu->info->domain_info[id]; 777 if (!pd_info) { 778 dev_err(pmu->dev, "%pOFn: undefined domain id %d\n", 779 node, id); 780 return -EINVAL; 781 } 782 783 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL); 784 if (!pd) 785 return -ENOMEM; 786 787 pd->info = pd_info; 788 pd->pmu = pmu; 789 pd->node = node; 790 791 pd->num_clks = of_clk_get_parent_count(node); 792 if (pd->num_clks > 0) { 793 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks, 794 sizeof(*pd->clks), GFP_KERNEL); 795 if (!pd->clks) 796 return -ENOMEM; 797 } else { 798 dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n", 799 node, pd->num_clks); 800 pd->num_clks = 0; 801 } 802 803 for (i = 0; i < pd->num_clks; i++) { 804 pd->clks[i].clk = of_clk_get(node, i); 805 if (IS_ERR(pd->clks[i].clk)) { 806 error = PTR_ERR(pd->clks[i].clk); 807 dev_err(pmu->dev, 808 "%pOFn: failed to get clk at index %d: %d\n", 809 node, i, error); 810 return error; 811 } 812 } 813 814 error = clk_bulk_prepare(pd->num_clks, pd->clks); 815 if (error) 816 goto err_put_clocks; 817 818 pd->num_qos = of_count_phandle_with_args(node, "pm_qos", 819 NULL); 820 821 if (pd->num_qos > 0) { 822 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos, 823 sizeof(*pd->qos_regmap), 824 GFP_KERNEL); 825 if (!pd->qos_regmap) { 826 error = -ENOMEM; 827 goto err_unprepare_clocks; 828 } 829 830 for (j = 0; j < MAX_QOS_REGS_NUM; j++) { 831 pd->qos_save_regs[j] = devm_kcalloc(pmu->dev, 832 pd->num_qos, 833 sizeof(u32), 834 GFP_KERNEL); 835 if (!pd->qos_save_regs[j]) { 836 error = -ENOMEM; 837 goto err_unprepare_clocks; 838 } 839 } 840 841 for (j = 0; j < pd->num_qos; j++) { 842 qos_node = of_parse_phandle(node, "pm_qos", j); 843 if (!qos_node) { 844 error = -ENODEV; 845 goto err_unprepare_clocks; 846 } 847 pd->qos_regmap[j] = syscon_node_to_regmap(qos_node); 848 of_node_put(qos_node); 849 if (IS_ERR(pd->qos_regmap[j])) { 850 error = -ENODEV; 851 goto err_unprepare_clocks; 852 } 853 } 854 } 855 856 if (pd->info->name) 857 pd->genpd.name = pd->info->name; 858 else 859 pd->genpd.name = kbasename(node->full_name); 860 pd->genpd.power_off = rockchip_pd_power_off; 861 pd->genpd.power_on = rockchip_pd_power_on; 862 pd->genpd.attach_dev = rockchip_pd_attach_dev; 863 pd->genpd.detach_dev = rockchip_pd_detach_dev; 864 pd->genpd.flags = GENPD_FLAG_PM_CLK; 865 if (pd_info->active_wakeup) 866 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; 867 pm_genpd_init(&pd->genpd, NULL, 868 !rockchip_pmu_domain_is_on(pd) || 869 (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd))); 870 871 pmu->genpd_data.domains[id] = &pd->genpd; 872 return 0; 873 874 err_unprepare_clocks: 875 clk_bulk_unprepare(pd->num_clks, pd->clks); 876 err_put_clocks: 877 clk_bulk_put(pd->num_clks, pd->clks); 878 return error; 879 } 880 881 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd) 882 { 883 int ret; 884 885 /* 886 * We're in the error cleanup already, so we only complain, 887 * but won't emit another error on top of the original one. 888 */ 889 ret = pm_genpd_remove(&pd->genpd); 890 if (ret < 0) 891 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n", 892 pd->genpd.name, ret); 893 894 clk_bulk_unprepare(pd->num_clks, pd->clks); 895 clk_bulk_put(pd->num_clks, pd->clks); 896 897 /* protect the zeroing of pm->num_clks */ 898 mutex_lock(&pd->pmu->mutex); 899 pd->num_clks = 0; 900 mutex_unlock(&pd->pmu->mutex); 901 902 /* devm will free our memory */ 903 } 904 905 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu) 906 { 907 struct generic_pm_domain *genpd; 908 struct rockchip_pm_domain *pd; 909 int i; 910 911 for (i = 0; i < pmu->genpd_data.num_domains; i++) { 912 genpd = pmu->genpd_data.domains[i]; 913 if (genpd) { 914 pd = to_rockchip_pd(genpd); 915 rockchip_pm_remove_one_domain(pd); 916 } 917 } 918 919 /* devm will free our memory */ 920 } 921 922 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu, 923 u32 domain_reg_offset, 924 unsigned int count) 925 { 926 /* First configure domain power down transition count ... */ 927 regmap_write(pmu->regmap, domain_reg_offset, count); 928 /* ... and then power up count. */ 929 regmap_write(pmu->regmap, domain_reg_offset + 4, count); 930 } 931 932 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu, 933 struct device_node *parent) 934 { 935 struct generic_pm_domain *child_domain, *parent_domain; 936 int error; 937 938 for_each_child_of_node_scoped(parent, np) { 939 u32 idx; 940 941 error = of_property_read_u32(parent, "reg", &idx); 942 if (error) { 943 dev_err(pmu->dev, 944 "%pOFn: failed to retrieve domain id (reg): %d\n", 945 parent, error); 946 return error; 947 } 948 parent_domain = pmu->genpd_data.domains[idx]; 949 950 error = rockchip_pm_add_one_domain(pmu, np); 951 if (error) { 952 dev_err(pmu->dev, "failed to handle node %pOFn: %d\n", 953 np, error); 954 return error; 955 } 956 957 error = of_property_read_u32(np, "reg", &idx); 958 if (error) { 959 dev_err(pmu->dev, 960 "%pOFn: failed to retrieve domain id (reg): %d\n", 961 np, error); 962 return error; 963 } 964 child_domain = pmu->genpd_data.domains[idx]; 965 966 error = pm_genpd_add_subdomain(parent_domain, child_domain); 967 if (error) { 968 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n", 969 parent_domain->name, child_domain->name, error); 970 return error; 971 } else { 972 dev_dbg(pmu->dev, "%s add subdomain: %s\n", 973 parent_domain->name, child_domain->name); 974 } 975 976 rockchip_pm_add_subdomain(pmu, np); 977 } 978 979 return 0; 980 } 981 982 static int rockchip_pm_domain_probe(struct platform_device *pdev) 983 { 984 struct device *dev = &pdev->dev; 985 struct device_node *np = dev->of_node; 986 struct device *parent; 987 struct rockchip_pmu *pmu; 988 const struct rockchip_pmu_info *pmu_info; 989 int error; 990 991 if (!np) { 992 dev_err(dev, "device tree node not found\n"); 993 return -ENODEV; 994 } 995 996 pmu_info = device_get_match_data(dev); 997 998 pmu = devm_kzalloc(dev, 999 struct_size(pmu, domains, pmu_info->num_domains), 1000 GFP_KERNEL); 1001 if (!pmu) 1002 return -ENOMEM; 1003 1004 pmu->dev = &pdev->dev; 1005 mutex_init(&pmu->mutex); 1006 1007 pmu->info = pmu_info; 1008 1009 pmu->genpd_data.domains = pmu->domains; 1010 pmu->genpd_data.num_domains = pmu_info->num_domains; 1011 1012 parent = dev->parent; 1013 if (!parent) { 1014 dev_err(dev, "no parent for syscon devices\n"); 1015 return -ENODEV; 1016 } 1017 1018 pmu->regmap = syscon_node_to_regmap(parent->of_node); 1019 if (IS_ERR(pmu->regmap)) { 1020 dev_err(dev, "no regmap available\n"); 1021 return PTR_ERR(pmu->regmap); 1022 } 1023 1024 /* 1025 * Configure power up and down transition delays for CORE 1026 * and GPU domains. 1027 */ 1028 if (pmu_info->core_power_transition_time) 1029 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset, 1030 pmu_info->core_power_transition_time); 1031 if (pmu_info->gpu_pwrcnt_offset) 1032 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset, 1033 pmu_info->gpu_power_transition_time); 1034 1035 error = -ENODEV; 1036 1037 /* 1038 * Prevent any rockchip_pmu_block() from racing with the remainder of 1039 * setup (clocks, register initialization). 1040 */ 1041 guard(mutex)(&dmc_pmu_mutex); 1042 1043 for_each_available_child_of_node_scoped(np, node) { 1044 error = rockchip_pm_add_one_domain(pmu, node); 1045 if (error) { 1046 dev_err(dev, "failed to handle node %pOFn: %d\n", 1047 node, error); 1048 goto err_out; 1049 } 1050 1051 error = rockchip_pm_add_subdomain(pmu, node); 1052 if (error < 0) { 1053 dev_err(dev, "failed to handle subdomain node %pOFn: %d\n", 1054 node, error); 1055 goto err_out; 1056 } 1057 } 1058 1059 if (error) { 1060 dev_dbg(dev, "no power domains defined\n"); 1061 goto err_out; 1062 } 1063 1064 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data); 1065 if (error) { 1066 dev_err(dev, "failed to add provider: %d\n", error); 1067 goto err_out; 1068 } 1069 1070 /* We only expect one PMU. */ 1071 if (!WARN_ON_ONCE(dmc_pmu)) 1072 dmc_pmu = pmu; 1073 1074 return 0; 1075 1076 err_out: 1077 rockchip_pm_domain_cleanup(pmu); 1078 return error; 1079 } 1080 1081 static const struct rockchip_domain_info px30_pm_domains[] = { 1082 [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), 1083 [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), 1084 [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), 1085 [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), 1086 [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), 1087 [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), 1088 [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), 1089 [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), 1090 }; 1091 1092 static const struct rockchip_domain_info rv1126_pm_domains[] = { 1093 [RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false), 1094 [RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false), 1095 [RV1126_PD_VO] = DOMAIN_RV1126("vo", BIT(5), BIT(7), BIT(7), false), 1096 [RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false), 1097 [RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false), 1098 [RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false), 1099 [RV1126_PD_SDIO] = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13), false), 1100 [RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), false), 1101 }; 1102 1103 static const struct rockchip_domain_info rk3036_pm_domains[] = { 1104 [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), 1105 [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), 1106 [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), 1107 [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), 1108 [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), 1109 [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), 1110 [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), 1111 }; 1112 1113 static const struct rockchip_domain_info rk3066_pm_domains[] = { 1114 [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), 1115 [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), 1116 [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), 1117 [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), 1118 [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), 1119 }; 1120 1121 static const struct rockchip_domain_info rk3128_pm_domains[] = { 1122 [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), 1123 [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), 1124 [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), 1125 [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), 1126 [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), 1127 }; 1128 1129 static const struct rockchip_domain_info rk3188_pm_domains[] = { 1130 [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), 1131 [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), 1132 [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), 1133 [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), 1134 [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), 1135 }; 1136 1137 static const struct rockchip_domain_info rk3228_pm_domains[] = { 1138 [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), 1139 [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), 1140 [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), 1141 [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), 1142 [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), 1143 [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), 1144 [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), 1145 [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), 1146 [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), 1147 [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), 1148 [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), 1149 }; 1150 1151 static const struct rockchip_domain_info rk3288_pm_domains[] = { 1152 [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), 1153 [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), 1154 [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), 1155 [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), 1156 }; 1157 1158 static const struct rockchip_domain_info rk3328_pm_domains[] = { 1159 [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), 1160 [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), 1161 [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), 1162 [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), 1163 [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), 1164 [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), 1165 [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), 1166 [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), 1167 [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), 1168 }; 1169 1170 static const struct rockchip_domain_info rk3366_pm_domains[] = { 1171 [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), 1172 [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), 1173 [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), 1174 [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), 1175 [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), 1176 [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), 1177 [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), 1178 }; 1179 1180 static const struct rockchip_domain_info rk3368_pm_domains[] = { 1181 [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), 1182 [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), 1183 [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), 1184 [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), 1185 [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), 1186 }; 1187 1188 static const struct rockchip_domain_info rk3399_pm_domains[] = { 1189 [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), 1190 [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), 1191 [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), 1192 [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), 1193 [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), 1194 [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), 1195 [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), 1196 [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), 1197 [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), 1198 [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), 1199 [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), 1200 [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), 1201 [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), 1202 [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), 1203 [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), 1204 [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), 1205 [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), 1206 [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), 1207 [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), 1208 [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), 1209 [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), 1210 [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), 1211 [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), 1212 [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), 1213 [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), 1214 [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), 1215 [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), 1216 }; 1217 1218 static const struct rockchip_domain_info rk3562_pm_domains[] = { 1219 /* name pwr req g_mask mem wakeup */ 1220 [RK3562_PD_GPU] = DOMAIN_RK3562("gpu", BIT(0), BIT(1), BIT(1), 0, false), 1221 [RK3562_PD_NPU] = DOMAIN_RK3562("npu", BIT(1), BIT(2), BIT(2), 0, false), 1222 [RK3562_PD_VDPU] = DOMAIN_RK3562("vdpu", BIT(2), BIT(6), BIT(6), 0, false), 1223 [RK3562_PD_VEPU] = DOMAIN_RK3562("vepu", BIT(3), BIT(7), BIT(7) | BIT(3), 0, false), 1224 [RK3562_PD_RGA] = DOMAIN_RK3562("rga", BIT(4), BIT(5), BIT(5) | BIT(4), 0, false), 1225 [RK3562_PD_VI] = DOMAIN_RK3562("vi", BIT(5), BIT(3), BIT(3), 0, false), 1226 [RK3562_PD_VO] = DOMAIN_RK3562("vo", BIT(6), BIT(4), BIT(4), 16, false), 1227 [RK3562_PD_PHP] = DOMAIN_RK3562("php", BIT(7), BIT(8), BIT(8), 0, false), 1228 }; 1229 1230 static const struct rockchip_domain_info rk3568_pm_domains[] = { 1231 [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false), 1232 [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), 1233 [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false), 1234 [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false), 1235 [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false), 1236 [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false), 1237 [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false), 1238 [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false), 1239 [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false), 1240 }; 1241 1242 static const struct rockchip_domain_info rk3576_pm_domains[] = { 1243 [RK3576_PD_NPU] = DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, 0x0, 0, 0, 0, false), 1244 [RK3576_PD_NVM] = DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6), 0x4, BIT(2), BIT(18), BIT(2), false), 1245 [RK3576_PD_SDGMAC] = DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(7), 0x4, BIT(1), BIT(17), 0x6, false), 1246 [RK3576_PD_AUDIO] = DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8), 0x4, BIT(0), BIT(16), BIT(0), false), 1247 [RK3576_PD_PHP] = DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9), 0x0, BIT(15), BIT(15), BIT(15), false), 1248 [RK3576_PD_SUBPHP] = DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(10), 0x0, 0, 0, 0, false), 1249 [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, false), 1250 [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, false), 1251 [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, false), 1252 [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, true), 1253 [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), false), 1254 [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, false), 1255 [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), false), 1256 [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), false), 1257 [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), false), 1258 [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, 0x18, false), 1259 [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, false), 1260 [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, false), 1261 [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false), 1262 }; 1263 1264 static const struct rockchip_domain_info rk3588_pm_domains[] = { 1265 [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false, true), 1266 [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false, true), 1267 [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false, false), 1268 [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false, false), 1269 [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false, false), 1270 [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false, false), 1271 [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false, false), 1272 [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false, false), 1273 [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false, false), 1274 [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false, false), 1275 [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false, false), 1276 [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false, false), 1277 [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false, false), 1278 [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false, false), 1279 [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false, false), 1280 [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false, false), 1281 [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false, false), 1282 [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false, false), 1283 [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false, false), 1284 [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false, false), 1285 [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false, false), 1286 [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false, false), 1287 [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false, false), 1288 [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true, false), 1289 [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false, false), 1290 [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false, false), 1291 [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false, false), 1292 [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true, false), 1293 [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false, false), 1294 }; 1295 1296 static const struct rockchip_pmu_info px30_pmu = { 1297 .pwr_offset = 0x18, 1298 .status_offset = 0x20, 1299 .req_offset = 0x64, 1300 .idle_offset = 0x6c, 1301 .ack_offset = 0x6c, 1302 1303 .num_domains = ARRAY_SIZE(px30_pm_domains), 1304 .domain_info = px30_pm_domains, 1305 }; 1306 1307 static const struct rockchip_pmu_info rk3036_pmu = { 1308 .req_offset = 0x148, 1309 .idle_offset = 0x14c, 1310 .ack_offset = 0x14c, 1311 1312 .num_domains = ARRAY_SIZE(rk3036_pm_domains), 1313 .domain_info = rk3036_pm_domains, 1314 }; 1315 1316 static const struct rockchip_pmu_info rk3066_pmu = { 1317 .pwr_offset = 0x08, 1318 .status_offset = 0x0c, 1319 .req_offset = 0x38, /* PMU_MISC_CON1 */ 1320 .idle_offset = 0x0c, 1321 .ack_offset = 0x0c, 1322 1323 .num_domains = ARRAY_SIZE(rk3066_pm_domains), 1324 .domain_info = rk3066_pm_domains, 1325 }; 1326 1327 static const struct rockchip_pmu_info rk3128_pmu = { 1328 .pwr_offset = 0x04, 1329 .status_offset = 0x08, 1330 .req_offset = 0x0c, 1331 .idle_offset = 0x10, 1332 .ack_offset = 0x10, 1333 1334 .num_domains = ARRAY_SIZE(rk3128_pm_domains), 1335 .domain_info = rk3128_pm_domains, 1336 }; 1337 1338 static const struct rockchip_pmu_info rk3188_pmu = { 1339 .pwr_offset = 0x08, 1340 .status_offset = 0x0c, 1341 .req_offset = 0x38, /* PMU_MISC_CON1 */ 1342 .idle_offset = 0x0c, 1343 .ack_offset = 0x0c, 1344 1345 .num_domains = ARRAY_SIZE(rk3188_pm_domains), 1346 .domain_info = rk3188_pm_domains, 1347 }; 1348 1349 static const struct rockchip_pmu_info rk3228_pmu = { 1350 .req_offset = 0x40c, 1351 .idle_offset = 0x488, 1352 .ack_offset = 0x488, 1353 1354 .num_domains = ARRAY_SIZE(rk3228_pm_domains), 1355 .domain_info = rk3228_pm_domains, 1356 }; 1357 1358 static const struct rockchip_pmu_info rk3288_pmu = { 1359 .pwr_offset = 0x08, 1360 .status_offset = 0x0c, 1361 .req_offset = 0x10, 1362 .idle_offset = 0x14, 1363 .ack_offset = 0x14, 1364 1365 .core_pwrcnt_offset = 0x34, 1366 .gpu_pwrcnt_offset = 0x3c, 1367 1368 .core_power_transition_time = 24, /* 1us */ 1369 .gpu_power_transition_time = 24, /* 1us */ 1370 1371 .num_domains = ARRAY_SIZE(rk3288_pm_domains), 1372 .domain_info = rk3288_pm_domains, 1373 }; 1374 1375 static const struct rockchip_pmu_info rk3328_pmu = { 1376 .req_offset = 0x414, 1377 .idle_offset = 0x484, 1378 .ack_offset = 0x484, 1379 1380 .num_domains = ARRAY_SIZE(rk3328_pm_domains), 1381 .domain_info = rk3328_pm_domains, 1382 }; 1383 1384 static const struct rockchip_pmu_info rk3366_pmu = { 1385 .pwr_offset = 0x0c, 1386 .status_offset = 0x10, 1387 .req_offset = 0x3c, 1388 .idle_offset = 0x40, 1389 .ack_offset = 0x40, 1390 1391 .core_pwrcnt_offset = 0x48, 1392 .gpu_pwrcnt_offset = 0x50, 1393 1394 .core_power_transition_time = 24, 1395 .gpu_power_transition_time = 24, 1396 1397 .num_domains = ARRAY_SIZE(rk3366_pm_domains), 1398 .domain_info = rk3366_pm_domains, 1399 }; 1400 1401 static const struct rockchip_pmu_info rk3368_pmu = { 1402 .pwr_offset = 0x0c, 1403 .status_offset = 0x10, 1404 .req_offset = 0x3c, 1405 .idle_offset = 0x40, 1406 .ack_offset = 0x40, 1407 1408 .core_pwrcnt_offset = 0x48, 1409 .gpu_pwrcnt_offset = 0x50, 1410 1411 .core_power_transition_time = 24, 1412 .gpu_power_transition_time = 24, 1413 1414 .num_domains = ARRAY_SIZE(rk3368_pm_domains), 1415 .domain_info = rk3368_pm_domains, 1416 }; 1417 1418 static const struct rockchip_pmu_info rk3399_pmu = { 1419 .pwr_offset = 0x14, 1420 .status_offset = 0x18, 1421 .req_offset = 0x60, 1422 .idle_offset = 0x64, 1423 .ack_offset = 0x68, 1424 1425 /* ARM Trusted Firmware manages power transition times */ 1426 1427 .num_domains = ARRAY_SIZE(rk3399_pm_domains), 1428 .domain_info = rk3399_pm_domains, 1429 }; 1430 1431 static const struct rockchip_pmu_info rk3562_pmu = { 1432 .pwr_offset = 0x210, 1433 .status_offset = 0x230, 1434 .req_offset = 0x110, 1435 .idle_offset = 0x128, 1436 .ack_offset = 0x120, 1437 .clk_ungate_offset = 0x140, 1438 1439 .num_domains = ARRAY_SIZE(rk3562_pm_domains), 1440 .domain_info = rk3562_pm_domains, 1441 }; 1442 1443 static const struct rockchip_pmu_info rk3568_pmu = { 1444 .pwr_offset = 0xa0, 1445 .status_offset = 0x98, 1446 .req_offset = 0x50, 1447 .idle_offset = 0x68, 1448 .ack_offset = 0x60, 1449 1450 .num_domains = ARRAY_SIZE(rk3568_pm_domains), 1451 .domain_info = rk3568_pm_domains, 1452 }; 1453 1454 static const struct rockchip_pmu_info rk3576_pmu = { 1455 .pwr_offset = 0x210, 1456 .status_offset = 0x230, 1457 .chain_status_offset = 0x248, 1458 .mem_status_offset = 0x250, 1459 .mem_pwr_offset = 0x300, 1460 .req_offset = 0x110, 1461 .idle_offset = 0x128, 1462 .ack_offset = 0x120, 1463 .repair_status_offset = 0x570, 1464 .clk_ungate_offset = 0x140, 1465 1466 .num_domains = ARRAY_SIZE(rk3576_pm_domains), 1467 .domain_info = rk3576_pm_domains, 1468 }; 1469 1470 static const struct rockchip_pmu_info rk3588_pmu = { 1471 .pwr_offset = 0x14c, 1472 .status_offset = 0x180, 1473 .req_offset = 0x10c, 1474 .idle_offset = 0x120, 1475 .ack_offset = 0x118, 1476 .mem_pwr_offset = 0x1a0, 1477 .chain_status_offset = 0x1f0, 1478 .mem_status_offset = 0x1f8, 1479 .repair_status_offset = 0x290, 1480 1481 .num_domains = ARRAY_SIZE(rk3588_pm_domains), 1482 .domain_info = rk3588_pm_domains, 1483 }; 1484 1485 static const struct rockchip_pmu_info rv1126_pmu = { 1486 .pwr_offset = 0x110, 1487 .status_offset = 0x108, 1488 .req_offset = 0xc0, 1489 .idle_offset = 0xd8, 1490 .ack_offset = 0xd0, 1491 1492 .num_domains = ARRAY_SIZE(rv1126_pm_domains), 1493 .domain_info = rv1126_pm_domains, 1494 }; 1495 1496 static const struct of_device_id rockchip_pm_domain_dt_match[] = { 1497 { 1498 .compatible = "rockchip,px30-power-controller", 1499 .data = (void *)&px30_pmu, 1500 }, 1501 { 1502 .compatible = "rockchip,rk3036-power-controller", 1503 .data = (void *)&rk3036_pmu, 1504 }, 1505 { 1506 .compatible = "rockchip,rk3066-power-controller", 1507 .data = (void *)&rk3066_pmu, 1508 }, 1509 { 1510 .compatible = "rockchip,rk3128-power-controller", 1511 .data = (void *)&rk3128_pmu, 1512 }, 1513 { 1514 .compatible = "rockchip,rk3188-power-controller", 1515 .data = (void *)&rk3188_pmu, 1516 }, 1517 { 1518 .compatible = "rockchip,rk3228-power-controller", 1519 .data = (void *)&rk3228_pmu, 1520 }, 1521 { 1522 .compatible = "rockchip,rk3288-power-controller", 1523 .data = (void *)&rk3288_pmu, 1524 }, 1525 { 1526 .compatible = "rockchip,rk3328-power-controller", 1527 .data = (void *)&rk3328_pmu, 1528 }, 1529 { 1530 .compatible = "rockchip,rk3366-power-controller", 1531 .data = (void *)&rk3366_pmu, 1532 }, 1533 { 1534 .compatible = "rockchip,rk3368-power-controller", 1535 .data = (void *)&rk3368_pmu, 1536 }, 1537 { 1538 .compatible = "rockchip,rk3399-power-controller", 1539 .data = (void *)&rk3399_pmu, 1540 }, 1541 { 1542 .compatible = "rockchip,rk3562-power-controller", 1543 .data = (void *)&rk3562_pmu, 1544 }, 1545 { 1546 .compatible = "rockchip,rk3568-power-controller", 1547 .data = (void *)&rk3568_pmu, 1548 }, 1549 { 1550 .compatible = "rockchip,rk3576-power-controller", 1551 .data = (void *)&rk3576_pmu, 1552 }, 1553 { 1554 .compatible = "rockchip,rk3588-power-controller", 1555 .data = (void *)&rk3588_pmu, 1556 }, 1557 { 1558 .compatible = "rockchip,rv1126-power-controller", 1559 .data = (void *)&rv1126_pmu, 1560 }, 1561 { /* sentinel */ }, 1562 }; 1563 1564 static struct platform_driver rockchip_pm_domain_driver = { 1565 .probe = rockchip_pm_domain_probe, 1566 .driver = { 1567 .name = "rockchip-pm-domain", 1568 .of_match_table = rockchip_pm_domain_dt_match, 1569 /* 1570 * We can't forcibly eject devices from the power 1571 * domain, so we can't really remove power domains 1572 * once they were added. 1573 */ 1574 .suppress_bind_attrs = true, 1575 }, 1576 }; 1577 1578 static int __init rockchip_pm_domain_drv_register(void) 1579 { 1580 return platform_driver_register(&rockchip_pm_domain_driver); 1581 } 1582 postcore_initcall(rockchip_pm_domain_drv_register); 1583