1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * AMD Platform Management Framework Driver 4 * 5 * Copyright (c) 2022, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #include <linux/debugfs.h> 12 #include <linux/iopoll.h> 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/platform_device.h> 16 #include <linux/power_supply.h> 17 #include <asm/amd/node.h> 18 #include "pmf.h" 19 20 /* PMF-SMU communication registers */ 21 #define AMD_PMF_REGISTER_MESSAGE 0xA18 22 #define AMD_PMF_REGISTER_RESPONSE 0xA78 23 #define AMD_PMF_REGISTER_ARGUMENT 0xA58 24 25 /* Base address of SMU for mapping physical address to virtual address */ 26 #define AMD_PMF_MAPPING_SIZE 0x01000 27 #define AMD_PMF_BASE_ADDR_OFFSET 0x10000 28 #define AMD_PMF_BASE_ADDR_LO 0x13B102E8 29 #define AMD_PMF_BASE_ADDR_HI 0x13B102EC 30 #define AMD_PMF_BASE_ADDR_LO_MASK GENMASK(15, 0) 31 #define AMD_PMF_BASE_ADDR_HI_MASK GENMASK(31, 20) 32 33 /* SMU Response Codes */ 34 #define AMD_PMF_RESULT_OK 0x01 35 #define AMD_PMF_RESULT_CMD_REJECT_BUSY 0xFC 36 #define AMD_PMF_RESULT_CMD_REJECT_PREREQ 0xFD 37 #define AMD_PMF_RESULT_CMD_UNKNOWN 0xFE 38 #define AMD_PMF_RESULT_FAILED 0xFF 39 40 #define PMF_MSG_DELAY_MIN_US 50 41 #define RESPONSE_REGISTER_LOOP_MAX 20000 42 43 #define DELAY_MIN_US 2000 44 #define DELAY_MAX_US 3000 45 46 /* override Metrics Table sample size time (in ms) */ 47 static int metrics_table_loop_ms = 1000; 48 module_param(metrics_table_loop_ms, int, 0644); 49 MODULE_PARM_DESC(metrics_table_loop_ms, "Metrics Table sample size time (default = 1000ms)"); 50 51 /* Force load on supported older platforms */ 52 static bool force_load; 53 module_param(force_load, bool, 0444); 54 MODULE_PARM_DESC(force_load, "Force load this driver on supported older platforms (experimental)"); 55 56 static int amd_pmf_pwr_src_notify_call(struct notifier_block *nb, unsigned long event, void *data) 57 { 58 struct amd_pmf_dev *pmf = container_of(nb, struct amd_pmf_dev, pwr_src_notifier); 59 60 if (event != PSY_EVENT_PROP_CHANGED) 61 return NOTIFY_OK; 62 63 if (is_apmf_func_supported(pmf, APMF_FUNC_AUTO_MODE) || 64 is_apmf_func_supported(pmf, APMF_FUNC_DYN_SLIDER_DC) || 65 is_apmf_func_supported(pmf, APMF_FUNC_DYN_SLIDER_AC)) { 66 if ((pmf->amt_enabled || pmf->cnqf_enabled) && is_pprof_balanced(pmf)) 67 return NOTIFY_DONE; 68 } 69 70 if (is_apmf_func_supported(pmf, APMF_FUNC_STATIC_SLIDER_GRANULAR)) 71 amd_pmf_set_sps_power_limits(pmf); 72 73 if (is_apmf_func_supported(pmf, APMF_FUNC_OS_POWER_SLIDER_UPDATE)) 74 amd_pmf_power_slider_update_event(pmf); 75 76 return NOTIFY_OK; 77 } 78 79 static int current_power_limits_show(struct seq_file *seq, void *unused) 80 { 81 struct amd_pmf_dev *dev = seq->private; 82 struct amd_pmf_static_slider_granular table; 83 int mode, src = 0; 84 85 mode = amd_pmf_get_pprof_modes(dev); 86 if (mode < 0) 87 return mode; 88 89 src = amd_pmf_get_power_source(); 90 amd_pmf_update_slider(dev, SLIDER_OP_GET, mode, &table); 91 seq_printf(seq, "spl:%u fppt:%u sppt:%u sppt_apu_only:%u stt_min:%u stt[APU]:%u stt[HS2]: %u\n", 92 table.prop[src][mode].spl, 93 table.prop[src][mode].fppt, 94 table.prop[src][mode].sppt, 95 table.prop[src][mode].sppt_apu_only, 96 table.prop[src][mode].stt_min, 97 table.prop[src][mode].stt_skin_temp[STT_TEMP_APU], 98 table.prop[src][mode].stt_skin_temp[STT_TEMP_HS2]); 99 return 0; 100 } 101 DEFINE_SHOW_ATTRIBUTE(current_power_limits); 102 103 static void amd_pmf_dbgfs_unregister(struct amd_pmf_dev *dev) 104 { 105 debugfs_remove_recursive(dev->dbgfs_dir); 106 } 107 108 static void amd_pmf_dbgfs_register(struct amd_pmf_dev *dev) 109 { 110 dev->dbgfs_dir = debugfs_create_dir("amd_pmf", NULL); 111 if (dev->pmf_if_version == PMF_IF_V1) 112 debugfs_create_file("current_power_limits", 0644, dev->dbgfs_dir, dev, 113 ¤t_power_limits_fops); 114 } 115 116 int amd_pmf_get_power_source(void) 117 { 118 if (power_supply_is_system_supplied() > 0) 119 return POWER_SOURCE_AC; 120 else 121 return POWER_SOURCE_DC; 122 } 123 124 static void amd_pmf_get_metrics(struct work_struct *work) 125 { 126 struct amd_pmf_dev *dev = container_of(work, struct amd_pmf_dev, work_buffer.work); 127 ktime_t time_elapsed_ms; 128 int socket_power; 129 130 guard(mutex)(&dev->update_mutex); 131 132 /* Transfer table contents */ 133 memset(dev->buf, 0, sizeof(dev->m_table)); 134 amd_pmf_send_cmd(dev, SET_TRANSFER_TABLE, 0, 7, NULL); 135 memcpy(&dev->m_table, dev->buf, sizeof(dev->m_table)); 136 137 time_elapsed_ms = ktime_to_ms(ktime_get()) - dev->start_time; 138 /* Calculate the avg SoC power consumption */ 139 socket_power = dev->m_table.apu_power + dev->m_table.dgpu_power; 140 141 if (dev->amt_enabled) { 142 /* Apply the Auto Mode transition */ 143 amd_pmf_trans_automode(dev, socket_power, time_elapsed_ms); 144 } 145 146 if (dev->cnqf_enabled) { 147 /* Apply the CnQF transition */ 148 amd_pmf_trans_cnqf(dev, socket_power, time_elapsed_ms); 149 } 150 151 dev->start_time = ktime_to_ms(ktime_get()); 152 schedule_delayed_work(&dev->work_buffer, msecs_to_jiffies(metrics_table_loop_ms)); 153 } 154 155 static inline u32 amd_pmf_reg_read(struct amd_pmf_dev *dev, int reg_offset) 156 { 157 return ioread32(dev->regbase + reg_offset); 158 } 159 160 static inline void amd_pmf_reg_write(struct amd_pmf_dev *dev, int reg_offset, u32 val) 161 { 162 iowrite32(val, dev->regbase + reg_offset); 163 } 164 165 static void __maybe_unused amd_pmf_dump_registers(struct amd_pmf_dev *dev) 166 { 167 u32 value; 168 169 value = amd_pmf_reg_read(dev, AMD_PMF_REGISTER_RESPONSE); 170 dev_dbg(dev->dev, "AMD_PMF_REGISTER_RESPONSE:%x\n", value); 171 172 value = amd_pmf_reg_read(dev, AMD_PMF_REGISTER_ARGUMENT); 173 dev_dbg(dev->dev, "AMD_PMF_REGISTER_ARGUMENT:%d\n", value); 174 175 value = amd_pmf_reg_read(dev, AMD_PMF_REGISTER_MESSAGE); 176 dev_dbg(dev->dev, "AMD_PMF_REGISTER_MESSAGE:%x\n", value); 177 } 178 179 /** 180 * fixp_q88_fromint: Convert integer to Q8.8 181 * @val: input value 182 * 183 * Converts an integer into binary fixed point format where 8 bits 184 * are used for integer and 8 bits are used for the decimal. 185 * 186 * Return: unsigned integer converted to Q8.8 format 187 */ 188 u32 fixp_q88_fromint(u32 val) 189 { 190 return val << 8; 191 } 192 193 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data) 194 { 195 int rc; 196 u32 val; 197 198 guard(mutex)(&dev->lock); 199 200 /* Wait until we get a valid response */ 201 rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMF_REGISTER_RESPONSE, 202 val, val != 0, PMF_MSG_DELAY_MIN_US, 203 PMF_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 204 if (rc) { 205 dev_err(dev->dev, "failed to talk to SMU\n"); 206 return rc; 207 } 208 209 /* Write zero to response register */ 210 amd_pmf_reg_write(dev, AMD_PMF_REGISTER_RESPONSE, 0); 211 212 /* Write argument into argument register */ 213 amd_pmf_reg_write(dev, AMD_PMF_REGISTER_ARGUMENT, arg); 214 215 /* Write message ID to message ID register */ 216 amd_pmf_reg_write(dev, AMD_PMF_REGISTER_MESSAGE, message); 217 218 /* Wait until we get a valid response */ 219 rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMF_REGISTER_RESPONSE, 220 val, val != 0, PMF_MSG_DELAY_MIN_US, 221 PMF_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 222 if (rc) { 223 dev_err(dev->dev, "SMU response timed out\n"); 224 return rc; 225 } 226 227 switch (val) { 228 case AMD_PMF_RESULT_OK: 229 if (get) { 230 /* PMFW may take longer time to return back the data */ 231 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US); 232 *data = amd_pmf_reg_read(dev, AMD_PMF_REGISTER_ARGUMENT); 233 } 234 break; 235 case AMD_PMF_RESULT_CMD_REJECT_BUSY: 236 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val); 237 rc = -EBUSY; 238 break; 239 case AMD_PMF_RESULT_CMD_UNKNOWN: 240 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val); 241 rc = -EINVAL; 242 break; 243 case AMD_PMF_RESULT_CMD_REJECT_PREREQ: 244 case AMD_PMF_RESULT_FAILED: 245 default: 246 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val); 247 rc = -EIO; 248 break; 249 } 250 251 amd_pmf_dump_registers(dev); 252 return rc; 253 } 254 255 static const struct pci_device_id pmf_pci_ids[] = { 256 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RMB) }, 257 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) }, 258 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) }, 259 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) }, 260 { } 261 }; 262 263 int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer) 264 { 265 u64 phys_addr; 266 u32 hi, low; 267 268 /* Get Metrics Table Address */ 269 if (alloc_buffer) { 270 switch (dev->cpu_id) { 271 case AMD_CPU_ID_PS: 272 case AMD_CPU_ID_RMB: 273 dev->mtable_size = sizeof(dev->m_table); 274 break; 275 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: 276 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: 277 dev->mtable_size = sizeof(dev->m_table_v2); 278 break; 279 default: 280 dev_err(dev->dev, "Invalid CPU id: 0x%x", dev->cpu_id); 281 } 282 283 dev->buf = devm_kzalloc(dev->dev, dev->mtable_size, GFP_KERNEL); 284 if (!dev->buf) 285 return -ENOMEM; 286 } 287 288 phys_addr = virt_to_phys(dev->buf); 289 hi = phys_addr >> 32; 290 low = phys_addr & GENMASK(31, 0); 291 292 amd_pmf_send_cmd(dev, SET_DRAM_ADDR_HIGH, 0, hi, NULL); 293 amd_pmf_send_cmd(dev, SET_DRAM_ADDR_LOW, 0, low, NULL); 294 295 return 0; 296 } 297 298 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev) 299 { 300 int ret; 301 302 INIT_DELAYED_WORK(&dev->work_buffer, amd_pmf_get_metrics); 303 304 ret = amd_pmf_set_dram_addr(dev, true); 305 if (ret) 306 return ret; 307 308 /* 309 * Start collecting the metrics data after a small delay 310 * or else, we might end up getting stale values from PMFW. 311 */ 312 schedule_delayed_work(&dev->work_buffer, msecs_to_jiffies(metrics_table_loop_ms * 3)); 313 314 return 0; 315 } 316 317 static int amd_pmf_suspend_handler(struct device *dev) 318 { 319 struct amd_pmf_dev *pdev = dev_get_drvdata(dev); 320 321 if (pdev->smart_pc_enabled) 322 cancel_delayed_work_sync(&pdev->pb_work); 323 324 if (is_apmf_func_supported(pdev, APMF_FUNC_SBIOS_HEARTBEAT_V2)) 325 amd_pmf_notify_sbios_heartbeat_event_v2(pdev, ON_SUSPEND); 326 327 return 0; 328 } 329 330 static int amd_pmf_resume_handler(struct device *dev) 331 { 332 struct amd_pmf_dev *pdev = dev_get_drvdata(dev); 333 int ret; 334 335 if (pdev->buf) { 336 ret = amd_pmf_set_dram_addr(pdev, false); 337 if (ret) 338 return ret; 339 } 340 341 if (is_apmf_func_supported(pdev, APMF_FUNC_SBIOS_HEARTBEAT_V2)) 342 amd_pmf_notify_sbios_heartbeat_event_v2(pdev, ON_RESUME); 343 344 if (pdev->smart_pc_enabled) 345 schedule_delayed_work(&pdev->pb_work, msecs_to_jiffies(2000)); 346 347 return 0; 348 } 349 350 static DEFINE_SIMPLE_DEV_PM_OPS(amd_pmf_pm, amd_pmf_suspend_handler, amd_pmf_resume_handler); 351 352 static void amd_pmf_init_features(struct amd_pmf_dev *dev) 353 { 354 int ret; 355 356 /* Enable Static Slider */ 357 if (is_apmf_func_supported(dev, APMF_FUNC_STATIC_SLIDER_GRANULAR) || 358 is_apmf_func_supported(dev, APMF_FUNC_OS_POWER_SLIDER_UPDATE)) { 359 amd_pmf_init_sps(dev); 360 dev->pwr_src_notifier.notifier_call = amd_pmf_pwr_src_notify_call; 361 power_supply_reg_notifier(&dev->pwr_src_notifier); 362 dev_dbg(dev->dev, "SPS enabled and Platform Profiles registered\n"); 363 } 364 365 amd_pmf_init_smart_pc(dev); 366 if (dev->smart_pc_enabled) { 367 dev_dbg(dev->dev, "Smart PC Solution Enabled\n"); 368 /* If Smart PC is enabled, no need to check for other features */ 369 return; 370 } 371 372 if (is_apmf_func_supported(dev, APMF_FUNC_AUTO_MODE)) { 373 amd_pmf_init_auto_mode(dev); 374 dev_dbg(dev->dev, "Auto Mode Init done\n"); 375 } else if (is_apmf_func_supported(dev, APMF_FUNC_DYN_SLIDER_AC) || 376 is_apmf_func_supported(dev, APMF_FUNC_DYN_SLIDER_DC)) { 377 ret = amd_pmf_init_cnqf(dev); 378 if (ret) 379 dev_warn(dev->dev, "CnQF Init failed\n"); 380 } 381 } 382 383 static void amd_pmf_deinit_features(struct amd_pmf_dev *dev) 384 { 385 if (is_apmf_func_supported(dev, APMF_FUNC_STATIC_SLIDER_GRANULAR) || 386 is_apmf_func_supported(dev, APMF_FUNC_OS_POWER_SLIDER_UPDATE)) { 387 power_supply_unreg_notifier(&dev->pwr_src_notifier); 388 } 389 390 if (dev->smart_pc_enabled) { 391 amd_pmf_deinit_smart_pc(dev); 392 } else if (is_apmf_func_supported(dev, APMF_FUNC_AUTO_MODE)) { 393 amd_pmf_deinit_auto_mode(dev); 394 } else if (is_apmf_func_supported(dev, APMF_FUNC_DYN_SLIDER_AC) || 395 is_apmf_func_supported(dev, APMF_FUNC_DYN_SLIDER_DC)) { 396 amd_pmf_deinit_cnqf(dev); 397 } 398 } 399 400 static const struct acpi_device_id amd_pmf_acpi_ids[] = { 401 {"AMDI0100", 0x100}, 402 {"AMDI0102", 0}, 403 {"AMDI0103", 0}, 404 {"AMDI0105", 0}, 405 {"AMDI0107", 0}, 406 {"AMDI0108", 0}, 407 { } 408 }; 409 MODULE_DEVICE_TABLE(acpi, amd_pmf_acpi_ids); 410 411 static int amd_pmf_probe(struct platform_device *pdev) 412 { 413 const struct acpi_device_id *id; 414 struct amd_pmf_dev *dev; 415 struct pci_dev *rdev; 416 u32 base_addr_lo; 417 u32 base_addr_hi; 418 u64 base_addr; 419 u32 val; 420 int err; 421 422 id = acpi_match_device(amd_pmf_acpi_ids, &pdev->dev); 423 if (!id) 424 return -ENODEV; 425 426 if (id->driver_data == 0x100 && !force_load) 427 return -ENODEV; 428 429 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 430 if (!dev) 431 return -ENOMEM; 432 433 dev->dev = &pdev->dev; 434 435 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); 436 if (!rdev || !pci_match_id(pmf_pci_ids, rdev)) { 437 pci_dev_put(rdev); 438 return -ENODEV; 439 } 440 441 dev->cpu_id = rdev->device; 442 443 err = amd_smn_read(0, AMD_PMF_BASE_ADDR_LO, &val); 444 if (err) { 445 pci_dev_put(rdev); 446 return dev_err_probe(dev->dev, pcibios_err_to_errno(err), 447 "error in reading from 0x%x\n", AMD_PMF_BASE_ADDR_LO); 448 } 449 450 base_addr_lo = val & AMD_PMF_BASE_ADDR_HI_MASK; 451 452 err = amd_smn_read(0, AMD_PMF_BASE_ADDR_HI, &val); 453 if (err) { 454 pci_dev_put(rdev); 455 return dev_err_probe(dev->dev, pcibios_err_to_errno(err), 456 "error in reading from 0x%x\n", AMD_PMF_BASE_ADDR_HI); 457 } 458 459 base_addr_hi = val & AMD_PMF_BASE_ADDR_LO_MASK; 460 pci_dev_put(rdev); 461 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo); 462 463 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMF_BASE_ADDR_OFFSET, 464 AMD_PMF_MAPPING_SIZE); 465 if (!dev->regbase) 466 return -ENOMEM; 467 468 mutex_init(&dev->lock); 469 mutex_init(&dev->update_mutex); 470 mutex_init(&dev->cb_mutex); 471 472 apmf_acpi_init(dev); 473 platform_set_drvdata(pdev, dev); 474 amd_pmf_dbgfs_register(dev); 475 amd_pmf_init_features(dev); 476 apmf_install_handler(dev); 477 if (is_apmf_func_supported(dev, APMF_FUNC_SBIOS_HEARTBEAT_V2)) 478 amd_pmf_notify_sbios_heartbeat_event_v2(dev, ON_LOAD); 479 480 dev_info(dev->dev, "registered PMF device successfully\n"); 481 482 return 0; 483 } 484 485 static void amd_pmf_remove(struct platform_device *pdev) 486 { 487 struct amd_pmf_dev *dev = platform_get_drvdata(pdev); 488 489 amd_pmf_deinit_features(dev); 490 if (is_apmf_func_supported(dev, APMF_FUNC_SBIOS_HEARTBEAT_V2)) 491 amd_pmf_notify_sbios_heartbeat_event_v2(dev, ON_UNLOAD); 492 apmf_acpi_deinit(dev); 493 amd_pmf_dbgfs_unregister(dev); 494 mutex_destroy(&dev->lock); 495 mutex_destroy(&dev->update_mutex); 496 mutex_destroy(&dev->cb_mutex); 497 } 498 499 static const struct attribute_group *amd_pmf_driver_groups[] = { 500 &cnqf_feature_attribute_group, 501 NULL, 502 }; 503 504 static struct platform_driver amd_pmf_driver = { 505 .driver = { 506 .name = "amd-pmf", 507 .acpi_match_table = amd_pmf_acpi_ids, 508 .dev_groups = amd_pmf_driver_groups, 509 .pm = pm_sleep_ptr(&amd_pmf_pm), 510 }, 511 .probe = amd_pmf_probe, 512 .remove = amd_pmf_remove, 513 }; 514 module_platform_driver(amd_pmf_driver); 515 516 MODULE_LICENSE("GPL"); 517 MODULE_DESCRIPTION("AMD Platform Management Framework Driver"); 518 MODULE_SOFTDEP("pre: amdtee"); 519