1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2024 Yixun Lan <dlan@gentoo.org> */ 3 4 #include <linux/bits.h> 5 #include <linux/cleanup.h> 6 #include <linux/io.h> 7 #include <linux/of.h> 8 #include <linux/platform_device.h> 9 #include <linux/seq_file.h> 10 #include <linux/spinlock.h> 11 #include <linux/module.h> 12 #include <linux/mutex.h> 13 14 #include <linux/pinctrl/pinconf-generic.h> 15 #include <linux/pinctrl/pinconf.h> 16 #include <linux/pinctrl/pinctrl.h> 17 #include <linux/pinctrl/pinmux.h> 18 19 #include "../core.h" 20 #include "../pinctrl-utils.h" 21 #include "../pinconf.h" 22 #include "../pinmux.h" 23 #include "pinctrl-k1.h" 24 25 /* 26 * +---------+----------+-----------+--------+--------+----------+--------+ 27 * | pull | drive | schmitter | slew | edge | strong | mux | 28 * | up/down | strength | trigger | rate | detect | pull | mode | 29 * +---------+----------+-----------+--------+--------+----------+--------+ 30 * 3 bits 3 bits 2 bits 1 bit 3 bits 1 bit 3 bits 31 */ 32 33 #define PAD_MUX GENMASK(2, 0) 34 #define PAD_STRONG_PULL BIT(3) 35 #define PAD_EDGE_RISE BIT(4) 36 #define PAD_EDGE_FALL BIT(5) 37 #define PAD_EDGE_CLEAR BIT(6) 38 #define PAD_SLEW_RATE GENMASK(12, 11) 39 #define PAD_SLEW_RATE_EN BIT(7) 40 #define PAD_SCHMITT GENMASK(9, 8) 41 #define PAD_DRIVE GENMASK(12, 10) 42 #define PAD_PULLDOWN BIT(13) 43 #define PAD_PULLUP BIT(14) 44 #define PAD_PULL_EN BIT(15) 45 46 struct spacemit_pin { 47 u16 pin; 48 u16 flags; 49 u8 gpiofunc; 50 }; 51 52 struct spacemit_pinctrl { 53 struct device *dev; 54 struct pinctrl_dev *pctl_dev; 55 const struct spacemit_pinctrl_data *data; 56 struct pinctrl_desc pdesc; 57 58 struct mutex mutex; 59 raw_spinlock_t lock; 60 61 void __iomem *regs; 62 }; 63 64 struct spacemit_pinctrl_data { 65 const struct pinctrl_pin_desc *pins; 66 const struct spacemit_pin *data; 67 u16 npins; 68 }; 69 70 struct spacemit_pin_mux_config { 71 const struct spacemit_pin *pin; 72 u32 config; 73 }; 74 75 struct spacemit_pin_drv_strength { 76 u8 val; 77 u32 mA; 78 }; 79 80 /* map pin id to pinctrl register offset, refer MFPR definition */ 81 static unsigned int spacemit_pin_to_offset(unsigned int pin) 82 { 83 unsigned int offset = 0; 84 85 switch (pin) { 86 case 0 ... 85: 87 offset = pin + 1; 88 break; 89 case 86 ... 92: 90 offset = pin + 37; 91 break; 92 case 93 ... 97: 93 offset = pin + 24; 94 break; 95 case 98: 96 offset = 93; 97 break; 98 case 99: 99 offset = 92; 100 break; 101 case 100: 102 offset = 91; 103 break; 104 case 101: 105 offset = 90; 106 break; 107 case 102: 108 offset = 95; 109 break; 110 case 103: 111 offset = 94; 112 break; 113 case 104 ... 110: 114 offset = pin + 6; 115 break; 116 case 111 ... 127: 117 offset = pin + 20; 118 break; 119 default: 120 break; 121 } 122 123 return offset << 2; 124 } 125 126 static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl, 127 unsigned int pin) 128 { 129 return pctrl->regs + spacemit_pin_to_offset(pin); 130 } 131 132 static u16 spacemit_dt_get_pin(u32 value) 133 { 134 return value >> 16; 135 } 136 137 static u16 spacemit_dt_get_pin_mux(u32 value) 138 { 139 return value & GENMASK(15, 0); 140 } 141 142 static const struct spacemit_pin *spacemit_get_pin(struct spacemit_pinctrl *pctrl, 143 unsigned long pin) 144 { 145 const struct spacemit_pin *pdata = pctrl->data->data; 146 int i; 147 148 for (i = 0; i < pctrl->data->npins; i++) { 149 if (pin == pdata[i].pin) 150 return &pdata[i]; 151 } 152 153 return NULL; 154 } 155 156 static inline enum spacemit_pin_io_type spacemit_to_pin_io_type( 157 const struct spacemit_pin *pin) 158 { 159 return K1_PIN_GET_IO_TYPE(pin->flags); 160 } 161 162 /* External: IO voltage via external source, can be 1.8V or 3.3V */ 163 static const char * const io_type_desc[] = { 164 "None", 165 "Fixed/1V8", 166 "Fixed/3V3", 167 "External", 168 }; 169 170 static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev, 171 struct seq_file *seq, unsigned int pin) 172 { 173 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 174 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); 175 enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin); 176 void __iomem *reg; 177 u32 value; 178 179 seq_printf(seq, "offset: 0x%04x ", spacemit_pin_to_offset(pin)); 180 seq_printf(seq, "type: %s ", io_type_desc[type]); 181 182 reg = spacemit_pin_to_reg(pctrl, pin); 183 value = readl(reg); 184 seq_printf(seq, "mux: %ld reg: 0x%04x", (value & PAD_MUX), value); 185 } 186 187 /* use IO high level output current as the table */ 188 static struct spacemit_pin_drv_strength spacemit_ds_1v8_tbl[4] = { 189 { 0, 11 }, 190 { 2, 21 }, 191 { 4, 32 }, 192 { 6, 42 }, 193 }; 194 195 static struct spacemit_pin_drv_strength spacemit_ds_3v3_tbl[8] = { 196 { 0, 7 }, 197 { 2, 10 }, 198 { 4, 13 }, 199 { 6, 16 }, 200 { 1, 19 }, 201 { 3, 23 }, 202 { 5, 26 }, 203 { 7, 29 }, 204 }; 205 206 static inline u8 spacemit_get_ds_value(struct spacemit_pin_drv_strength *tbl, 207 u32 num, u32 mA) 208 { 209 int i; 210 211 for (i = 0; i < num; i++) 212 if (mA <= tbl[i].mA) 213 return tbl[i].val; 214 215 return tbl[num - 1].val; 216 } 217 218 static inline u32 spacemit_get_ds_mA(struct spacemit_pin_drv_strength *tbl, 219 u32 num, u32 val) 220 { 221 int i; 222 223 for (i = 0; i < num; i++) 224 if (val == tbl[i].val) 225 return tbl[i].mA; 226 227 return 0; 228 } 229 230 static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type, 231 u32 mA) 232 { 233 switch (type) { 234 case IO_TYPE_1V8: 235 return spacemit_get_ds_value(spacemit_ds_1v8_tbl, 236 ARRAY_SIZE(spacemit_ds_1v8_tbl), 237 mA); 238 case IO_TYPE_3V3: 239 return spacemit_get_ds_value(spacemit_ds_3v3_tbl, 240 ARRAY_SIZE(spacemit_ds_3v3_tbl), 241 mA); 242 default: 243 return 0; 244 } 245 } 246 247 static inline u32 spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type, 248 u32 value) 249 { 250 switch (type) { 251 case IO_TYPE_1V8: 252 return spacemit_get_ds_mA(spacemit_ds_1v8_tbl, 253 ARRAY_SIZE(spacemit_ds_1v8_tbl), 254 value & 0x6); 255 case IO_TYPE_3V3: 256 return spacemit_get_ds_mA(spacemit_ds_3v3_tbl, 257 ARRAY_SIZE(spacemit_ds_3v3_tbl), 258 value); 259 default: 260 return 0; 261 } 262 } 263 264 static int spacemit_pctrl_check_power(struct pinctrl_dev *pctldev, 265 struct device_node *dn, 266 struct spacemit_pin_mux_config *pinmuxs, 267 int num_pins, const char *grpname) 268 { 269 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 270 struct device *dev = pctrl->dev; 271 enum spacemit_pin_io_type type; 272 u32 power = 0, i; 273 274 of_property_read_u32(dn, "power-source", &power); 275 276 for (i = 0; i < num_pins; i++) { 277 type = spacemit_to_pin_io_type(pinmuxs[i].pin); 278 279 if (type != IO_TYPE_EXTERNAL) 280 continue; 281 282 switch (power) { 283 case PIN_POWER_STATE_1V8: 284 case PIN_POWER_STATE_3V3: 285 break; 286 default: 287 dev_err(dev, "group %s has unsupported power\n", 288 grpname); 289 return -ENOTSUPP; 290 } 291 } 292 293 return 0; 294 } 295 296 static int spacemit_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 297 struct device_node *np, 298 struct pinctrl_map **maps, 299 unsigned int *num_maps) 300 { 301 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 302 struct device *dev = pctrl->dev; 303 struct device_node *child; 304 struct pinctrl_map *map; 305 const char **grpnames; 306 const char *grpname; 307 int ngroups = 0; 308 int nmaps = 0; 309 int ret; 310 311 for_each_available_child_of_node(np, child) 312 ngroups += 1; 313 314 grpnames = devm_kcalloc(dev, ngroups, sizeof(*grpnames), GFP_KERNEL); 315 if (!grpnames) 316 return -ENOMEM; 317 318 map = kcalloc(ngroups * 2, sizeof(*map), GFP_KERNEL); 319 if (!map) 320 return -ENOMEM; 321 322 ngroups = 0; 323 guard(mutex)(&pctrl->mutex); 324 for_each_available_child_of_node_scoped(np, child) { 325 struct spacemit_pin_mux_config *pinmuxs; 326 unsigned int config, *pins; 327 int i, npins; 328 329 npins = of_property_count_u32_elems(child, "pinmux"); 330 331 if (npins < 1) { 332 dev_err(dev, "invalid pinctrl group %pOFn.%pOFn\n", 333 np, child); 334 return -EINVAL; 335 } 336 337 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", 338 np, child); 339 if (!grpname) 340 return -ENOMEM; 341 342 grpnames[ngroups++] = grpname; 343 344 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); 345 if (!pins) 346 return -ENOMEM; 347 348 pinmuxs = devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL); 349 if (!pinmuxs) 350 return -ENOMEM; 351 352 for (i = 0; i < npins; i++) { 353 ret = of_property_read_u32_index(child, "pinmux", 354 i, &config); 355 356 if (ret) 357 return -EINVAL; 358 359 pins[i] = spacemit_dt_get_pin(config); 360 pinmuxs[i].config = config; 361 pinmuxs[i].pin = spacemit_get_pin(pctrl, pins[i]); 362 363 if (!pinmuxs[i].pin) 364 return dev_err_probe(dev, -ENODEV, "failed to get pin %d\n", pins[i]); 365 } 366 367 ret = spacemit_pctrl_check_power(pctldev, child, pinmuxs, 368 npins, grpname); 369 if (ret < 0) 370 return ret; 371 372 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; 373 map[nmaps].data.mux.function = np->name; 374 map[nmaps].data.mux.group = grpname; 375 nmaps += 1; 376 377 ret = pinctrl_generic_add_group(pctldev, grpname, 378 pins, npins, pinmuxs); 379 if (ret < 0) 380 return dev_err_probe(dev, ret, "failed to add group %s: %d\n", grpname, ret); 381 382 ret = pinconf_generic_parse_dt_config(child, pctldev, 383 &map[nmaps].data.configs.configs, 384 &map[nmaps].data.configs.num_configs); 385 if (ret) 386 return dev_err_probe(dev, ret, "failed to parse pin config of group %s\n", 387 grpname); 388 389 if (map[nmaps].data.configs.num_configs == 0) 390 continue; 391 392 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; 393 map[nmaps].data.configs.group_or_pin = grpname; 394 nmaps += 1; 395 } 396 397 ret = pinmux_generic_add_function(pctldev, np->name, 398 grpnames, ngroups, NULL); 399 if (ret < 0) { 400 pinctrl_utils_free_map(pctldev, map, nmaps); 401 return dev_err_probe(dev, ret, "error adding function %s\n", np->name); 402 } 403 404 *maps = map; 405 *num_maps = nmaps; 406 407 return 0; 408 } 409 410 static const struct pinctrl_ops spacemit_pctrl_ops = { 411 .get_groups_count = pinctrl_generic_get_group_count, 412 .get_group_name = pinctrl_generic_get_group_name, 413 .get_group_pins = pinctrl_generic_get_group_pins, 414 .pin_dbg_show = spacemit_pctrl_dbg_show, 415 .dt_node_to_map = spacemit_pctrl_dt_node_to_map, 416 .dt_free_map = pinctrl_utils_free_map, 417 }; 418 419 static int spacemit_pmx_set_mux(struct pinctrl_dev *pctldev, 420 unsigned int fsel, unsigned int gsel) 421 { 422 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 423 const struct group_desc *group; 424 const struct spacemit_pin_mux_config *configs; 425 unsigned int i, mux; 426 void __iomem *reg; 427 428 group = pinctrl_generic_get_group(pctldev, gsel); 429 if (!group) 430 return -EINVAL; 431 432 configs = group->data; 433 434 for (i = 0; i < group->grp.npins; i++) { 435 const struct spacemit_pin *spin = configs[i].pin; 436 u32 value = configs[i].config; 437 438 reg = spacemit_pin_to_reg(pctrl, spin->pin); 439 mux = spacemit_dt_get_pin_mux(value); 440 441 guard(raw_spinlock_irqsave)(&pctrl->lock); 442 value = readl_relaxed(reg) & ~PAD_MUX; 443 writel_relaxed(mux | value, reg); 444 } 445 446 return 0; 447 } 448 449 static int spacemit_request_gpio(struct pinctrl_dev *pctldev, 450 struct pinctrl_gpio_range *range, 451 unsigned int pin) 452 { 453 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 454 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); 455 void __iomem *reg; 456 457 reg = spacemit_pin_to_reg(pctrl, pin); 458 guard(raw_spinlock_irqsave)(&pctrl->lock); 459 writel_relaxed(spin->gpiofunc, reg); 460 461 return 0; 462 } 463 464 static const struct pinmux_ops spacemit_pmx_ops = { 465 .get_functions_count = pinmux_generic_get_function_count, 466 .get_function_name = pinmux_generic_get_function_name, 467 .get_function_groups = pinmux_generic_get_function_groups, 468 .set_mux = spacemit_pmx_set_mux, 469 .gpio_request_enable = spacemit_request_gpio, 470 .strict = true, 471 }; 472 473 static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, 474 unsigned int pin, unsigned long *config) 475 { 476 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 477 int param = pinconf_to_config_param(*config); 478 u32 value, arg = 0; 479 480 if (!pin) 481 return -EINVAL; 482 483 value = readl(spacemit_pin_to_reg(pctrl, pin)); 484 485 switch (param) { 486 case PIN_CONFIG_SLEW_RATE: 487 if (FIELD_GET(PAD_SLEW_RATE_EN, value)) 488 arg = FIELD_GET(PAD_SLEW_RATE, value) + 2; 489 else 490 arg = 0; 491 break; 492 default: 493 return -EINVAL; 494 } 495 496 *config = pinconf_to_config_packed(param, arg); 497 498 return 0; 499 } 500 501 #define ENABLE_DRV_STRENGTH BIT(1) 502 #define ENABLE_SLEW_RATE BIT(2) 503 static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, 504 unsigned long *configs, 505 unsigned int num_configs, 506 u32 *value) 507 { 508 enum spacemit_pin_io_type type; 509 int i, param; 510 u32 v = 0, voltage = 0, arg, val; 511 u32 flag = 0, drv_strength, slew_rate; 512 513 if (!spin) 514 return -EINVAL; 515 516 for (i = 0; i < num_configs; i++) { 517 param = pinconf_to_config_param(configs[i]); 518 arg = pinconf_to_config_argument(configs[i]); 519 520 switch (param) { 521 case PIN_CONFIG_BIAS_DISABLE: 522 v &= ~(PAD_PULL_EN | PAD_PULLDOWN | PAD_PULLUP); 523 v &= ~PAD_STRONG_PULL; 524 break; 525 case PIN_CONFIG_BIAS_PULL_DOWN: 526 v &= ~(PAD_PULLUP | PAD_STRONG_PULL); 527 v |= (PAD_PULL_EN | PAD_PULLDOWN); 528 break; 529 case PIN_CONFIG_BIAS_PULL_UP: 530 v &= ~PAD_PULLDOWN; 531 v |= (PAD_PULL_EN | PAD_PULLUP); 532 533 if (arg == 1) 534 v |= PAD_STRONG_PULL; 535 break; 536 case PIN_CONFIG_DRIVE_STRENGTH: 537 flag |= ENABLE_DRV_STRENGTH; 538 drv_strength = arg; 539 break; 540 case PIN_CONFIG_INPUT_SCHMITT: 541 v &= ~PAD_SCHMITT; 542 v |= FIELD_PREP(PAD_SCHMITT, arg); 543 break; 544 case PIN_CONFIG_POWER_SOURCE: 545 voltage = arg; 546 break; 547 case PIN_CONFIG_SLEW_RATE: 548 if (arg) { 549 flag |= ENABLE_SLEW_RATE; 550 v |= PAD_SLEW_RATE_EN; 551 slew_rate = arg; 552 } else { 553 v &= ~PAD_SLEW_RATE_EN; 554 } 555 break; 556 default: 557 return -EINVAL; 558 } 559 } 560 561 if (flag & ENABLE_DRV_STRENGTH) { 562 type = spacemit_to_pin_io_type(spin); 563 564 /* fix external io type */ 565 if (type == IO_TYPE_EXTERNAL) { 566 switch (voltage) { 567 case 1800: 568 type = IO_TYPE_1V8; 569 break; 570 case 3300: 571 type = IO_TYPE_3V3; 572 break; 573 default: 574 return -EINVAL; 575 } 576 } 577 578 val = spacemit_get_driver_strength(type, drv_strength); 579 580 v &= ~PAD_DRIVE; 581 v |= FIELD_PREP(PAD_DRIVE, val); 582 } 583 584 if (flag & ENABLE_SLEW_RATE) { 585 /* check, driver strength & slew rate */ 586 if (flag & ENABLE_DRV_STRENGTH) { 587 val = FIELD_GET(PAD_SLEW_RATE, v) + 2; 588 if (slew_rate > 1 && slew_rate != val) { 589 pr_err("slew rate conflict with drive strength\n"); 590 return -EINVAL; 591 } 592 } else { 593 v &= ~PAD_SLEW_RATE; 594 slew_rate = slew_rate > 1 ? (slew_rate - 2) : 0; 595 v |= FIELD_PREP(PAD_SLEW_RATE, slew_rate); 596 } 597 } 598 599 *value = v; 600 601 return 0; 602 } 603 604 static int spacemit_pin_set_config(struct spacemit_pinctrl *pctrl, 605 unsigned int pin, u32 value) 606 { 607 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); 608 void __iomem *reg; 609 unsigned int mux; 610 611 if (!pin) 612 return -EINVAL; 613 614 reg = spacemit_pin_to_reg(pctrl, spin->pin); 615 616 guard(raw_spinlock_irqsave)(&pctrl->lock); 617 mux = readl_relaxed(reg) & PAD_MUX; 618 writel_relaxed(mux | value, reg); 619 620 return 0; 621 } 622 623 static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, 624 unsigned int pin, unsigned long *configs, 625 unsigned int num_configs) 626 { 627 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 628 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); 629 u32 value; 630 631 if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value)) 632 return -EINVAL; 633 634 return spacemit_pin_set_config(pctrl, pin, value); 635 } 636 637 static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, 638 unsigned int gsel, 639 unsigned long *configs, 640 unsigned int num_configs) 641 { 642 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 643 const struct spacemit_pin *spin; 644 const struct group_desc *group; 645 u32 value; 646 int i; 647 648 group = pinctrl_generic_get_group(pctldev, gsel); 649 if (!group) 650 return -EINVAL; 651 652 spin = spacemit_get_pin(pctrl, group->grp.pins[0]); 653 if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value)) 654 return -EINVAL; 655 656 for (i = 0; i < group->grp.npins; i++) 657 spacemit_pin_set_config(pctrl, group->grp.pins[i], value); 658 659 return 0; 660 } 661 662 static void spacemit_pinconf_dbg_pull(struct seq_file *seq, unsigned int value) 663 { 664 u32 normal, strong; 665 666 if (!FIELD_GET(PAD_PULL_EN, value)) { 667 seq_puts(seq, ", bias pull disabled"); 668 return; 669 } 670 671 if (FIELD_GET(PAD_PULLDOWN, value)) 672 seq_puts(seq, ", bias pull down"); 673 674 normal = FIELD_GET(PAD_PULLUP, value); 675 strong = FIELD_GET(PAD_STRONG_PULL, value); 676 677 if (normal && strong) 678 seq_puts(seq, ", bias strong pull up"); 679 else if (normal) 680 seq_puts(seq, ", bias normal pull up"); 681 } 682 683 static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev, 684 struct seq_file *seq, unsigned int pin) 685 { 686 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 687 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); 688 enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin); 689 void __iomem *reg = spacemit_pin_to_reg(pctrl, pin); 690 u32 value, tmp, mA; 691 692 value = readl(reg); 693 spacemit_pinconf_dbg_pull(seq, value); 694 695 seq_printf(seq, ", io type (%s)", io_type_desc[type]); 696 697 tmp = FIELD_GET(PAD_DRIVE, value); 698 if (type == IO_TYPE_1V8 || type == IO_TYPE_3V3) { 699 mA = spacemit_get_drive_strength_mA(type, tmp); 700 seq_printf(seq, ", drive strength (%d mA)", mA); 701 } 702 703 /* drive strength depend on power source, so show all values */ 704 if (type == IO_TYPE_EXTERNAL) 705 seq_printf(seq, ", drive strength (%d or %d mA)", 706 spacemit_get_drive_strength_mA(IO_TYPE_1V8, tmp), 707 spacemit_get_drive_strength_mA(IO_TYPE_3V3, tmp)); 708 709 seq_printf(seq, ", register (0x%04x)\n", value); 710 } 711 712 static const struct pinconf_ops spacemit_pinconf_ops = { 713 .pin_config_get = spacemit_pinconf_get, 714 .pin_config_set = spacemit_pinconf_set, 715 .pin_config_group_set = spacemit_pinconf_group_set, 716 .pin_config_dbg_show = spacemit_pinconf_dbg_show, 717 .is_generic = true, 718 }; 719 720 static int spacemit_pinctrl_probe(struct platform_device *pdev) 721 { 722 struct device *dev = &pdev->dev; 723 struct spacemit_pinctrl *pctrl; 724 const struct spacemit_pinctrl_data *pctrl_data; 725 int ret; 726 727 pctrl_data = device_get_match_data(dev); 728 if (!pctrl_data) 729 return -ENODEV; 730 731 if (pctrl_data->npins == 0) 732 return dev_err_probe(dev, -EINVAL, "invalid pin data\n"); 733 734 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 735 if (!pctrl) 736 return -ENOMEM; 737 738 pctrl->regs = devm_platform_ioremap_resource(pdev, 0); 739 if (IS_ERR(pctrl->regs)) 740 return PTR_ERR(pctrl->regs); 741 742 pctrl->pdesc.name = dev_name(dev); 743 pctrl->pdesc.pins = pctrl_data->pins; 744 pctrl->pdesc.npins = pctrl_data->npins; 745 pctrl->pdesc.pctlops = &spacemit_pctrl_ops; 746 pctrl->pdesc.pmxops = &spacemit_pmx_ops; 747 pctrl->pdesc.confops = &spacemit_pinconf_ops; 748 pctrl->pdesc.owner = THIS_MODULE; 749 750 pctrl->data = pctrl_data; 751 pctrl->dev = dev; 752 raw_spin_lock_init(&pctrl->lock); 753 754 ret = devm_mutex_init(dev, &pctrl->mutex); 755 if (ret) 756 return ret; 757 758 platform_set_drvdata(pdev, pctrl); 759 760 ret = devm_pinctrl_register_and_init(dev, &pctrl->pdesc, 761 pctrl, &pctrl->pctl_dev); 762 if (ret) 763 return dev_err_probe(dev, ret, 764 "fail to register pinctrl driver\n"); 765 766 return pinctrl_enable(pctrl->pctl_dev); 767 } 768 769 static const struct pinctrl_pin_desc k1_pin_desc[] = { 770 PINCTRL_PIN(0, "GPIO_00"), 771 PINCTRL_PIN(1, "GPIO_01"), 772 PINCTRL_PIN(2, "GPIO_02"), 773 PINCTRL_PIN(3, "GPIO_03"), 774 PINCTRL_PIN(4, "GPIO_04"), 775 PINCTRL_PIN(5, "GPIO_05"), 776 PINCTRL_PIN(6, "GPIO_06"), 777 PINCTRL_PIN(7, "GPIO_07"), 778 PINCTRL_PIN(8, "GPIO_08"), 779 PINCTRL_PIN(9, "GPIO_09"), 780 PINCTRL_PIN(10, "GPIO_10"), 781 PINCTRL_PIN(11, "GPIO_11"), 782 PINCTRL_PIN(12, "GPIO_12"), 783 PINCTRL_PIN(13, "GPIO_13"), 784 PINCTRL_PIN(14, "GPIO_14"), 785 PINCTRL_PIN(15, "GPIO_15"), 786 PINCTRL_PIN(16, "GPIO_16"), 787 PINCTRL_PIN(17, "GPIO_17"), 788 PINCTRL_PIN(18, "GPIO_18"), 789 PINCTRL_PIN(19, "GPIO_19"), 790 PINCTRL_PIN(20, "GPIO_20"), 791 PINCTRL_PIN(21, "GPIO_21"), 792 PINCTRL_PIN(22, "GPIO_22"), 793 PINCTRL_PIN(23, "GPIO_23"), 794 PINCTRL_PIN(24, "GPIO_24"), 795 PINCTRL_PIN(25, "GPIO_25"), 796 PINCTRL_PIN(26, "GPIO_26"), 797 PINCTRL_PIN(27, "GPIO_27"), 798 PINCTRL_PIN(28, "GPIO_28"), 799 PINCTRL_PIN(29, "GPIO_29"), 800 PINCTRL_PIN(30, "GPIO_30"), 801 PINCTRL_PIN(31, "GPIO_31"), 802 PINCTRL_PIN(32, "GPIO_32"), 803 PINCTRL_PIN(33, "GPIO_33"), 804 PINCTRL_PIN(34, "GPIO_34"), 805 PINCTRL_PIN(35, "GPIO_35"), 806 PINCTRL_PIN(36, "GPIO_36"), 807 PINCTRL_PIN(37, "GPIO_37"), 808 PINCTRL_PIN(38, "GPIO_38"), 809 PINCTRL_PIN(39, "GPIO_39"), 810 PINCTRL_PIN(40, "GPIO_40"), 811 PINCTRL_PIN(41, "GPIO_41"), 812 PINCTRL_PIN(42, "GPIO_42"), 813 PINCTRL_PIN(43, "GPIO_43"), 814 PINCTRL_PIN(44, "GPIO_44"), 815 PINCTRL_PIN(45, "GPIO_45"), 816 PINCTRL_PIN(46, "GPIO_46"), 817 PINCTRL_PIN(47, "GPIO_47"), 818 PINCTRL_PIN(48, "GPIO_48"), 819 PINCTRL_PIN(49, "GPIO_49"), 820 PINCTRL_PIN(50, "GPIO_50"), 821 PINCTRL_PIN(51, "GPIO_51"), 822 PINCTRL_PIN(52, "GPIO_52"), 823 PINCTRL_PIN(53, "GPIO_53"), 824 PINCTRL_PIN(54, "GPIO_54"), 825 PINCTRL_PIN(55, "GPIO_55"), 826 PINCTRL_PIN(56, "GPIO_56"), 827 PINCTRL_PIN(57, "GPIO_57"), 828 PINCTRL_PIN(58, "GPIO_58"), 829 PINCTRL_PIN(59, "GPIO_59"), 830 PINCTRL_PIN(60, "GPIO_60"), 831 PINCTRL_PIN(61, "GPIO_61"), 832 PINCTRL_PIN(62, "GPIO_62"), 833 PINCTRL_PIN(63, "GPIO_63"), 834 PINCTRL_PIN(64, "GPIO_64"), 835 PINCTRL_PIN(65, "GPIO_65"), 836 PINCTRL_PIN(66, "GPIO_66"), 837 PINCTRL_PIN(67, "GPIO_67"), 838 PINCTRL_PIN(68, "GPIO_68"), 839 PINCTRL_PIN(69, "GPIO_69"), 840 PINCTRL_PIN(70, "GPIO_70/PRI_DTI"), 841 PINCTRL_PIN(71, "GPIO_71/PRI_TMS"), 842 PINCTRL_PIN(72, "GPIO_72/PRI_TCK"), 843 PINCTRL_PIN(73, "GPIO_73/PRI_TDO"), 844 PINCTRL_PIN(74, "GPIO_74"), 845 PINCTRL_PIN(75, "GPIO_75"), 846 PINCTRL_PIN(76, "GPIO_76"), 847 PINCTRL_PIN(77, "GPIO_77"), 848 PINCTRL_PIN(78, "GPIO_78"), 849 PINCTRL_PIN(79, "GPIO_79"), 850 PINCTRL_PIN(80, "GPIO_80"), 851 PINCTRL_PIN(81, "GPIO_81"), 852 PINCTRL_PIN(82, "GPIO_82"), 853 PINCTRL_PIN(83, "GPIO_83"), 854 PINCTRL_PIN(84, "GPIO_84"), 855 PINCTRL_PIN(85, "GPIO_85"), 856 PINCTRL_PIN(86, "GPIO_86"), 857 PINCTRL_PIN(87, "GPIO_87"), 858 PINCTRL_PIN(88, "GPIO_88"), 859 PINCTRL_PIN(89, "GPIO_89"), 860 PINCTRL_PIN(90, "GPIO_90"), 861 PINCTRL_PIN(91, "GPIO_91"), 862 PINCTRL_PIN(92, "GPIO_92"), 863 PINCTRL_PIN(93, "GPIO_93/PWR_SCL"), 864 PINCTRL_PIN(94, "GPIO_94/PWR_SDA"), 865 PINCTRL_PIN(95, "GPIO_95/VCX0_EN"), 866 PINCTRL_PIN(96, "GPIO_96/DVL0"), 867 PINCTRL_PIN(97, "GPIO_97/DVL1"), 868 PINCTRL_PIN(98, "GPIO_98/QSPI_DAT3"), 869 PINCTRL_PIN(99, "GPIO_99/QSPI_DAT2"), 870 PINCTRL_PIN(100, "GPIO_100/QSPI_DAT1"), 871 PINCTRL_PIN(101, "GPIO_101/QSPI_DAT0"), 872 PINCTRL_PIN(102, "GPIO_102/QSPI_CLK"), 873 PINCTRL_PIN(103, "GPIO_103/QSPI_CS1"), 874 PINCTRL_PIN(104, "GPIO_104/MMC1_DAT3"), 875 PINCTRL_PIN(105, "GPIO_105/MMC1_DAT2"), 876 PINCTRL_PIN(106, "GPIO_106/MMC1_DAT1"), 877 PINCTRL_PIN(107, "GPIO_107/MMC1_DAT0"), 878 PINCTRL_PIN(108, "GPIO_108/MMC1_CMD"), 879 PINCTRL_PIN(109, "GPIO_109/MMC1_CLK"), 880 PINCTRL_PIN(110, "GPIO_110"), 881 PINCTRL_PIN(111, "GPIO_111"), 882 PINCTRL_PIN(112, "GPIO_112"), 883 PINCTRL_PIN(113, "GPIO_113"), 884 PINCTRL_PIN(114, "GPIO_114"), 885 PINCTRL_PIN(115, "GPIO_115"), 886 PINCTRL_PIN(116, "GPIO_116"), 887 PINCTRL_PIN(117, "GPIO_117"), 888 PINCTRL_PIN(118, "GPIO_118"), 889 PINCTRL_PIN(119, "GPIO_119"), 890 PINCTRL_PIN(120, "GPIO_120"), 891 PINCTRL_PIN(121, "GPIO_121"), 892 PINCTRL_PIN(122, "GPIO_122"), 893 PINCTRL_PIN(123, "GPIO_123"), 894 PINCTRL_PIN(124, "GPIO_124"), 895 PINCTRL_PIN(125, "GPIO_125"), 896 PINCTRL_PIN(126, "GPIO_126"), 897 PINCTRL_PIN(127, "GPIO_127"), 898 }; 899 900 static const struct spacemit_pin k1_pin_data[ARRAY_SIZE(k1_pin_desc)] = { 901 K1_FUNC_PIN(0, 0, IO_TYPE_1V8), 902 K1_FUNC_PIN(1, 0, IO_TYPE_1V8), 903 K1_FUNC_PIN(2, 0, IO_TYPE_1V8), 904 K1_FUNC_PIN(3, 0, IO_TYPE_1V8), 905 K1_FUNC_PIN(4, 0, IO_TYPE_1V8), 906 K1_FUNC_PIN(5, 0, IO_TYPE_1V8), 907 K1_FUNC_PIN(6, 0, IO_TYPE_1V8), 908 K1_FUNC_PIN(7, 0, IO_TYPE_1V8), 909 K1_FUNC_PIN(8, 0, IO_TYPE_1V8), 910 K1_FUNC_PIN(9, 0, IO_TYPE_1V8), 911 K1_FUNC_PIN(10, 0, IO_TYPE_1V8), 912 K1_FUNC_PIN(11, 0, IO_TYPE_1V8), 913 K1_FUNC_PIN(12, 0, IO_TYPE_1V8), 914 K1_FUNC_PIN(13, 0, IO_TYPE_1V8), 915 K1_FUNC_PIN(14, 0, IO_TYPE_1V8), 916 K1_FUNC_PIN(15, 0, IO_TYPE_1V8), 917 K1_FUNC_PIN(16, 0, IO_TYPE_1V8), 918 K1_FUNC_PIN(17, 0, IO_TYPE_1V8), 919 K1_FUNC_PIN(18, 0, IO_TYPE_1V8), 920 K1_FUNC_PIN(19, 0, IO_TYPE_1V8), 921 K1_FUNC_PIN(20, 0, IO_TYPE_1V8), 922 K1_FUNC_PIN(21, 0, IO_TYPE_1V8), 923 K1_FUNC_PIN(22, 0, IO_TYPE_1V8), 924 K1_FUNC_PIN(23, 0, IO_TYPE_1V8), 925 K1_FUNC_PIN(24, 0, IO_TYPE_1V8), 926 K1_FUNC_PIN(25, 0, IO_TYPE_1V8), 927 K1_FUNC_PIN(26, 0, IO_TYPE_1V8), 928 K1_FUNC_PIN(27, 0, IO_TYPE_1V8), 929 K1_FUNC_PIN(28, 0, IO_TYPE_1V8), 930 K1_FUNC_PIN(29, 0, IO_TYPE_1V8), 931 K1_FUNC_PIN(30, 0, IO_TYPE_1V8), 932 K1_FUNC_PIN(31, 0, IO_TYPE_1V8), 933 K1_FUNC_PIN(32, 0, IO_TYPE_1V8), 934 K1_FUNC_PIN(33, 0, IO_TYPE_1V8), 935 K1_FUNC_PIN(34, 0, IO_TYPE_1V8), 936 K1_FUNC_PIN(35, 0, IO_TYPE_1V8), 937 K1_FUNC_PIN(36, 0, IO_TYPE_1V8), 938 K1_FUNC_PIN(37, 0, IO_TYPE_1V8), 939 K1_FUNC_PIN(38, 0, IO_TYPE_1V8), 940 K1_FUNC_PIN(39, 0, IO_TYPE_1V8), 941 K1_FUNC_PIN(40, 0, IO_TYPE_1V8), 942 K1_FUNC_PIN(41, 0, IO_TYPE_1V8), 943 K1_FUNC_PIN(42, 0, IO_TYPE_1V8), 944 K1_FUNC_PIN(43, 0, IO_TYPE_1V8), 945 K1_FUNC_PIN(44, 0, IO_TYPE_1V8), 946 K1_FUNC_PIN(45, 0, IO_TYPE_1V8), 947 K1_FUNC_PIN(46, 0, IO_TYPE_1V8), 948 K1_FUNC_PIN(47, 0, IO_TYPE_EXTERNAL), 949 K1_FUNC_PIN(48, 0, IO_TYPE_EXTERNAL), 950 K1_FUNC_PIN(49, 0, IO_TYPE_EXTERNAL), 951 K1_FUNC_PIN(50, 0, IO_TYPE_EXTERNAL), 952 K1_FUNC_PIN(51, 0, IO_TYPE_EXTERNAL), 953 K1_FUNC_PIN(52, 0, IO_TYPE_EXTERNAL), 954 K1_FUNC_PIN(53, 0, IO_TYPE_1V8), 955 K1_FUNC_PIN(54, 0, IO_TYPE_1V8), 956 K1_FUNC_PIN(55, 0, IO_TYPE_1V8), 957 K1_FUNC_PIN(56, 0, IO_TYPE_1V8), 958 K1_FUNC_PIN(57, 0, IO_TYPE_1V8), 959 K1_FUNC_PIN(58, 0, IO_TYPE_1V8), 960 K1_FUNC_PIN(59, 0, IO_TYPE_1V8), 961 K1_FUNC_PIN(60, 0, IO_TYPE_1V8), 962 K1_FUNC_PIN(61, 0, IO_TYPE_1V8), 963 K1_FUNC_PIN(62, 0, IO_TYPE_1V8), 964 K1_FUNC_PIN(63, 0, IO_TYPE_1V8), 965 K1_FUNC_PIN(64, 0, IO_TYPE_1V8), 966 K1_FUNC_PIN(65, 0, IO_TYPE_1V8), 967 K1_FUNC_PIN(66, 0, IO_TYPE_1V8), 968 K1_FUNC_PIN(67, 0, IO_TYPE_1V8), 969 K1_FUNC_PIN(68, 0, IO_TYPE_1V8), 970 K1_FUNC_PIN(69, 0, IO_TYPE_1V8), 971 K1_FUNC_PIN(70, 1, IO_TYPE_1V8), 972 K1_FUNC_PIN(71, 1, IO_TYPE_1V8), 973 K1_FUNC_PIN(72, 1, IO_TYPE_1V8), 974 K1_FUNC_PIN(73, 1, IO_TYPE_1V8), 975 K1_FUNC_PIN(74, 0, IO_TYPE_1V8), 976 K1_FUNC_PIN(75, 0, IO_TYPE_EXTERNAL), 977 K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL), 978 K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL), 979 K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL), 980 K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL), 981 K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL), 982 K1_FUNC_PIN(81, 0, IO_TYPE_1V8), 983 K1_FUNC_PIN(82, 0, IO_TYPE_1V8), 984 K1_FUNC_PIN(83, 0, IO_TYPE_1V8), 985 K1_FUNC_PIN(84, 0, IO_TYPE_1V8), 986 K1_FUNC_PIN(85, 0, IO_TYPE_1V8), 987 K1_FUNC_PIN(86, 0, IO_TYPE_1V8), 988 K1_FUNC_PIN(87, 0, IO_TYPE_1V8), 989 K1_FUNC_PIN(88, 0, IO_TYPE_1V8), 990 K1_FUNC_PIN(89, 0, IO_TYPE_1V8), 991 K1_FUNC_PIN(90, 0, IO_TYPE_1V8), 992 K1_FUNC_PIN(91, 0, IO_TYPE_1V8), 993 K1_FUNC_PIN(92, 0, IO_TYPE_1V8), 994 K1_FUNC_PIN(93, 1, IO_TYPE_1V8), 995 K1_FUNC_PIN(94, 1, IO_TYPE_1V8), 996 K1_FUNC_PIN(95, 1, IO_TYPE_1V8), 997 K1_FUNC_PIN(96, 1, IO_TYPE_1V8), 998 K1_FUNC_PIN(97, 1, IO_TYPE_1V8), 999 K1_FUNC_PIN(98, 1, IO_TYPE_EXTERNAL), 1000 K1_FUNC_PIN(99, 1, IO_TYPE_EXTERNAL), 1001 K1_FUNC_PIN(100, 1, IO_TYPE_EXTERNAL), 1002 K1_FUNC_PIN(101, 1, IO_TYPE_EXTERNAL), 1003 K1_FUNC_PIN(102, 1, IO_TYPE_EXTERNAL), 1004 K1_FUNC_PIN(103, 1, IO_TYPE_EXTERNAL), 1005 K1_FUNC_PIN(104, 4, IO_TYPE_EXTERNAL), 1006 K1_FUNC_PIN(105, 4, IO_TYPE_EXTERNAL), 1007 K1_FUNC_PIN(106, 4, IO_TYPE_EXTERNAL), 1008 K1_FUNC_PIN(107, 4, IO_TYPE_EXTERNAL), 1009 K1_FUNC_PIN(108, 4, IO_TYPE_EXTERNAL), 1010 K1_FUNC_PIN(109, 4, IO_TYPE_EXTERNAL), 1011 K1_FUNC_PIN(110, 0, IO_TYPE_1V8), 1012 K1_FUNC_PIN(111, 0, IO_TYPE_1V8), 1013 K1_FUNC_PIN(112, 0, IO_TYPE_1V8), 1014 K1_FUNC_PIN(113, 0, IO_TYPE_1V8), 1015 K1_FUNC_PIN(114, 0, IO_TYPE_1V8), 1016 K1_FUNC_PIN(115, 0, IO_TYPE_1V8), 1017 K1_FUNC_PIN(116, 0, IO_TYPE_1V8), 1018 K1_FUNC_PIN(117, 0, IO_TYPE_1V8), 1019 K1_FUNC_PIN(118, 0, IO_TYPE_1V8), 1020 K1_FUNC_PIN(119, 0, IO_TYPE_1V8), 1021 K1_FUNC_PIN(120, 0, IO_TYPE_1V8), 1022 K1_FUNC_PIN(121, 0, IO_TYPE_1V8), 1023 K1_FUNC_PIN(122, 0, IO_TYPE_1V8), 1024 K1_FUNC_PIN(123, 0, IO_TYPE_1V8), 1025 K1_FUNC_PIN(124, 0, IO_TYPE_1V8), 1026 K1_FUNC_PIN(125, 0, IO_TYPE_1V8), 1027 K1_FUNC_PIN(126, 0, IO_TYPE_1V8), 1028 K1_FUNC_PIN(127, 0, IO_TYPE_1V8), 1029 }; 1030 1031 static const struct spacemit_pinctrl_data k1_pinctrl_data = { 1032 .pins = k1_pin_desc, 1033 .data = k1_pin_data, 1034 .npins = ARRAY_SIZE(k1_pin_desc), 1035 }; 1036 1037 static const struct of_device_id k1_pinctrl_ids[] = { 1038 { .compatible = "spacemit,k1-pinctrl", .data = &k1_pinctrl_data }, 1039 { /* sentinel */ } 1040 }; 1041 MODULE_DEVICE_TABLE(of, k1_pinctrl_ids); 1042 1043 static struct platform_driver k1_pinctrl_driver = { 1044 .probe = spacemit_pinctrl_probe, 1045 .driver = { 1046 .name = "k1-pinctrl", 1047 .suppress_bind_attrs = true, 1048 .of_match_table = k1_pinctrl_ids, 1049 }, 1050 }; 1051 builtin_platform_driver(k1_pinctrl_driver); 1052 1053 MODULE_AUTHOR("Yixun Lan <dlan@gentoo.org>"); 1054 MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1 SoC"); 1055 MODULE_LICENSE("GPL"); 1056