1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Sophgo CV1800B SoC pinctrl driver. 4 * 5 * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> 6 * 7 * This file is generated from vendor pinout definition. 8 */ 9 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/of.h> 13 14 #include <linux/pinctrl/pinctrl.h> 15 #include <linux/pinctrl/pinmux.h> 16 17 #include <dt-bindings/pinctrl/pinctrl-cv1800b.h> 18 19 #include "pinctrl-cv18xx.h" 20 21 enum CV1800B_POWER_DOMAIN { 22 VDD18A_AUD = 0, 23 VDD18A_USB_PLL_ETH_CSI = 1, 24 VDD33A_ETH_USB_SD1 = 2, 25 VDDIO_RTC = 3, 26 VDDIO_SD0_SPI = 4 27 }; 28 29 static const char *const cv1800b_power_domain_desc[] = { 30 [VDD18A_AUD] = "VDD18A_AUD", 31 [VDD18A_USB_PLL_ETH_CSI] = "VDD18A_USB_PLL_ETH_CSI", 32 [VDD33A_ETH_USB_SD1] = "VDD33A_ETH_USB_SD1", 33 [VDDIO_RTC] = "VDDIO_RTC", 34 [VDDIO_SD0_SPI] = "VDDIO_SD0_SPI", 35 }; 36 37 static int cv1800b_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap) 38 { 39 const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); 40 u32 pstate = psmap[pin->power_domain]; 41 enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); 42 43 if (type == IO_TYPE_1V8_ONLY) 44 return 79000; 45 46 if (type == IO_TYPE_1V8_OR_3V3) { 47 if (pstate == PIN_POWER_STATE_1V8) 48 return 60000; 49 if (pstate == PIN_POWER_STATE_3V3) 50 return 60000; 51 52 return -EINVAL; 53 } 54 55 return -ENOTSUPP; 56 } 57 58 static int cv1800b_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap) 59 { 60 const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); 61 u32 pstate = psmap[pin->power_domain]; 62 enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); 63 64 if (type == IO_TYPE_1V8_ONLY) 65 return 87000; 66 67 if (type == IO_TYPE_1V8_OR_3V3) { 68 if (pstate == PIN_POWER_STATE_1V8) 69 return 61000; 70 if (pstate == PIN_POWER_STATE_3V3) 71 return 62000; 72 73 return -EINVAL; 74 } 75 76 return -ENOTSUPP; 77 } 78 79 static const u32 cv1800b_1v8_oc_map[] = { 80 12800, 81 25300, 82 37400, 83 49000 84 }; 85 86 static const u32 cv1800b_18od33_1v8_oc_map[] = { 87 7800, 88 11700, 89 15500, 90 19200, 91 23000, 92 26600, 93 30200, 94 33700 95 }; 96 97 static const u32 cv1800b_18od33_3v3_oc_map[] = { 98 5500, 99 8200, 100 10800, 101 13400, 102 16100, 103 18700, 104 21200, 105 23700 106 }; 107 108 static const u32 cv1800b_eth_oc_map[] = { 109 15700, 110 17800 111 }; 112 113 static int cv1800b_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap, 114 const u32 **map) 115 { 116 const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); 117 enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); 118 u32 pstate = psmap[pin->power_domain]; 119 120 if (type == IO_TYPE_1V8_ONLY) { 121 *map = cv1800b_1v8_oc_map; 122 return ARRAY_SIZE(cv1800b_1v8_oc_map); 123 } 124 125 if (type == IO_TYPE_1V8_OR_3V3) { 126 if (pstate == PIN_POWER_STATE_1V8) { 127 *map = cv1800b_18od33_1v8_oc_map; 128 return ARRAY_SIZE(cv1800b_18od33_1v8_oc_map); 129 } else if (pstate == PIN_POWER_STATE_3V3) { 130 *map = cv1800b_18od33_3v3_oc_map; 131 return ARRAY_SIZE(cv1800b_18od33_3v3_oc_map); 132 } 133 } 134 135 if (type == IO_TYPE_ETH) { 136 *map = cv1800b_eth_oc_map; 137 return ARRAY_SIZE(cv1800b_eth_oc_map); 138 } 139 140 return -ENOTSUPP; 141 } 142 143 static const u32 cv1800b_1v8_schmitt_map[] = { 144 0, 145 970000, 146 1040000 147 }; 148 149 static const u32 cv1800b_18od33_1v8_schmitt_map[] = { 150 0, 151 1070000 152 }; 153 154 static const u32 cv1800b_18od33_3v3_schmitt_map[] = { 155 0, 156 1100000 157 }; 158 159 static int cv1800b_get_schmitt_map(const struct sophgo_pin *sp, const u32 *psmap, 160 const u32 **map) 161 { 162 const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); 163 enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); 164 u32 pstate = psmap[pin->power_domain]; 165 166 if (type == IO_TYPE_1V8_ONLY) { 167 *map = cv1800b_1v8_schmitt_map; 168 return ARRAY_SIZE(cv1800b_1v8_schmitt_map); 169 } 170 171 if (type == IO_TYPE_1V8_OR_3V3) { 172 if (pstate == PIN_POWER_STATE_1V8) { 173 *map = cv1800b_18od33_1v8_schmitt_map; 174 return ARRAY_SIZE(cv1800b_18od33_1v8_schmitt_map); 175 } else if (pstate == PIN_POWER_STATE_3V3) { 176 *map = cv1800b_18od33_3v3_schmitt_map; 177 return ARRAY_SIZE(cv1800b_18od33_3v3_schmitt_map); 178 } 179 } 180 181 return -ENOTSUPP; 182 } 183 184 static const struct sophgo_vddio_cfg_ops cv1800b_vddio_cfg_ops = { 185 .get_pull_up = cv1800b_get_pull_up, 186 .get_pull_down = cv1800b_get_pull_down, 187 .get_oc_map = cv1800b_get_oc_map, 188 .get_schmitt_map = cv1800b_get_schmitt_map, 189 }; 190 191 static const struct pinctrl_pin_desc cv1800b_pins[] = { 192 PINCTRL_PIN(PIN_AUD_AOUTR, "AUD_AOUTR"), 193 PINCTRL_PIN(PIN_SD0_CLK, "SD0_CLK"), 194 PINCTRL_PIN(PIN_SD0_CMD, "SD0_CMD"), 195 PINCTRL_PIN(PIN_SD0_D0, "SD0_D0"), 196 PINCTRL_PIN(PIN_SD0_D1, "SD0_D1"), 197 PINCTRL_PIN(PIN_SD0_D2, "SD0_D2"), 198 PINCTRL_PIN(PIN_SD0_D3, "SD0_D3"), 199 PINCTRL_PIN(PIN_SD0_CD, "SD0_CD"), 200 PINCTRL_PIN(PIN_SD0_PWR_EN, "SD0_PWR_EN"), 201 PINCTRL_PIN(PIN_SPK_EN, "SPK_EN"), 202 PINCTRL_PIN(PIN_UART0_TX, "UART0_TX"), 203 PINCTRL_PIN(PIN_UART0_RX, "UART0_RX"), 204 PINCTRL_PIN(PIN_SPINOR_HOLD_X, "SPINOR_HOLD_X"), 205 PINCTRL_PIN(PIN_SPINOR_SCK, "SPINOR_SCK"), 206 PINCTRL_PIN(PIN_SPINOR_MOSI, "SPINOR_MOSI"), 207 PINCTRL_PIN(PIN_SPINOR_WP_X, "SPINOR_WP_X"), 208 PINCTRL_PIN(PIN_SPINOR_MISO, "SPINOR_MISO"), 209 PINCTRL_PIN(PIN_SPINOR_CS_X, "SPINOR_CS_X"), 210 PINCTRL_PIN(PIN_IIC0_SCL, "IIC0_SCL"), 211 PINCTRL_PIN(PIN_IIC0_SDA, "IIC0_SDA"), 212 PINCTRL_PIN(PIN_AUX0, "AUX0"), 213 PINCTRL_PIN(PIN_PWR_VBAT_DET, "PWR_VBAT_DET"), 214 PINCTRL_PIN(PIN_PWR_SEQ2, "PWR_SEQ2"), 215 PINCTRL_PIN(PIN_XTAL_XIN, "XTAL_XIN"), 216 PINCTRL_PIN(PIN_SD1_GPIO0, "SD1_GPIO0"), 217 PINCTRL_PIN(PIN_SD1_GPIO1, "SD1_GPIO1"), 218 PINCTRL_PIN(PIN_SD1_D3, "SD1_D3"), 219 PINCTRL_PIN(PIN_SD1_D2, "SD1_D2"), 220 PINCTRL_PIN(PIN_SD1_D1, "SD1_D1"), 221 PINCTRL_PIN(PIN_SD1_D0, "SD1_D0"), 222 PINCTRL_PIN(PIN_SD1_CMD, "SD1_CMD"), 223 PINCTRL_PIN(PIN_SD1_CLK, "SD1_CLK"), 224 PINCTRL_PIN(PIN_ADC1, "ADC1"), 225 PINCTRL_PIN(PIN_USB_VBUS_DET, "USB_VBUS_DET"), 226 PINCTRL_PIN(PIN_ETH_TXP, "ETH_TXP"), 227 PINCTRL_PIN(PIN_ETH_TXM, "ETH_TXM"), 228 PINCTRL_PIN(PIN_ETH_RXP, "ETH_RXP"), 229 PINCTRL_PIN(PIN_ETH_RXM, "ETH_RXM"), 230 PINCTRL_PIN(PIN_MIPIRX4N, "MIPIRX4N"), 231 PINCTRL_PIN(PIN_MIPIRX4P, "MIPIRX4P"), 232 PINCTRL_PIN(PIN_MIPIRX3N, "MIPIRX3N"), 233 PINCTRL_PIN(PIN_MIPIRX3P, "MIPIRX3P"), 234 PINCTRL_PIN(PIN_MIPIRX2N, "MIPIRX2N"), 235 PINCTRL_PIN(PIN_MIPIRX2P, "MIPIRX2P"), 236 PINCTRL_PIN(PIN_MIPIRX1N, "MIPIRX1N"), 237 PINCTRL_PIN(PIN_MIPIRX1P, "MIPIRX1P"), 238 PINCTRL_PIN(PIN_MIPIRX0N, "MIPIRX0N"), 239 PINCTRL_PIN(PIN_MIPIRX0P, "MIPIRX0P"), 240 PINCTRL_PIN(PIN_AUD_AINL_MIC, "AUD_AINL_MIC"), 241 }; 242 243 static const struct cv1800_pin cv1800b_pin_data[ARRAY_SIZE(cv1800b_pins)] = { 244 CV1800_FUNC_PIN(PIN_AUD_AOUTR, VDD18A_AUD, 245 IO_TYPE_AUDIO, 246 CV1800_PINCONF_AREA_SYS, 0x12c, 6), 247 CV1800_GENERAL_PIN(PIN_SD0_CLK, VDDIO_SD0_SPI, 248 IO_TYPE_1V8_OR_3V3, 249 CV1800_PINCONF_AREA_SYS, 0x000, 7, 250 CV1800_PINCONF_AREA_SYS, 0xa00), 251 CV1800_GENERAL_PIN(PIN_SD0_CMD, VDDIO_SD0_SPI, 252 IO_TYPE_1V8_OR_3V3, 253 CV1800_PINCONF_AREA_SYS, 0x004, 7, 254 CV1800_PINCONF_AREA_SYS, 0xa04), 255 CV1800_GENERAL_PIN(PIN_SD0_D0, VDDIO_SD0_SPI, 256 IO_TYPE_1V8_OR_3V3, 257 CV1800_PINCONF_AREA_SYS, 0x008, 7, 258 CV1800_PINCONF_AREA_SYS, 0xa08), 259 CV1800_GENERAL_PIN(PIN_SD0_D1, VDDIO_SD0_SPI, 260 IO_TYPE_1V8_OR_3V3, 261 CV1800_PINCONF_AREA_SYS, 0x00c, 7, 262 CV1800_PINCONF_AREA_SYS, 0xa0c), 263 CV1800_GENERAL_PIN(PIN_SD0_D2, VDDIO_SD0_SPI, 264 IO_TYPE_1V8_OR_3V3, 265 CV1800_PINCONF_AREA_SYS, 0x010, 7, 266 CV1800_PINCONF_AREA_SYS, 0xa10), 267 CV1800_GENERAL_PIN(PIN_SD0_D3, VDDIO_SD0_SPI, 268 IO_TYPE_1V8_OR_3V3, 269 CV1800_PINCONF_AREA_SYS, 0x014, 7, 270 CV1800_PINCONF_AREA_SYS, 0xa14), 271 CV1800_GENERAL_PIN(PIN_SD0_CD, VDDIO_SD0_SPI, 272 IO_TYPE_1V8_OR_3V3, 273 CV1800_PINCONF_AREA_SYS, 0x018, 3, 274 CV1800_PINCONF_AREA_SYS, 0x900), 275 CV1800_GENERAL_PIN(PIN_SD0_PWR_EN, VDDIO_SD0_SPI, 276 IO_TYPE_1V8_OR_3V3, 277 CV1800_PINCONF_AREA_SYS, 0x01c, 3, 278 CV1800_PINCONF_AREA_SYS, 0x904), 279 CV1800_GENERAL_PIN(PIN_SPK_EN, VDDIO_SD0_SPI, 280 IO_TYPE_1V8_OR_3V3, 281 CV1800_PINCONF_AREA_SYS, 0x020, 3, 282 CV1800_PINCONF_AREA_SYS, 0x908), 283 CV1800_GENERAL_PIN(PIN_UART0_TX, VDDIO_SD0_SPI, 284 IO_TYPE_1V8_OR_3V3, 285 CV1800_PINCONF_AREA_SYS, 0x024, 7, 286 CV1800_PINCONF_AREA_SYS, 0x90c), 287 CV1800_GENERAL_PIN(PIN_UART0_RX, VDDIO_SD0_SPI, 288 IO_TYPE_1V8_OR_3V3, 289 CV1800_PINCONF_AREA_SYS, 0x028, 7, 290 CV1800_PINCONF_AREA_SYS, 0x910), 291 CV1800_GENERAL_PIN(PIN_SPINOR_HOLD_X, VDDIO_SD0_SPI, 292 IO_TYPE_1V8_OR_3V3, 293 CV1800_PINCONF_AREA_SYS, 0x02c, 3, 294 CV1800_PINCONF_AREA_SYS, 0x914), 295 CV1800_GENERAL_PIN(PIN_SPINOR_SCK, VDDIO_SD0_SPI, 296 IO_TYPE_1V8_OR_3V3, 297 CV1800_PINCONF_AREA_SYS, 0x030, 3, 298 CV1800_PINCONF_AREA_SYS, 0x918), 299 CV1800_GENERAL_PIN(PIN_SPINOR_MOSI, VDDIO_SD0_SPI, 300 IO_TYPE_1V8_OR_3V3, 301 CV1800_PINCONF_AREA_SYS, 0x034, 3, 302 CV1800_PINCONF_AREA_SYS, 0x91c), 303 CV1800_GENERAL_PIN(PIN_SPINOR_WP_X, VDDIO_SD0_SPI, 304 IO_TYPE_1V8_OR_3V3, 305 CV1800_PINCONF_AREA_SYS, 0x038, 3, 306 CV1800_PINCONF_AREA_SYS, 0x920), 307 CV1800_GENERAL_PIN(PIN_SPINOR_MISO, VDDIO_SD0_SPI, 308 IO_TYPE_1V8_OR_3V3, 309 CV1800_PINCONF_AREA_SYS, 0x03c, 3, 310 CV1800_PINCONF_AREA_SYS, 0x924), 311 CV1800_GENERAL_PIN(PIN_SPINOR_CS_X, VDDIO_SD0_SPI, 312 IO_TYPE_1V8_OR_3V3, 313 CV1800_PINCONF_AREA_SYS, 0x040, 3, 314 CV1800_PINCONF_AREA_SYS, 0x928), 315 CV1800_GENERAL_PIN(PIN_IIC0_SCL, VDDIO_SD0_SPI, 316 IO_TYPE_1V8_OR_3V3, 317 CV1800_PINCONF_AREA_SYS, 0x04c, 7, 318 CV1800_PINCONF_AREA_SYS, 0x934), 319 CV1800_GENERAL_PIN(PIN_IIC0_SDA, VDDIO_SD0_SPI, 320 IO_TYPE_1V8_OR_3V3, 321 CV1800_PINCONF_AREA_SYS, 0x050, 7, 322 CV1800_PINCONF_AREA_SYS, 0x938), 323 CV1800_GENERAL_PIN(PIN_AUX0, VDDIO_SD0_SPI, 324 IO_TYPE_1V8_OR_3V3, 325 CV1800_PINCONF_AREA_SYS, 0x054, 7, 326 CV1800_PINCONF_AREA_SYS, 0x93c), 327 CV1800_GENERAL_PIN(PIN_PWR_VBAT_DET, VDDIO_RTC, 328 IO_TYPE_1V8_ONLY, 329 CV1800_PINCONF_AREA_SYS, 0x05c, 0, 330 CV1800_PINCONF_AREA_RTC, 0x004), 331 CV1800_GENERAL_PIN(PIN_PWR_SEQ2, VDDIO_RTC, 332 IO_TYPE_1V8_ONLY, 333 CV1800_PINCONF_AREA_SYS, 0x068, 3, 334 CV1800_PINCONF_AREA_RTC, 0x010), 335 CV1800_GENERAL_PIN(PIN_XTAL_XIN, VDDIO_RTC, 336 IO_TYPE_1V8_ONLY, 337 CV1800_PINCONF_AREA_SYS, 0x074, 0, 338 CV1800_PINCONF_AREA_RTC, 0x020), 339 CV1800_GENERAL_PIN(PIN_SD1_GPIO0, VDD33A_ETH_USB_SD1, 340 IO_TYPE_1V8_OR_3V3, 341 CV1800_PINCONF_AREA_SYS, 0x088, 7, 342 CV1800_PINCONF_AREA_RTC, 0x034), 343 CV1800_GENERAL_PIN(PIN_SD1_GPIO1, VDD33A_ETH_USB_SD1, 344 IO_TYPE_1V8_OR_3V3, 345 CV1800_PINCONF_AREA_SYS, 0x084, 7, 346 CV1800_PINCONF_AREA_RTC, 0x030), 347 CV1800_GENERAL_PIN(PIN_SD1_D3, VDD33A_ETH_USB_SD1, 348 IO_TYPE_1V8_OR_3V3, 349 CV1800_PINCONF_AREA_SYS, 0x08c, 7, 350 CV1800_PINCONF_AREA_RTC, 0x038), 351 CV1800_GENERAL_PIN(PIN_SD1_D2, VDD33A_ETH_USB_SD1, 352 IO_TYPE_1V8_OR_3V3, 353 CV1800_PINCONF_AREA_SYS, 0x090, 7, 354 CV1800_PINCONF_AREA_RTC, 0x03c), 355 CV1800_GENERAL_PIN(PIN_SD1_D1, VDD33A_ETH_USB_SD1, 356 IO_TYPE_1V8_OR_3V3, 357 CV1800_PINCONF_AREA_SYS, 0x094, 7, 358 CV1800_PINCONF_AREA_RTC, 0x040), 359 CV1800_GENERAL_PIN(PIN_SD1_D0, VDD33A_ETH_USB_SD1, 360 IO_TYPE_1V8_OR_3V3, 361 CV1800_PINCONF_AREA_SYS, 0x098, 7, 362 CV1800_PINCONF_AREA_RTC, 0x044), 363 CV1800_GENERAL_PIN(PIN_SD1_CMD, VDD33A_ETH_USB_SD1, 364 IO_TYPE_1V8_OR_3V3, 365 CV1800_PINCONF_AREA_SYS, 0x09c, 7, 366 CV1800_PINCONF_AREA_RTC, 0x048), 367 CV1800_GENERAL_PIN(PIN_SD1_CLK, VDD33A_ETH_USB_SD1, 368 IO_TYPE_1V8_OR_3V3, 369 CV1800_PINCONF_AREA_SYS, 0x0a0, 7, 370 CV1800_PINCONF_AREA_RTC, 0x04c), 371 CV1800_GENERAL_PIN(PIN_ADC1, VDD18A_USB_PLL_ETH_CSI, 372 IO_TYPE_1V8_ONLY, 373 CV1800_PINCONF_AREA_SYS, 0x0a8, 6, 374 CV1800_PINCONF_AREA_SYS, 0x804), 375 CV1800_GENERAL_PIN(PIN_USB_VBUS_DET, VDD18A_USB_PLL_ETH_CSI, 376 IO_TYPE_1V8_ONLY, 377 CV1800_PINCONF_AREA_SYS, 0x0ac, 6, 378 CV1800_PINCONF_AREA_SYS, 0x808), 379 CV1800_FUNC_PIN(PIN_ETH_TXP, VDD18A_USB_PLL_ETH_CSI, 380 IO_TYPE_ETH, 381 CV1800_PINCONF_AREA_SYS, 0x0c0, 7), 382 CV1800_FUNC_PIN(PIN_ETH_TXM, VDD18A_USB_PLL_ETH_CSI, 383 IO_TYPE_ETH, 384 CV1800_PINCONF_AREA_SYS, 0x0c4, 7), 385 CV1800_FUNC_PIN(PIN_ETH_RXP, VDD18A_USB_PLL_ETH_CSI, 386 IO_TYPE_ETH, 387 CV1800_PINCONF_AREA_SYS, 0x0c8, 7), 388 CV1800_FUNC_PIN(PIN_ETH_RXM, VDD18A_USB_PLL_ETH_CSI, 389 IO_TYPE_ETH, 390 CV1800_PINCONF_AREA_SYS, 0x0cc, 7), 391 CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4N, VDD18A_USB_PLL_ETH_CSI, 392 IO_TYPE_1V8_ONLY, 393 CV1800_PINCONF_AREA_SYS, 0x0d4, 7, 394 CV1800_PINCONF_AREA_SYS, 0x0bc, 7, 395 CV1800_PINCONF_AREA_SYS, 0xc04), 396 CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4P, VDD18A_USB_PLL_ETH_CSI, 397 IO_TYPE_1V8_ONLY, 398 CV1800_PINCONF_AREA_SYS, 0x0d8, 7, 399 CV1800_PINCONF_AREA_SYS, 0x0b8, 7, 400 CV1800_PINCONF_AREA_SYS, 0xc08), 401 CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3N, VDD18A_USB_PLL_ETH_CSI, 402 IO_TYPE_1V8_ONLY, 403 CV1800_PINCONF_AREA_SYS, 0x0dc, 7, 404 CV1800_PINCONF_AREA_SYS, 0x0b0, 7, 405 CV1800_PINCONF_AREA_SYS, 0xc0c), 406 CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3P, VDD18A_USB_PLL_ETH_CSI, 407 IO_TYPE_1V8_ONLY, 408 CV1800_PINCONF_AREA_SYS, 0x0e0, 7, 409 CV1800_PINCONF_AREA_SYS, 0x0b4, 7, 410 CV1800_PINCONF_AREA_SYS, 0xc10), 411 CV1800_GENERAL_PIN(PIN_MIPIRX2N, VDD18A_USB_PLL_ETH_CSI, 412 IO_TYPE_1V8_ONLY, 413 CV1800_PINCONF_AREA_SYS, 0x0e4, 7, 414 CV1800_PINCONF_AREA_SYS, 0xc14), 415 CV1800_GENERAL_PIN(PIN_MIPIRX2P, VDD18A_USB_PLL_ETH_CSI, 416 IO_TYPE_1V8_ONLY, 417 CV1800_PINCONF_AREA_SYS, 0x0e8, 7, 418 CV1800_PINCONF_AREA_SYS, 0xc18), 419 CV1800_GENERAL_PIN(PIN_MIPIRX1N, VDD18A_USB_PLL_ETH_CSI, 420 IO_TYPE_1V8_ONLY, 421 CV1800_PINCONF_AREA_SYS, 0x0ec, 7, 422 CV1800_PINCONF_AREA_SYS, 0xc1c), 423 CV1800_GENERAL_PIN(PIN_MIPIRX1P, VDD18A_USB_PLL_ETH_CSI, 424 IO_TYPE_1V8_ONLY, 425 CV1800_PINCONF_AREA_SYS, 0x0f0, 7, 426 CV1800_PINCONF_AREA_SYS, 0xc20), 427 CV1800_GENERAL_PIN(PIN_MIPIRX0N, VDD18A_USB_PLL_ETH_CSI, 428 IO_TYPE_1V8_ONLY, 429 CV1800_PINCONF_AREA_SYS, 0x0f4, 7, 430 CV1800_PINCONF_AREA_SYS, 0xc24), 431 CV1800_GENERAL_PIN(PIN_MIPIRX0P, VDD18A_USB_PLL_ETH_CSI, 432 IO_TYPE_1V8_ONLY, 433 CV1800_PINCONF_AREA_SYS, 0x0f8, 7, 434 CV1800_PINCONF_AREA_SYS, 0xc28), 435 CV1800_FUNC_PIN(PIN_AUD_AINL_MIC, VDD18A_AUD, 436 IO_TYPE_AUDIO, 437 CV1800_PINCONF_AREA_SYS, 0x120, 5), 438 }; 439 440 static const struct sophgo_pinctrl_data cv1800b_pindata = { 441 .pins = cv1800b_pins, 442 .pindata = cv1800b_pin_data, 443 .pdnames = cv1800b_power_domain_desc, 444 .vddio_ops = &cv1800b_vddio_cfg_ops, 445 .cfg_ops = &cv1800_cfg_ops, 446 .pctl_ops = &cv1800_pctrl_ops, 447 .pmx_ops = &cv1800_pmx_ops, 448 .pconf_ops = &cv1800_pconf_ops, 449 .npins = ARRAY_SIZE(cv1800b_pins), 450 .npds = ARRAY_SIZE(cv1800b_power_domain_desc), 451 .pinsize = sizeof(struct cv1800_pin), 452 }; 453 454 static const struct of_device_id cv1800b_pinctrl_ids[] = { 455 { .compatible = "sophgo,cv1800b-pinctrl", .data = &cv1800b_pindata }, 456 { } 457 }; 458 MODULE_DEVICE_TABLE(of, cv1800b_pinctrl_ids); 459 460 static struct platform_driver cv1800b_pinctrl_driver = { 461 .probe = sophgo_pinctrl_probe, 462 .driver = { 463 .name = "cv1800b-pinctrl", 464 .suppress_bind_attrs = true, 465 .of_match_table = cv1800b_pinctrl_ids, 466 }, 467 }; 468 module_platform_driver(cv1800b_pinctrl_driver); 469 470 MODULE_DESCRIPTION("Pinctrl driver for the CV1800B series SoC"); 471 MODULE_LICENSE("GPL"); 472