1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. 4 // 5 // Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 // http://www.samsung.com 7 // Copyright (c) 2012 Linaro Ltd 8 // http://www.linaro.org 9 // 10 // Author: Thomas Abraham <thomas.ab@samsung.com> 11 // 12 // This file contains the Samsung Exynos specific information required by the 13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of 14 // external gpio and wakeup interrupt support. 15 16 #include <linux/clk.h> 17 #include <linux/device.h> 18 #include <linux/interrupt.h> 19 #include <linux/irqdomain.h> 20 #include <linux/irq.h> 21 #include <linux/irqchip/chained_irq.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/slab.h> 25 #include <linux/spinlock.h> 26 #include <linux/string_choices.h> 27 #include <linux/regmap.h> 28 #include <linux/err.h> 29 #include <linux/soc/samsung/exynos-pmu.h> 30 #include <linux/soc/samsung/exynos-regs-pmu.h> 31 32 #include "pinctrl-samsung.h" 33 #include "pinctrl-exynos.h" 34 35 struct exynos_irq_chip { 36 struct irq_chip chip; 37 38 u32 eint_con; 39 u32 eint_mask; 40 u32 eint_pend; 41 u32 *eint_wake_mask_value; 42 u32 eint_wake_mask_reg; 43 void (*set_eint_wakeup_mask)(struct samsung_pinctrl_drv_data *drvdata, 44 struct exynos_irq_chip *irq_chip); 45 }; 46 47 static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip) 48 { 49 return container_of(chip, struct exynos_irq_chip, chip); 50 } 51 52 static void exynos_irq_mask(struct irq_data *irqd) 53 { 54 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 55 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 57 unsigned long reg_mask; 58 unsigned int mask; 59 unsigned long flags; 60 61 if (bank->eint_mask_offset) 62 reg_mask = bank->pctl_offset + bank->eint_mask_offset; 63 else 64 reg_mask = our_chip->eint_mask + bank->eint_offset; 65 66 if (clk_enable(bank->drvdata->pclk)) { 67 dev_err(bank->gpio_chip.parent, 68 "unable to enable clock for masking IRQ\n"); 69 return; 70 } 71 72 raw_spin_lock_irqsave(&bank->slock, flags); 73 74 mask = readl(bank->eint_base + reg_mask); 75 mask |= 1 << irqd->hwirq; 76 writel(mask, bank->eint_base + reg_mask); 77 78 raw_spin_unlock_irqrestore(&bank->slock, flags); 79 80 clk_disable(bank->drvdata->pclk); 81 } 82 83 static void exynos_irq_ack(struct irq_data *irqd) 84 { 85 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 86 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 87 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 88 unsigned long reg_pend; 89 90 if (bank->eint_pend_offset) 91 reg_pend = bank->pctl_offset + bank->eint_pend_offset; 92 else 93 reg_pend = our_chip->eint_pend + bank->eint_offset; 94 95 if (clk_enable(bank->drvdata->pclk)) { 96 dev_err(bank->gpio_chip.parent, 97 "unable to enable clock to ack IRQ\n"); 98 return; 99 } 100 101 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); 102 103 clk_disable(bank->drvdata->pclk); 104 } 105 106 static void exynos_irq_unmask(struct irq_data *irqd) 107 { 108 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 109 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 110 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 111 unsigned long reg_mask; 112 unsigned int mask; 113 unsigned long flags; 114 115 /* 116 * Ack level interrupts right before unmask 117 * 118 * If we don't do this we'll get a double-interrupt. Level triggered 119 * interrupts must not fire an interrupt if the level is not 120 * _currently_ active, even if it was active while the interrupt was 121 * masked. 122 */ 123 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) 124 exynos_irq_ack(irqd); 125 126 if (bank->eint_mask_offset) 127 reg_mask = bank->pctl_offset + bank->eint_mask_offset; 128 else 129 reg_mask = our_chip->eint_mask + bank->eint_offset; 130 131 if (clk_enable(bank->drvdata->pclk)) { 132 dev_err(bank->gpio_chip.parent, 133 "unable to enable clock for unmasking IRQ\n"); 134 return; 135 } 136 137 raw_spin_lock_irqsave(&bank->slock, flags); 138 139 mask = readl(bank->eint_base + reg_mask); 140 mask &= ~(1 << irqd->hwirq); 141 writel(mask, bank->eint_base + reg_mask); 142 143 raw_spin_unlock_irqrestore(&bank->slock, flags); 144 145 clk_disable(bank->drvdata->pclk); 146 } 147 148 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) 149 { 150 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 151 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 152 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 153 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; 154 unsigned int con, trig_type; 155 unsigned long reg_con; 156 int ret; 157 158 switch (type) { 159 case IRQ_TYPE_EDGE_RISING: 160 trig_type = EXYNOS_EINT_EDGE_RISING; 161 break; 162 case IRQ_TYPE_EDGE_FALLING: 163 trig_type = EXYNOS_EINT_EDGE_FALLING; 164 break; 165 case IRQ_TYPE_EDGE_BOTH: 166 trig_type = EXYNOS_EINT_EDGE_BOTH; 167 break; 168 case IRQ_TYPE_LEVEL_HIGH: 169 trig_type = EXYNOS_EINT_LEVEL_HIGH; 170 break; 171 case IRQ_TYPE_LEVEL_LOW: 172 trig_type = EXYNOS_EINT_LEVEL_LOW; 173 break; 174 default: 175 pr_err("unsupported external interrupt type\n"); 176 return -EINVAL; 177 } 178 179 if (type & IRQ_TYPE_EDGE_BOTH) 180 irq_set_handler_locked(irqd, handle_edge_irq); 181 else 182 irq_set_handler_locked(irqd, handle_level_irq); 183 184 if (bank->eint_con_offset) 185 reg_con = bank->pctl_offset + bank->eint_con_offset; 186 else 187 reg_con = our_chip->eint_con + bank->eint_offset; 188 189 ret = clk_enable(bank->drvdata->pclk); 190 if (ret) { 191 dev_err(bank->gpio_chip.parent, 192 "unable to enable clock for configuring IRQ type\n"); 193 return ret; 194 } 195 196 con = readl(bank->eint_base + reg_con); 197 con &= ~(EXYNOS_EINT_CON_MASK << shift); 198 con |= trig_type << shift; 199 writel(con, bank->eint_base + reg_con); 200 201 clk_disable(bank->drvdata->pclk); 202 203 return 0; 204 } 205 206 static int exynos_irq_set_affinity(struct irq_data *irqd, 207 const struct cpumask *dest, bool force) 208 { 209 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 210 struct samsung_pinctrl_drv_data *d = bank->drvdata; 211 struct irq_data *parent = irq_get_irq_data(d->irq); 212 213 if (parent) 214 return parent->chip->irq_set_affinity(parent, dest, force); 215 216 return -EINVAL; 217 } 218 219 static int exynos_irq_request_resources(struct irq_data *irqd) 220 { 221 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 222 const struct samsung_pin_bank_type *bank_type = bank->type; 223 unsigned long reg_con, flags; 224 unsigned int shift, mask, con; 225 int ret; 226 227 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); 228 if (ret) { 229 dev_err(bank->gpio_chip.parent, 230 "unable to lock pin %s-%lu IRQ\n", 231 bank->name, irqd->hwirq); 232 return ret; 233 } 234 235 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; 236 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; 237 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; 238 239 ret = clk_enable(bank->drvdata->pclk); 240 if (ret) { 241 dev_err(bank->gpio_chip.parent, 242 "unable to enable clock for configuring pin %s-%lu\n", 243 bank->name, irqd->hwirq); 244 return ret; 245 } 246 247 raw_spin_lock_irqsave(&bank->slock, flags); 248 249 con = readl(bank->pctl_base + reg_con); 250 con &= ~(mask << shift); 251 con |= EXYNOS_PIN_CON_FUNC_EINT << shift; 252 writel(con, bank->pctl_base + reg_con); 253 254 raw_spin_unlock_irqrestore(&bank->slock, flags); 255 256 clk_disable(bank->drvdata->pclk); 257 258 return 0; 259 } 260 261 static void exynos_irq_release_resources(struct irq_data *irqd) 262 { 263 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 264 const struct samsung_pin_bank_type *bank_type = bank->type; 265 unsigned long reg_con, flags; 266 unsigned int shift, mask, con; 267 268 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; 269 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; 270 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; 271 272 if (clk_enable(bank->drvdata->pclk)) { 273 dev_err(bank->gpio_chip.parent, 274 "unable to enable clock for deconfiguring pin %s-%lu\n", 275 bank->name, irqd->hwirq); 276 return; 277 } 278 279 raw_spin_lock_irqsave(&bank->slock, flags); 280 281 con = readl(bank->pctl_base + reg_con); 282 con &= ~(mask << shift); 283 con |= PIN_CON_FUNC_INPUT << shift; 284 writel(con, bank->pctl_base + reg_con); 285 286 raw_spin_unlock_irqrestore(&bank->slock, flags); 287 288 clk_disable(bank->drvdata->pclk); 289 290 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); 291 } 292 293 /* 294 * irq_chip for gpio interrupts. 295 */ 296 static const struct exynos_irq_chip exynos_gpio_irq_chip __initconst = { 297 .chip = { 298 .name = "exynos_gpio_irq_chip", 299 .irq_unmask = exynos_irq_unmask, 300 .irq_mask = exynos_irq_mask, 301 .irq_ack = exynos_irq_ack, 302 .irq_set_type = exynos_irq_set_type, 303 .irq_set_affinity = exynos_irq_set_affinity, 304 .irq_request_resources = exynos_irq_request_resources, 305 .irq_release_resources = exynos_irq_release_resources, 306 }, 307 .eint_con = EXYNOS_GPIO_ECON_OFFSET, 308 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET, 309 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET, 310 /* eint_wake_mask_value not used */ 311 }; 312 313 static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq, 314 irq_hw_number_t hw) 315 { 316 struct samsung_pin_bank *b = h->host_data; 317 318 irq_set_chip_data(virq, b); 319 irq_set_chip_and_handler(virq, &b->irq_chip->chip, 320 handle_level_irq); 321 return 0; 322 } 323 324 /* 325 * irq domain callbacks for external gpio and wakeup interrupt controllers. 326 */ 327 static const struct irq_domain_ops exynos_eint_irqd_ops = { 328 .map = exynos_eint_irq_map, 329 .xlate = irq_domain_xlate_twocell, 330 }; 331 332 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) 333 { 334 struct samsung_pinctrl_drv_data *d = data; 335 struct samsung_pin_bank *bank = d->pin_banks; 336 unsigned int svc, group, pin; 337 int ret; 338 339 if (clk_enable(bank->drvdata->pclk)) { 340 dev_err(bank->gpio_chip.parent, 341 "unable to enable clock for handling IRQ\n"); 342 return IRQ_NONE; 343 } 344 345 if (bank->eint_con_offset) 346 svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET); 347 else 348 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); 349 350 clk_disable(bank->drvdata->pclk); 351 352 group = EXYNOS_SVC_GROUP(svc); 353 pin = svc & EXYNOS_SVC_NUM_MASK; 354 355 if (!group) 356 return IRQ_HANDLED; 357 bank += (group - 1); 358 359 ret = generic_handle_domain_irq(bank->irq_domain, pin); 360 if (ret) 361 return IRQ_NONE; 362 363 return IRQ_HANDLED; 364 } 365 366 struct exynos_eint_gpio_save { 367 u32 eint_con; 368 u32 eint_fltcon0; 369 u32 eint_fltcon1; 370 u32 eint_mask; 371 }; 372 373 static void exynos_eint_update_flt_reg(void __iomem *reg, int cnt, int con) 374 { 375 unsigned int val, shift; 376 int i; 377 378 val = readl(reg); 379 for (i = 0; i < cnt; i++) { 380 shift = i * EXYNOS_FLTCON_LEN; 381 val &= ~(EXYNOS_FLTCON_DIGITAL << shift); 382 val |= con << shift; 383 } 384 writel(val, reg); 385 } 386 387 /* 388 * Set the desired filter (digital or analog delay) and enable it to 389 * every pin in the bank. Note the filter selection bitfield is only 390 * found on alive banks. The filter determines to what extent signal 391 * fluctuations received through the pad are considered glitches. 392 */ 393 static void exynos_eint_set_filter(struct samsung_pin_bank *bank, int filter) 394 { 395 unsigned int off = EXYNOS_GPIO_EFLTCON_OFFSET + bank->eint_fltcon_offset; 396 void __iomem *reg = bank->drvdata->virt_base + off; 397 unsigned int con = EXYNOS_FLTCON_EN | filter; 398 399 for (int n = 0; n < bank->nr_pins; n += 4) 400 exynos_eint_update_flt_reg(reg + n, 401 min(bank->nr_pins - n, 4), con); 402 } 403 404 /* 405 * exynos_eint_gpio_init() - setup handling of external gpio interrupts. 406 * @d: driver data of samsung pinctrl driver. 407 */ 408 __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) 409 { 410 struct samsung_pin_bank *bank; 411 struct device *dev = d->dev; 412 int ret; 413 int i; 414 415 if (!d->irq) { 416 dev_err(dev, "irq number not available\n"); 417 return -EINVAL; 418 } 419 420 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, 421 0, dev_name(dev), d); 422 if (ret) { 423 dev_err(dev, "irq request failed\n"); 424 return -ENXIO; 425 } 426 427 bank = d->pin_banks; 428 for (i = 0; i < d->nr_banks; ++i, ++bank) { 429 if (bank->eint_type != EINT_TYPE_GPIO) 430 continue; 431 432 bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip, 433 sizeof(*bank->irq_chip), GFP_KERNEL); 434 if (!bank->irq_chip) { 435 ret = -ENOMEM; 436 goto err_domains; 437 } 438 bank->irq_chip->chip.name = bank->name; 439 440 bank->irq_domain = irq_domain_create_linear(bank->fwnode, 441 bank->nr_pins, &exynos_eint_irqd_ops, bank); 442 if (!bank->irq_domain) { 443 dev_err(dev, "gpio irq domain add failed\n"); 444 ret = -ENXIO; 445 goto err_domains; 446 } 447 448 bank->soc_priv = devm_kzalloc(d->dev, 449 sizeof(struct exynos_eint_gpio_save), GFP_KERNEL); 450 if (!bank->soc_priv) { 451 irq_domain_remove(bank->irq_domain); 452 ret = -ENOMEM; 453 goto err_domains; 454 } 455 456 } 457 458 return 0; 459 460 err_domains: 461 for (--i, --bank; i >= 0; --i, --bank) { 462 if (bank->eint_type != EINT_TYPE_GPIO) 463 continue; 464 irq_domain_remove(bank->irq_domain); 465 } 466 467 return ret; 468 } 469 470 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) 471 { 472 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 473 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 474 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 475 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); 476 477 pr_info("wake %s for irq %u (%s-%lu)\n", str_enabled_disabled(on), 478 irqd->irq, bank->name, irqd->hwirq); 479 480 if (!on) 481 *our_chip->eint_wake_mask_value |= bit; 482 else 483 *our_chip->eint_wake_mask_value &= ~bit; 484 485 return 0; 486 } 487 488 static void 489 exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata, 490 struct exynos_irq_chip *irq_chip) 491 { 492 struct regmap *pmu_regs; 493 494 if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { 495 dev_warn(drvdata->dev, 496 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n"); 497 return; 498 } 499 500 pmu_regs = drvdata->retention_ctrl->priv; 501 dev_info(drvdata->dev, 502 "Setting external wakeup interrupt mask: 0x%x\n", 503 *irq_chip->eint_wake_mask_value); 504 505 regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg, 506 *irq_chip->eint_wake_mask_value); 507 } 508 509 static void 510 s5pv210_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata, 511 struct exynos_irq_chip *irq_chip) 512 513 { 514 void __iomem *clk_base; 515 516 if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { 517 dev_warn(drvdata->dev, 518 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n"); 519 return; 520 } 521 522 523 clk_base = (void __iomem *) drvdata->retention_ctrl->priv; 524 525 __raw_writel(*irq_chip->eint_wake_mask_value, 526 clk_base + irq_chip->eint_wake_mask_reg); 527 } 528 529 static u32 eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED; 530 /* 531 * irq_chip for wakeup interrupts 532 */ 533 static const struct exynos_irq_chip s5pv210_wkup_irq_chip __initconst = { 534 .chip = { 535 .name = "s5pv210_wkup_irq_chip", 536 .irq_unmask = exynos_irq_unmask, 537 .irq_mask = exynos_irq_mask, 538 .irq_ack = exynos_irq_ack, 539 .irq_set_type = exynos_irq_set_type, 540 .irq_set_wake = exynos_wkup_irq_set_wake, 541 .irq_request_resources = exynos_irq_request_resources, 542 .irq_release_resources = exynos_irq_release_resources, 543 }, 544 .eint_con = EXYNOS_WKUP_ECON_OFFSET, 545 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, 546 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, 547 .eint_wake_mask_value = &eint_wake_mask_value, 548 /* Only differences with exynos4210_wkup_irq_chip: */ 549 .eint_wake_mask_reg = S5PV210_EINT_WAKEUP_MASK, 550 .set_eint_wakeup_mask = s5pv210_pinctrl_set_eint_wakeup_mask, 551 }; 552 553 static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = { 554 .chip = { 555 .name = "exynos4210_wkup_irq_chip", 556 .irq_unmask = exynos_irq_unmask, 557 .irq_mask = exynos_irq_mask, 558 .irq_ack = exynos_irq_ack, 559 .irq_set_type = exynos_irq_set_type, 560 .irq_set_wake = exynos_wkup_irq_set_wake, 561 .irq_request_resources = exynos_irq_request_resources, 562 .irq_release_resources = exynos_irq_release_resources, 563 }, 564 .eint_con = EXYNOS_WKUP_ECON_OFFSET, 565 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, 566 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, 567 .eint_wake_mask_value = &eint_wake_mask_value, 568 .eint_wake_mask_reg = EXYNOS_EINT_WAKEUP_MASK, 569 .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, 570 }; 571 572 static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = { 573 .chip = { 574 .name = "exynos7_wkup_irq_chip", 575 .irq_unmask = exynos_irq_unmask, 576 .irq_mask = exynos_irq_mask, 577 .irq_ack = exynos_irq_ack, 578 .irq_set_type = exynos_irq_set_type, 579 .irq_set_wake = exynos_wkup_irq_set_wake, 580 .irq_request_resources = exynos_irq_request_resources, 581 .irq_release_resources = exynos_irq_release_resources, 582 }, 583 .eint_con = EXYNOS7_WKUP_ECON_OFFSET, 584 .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET, 585 .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET, 586 .eint_wake_mask_value = &eint_wake_mask_value, 587 .eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK, 588 .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, 589 }; 590 591 static const struct exynos_irq_chip exynosautov920_wkup_irq_chip __initconst = { 592 .chip = { 593 .name = "exynosautov920_wkup_irq_chip", 594 .irq_unmask = exynos_irq_unmask, 595 .irq_mask = exynos_irq_mask, 596 .irq_ack = exynos_irq_ack, 597 .irq_set_type = exynos_irq_set_type, 598 .irq_set_wake = exynos_wkup_irq_set_wake, 599 .irq_request_resources = exynos_irq_request_resources, 600 .irq_release_resources = exynos_irq_release_resources, 601 }, 602 .eint_wake_mask_value = &eint_wake_mask_value, 603 .eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK, 604 .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, 605 }; 606 607 /* list of external wakeup controllers supported */ 608 static const struct of_device_id exynos_wkup_irq_ids[] = { 609 { .compatible = "samsung,s5pv210-wakeup-eint", 610 .data = &s5pv210_wkup_irq_chip }, 611 { .compatible = "samsung,exynos4210-wakeup-eint", 612 .data = &exynos4210_wkup_irq_chip }, 613 { .compatible = "samsung,exynos7-wakeup-eint", 614 .data = &exynos7_wkup_irq_chip }, 615 { .compatible = "samsung,exynos850-wakeup-eint", 616 .data = &exynos7_wkup_irq_chip }, 617 { .compatible = "samsung,exynosautov9-wakeup-eint", 618 .data = &exynos7_wkup_irq_chip }, 619 { .compatible = "samsung,exynosautov920-wakeup-eint", 620 .data = &exynosautov920_wkup_irq_chip }, 621 { } 622 }; 623 624 /* interrupt handler for wakeup interrupts 0..15 */ 625 static void exynos_irq_eint0_15(struct irq_desc *desc) 626 { 627 struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc); 628 struct samsung_pin_bank *bank = eintd->bank; 629 struct irq_chip *chip = irq_desc_get_chip(desc); 630 631 chained_irq_enter(chip, desc); 632 633 generic_handle_domain_irq(bank->irq_domain, eintd->irq); 634 635 chained_irq_exit(chip, desc); 636 } 637 638 static inline void exynos_irq_demux_eint(unsigned int pend, 639 struct irq_domain *domain) 640 { 641 unsigned int irq; 642 643 while (pend) { 644 irq = fls(pend) - 1; 645 generic_handle_domain_irq(domain, irq); 646 pend &= ~(1 << irq); 647 } 648 } 649 650 /* interrupt handler for wakeup interrupt 16 */ 651 static void exynos_irq_demux_eint16_31(struct irq_desc *desc) 652 { 653 struct irq_chip *chip = irq_desc_get_chip(desc); 654 struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc); 655 unsigned int pend; 656 unsigned int mask; 657 int i; 658 659 chained_irq_enter(chip, desc); 660 661 /* 662 * just enable the clock once here, to avoid an enable/disable dance for 663 * each bank. 664 */ 665 if (eintd->nr_banks) { 666 struct samsung_pin_bank *b = eintd->banks[0]; 667 668 if (clk_enable(b->drvdata->pclk)) { 669 dev_err(b->gpio_chip.parent, 670 "unable to enable clock for pending IRQs\n"); 671 goto out; 672 } 673 } 674 675 for (i = 0; i < eintd->nr_banks; ++i) { 676 struct samsung_pin_bank *b = eintd->banks[i]; 677 pend = readl(b->eint_base + b->irq_chip->eint_pend 678 + b->eint_offset); 679 mask = readl(b->eint_base + b->irq_chip->eint_mask 680 + b->eint_offset); 681 exynos_irq_demux_eint(pend & ~mask, b->irq_domain); 682 } 683 684 if (eintd->nr_banks) 685 clk_disable(eintd->banks[0]->drvdata->pclk); 686 687 out: 688 chained_irq_exit(chip, desc); 689 } 690 691 /* 692 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. 693 * @d: driver data of samsung pinctrl driver. 694 */ 695 __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) 696 { 697 struct device *dev = d->dev; 698 struct device_node *wkup_np __free(device_node) = NULL; 699 struct device_node *np; 700 struct samsung_pin_bank *bank; 701 struct exynos_weint_data *weint_data; 702 struct exynos_muxed_weint_data *muxed_data; 703 const struct exynos_irq_chip *irq_chip; 704 unsigned int muxed_banks = 0; 705 unsigned int i; 706 int idx, irq; 707 708 for_each_child_of_node(dev->of_node, np) { 709 const struct of_device_id *match; 710 711 match = of_match_node(exynos_wkup_irq_ids, np); 712 if (match) { 713 irq_chip = match->data; 714 wkup_np = np; 715 break; 716 } 717 } 718 if (!wkup_np) 719 return -ENODEV; 720 721 bank = d->pin_banks; 722 for (i = 0; i < d->nr_banks; ++i, ++bank) { 723 if (bank->eint_type != EINT_TYPE_WKUP) 724 continue; 725 726 bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), 727 GFP_KERNEL); 728 if (!bank->irq_chip) 729 return -ENOMEM; 730 bank->irq_chip->chip.name = bank->name; 731 732 bank->irq_domain = irq_domain_create_linear(bank->fwnode, 733 bank->nr_pins, &exynos_eint_irqd_ops, bank); 734 if (!bank->irq_domain) { 735 dev_err(dev, "wkup irq domain add failed\n"); 736 return -ENXIO; 737 } 738 739 if (!fwnode_property_present(bank->fwnode, "interrupts")) { 740 bank->eint_type = EINT_TYPE_WKUP_MUX; 741 ++muxed_banks; 742 continue; 743 } 744 745 weint_data = devm_kcalloc(dev, 746 bank->nr_pins, sizeof(*weint_data), 747 GFP_KERNEL); 748 if (!weint_data) 749 return -ENOMEM; 750 751 for (idx = 0; idx < bank->nr_pins; ++idx) { 752 irq = irq_of_parse_and_map(to_of_node(bank->fwnode), idx); 753 if (!irq) { 754 dev_err(dev, "irq number for eint-%s-%d not found\n", 755 bank->name, idx); 756 continue; 757 } 758 weint_data[idx].irq = idx; 759 weint_data[idx].bank = bank; 760 irq_set_chained_handler_and_data(irq, 761 exynos_irq_eint0_15, 762 &weint_data[idx]); 763 } 764 } 765 766 if (!muxed_banks) 767 return 0; 768 769 irq = irq_of_parse_and_map(wkup_np, 0); 770 if (!irq) { 771 dev_err(dev, "irq number for muxed EINTs not found\n"); 772 return 0; 773 } 774 775 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data) 776 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL); 777 if (!muxed_data) 778 return -ENOMEM; 779 muxed_data->nr_banks = muxed_banks; 780 781 irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31, 782 muxed_data); 783 784 bank = d->pin_banks; 785 idx = 0; 786 for (i = 0; i < d->nr_banks; ++i, ++bank) { 787 if (bank->eint_type != EINT_TYPE_WKUP_MUX) 788 continue; 789 790 muxed_data->banks[idx++] = bank; 791 } 792 793 return 0; 794 } 795 796 static void exynos_set_wakeup(struct samsung_pin_bank *bank) 797 { 798 struct exynos_irq_chip *irq_chip; 799 800 if (bank->irq_chip) { 801 irq_chip = bank->irq_chip; 802 irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip); 803 } 804 } 805 806 void exynos_pinctrl_suspend(struct samsung_pin_bank *bank) 807 { 808 struct exynos_eint_gpio_save *save = bank->soc_priv; 809 const void __iomem *regs = bank->eint_base; 810 811 if (bank->eint_type == EINT_TYPE_GPIO) { 812 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET 813 + bank->eint_offset); 814 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 815 + 2 * bank->eint_offset); 816 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 817 + 2 * bank->eint_offset + 4); 818 save->eint_mask = readl(regs + bank->irq_chip->eint_mask 819 + bank->eint_offset); 820 821 pr_debug("%s: save con %#010x\n", 822 bank->name, save->eint_con); 823 pr_debug("%s: save fltcon0 %#010x\n", 824 bank->name, save->eint_fltcon0); 825 pr_debug("%s: save fltcon1 %#010x\n", 826 bank->name, save->eint_fltcon1); 827 pr_debug("%s: save mask %#010x\n", 828 bank->name, save->eint_mask); 829 } else if (bank->eint_type == EINT_TYPE_WKUP) { 830 exynos_set_wakeup(bank); 831 } 832 } 833 834 void gs101_pinctrl_suspend(struct samsung_pin_bank *bank) 835 { 836 struct exynos_eint_gpio_save *save = bank->soc_priv; 837 const void __iomem *regs = bank->eint_base; 838 839 if (bank->eint_type == EINT_TYPE_GPIO) { 840 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET 841 + bank->eint_offset); 842 843 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 844 + bank->eint_fltcon_offset); 845 846 /* fltcon1 register only exists for pins 4-7 */ 847 if (bank->nr_pins > 4) 848 save->eint_fltcon1 = readl(regs + 849 EXYNOS_GPIO_EFLTCON_OFFSET 850 + bank->eint_fltcon_offset + 4); 851 852 save->eint_mask = readl(regs + bank->irq_chip->eint_mask 853 + bank->eint_offset); 854 855 pr_debug("%s: save con %#010x\n", 856 bank->name, save->eint_con); 857 pr_debug("%s: save fltcon0 %#010x\n", 858 bank->name, save->eint_fltcon0); 859 if (bank->nr_pins > 4) 860 pr_debug("%s: save fltcon1 %#010x\n", 861 bank->name, save->eint_fltcon1); 862 pr_debug("%s: save mask %#010x\n", 863 bank->name, save->eint_mask); 864 } else if (bank->eint_type == EINT_TYPE_WKUP) { 865 exynos_set_wakeup(bank); 866 exynos_eint_set_filter(bank, EXYNOS_FLTCON_ANALOG); 867 } 868 } 869 870 void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank) 871 { 872 struct exynos_eint_gpio_save *save = bank->soc_priv; 873 const void __iomem *regs = bank->eint_base; 874 875 if (bank->eint_type == EINT_TYPE_GPIO) { 876 save->eint_con = readl(regs + bank->pctl_offset + 877 bank->eint_con_offset); 878 save->eint_mask = readl(regs + bank->pctl_offset + 879 bank->eint_mask_offset); 880 pr_debug("%s: save con %#010x\n", 881 bank->name, save->eint_con); 882 pr_debug("%s: save mask %#010x\n", 883 bank->name, save->eint_mask); 884 } else if (bank->eint_type == EINT_TYPE_WKUP) { 885 exynos_set_wakeup(bank); 886 } 887 } 888 889 void gs101_pinctrl_resume(struct samsung_pin_bank *bank) 890 { 891 struct exynos_eint_gpio_save *save = bank->soc_priv; 892 893 void __iomem *regs = bank->eint_base; 894 void __iomem *eint_fltcfg0 = regs + EXYNOS_GPIO_EFLTCON_OFFSET 895 + bank->eint_fltcon_offset; 896 897 if (bank->eint_type == EINT_TYPE_GPIO) { 898 pr_debug("%s: con %#010x => %#010x\n", bank->name, 899 readl(regs + EXYNOS_GPIO_ECON_OFFSET 900 + bank->eint_offset), save->eint_con); 901 902 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, 903 readl(eint_fltcfg0), save->eint_fltcon0); 904 905 /* fltcon1 register only exists for pins 4-7 */ 906 if (bank->nr_pins > 4) 907 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, 908 readl(eint_fltcfg0 + 4), save->eint_fltcon1); 909 910 pr_debug("%s: mask %#010x => %#010x\n", bank->name, 911 readl(regs + bank->irq_chip->eint_mask 912 + bank->eint_offset), save->eint_mask); 913 914 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET 915 + bank->eint_offset); 916 writel(save->eint_fltcon0, eint_fltcfg0); 917 918 if (bank->nr_pins > 4) 919 writel(save->eint_fltcon1, eint_fltcfg0 + 4); 920 writel(save->eint_mask, regs + bank->irq_chip->eint_mask 921 + bank->eint_offset); 922 } else if (bank->eint_type == EINT_TYPE_WKUP) { 923 exynos_eint_set_filter(bank, EXYNOS_FLTCON_DIGITAL); 924 } 925 } 926 927 void exynos_pinctrl_resume(struct samsung_pin_bank *bank) 928 { 929 struct exynos_eint_gpio_save *save = bank->soc_priv; 930 void __iomem *regs = bank->eint_base; 931 932 if (bank->eint_type == EINT_TYPE_GPIO) { 933 pr_debug("%s: con %#010x => %#010x\n", bank->name, 934 readl(regs + EXYNOS_GPIO_ECON_OFFSET 935 + bank->eint_offset), save->eint_con); 936 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, 937 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 938 + 2 * bank->eint_offset), save->eint_fltcon0); 939 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, 940 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 941 + 2 * bank->eint_offset + 4), 942 save->eint_fltcon1); 943 pr_debug("%s: mask %#010x => %#010x\n", bank->name, 944 readl(regs + bank->irq_chip->eint_mask 945 + bank->eint_offset), save->eint_mask); 946 947 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET 948 + bank->eint_offset); 949 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET 950 + 2 * bank->eint_offset); 951 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET 952 + 2 * bank->eint_offset + 4); 953 writel(save->eint_mask, regs + bank->irq_chip->eint_mask 954 + bank->eint_offset); 955 } 956 } 957 958 void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank) 959 { 960 struct exynos_eint_gpio_save *save = bank->soc_priv; 961 void __iomem *regs = bank->eint_base; 962 963 if (bank->eint_type == EINT_TYPE_GPIO) { 964 /* exynosautov920 has eint_con_offset for all but one bank */ 965 if (!bank->eint_con_offset) 966 exynos_pinctrl_resume(bank); 967 968 pr_debug("%s: con %#010x => %#010x\n", bank->name, 969 readl(regs + bank->pctl_offset + bank->eint_con_offset), 970 save->eint_con); 971 pr_debug("%s: mask %#010x => %#010x\n", bank->name, 972 readl(regs + bank->pctl_offset + 973 bank->eint_mask_offset), save->eint_mask); 974 975 writel(save->eint_con, 976 regs + bank->pctl_offset + bank->eint_con_offset); 977 writel(save->eint_mask, 978 regs + bank->pctl_offset + bank->eint_mask_offset); 979 } 980 } 981 982 static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) 983 { 984 if (drvdata->retention_ctrl->refcnt) 985 atomic_inc(drvdata->retention_ctrl->refcnt); 986 } 987 988 static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata) 989 { 990 struct samsung_retention_ctrl *ctrl = drvdata->retention_ctrl; 991 struct regmap *pmu_regs = ctrl->priv; 992 int i; 993 994 if (ctrl->refcnt && !atomic_dec_and_test(ctrl->refcnt)) 995 return; 996 997 for (i = 0; i < ctrl->nr_regs; i++) 998 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); 999 } 1000 1001 struct samsung_retention_ctrl * 1002 exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, 1003 const struct samsung_retention_data *data) 1004 { 1005 struct samsung_retention_ctrl *ctrl; 1006 struct regmap *pmu_regs; 1007 int i; 1008 1009 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); 1010 if (!ctrl) 1011 return ERR_PTR(-ENOMEM); 1012 1013 pmu_regs = exynos_get_pmu_regmap(); 1014 if (IS_ERR(pmu_regs)) 1015 return ERR_CAST(pmu_regs); 1016 1017 ctrl->priv = pmu_regs; 1018 ctrl->regs = data->regs; 1019 ctrl->nr_regs = data->nr_regs; 1020 ctrl->value = data->value; 1021 ctrl->refcnt = data->refcnt; 1022 ctrl->enable = exynos_retention_enable; 1023 ctrl->disable = exynos_retention_disable; 1024 1025 /* Ensure that retention is disabled on driver init */ 1026 for (i = 0; i < ctrl->nr_regs; i++) 1027 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); 1028 1029 return ctrl; 1030 } 1031