1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Raspberry Pi RP1 GPIO unit
4 *
5 * Copyright (C) 2023 Raspberry Pi Ltd.
6 *
7 * This driver is inspired by:
8 * pinctrl-bcm2835.c, please see original file for copyright information
9 */
10
11 #include <linux/gpio/driver.h>
12 #include <linux/of_irq.h>
13 #include <linux/pinctrl/pinconf.h>
14 #include <linux/pinctrl/pinmux.h>
15 #include <linux/platform_device.h>
16 #include <linux/seq_file.h>
17 #include <linux/regmap.h>
18
19 #include "pinmux.h"
20 #include "pinconf.h"
21 #include "pinctrl-utils.h"
22
23 #define MODULE_NAME "pinctrl-rp1"
24 #define RP1_NUM_GPIOS 54
25 #define RP1_NUM_BANKS 3
26
27 #define RP1_INT_EDGE_FALLING BIT(0)
28 #define RP1_INT_EDGE_RISING BIT(1)
29 #define RP1_INT_LEVEL_LOW BIT(2)
30 #define RP1_INT_LEVEL_HIGH BIT(3)
31 #define RP1_INT_MASK GENMASK(3, 0)
32 #define RP1_INT_EDGE_BOTH (RP1_INT_EDGE_FALLING | \
33 RP1_INT_EDGE_RISING)
34
35 #define RP1_FSEL_COUNT 9
36
37 #define RP1_FSEL_ALT0 0x00
38 #define RP1_FSEL_GPIO 0x05
39 #define RP1_FSEL_NONE 0x09
40 #define RP1_FSEL_NONE_HW 0x1f
41
42 #define RP1_PAD_DRIVE_2MA 0x0
43 #define RP1_PAD_DRIVE_4MA 0x1
44 #define RP1_PAD_DRIVE_8MA 0x2
45 #define RP1_PAD_DRIVE_12MA 0x3
46
47 enum {
48 RP1_PUD_OFF = 0,
49 RP1_PUD_DOWN = 1,
50 RP1_PUD_UP = 2,
51 };
52
53 enum {
54 RP1_DIR_OUTPUT = 0,
55 RP1_DIR_INPUT = 1,
56 };
57
58 enum {
59 RP1_OUTOVER_PERI = 0,
60 RP1_OUTOVER_INVPERI = 1,
61 RP1_OUTOVER_LOW = 2,
62 RP1_OUTOVER_HIGH = 3,
63 };
64
65 enum {
66 RP1_OEOVER_PERI = 0,
67 RP1_OEOVER_INVPERI = 1,
68 RP1_OEOVER_DISABLE = 2,
69 RP1_OEOVER_ENABLE = 3,
70 };
71
72 enum {
73 RP1_INOVER_PERI = 0,
74 RP1_INOVER_INVPERI = 1,
75 RP1_INOVER_LOW = 2,
76 RP1_INOVER_HIGH = 3,
77 };
78
79 enum {
80 RP1_GPIO_CTRL_IRQRESET_SET = 0,
81 RP1_GPIO_CTRL_INT_CLR = 1,
82 RP1_GPIO_CTRL_INT_SET = 2,
83 RP1_GPIO_CTRL_OEOVER = 3,
84 RP1_GPIO_CTRL_FUNCSEL = 4,
85 RP1_GPIO_CTRL_OUTOVER = 5,
86 RP1_GPIO_CTRL = 6,
87 };
88
89 enum {
90 RP1_INTE_SET = 0,
91 RP1_INTE_CLR = 1,
92 };
93
94 enum {
95 RP1_RIO_OUT_SET = 0,
96 RP1_RIO_OUT_CLR = 1,
97 RP1_RIO_OE = 2,
98 RP1_RIO_OE_SET = 3,
99 RP1_RIO_OE_CLR = 4,
100 RP1_RIO_IN = 5,
101 };
102
103 enum {
104 RP1_PAD_SLEWFAST = 0,
105 RP1_PAD_SCHMITT = 1,
106 RP1_PAD_PULL = 2,
107 RP1_PAD_DRIVE = 3,
108 RP1_PAD_IN_ENABLE = 4,
109 RP1_PAD_OUT_DISABLE = 5,
110 };
111
112 static const struct reg_field rp1_gpio_fields[] = {
113 [RP1_GPIO_CTRL_IRQRESET_SET] = REG_FIELD(0x2004, 28, 28),
114 [RP1_GPIO_CTRL_INT_CLR] = REG_FIELD(0x3004, 20, 23),
115 [RP1_GPIO_CTRL_INT_SET] = REG_FIELD(0x2004, 20, 23),
116 [RP1_GPIO_CTRL_OEOVER] = REG_FIELD(0x0004, 14, 15),
117 [RP1_GPIO_CTRL_FUNCSEL] = REG_FIELD(0x0004, 0, 4),
118 [RP1_GPIO_CTRL_OUTOVER] = REG_FIELD(0x0004, 12, 13),
119 [RP1_GPIO_CTRL] = REG_FIELD(0x0004, 0, 31),
120 };
121
122 static const struct reg_field rp1_inte_fields[] = {
123 [RP1_INTE_SET] = REG_FIELD(0x2000, 0, 0),
124 [RP1_INTE_CLR] = REG_FIELD(0x3000, 0, 0),
125 };
126
127 static const struct reg_field rp1_rio_fields[] = {
128 [RP1_RIO_OUT_SET] = REG_FIELD(0x2000, 0, 0),
129 [RP1_RIO_OUT_CLR] = REG_FIELD(0x3000, 0, 0),
130 [RP1_RIO_OE] = REG_FIELD(0x0004, 0, 0),
131 [RP1_RIO_OE_SET] = REG_FIELD(0x2004, 0, 0),
132 [RP1_RIO_OE_CLR] = REG_FIELD(0x3004, 0, 0),
133 [RP1_RIO_IN] = REG_FIELD(0x0008, 0, 0),
134 };
135
136 static const struct reg_field rp1_pad_fields[] = {
137 [RP1_PAD_SLEWFAST] = REG_FIELD(0, 0, 0),
138 [RP1_PAD_SCHMITT] = REG_FIELD(0, 1, 1),
139 [RP1_PAD_PULL] = REG_FIELD(0, 2, 3),
140 [RP1_PAD_DRIVE] = REG_FIELD(0, 4, 5),
141 [RP1_PAD_IN_ENABLE] = REG_FIELD(0, 6, 6),
142 [RP1_PAD_OUT_DISABLE] = REG_FIELD(0, 7, 7),
143 };
144
145 #define FUNC(f) \
146 [func_##f] = #f
147 #define RP1_MAX_FSEL 8
148 #define PIN(i, f0, f1, f2, f3, f4, f5, f6, f7, f8) \
149 [i] = { \
150 .funcs = { \
151 func_##f0, \
152 func_##f1, \
153 func_##f2, \
154 func_##f3, \
155 func_##f4, \
156 func_##f5, \
157 func_##f6, \
158 func_##f7, \
159 func_##f8, \
160 }, \
161 }
162
163 #define LEGACY_MAP(n, f0, f1, f2, f3, f4, f5) \
164 [n] = { \
165 func_gpio, \
166 func_gpio, \
167 func_##f5, \
168 func_##f4, \
169 func_##f0, \
170 func_##f1, \
171 func_##f2, \
172 func_##f3, \
173 }
174
175 enum funcs {
176 func_alt0,
177 func_alt1,
178 func_alt2,
179 func_alt3,
180 func_alt4,
181 func_gpio,
182 func_alt6,
183 func_alt7,
184 func_alt8,
185 func_none,
186 func_aaud,
187 func_dpi,
188 func_dsi0_te_ext,
189 func_dsi1_te_ext,
190 func_gpclk0,
191 func_gpclk1,
192 func_gpclk2,
193 func_gpclk3,
194 func_gpclk4,
195 func_gpclk5,
196 func_i2c0,
197 func_i2c1,
198 func_i2c2,
199 func_i2c3,
200 func_i2c4,
201 func_i2c5,
202 func_i2c6,
203 func_i2s0,
204 func_i2s1,
205 func_i2s2,
206 func_ir,
207 func_mic,
208 func_pcie_clkreq_n,
209 func_pio,
210 func_proc_rio,
211 func_pwm0,
212 func_pwm1,
213 func_sd0,
214 func_sd1,
215 func_spi0,
216 func_spi1,
217 func_spi2,
218 func_spi3,
219 func_spi4,
220 func_spi5,
221 func_spi6,
222 func_spi7,
223 func_spi8,
224 func_uart0,
225 func_uart1,
226 func_uart2,
227 func_uart3,
228 func_uart4,
229 func_uart5,
230 func_vbus0,
231 func_vbus1,
232 func_vbus2,
233 func_vbus3,
234 func__,
235 func_count = func__,
236 func_invalid = func__,
237 };
238
239 struct rp1_pin_funcs {
240 u8 funcs[RP1_FSEL_COUNT];
241 };
242
243 struct rp1_iobank_desc {
244 int min_gpio;
245 int num_gpios;
246 int gpio_offset;
247 int inte_offset;
248 int ints_offset;
249 int rio_offset;
250 int pads_offset;
251 };
252
253 struct rp1_pin_info {
254 u8 num;
255 u8 bank;
256 u8 offset;
257 u8 fsel;
258 u8 irq_type;
259
260 struct regmap_field *gpio[ARRAY_SIZE(rp1_gpio_fields)];
261 struct regmap_field *rio[ARRAY_SIZE(rp1_rio_fields)];
262 struct regmap_field *inte[ARRAY_SIZE(rp1_inte_fields)];
263 struct regmap_field *pad[ARRAY_SIZE(rp1_pad_fields)];
264 };
265
266 struct rp1_pinctrl {
267 struct device *dev;
268 void __iomem *gpio_base;
269 void __iomem *rio_base;
270 void __iomem *pads_base;
271 int irq[RP1_NUM_BANKS];
272 struct rp1_pin_info pins[RP1_NUM_GPIOS];
273
274 struct pinctrl_dev *pctl_dev;
275 struct gpio_chip gpio_chip;
276 struct pinctrl_gpio_range gpio_range;
277
278 raw_spinlock_t irq_lock[RP1_NUM_BANKS];
279 };
280
281 /* pins are just named GPIO0..GPIO53 */
282 #define RP1_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
283 static struct pinctrl_pin_desc rp1_gpio_pins[] = {
284 RP1_GPIO_PIN(0),
285 RP1_GPIO_PIN(1),
286 RP1_GPIO_PIN(2),
287 RP1_GPIO_PIN(3),
288 RP1_GPIO_PIN(4),
289 RP1_GPIO_PIN(5),
290 RP1_GPIO_PIN(6),
291 RP1_GPIO_PIN(7),
292 RP1_GPIO_PIN(8),
293 RP1_GPIO_PIN(9),
294 RP1_GPIO_PIN(10),
295 RP1_GPIO_PIN(11),
296 RP1_GPIO_PIN(12),
297 RP1_GPIO_PIN(13),
298 RP1_GPIO_PIN(14),
299 RP1_GPIO_PIN(15),
300 RP1_GPIO_PIN(16),
301 RP1_GPIO_PIN(17),
302 RP1_GPIO_PIN(18),
303 RP1_GPIO_PIN(19),
304 RP1_GPIO_PIN(20),
305 RP1_GPIO_PIN(21),
306 RP1_GPIO_PIN(22),
307 RP1_GPIO_PIN(23),
308 RP1_GPIO_PIN(24),
309 RP1_GPIO_PIN(25),
310 RP1_GPIO_PIN(26),
311 RP1_GPIO_PIN(27),
312 RP1_GPIO_PIN(28),
313 RP1_GPIO_PIN(29),
314 RP1_GPIO_PIN(30),
315 RP1_GPIO_PIN(31),
316 RP1_GPIO_PIN(32),
317 RP1_GPIO_PIN(33),
318 RP1_GPIO_PIN(34),
319 RP1_GPIO_PIN(35),
320 RP1_GPIO_PIN(36),
321 RP1_GPIO_PIN(37),
322 RP1_GPIO_PIN(38),
323 RP1_GPIO_PIN(39),
324 RP1_GPIO_PIN(40),
325 RP1_GPIO_PIN(41),
326 RP1_GPIO_PIN(42),
327 RP1_GPIO_PIN(43),
328 RP1_GPIO_PIN(44),
329 RP1_GPIO_PIN(45),
330 RP1_GPIO_PIN(46),
331 RP1_GPIO_PIN(47),
332 RP1_GPIO_PIN(48),
333 RP1_GPIO_PIN(49),
334 RP1_GPIO_PIN(50),
335 RP1_GPIO_PIN(51),
336 RP1_GPIO_PIN(52),
337 RP1_GPIO_PIN(53),
338 };
339
340 #define PIN_ARRAY(...) \
341 (const unsigned int []) {__VA_ARGS__}
342 #define PIN_ARRAY_SIZE(...) \
343 (sizeof((unsigned int[]) {__VA_ARGS__}) / sizeof(unsigned int))
344 #define RP1_GROUP(name, ...) \
345 PINCTRL_PINGROUP(#name, PIN_ARRAY(__VA_ARGS__), \
346 PIN_ARRAY_SIZE(__VA_ARGS__))
347
348 static const struct pingroup rp1_gpio_groups[] = {
349 RP1_GROUP(uart0, 14, 15),
350 RP1_GROUP(uart0_ctrl, 4, 5, 6, 7, 16, 17),
351 RP1_GROUP(uart1, 0, 1),
352 RP1_GROUP(uart1_ctrl, 2, 3),
353 RP1_GROUP(uart2, 4, 5),
354 RP1_GROUP(uart2_ctrl, 6, 7),
355 RP1_GROUP(uart3, 8, 9),
356 RP1_GROUP(uart3_ctrl, 10, 11),
357 RP1_GROUP(uart4, 12, 13),
358 RP1_GROUP(uart4_ctrl, 14, 15),
359 RP1_GROUP(uart5_0, 30, 31),
360 RP1_GROUP(uart5_0_ctrl, 32, 33),
361 RP1_GROUP(uart5_1, 36, 37),
362 RP1_GROUP(uart5_1_ctrl, 38, 39),
363 RP1_GROUP(uart5_2, 40, 41),
364 RP1_GROUP(uart5_2_ctrl, 42, 43),
365 RP1_GROUP(uart5_3, 48, 49),
366 RP1_GROUP(sd0, 22, 23, 24, 25, 26, 27),
367 RP1_GROUP(sd1, 28, 29, 30, 31, 32, 33),
368 RP1_GROUP(i2s0, 18, 19, 20, 21),
369 RP1_GROUP(i2s0_dual, 18, 19, 20, 21, 22, 23),
370 RP1_GROUP(i2s0_quad, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27),
371 RP1_GROUP(i2s1, 18, 19, 20, 21),
372 RP1_GROUP(i2s1_dual, 18, 19, 20, 21, 22, 23),
373 RP1_GROUP(i2s1_quad, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27),
374 RP1_GROUP(i2s2_0, 28, 29, 30, 31),
375 RP1_GROUP(i2s2_0_dual, 28, 29, 30, 31, 32, 33),
376 RP1_GROUP(i2s2_1, 42, 43, 44, 45),
377 RP1_GROUP(i2s2_1_dual, 42, 43, 44, 45, 46, 47),
378 RP1_GROUP(i2c4_0, 28, 29),
379 RP1_GROUP(i2c4_1, 34, 35),
380 RP1_GROUP(i2c4_2, 40, 41),
381 RP1_GROUP(i2c4_3, 46, 47),
382 RP1_GROUP(i2c6_0, 38, 39),
383 RP1_GROUP(i2c6_1, 51, 52),
384 RP1_GROUP(i2c5_0, 30, 31),
385 RP1_GROUP(i2c5_1, 36, 37),
386 RP1_GROUP(i2c5_2, 44, 45),
387 RP1_GROUP(i2c5_3, 49, 50),
388 RP1_GROUP(i2c0_0, 0, 1),
389 RP1_GROUP(i2c0_1, 8, 9),
390 RP1_GROUP(i2c1_0, 2, 3),
391 RP1_GROUP(i2c1_1, 10, 11),
392 RP1_GROUP(i2c2_0, 4, 5),
393 RP1_GROUP(i2c2_1, 12, 13),
394 RP1_GROUP(i2c3_0, 6, 7),
395 RP1_GROUP(i2c3_1, 14, 15),
396 RP1_GROUP(i2c3_2, 22, 23),
397 RP1_GROUP(dpi_16bit, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
398 11, 12, 13, 14, 15, 16, 17, 18, 19),
399 RP1_GROUP(dpi_16bit_cpadhi, 0, 1, 2, 3, 4, 5, 6, 7, 8,
400 12, 13, 14, 15, 16, 17, 20, 21, 22, 23, 24),
401 RP1_GROUP(dpi_16bit_pad666, 0, 1, 2, 3, 5, 6, 7, 8, 9,
402 12, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25),
403 RP1_GROUP(dpi_18bit, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
404 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21),
405 RP1_GROUP(dpi_18bit_cpadhi, 0, 1, 2, 3, 4, 5, 6, 7, 8,
406 9, 12, 13, 14, 15, 16, 17, 20, 21, 22, 23, 24,
407 25),
408 RP1_GROUP(dpi_24bit, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
409 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
410 22, 23, 24, 25, 26, 27),
411 RP1_GROUP(spi0, 9, 10, 11),
412 RP1_GROUP(spi0_quad, 0, 1, 9, 10, 11),
413 RP1_GROUP(spi1, 19, 20, 21),
414 RP1_GROUP(spi2, 1, 2, 3),
415 RP1_GROUP(spi3, 5, 6, 7),
416 RP1_GROUP(spi4, 9, 10, 11),
417 RP1_GROUP(spi5, 13, 14, 15),
418 RP1_GROUP(spi6_0, 28, 29, 30),
419 RP1_GROUP(spi6_1, 40, 41, 42),
420 RP1_GROUP(spi7_0, 46, 47, 48),
421 RP1_GROUP(spi7_1, 49, 50, 51),
422 RP1_GROUP(spi8_0, 37, 38, 39),
423 RP1_GROUP(spi8_1, 49, 50, 51),
424 RP1_GROUP(aaud_0, 12, 13),
425 RP1_GROUP(aaud_1, 38, 39),
426 RP1_GROUP(aaud_2, 40, 41),
427 RP1_GROUP(aaud_3, 49, 50),
428 RP1_GROUP(aaud_4, 51, 52),
429 RP1_GROUP(vbus0_0, 28, 29),
430 RP1_GROUP(vbus0_1, 34, 35),
431 RP1_GROUP(vbus1, 42, 43),
432 RP1_GROUP(vbus2, 50, 51),
433 RP1_GROUP(vbus3, 52, 53),
434 RP1_GROUP(mic_0, 25, 26, 27),
435 RP1_GROUP(mic_1, 34, 35, 36),
436 RP1_GROUP(mic_2, 37, 38, 39),
437 RP1_GROUP(mic_3, 46, 47, 48),
438 RP1_GROUP(ir, 2, 3),
439 };
440
441 #define GRP_ARRAY(...) \
442 (const char * []) {__VA_ARGS__}
443 #define GRP_ARRAY_SIZE(...) \
444 (sizeof((char *[]) {__VA_ARGS__}) / sizeof(char *))
445 #define RP1_FNC(f, ...) \
446 [func_##f] = PINCTRL_PINFUNCTION(#f, GRP_ARRAY(__VA_ARGS__), \
447 GRP_ARRAY_SIZE(__VA_ARGS__))
448 #define RP1_NULL_FNC(f) \
449 [func_##f] = PINCTRL_PINFUNCTION(#f, NULL, 0)
450 #define RP1_ALL_LEGACY_PINS \
451 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", \
452 "gpio5", "gpio6", "gpio7", "gpio8", "gpio9", \
453 "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", \
454 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", \
455 "gpio20", "gpio21", "gpio22", "gpio32", "gpio24", \
456 "gpio25", "gpio26", "gpio27"
457 #define RP1_ALL_PINS RP1_ALL_LEGACY_PINS, \
458 "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", \
459 "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", \
460 "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", \
461 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", \
462 "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", \
463 "gpio53"
464
465 static const struct pinfunction rp1_func_names[] = {
466 RP1_NULL_FNC(alt0),
467 RP1_NULL_FNC(alt1),
468 RP1_NULL_FNC(alt2),
469 RP1_NULL_FNC(alt3),
470 RP1_NULL_FNC(alt4),
471 RP1_FNC(gpio, RP1_ALL_PINS),
472 RP1_NULL_FNC(alt6),
473 RP1_NULL_FNC(alt7),
474 RP1_NULL_FNC(alt8),
475 RP1_NULL_FNC(none),
476 RP1_FNC(aaud, "aaud_0", "aaud_1", "aaud_2", "aaud_3", "aaud_4",
477 "gpio12", "gpio13", "gpio38", "gpio39", "gpio40", "gpio41",
478 "gpio49", "gpio50", "gpio51", "gpio52"),
479 RP1_FNC(dpi, "dpi_16bit", "dpi_16bit_cpadhi",
480 "dpi_16bit_pad666", "dpi_18bit, dpi_18bit_cpadhi",
481 "dpi_24bit", RP1_ALL_LEGACY_PINS),
482 RP1_FNC(dsi0_te_ext, "gpio16", "gpio38", "gpio46"),
483 RP1_FNC(dsi1_te_ext, "gpio17", "gpio39", "gpio47"),
484 RP1_FNC(gpclk0, "gpio4", "gpio20"),
485 RP1_FNC(gpclk1, "gpio5", "gpio18", "gpio21"),
486 RP1_FNC(gpclk2, "gpio6"),
487 RP1_FNC(gpclk3, "gpio32", "gpio34", "gpio46"),
488 RP1_FNC(gpclk4, "gpio33", "gpio43"),
489 RP1_FNC(gpclk5, "gpio42", "gpio44", "gpio47"),
490 RP1_FNC(i2c0, "i2c0_0", "i2c0_1", "gpio0", "gpio1", "gpio8", "gpio9"),
491 RP1_FNC(i2c1, "i2c1_0", "i2c1_1", "gpio2", "gpio3", "gpio10", "gpio11"),
492 RP1_FNC(i2c2, "i2c2_0", "i2c2_1", "gpio4", "gpio5", "gpio12", "gpio13"),
493 RP1_FNC(i2c3, "i2c3_0", "i2c3_1", "i2c3_2", "gpio6", "gpio7", "gpio14",
494 "gpio15", "gpio22", "gpio23"),
495 RP1_FNC(i2c4, "i2c4_0", "i2c4_1", "i2c4_2", "i2c4_3", "gpio28",
496 "gpio29", "gpio34", "gpio35", "gpio40", "gpio41", "gpio46",
497 "gpio47"),
498 RP1_FNC(i2c5, "i2c5_0", "i2c5_1", "i2c5_2", "i2c5_3", "gpio30",
499 "gpio31", "gpio36", "gpio37", "gpio44", "gpio45", "gpio49",
500 "gpio50"),
501 RP1_FNC(i2c6, "i2c6_0", "i2c6_1", "gpio38", "gpio39", "gpio51",
502 "gpio52"),
503 RP1_FNC(i2s0, "i2s0", "i2s0_dual", "i2s0_quad", "gpio18", "gpio19",
504 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25",
505 "gpio26", "gpio27"),
506 RP1_FNC(i2s1, "i2s1", "i2s1_dual", "i2s1_quad", "gpio18", "gpio19",
507 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25",
508 "gpio26", "gpio27"),
509 RP1_FNC(i2s2, "i2s2_0", "i2s2_0_dual", "i2s2_1", "i2s2_1_dual",
510 "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33",
511 "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47"),
512 RP1_FNC(ir, "gpio2", "gpio3"),
513 RP1_FNC(mic, "mic_0", "mic_1", "mic_2", "mic_3", "gpio25", "gpio26",
514 "gpio27", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38",
515 "gpio39", "gpio46", "gpio47", "gpio48"),
516 RP1_FNC(pcie_clkreq_n, "gpio36", "gpio37", "gpio48", "gpio53"),
517 RP1_FNC(pio, RP1_ALL_LEGACY_PINS),
518 RP1_FNC(proc_rio, RP1_ALL_PINS),
519 RP1_FNC(pwm0, "gpio12", "gpio13", "gpio14", "gpio15", "gpio18",
520 "gpio19"),
521 RP1_FNC(pwm1, "gpio34", "gpio35", "gpio40", "gpio41", "gpio44",
522 "gpio45", "gpio48"),
523 RP1_FNC(sd0, "sd0", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
524 "gpio27"),
525 RP1_FNC(sd1, "sd1", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
526 "gpio33"),
527 RP1_FNC(spi0, "spi0", "spi0_quad", "gpio0", "gpio1", "gpio2", "gpio3",
528 "gpio7", "gpio8", "gpio9", "gpio10", "gpio11"),
529 RP1_FNC(spi1, "spi1", "gpio19", "gpio20", "gpio21", "gpio16", "gpio17",
530 "gpio18", "gpio27"),
531 RP1_FNC(spi2, "spi2", "gpio0", "gpio1", "gpio2", "gpio3", "gpio24"),
532 RP1_FNC(spi3, "spi3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio25"),
533 RP1_FNC(spi4, "spi4", "gpio8", "gpio9", "gpio10", "gpio11"),
534 RP1_FNC(spi5, "spi5", "gpio12", "gpio13", "gpio14", "gpio15", "gpio26"),
535 RP1_FNC(spi6, "spi6_0", "spi6_1", "gpio28", "gpio29", "gpio30",
536 "gpio31", "gpio32", "gpio33", "gpio40", "gpio41", "gpio42",
537 "gpio43", "gpio44", "gpio45"),
538 RP1_FNC(spi7, "spi7_0", "spi7_1", "gpio45", "gpio46", "gpio47",
539 "gpio48", "gpio49", "gpio50", "gpio51", "gpio53"),
540 RP1_FNC(spi8, "spi8_0", "spi8_1", "gpio35", "gpio36", "gpio37",
541 "gpio38", "gpio39", "gpio49", "gpio50", "gpio51", "gpio52",
542 "gpio53"),
543 RP1_FNC(uart0, "uart0", "uart0_ctrl", "gpio4", "gpio5", "gpio6",
544 "gpio7", "gpio14", "gpio15", "gpio16", "gpio17"),
545 RP1_FNC(uart1, "uart1", "uart1_ctrl", "gpio0", "gpio1", "gpio2",
546 "gpio3"),
547 RP1_FNC(uart2, "uart2", "uart2_ctrl", "gpio4", "gpio5", "gpio6",
548 "gpio7"),
549 RP1_FNC(uart3, "uart3", "uart3_ctrl", "gpio8", "gpio9", "gpio10",
550 "gpio11"),
551 RP1_FNC(uart4, "uart4", "uart4_ctrl", "gpio12", "gpio13", "gpio14",
552 "gpio15"),
553 RP1_FNC(uart5, "uart5_0", "uart5_0_ctrl", "uart5_1", "uart5_1_ctrl",
554 "uart5_2", "uart5_2_ctrl", "uart5_3"),
555 RP1_FNC(vbus0, "vbus0_0", "vbus0_1", "gpio28", "gpio29", "gpio34",
556 "gpio35"),
557 RP1_FNC(vbus1, "vbus1", "gpio42", "gpio43"),
558 RP1_FNC(vbus2, "vbus2", "gpio50", "gpio51"),
559 RP1_FNC(vbus3, "vbus3", "gpio52", "gpio53"),
560 RP1_NULL_FNC(invalid), //[func_invalid] = "?"
561 };
562
563 static const struct rp1_pin_funcs rp1_gpio_pin_funcs[] = {
564 PIN(0, spi0, dpi, uart1, i2c0, _, gpio, proc_rio, pio, spi2),
565 PIN(1, spi0, dpi, uart1, i2c0, _, gpio, proc_rio, pio, spi2),
566 PIN(2, spi0, dpi, uart1, i2c1, ir, gpio, proc_rio, pio, spi2),
567 PIN(3, spi0, dpi, uart1, i2c1, ir, gpio, proc_rio, pio, spi2),
568 PIN(4, gpclk0, dpi, uart2, i2c2, uart0, gpio, proc_rio, pio, spi3),
569 PIN(5, gpclk1, dpi, uart2, i2c2, uart0, gpio, proc_rio, pio, spi3),
570 PIN(6, gpclk2, dpi, uart2, i2c3, uart0, gpio, proc_rio, pio, spi3),
571 PIN(7, spi0, dpi, uart2, i2c3, uart0, gpio, proc_rio, pio, spi3),
572 PIN(8, spi0, dpi, uart3, i2c0, _, gpio, proc_rio, pio, spi4),
573 PIN(9, spi0, dpi, uart3, i2c0, _, gpio, proc_rio, pio, spi4),
574 PIN(10, spi0, dpi, uart3, i2c1, _, gpio, proc_rio, pio, spi4),
575 PIN(11, spi0, dpi, uart3, i2c1, _, gpio, proc_rio, pio, spi4),
576 PIN(12, pwm0, dpi, uart4, i2c2, aaud, gpio, proc_rio, pio, spi5),
577 PIN(13, pwm0, dpi, uart4, i2c2, aaud, gpio, proc_rio, pio, spi5),
578 PIN(14, pwm0, dpi, uart4, i2c3, uart0, gpio, proc_rio, pio, spi5),
579 PIN(15, pwm0, dpi, uart4, i2c3, uart0, gpio, proc_rio, pio, spi5),
580 PIN(16, spi1, dpi, dsi0_te_ext, _, uart0, gpio, proc_rio, pio, _),
581 PIN(17, spi1, dpi, dsi1_te_ext, _, uart0, gpio, proc_rio, pio, _),
582 PIN(18, spi1, dpi, i2s0, pwm0, i2s1, gpio, proc_rio, pio, gpclk1),
583 PIN(19, spi1, dpi, i2s0, pwm0, i2s1, gpio, proc_rio, pio, _),
584 PIN(20, spi1, dpi, i2s0, gpclk0, i2s1, gpio, proc_rio, pio, _),
585 PIN(21, spi1, dpi, i2s0, gpclk1, i2s1, gpio, proc_rio, pio, _),
586 PIN(22, sd0, dpi, i2s0, i2c3, i2s1, gpio, proc_rio, pio, _),
587 PIN(23, sd0, dpi, i2s0, i2c3, i2s1, gpio, proc_rio, pio, _),
588 PIN(24, sd0, dpi, i2s0, _, i2s1, gpio, proc_rio, pio, spi2),
589 PIN(25, sd0, dpi, i2s0, mic, i2s1, gpio, proc_rio, pio, spi3),
590 PIN(26, sd0, dpi, i2s0, mic, i2s1, gpio, proc_rio, pio, spi5),
591 PIN(27, sd0, dpi, i2s0, mic, i2s1, gpio, proc_rio, pio, spi1),
592 PIN(28, sd1, i2c4, i2s2, spi6, vbus0, gpio, proc_rio, _, _),
593 PIN(29, sd1, i2c4, i2s2, spi6, vbus0, gpio, proc_rio, _, _),
594 PIN(30, sd1, i2c5, i2s2, spi6, uart5, gpio, proc_rio, _, _),
595 PIN(31, sd1, i2c5, i2s2, spi6, uart5, gpio, proc_rio, _, _),
596 PIN(32, sd1, gpclk3, i2s2, spi6, uart5, gpio, proc_rio, _, _),
597 PIN(33, sd1, gpclk4, i2s2, spi6, uart5, gpio, proc_rio, _, _),
598 PIN(34, pwm1, gpclk3, vbus0, i2c4, mic, gpio, proc_rio, _, _),
599 PIN(35, spi8, pwm1, vbus0, i2c4, mic, gpio, proc_rio, _, _),
600 PIN(36, spi8, uart5, pcie_clkreq_n, i2c5, mic, gpio, proc_rio, _, _),
601 PIN(37, spi8, uart5, mic, i2c5, pcie_clkreq_n, gpio, proc_rio, _, _),
602 PIN(38, spi8, uart5, mic, i2c6, aaud, gpio, proc_rio, dsi0_te_ext, _),
603 PIN(39, spi8, uart5, mic, i2c6, aaud, gpio, proc_rio, dsi1_te_ext, _),
604 PIN(40, pwm1, uart5, i2c4, spi6, aaud, gpio, proc_rio, _, _),
605 PIN(41, pwm1, uart5, i2c4, spi6, aaud, gpio, proc_rio, _, _),
606 PIN(42, gpclk5, uart5, vbus1, spi6, i2s2, gpio, proc_rio, _, _),
607 PIN(43, gpclk4, uart5, vbus1, spi6, i2s2, gpio, proc_rio, _, _),
608 PIN(44, gpclk5, i2c5, pwm1, spi6, i2s2, gpio, proc_rio, _, _),
609 PIN(45, pwm1, i2c5, spi7, spi6, i2s2, gpio, proc_rio, _, _),
610 PIN(46, gpclk3, i2c4, spi7, mic, i2s2, gpio, proc_rio, dsi0_te_ext, _),
611 PIN(47, gpclk5, i2c4, spi7, mic, i2s2, gpio, proc_rio, dsi1_te_ext, _),
612 PIN(48, pwm1, pcie_clkreq_n, spi7, mic, uart5, gpio, proc_rio, _, _),
613 PIN(49, spi8, spi7, i2c5, aaud, uart5, gpio, proc_rio, _, _),
614 PIN(50, spi8, spi7, i2c5, aaud, vbus2, gpio, proc_rio, _, _),
615 PIN(51, spi8, spi7, i2c6, aaud, vbus2, gpio, proc_rio, _, _),
616 PIN(52, spi8, _, i2c6, aaud, vbus3, gpio, proc_rio, _, _),
617 PIN(53, spi8, spi7, _, pcie_clkreq_n, vbus3, gpio, proc_rio, _, _),
618 };
619
620 static const u8 legacy_fsel_map[][8] = {
621 LEGACY_MAP(0, i2c0, _, dpi, spi2, uart1, _),
622 LEGACY_MAP(1, i2c0, _, dpi, spi2, uart1, _),
623 LEGACY_MAP(2, i2c1, _, dpi, spi2, uart1, _),
624 LEGACY_MAP(3, i2c1, _, dpi, spi2, uart1, _),
625 LEGACY_MAP(4, gpclk0, _, dpi, spi3, uart2, i2c2),
626 LEGACY_MAP(5, gpclk1, _, dpi, spi3, uart2, i2c2),
627 LEGACY_MAP(6, gpclk2, _, dpi, spi3, uart2, i2c3),
628 LEGACY_MAP(7, spi0, _, dpi, spi3, uart2, i2c3),
629 LEGACY_MAP(8, spi0, _, dpi, _, uart3, i2c0),
630 LEGACY_MAP(9, spi0, _, dpi, _, uart3, i2c0),
631 LEGACY_MAP(10, spi0, _, dpi, _, uart3, i2c1),
632 LEGACY_MAP(11, spi0, _, dpi, _, uart3, i2c1),
633 LEGACY_MAP(12, pwm0, _, dpi, spi5, uart4, i2c2),
634 LEGACY_MAP(13, pwm0, _, dpi, spi5, uart4, i2c2),
635 LEGACY_MAP(14, uart0, _, dpi, spi5, uart4, _),
636 LEGACY_MAP(15, uart0, _, dpi, spi5, uart4, _),
637 LEGACY_MAP(16, _, _, dpi, uart0, spi1, _),
638 LEGACY_MAP(17, _, _, dpi, uart0, spi1, _),
639 LEGACY_MAP(18, i2s0, _, dpi, _, spi1, pwm0),
640 LEGACY_MAP(19, i2s0, _, dpi, _, spi1, pwm0),
641 LEGACY_MAP(20, i2s0, _, dpi, _, spi1, gpclk0),
642 LEGACY_MAP(21, i2s0, _, dpi, _, spi1, gpclk1),
643 LEGACY_MAP(22, sd0, _, dpi, _, _, i2c3),
644 LEGACY_MAP(23, sd0, _, dpi, _, _, i2c3),
645 LEGACY_MAP(24, sd0, _, dpi, _, _, spi2),
646 LEGACY_MAP(25, sd0, _, dpi, _, _, spi3),
647 LEGACY_MAP(26, sd0, _, dpi, _, _, spi5),
648 LEGACY_MAP(27, sd0, _, dpi, _, _, _),
649 };
650
651 static const char * const irq_type_names[] = {
652 [IRQ_TYPE_NONE] = "none",
653 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
654 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
655 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
656 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
657 [IRQ_TYPE_LEVEL_LOW] = "level-low",
658 };
659
660 static bool persist_gpio_outputs = true;
661 module_param(persist_gpio_outputs, bool, 0644);
662 MODULE_PARM_DESC(persist_gpio_outputs, "Enable GPIO_OUT persistence when pin is freed");
663
664 static const struct rp1_iobank_desc rp1_iobanks[RP1_NUM_BANKS] = {
665 /* gpio inte ints rio pads */
666 { 0, 28, 0x0000, 0x011c, 0x0124, 0x0000, 0x0004 },
667 { 28, 6, 0x4000, 0x411c, 0x4124, 0x4000, 0x4004 },
668 { 34, 20, 0x8000, 0x811c, 0x8124, 0x8000, 0x8004 },
669 };
670
671 static int rp1_pinconf_set(struct pinctrl_dev *pctldev,
672 unsigned int offset, unsigned long *configs,
673 unsigned int num_configs);
674
rp1_get_pin(struct gpio_chip * chip,unsigned int offset)675 static struct rp1_pin_info *rp1_get_pin(struct gpio_chip *chip,
676 unsigned int offset)
677 {
678 struct rp1_pinctrl *pc = gpiochip_get_data(chip);
679
680 if (pc && offset < RP1_NUM_GPIOS)
681 return &pc->pins[offset];
682 return NULL;
683 }
684
rp1_get_pin_pctl(struct pinctrl_dev * pctldev,unsigned int offset)685 static struct rp1_pin_info *rp1_get_pin_pctl(struct pinctrl_dev *pctldev,
686 unsigned int offset)
687 {
688 struct rp1_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
689
690 if (pc && offset < RP1_NUM_GPIOS)
691 return &pc->pins[offset];
692 return NULL;
693 }
694
rp1_input_enable(struct rp1_pin_info * pin,int value)695 static void rp1_input_enable(struct rp1_pin_info *pin, int value)
696 {
697 regmap_field_write(pin->pad[RP1_PAD_IN_ENABLE], !!value);
698 }
699
rp1_output_enable(struct rp1_pin_info * pin,int value)700 static void rp1_output_enable(struct rp1_pin_info *pin, int value)
701 {
702 regmap_field_write(pin->pad[RP1_PAD_OUT_DISABLE], !value);
703 }
704
rp1_get_fsel(struct rp1_pin_info * pin)705 static u32 rp1_get_fsel(struct rp1_pin_info *pin)
706 {
707 u32 oeover, fsel;
708
709 regmap_field_read(pin->gpio[RP1_GPIO_CTRL_OEOVER], &oeover);
710 regmap_field_read(pin->gpio[RP1_GPIO_CTRL_FUNCSEL], &fsel);
711
712 if (oeover != RP1_OEOVER_PERI || fsel >= RP1_FSEL_COUNT)
713 fsel = RP1_FSEL_NONE;
714
715 return fsel;
716 }
717
rp1_set_fsel(struct rp1_pin_info * pin,u32 fsel)718 static void rp1_set_fsel(struct rp1_pin_info *pin, u32 fsel)
719 {
720 if (fsel >= RP1_FSEL_COUNT)
721 fsel = RP1_FSEL_NONE_HW;
722
723 rp1_input_enable(pin, 1);
724 rp1_output_enable(pin, 1);
725
726 if (fsel == RP1_FSEL_NONE) {
727 regmap_field_write(pin->gpio[RP1_GPIO_CTRL_OEOVER], RP1_OEOVER_DISABLE);
728 } else {
729 regmap_field_write(pin->gpio[RP1_GPIO_CTRL_OUTOVER], RP1_OUTOVER_PERI);
730 regmap_field_write(pin->gpio[RP1_GPIO_CTRL_OEOVER], RP1_OEOVER_PERI);
731 }
732
733 regmap_field_write(pin->gpio[RP1_GPIO_CTRL_FUNCSEL], fsel);
734 }
735
rp1_get_dir(struct rp1_pin_info * pin)736 static int rp1_get_dir(struct rp1_pin_info *pin)
737 {
738 unsigned int val;
739
740 regmap_field_read(pin->rio[RP1_RIO_OE], &val);
741
742 return !val ? RP1_DIR_INPUT : RP1_DIR_OUTPUT;
743 }
744
rp1_set_dir(struct rp1_pin_info * pin,bool is_input)745 static void rp1_set_dir(struct rp1_pin_info *pin, bool is_input)
746 {
747 int reg = is_input ? RP1_RIO_OE_CLR : RP1_RIO_OE_SET;
748
749 regmap_field_write(pin->rio[reg], 1);
750 }
751
rp1_get_value(struct rp1_pin_info * pin)752 static int rp1_get_value(struct rp1_pin_info *pin)
753 {
754 unsigned int val;
755
756 regmap_field_read(pin->rio[RP1_RIO_IN], &val);
757
758 return !!val;
759 }
760
rp1_set_value(struct rp1_pin_info * pin,int value)761 static void rp1_set_value(struct rp1_pin_info *pin, int value)
762 {
763 /* Assume the pin is already an output */
764 int reg = value ? RP1_RIO_OUT_SET : RP1_RIO_OUT_CLR;
765
766 regmap_field_write(pin->rio[reg], 1);
767 }
768
rp1_gpio_get(struct gpio_chip * chip,unsigned int offset)769 static int rp1_gpio_get(struct gpio_chip *chip, unsigned int offset)
770 {
771 struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
772 int ret;
773
774 if (!pin)
775 return -EINVAL;
776
777 ret = rp1_get_value(pin);
778
779 return ret;
780 }
781
rp1_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)782 static int rp1_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
783 {
784 struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
785
786 if (pin)
787 rp1_set_value(pin, value);
788
789 return 0;
790 }
791
rp1_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)792 static int rp1_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
793 {
794 struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
795 u32 fsel;
796
797 if (!pin)
798 return -EINVAL;
799
800 fsel = rp1_get_fsel(pin);
801 if (fsel != RP1_FSEL_GPIO)
802 return -EINVAL;
803
804 return (rp1_get_dir(pin) == RP1_DIR_OUTPUT) ?
805 GPIO_LINE_DIRECTION_OUT :
806 GPIO_LINE_DIRECTION_IN;
807 }
808
rp1_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)809 static int rp1_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
810 {
811 struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
812
813 if (!pin)
814 return -EINVAL;
815 rp1_set_dir(pin, RP1_DIR_INPUT);
816 rp1_set_fsel(pin, RP1_FSEL_GPIO);
817
818 return 0;
819 }
820
rp1_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)821 static int rp1_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
822 int value)
823 {
824 struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
825
826 if (!pin)
827 return -EINVAL;
828 rp1_set_value(pin, value);
829 rp1_set_dir(pin, RP1_DIR_OUTPUT);
830 rp1_set_fsel(pin, RP1_FSEL_GPIO);
831
832 return 0;
833 }
834
rp1_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)835 static int rp1_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
836 unsigned long config)
837 {
838 struct rp1_pinctrl *pc = gpiochip_get_data(chip);
839 unsigned long configs[] = { config };
840
841 return rp1_pinconf_set(pc->pctl_dev, offset, configs,
842 ARRAY_SIZE(configs));
843 }
844
845 static const struct gpio_chip rp1_gpio_chip = {
846 .label = MODULE_NAME,
847 .owner = THIS_MODULE,
848 .request = gpiochip_generic_request,
849 .free = gpiochip_generic_free,
850 .direction_input = rp1_gpio_direction_input,
851 .direction_output = rp1_gpio_direction_output,
852 .get_direction = rp1_gpio_get_direction,
853 .get = rp1_gpio_get,
854 .set = rp1_gpio_set,
855 .base = -1,
856 .set_config = rp1_gpio_set_config,
857 .ngpio = RP1_NUM_GPIOS,
858 .can_sleep = false,
859 };
860
rp1_gpio_irq_handler(struct irq_desc * desc)861 static void rp1_gpio_irq_handler(struct irq_desc *desc)
862 {
863 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
864 struct irq_chip *host_chip = irq_desc_get_chip(desc);
865 struct rp1_pinctrl *pc = gpiochip_get_data(chip);
866 const struct rp1_iobank_desc *bank;
867 int irq = irq_desc_get_irq(desc);
868 unsigned long ints;
869 int bit_pos;
870
871 if (pc->irq[0] == irq)
872 bank = &rp1_iobanks[0];
873 else if (pc->irq[1] == irq)
874 bank = &rp1_iobanks[1];
875 else
876 bank = &rp1_iobanks[2];
877
878 chained_irq_enter(host_chip, desc);
879
880 ints = readl(pc->gpio_base + bank->ints_offset);
881 for_each_set_bit(bit_pos, &ints, 32) {
882 struct rp1_pin_info *pin = rp1_get_pin(chip, bit_pos);
883
884 regmap_field_write(pin->gpio[RP1_GPIO_CTRL_IRQRESET_SET], 1);
885 generic_handle_irq(irq_find_mapping(pc->gpio_chip.irq.domain,
886 bank->gpio_offset + bit_pos));
887 }
888
889 chained_irq_exit(host_chip, desc);
890 }
891
rp1_gpio_irq_config(struct rp1_pin_info * pin,bool enable)892 static void rp1_gpio_irq_config(struct rp1_pin_info *pin, bool enable)
893 {
894 int reg = enable ? RP1_INTE_SET : RP1_INTE_CLR;
895
896 regmap_field_write(pin->inte[reg], 1);
897 if (!enable)
898 /* Clear any latched events */
899 regmap_field_write(pin->gpio[RP1_GPIO_CTRL_IRQRESET_SET], 1);
900 }
901
rp1_gpio_irq_enable(struct irq_data * data)902 static void rp1_gpio_irq_enable(struct irq_data *data)
903 {
904 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
905 unsigned int gpio = irqd_to_hwirq(data);
906 struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
907
908 rp1_gpio_irq_config(pin, true);
909 }
910
rp1_gpio_irq_disable(struct irq_data * data)911 static void rp1_gpio_irq_disable(struct irq_data *data)
912 {
913 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
914 unsigned int gpio = irqd_to_hwirq(data);
915 struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
916
917 rp1_gpio_irq_config(pin, false);
918 }
919
rp1_irq_set_type(struct rp1_pin_info * pin,unsigned int type)920 static int rp1_irq_set_type(struct rp1_pin_info *pin, unsigned int type)
921 {
922 u32 irq_flags;
923
924 switch (type) {
925 case IRQ_TYPE_NONE:
926 irq_flags = 0;
927 break;
928 case IRQ_TYPE_EDGE_RISING:
929 irq_flags = RP1_INT_EDGE_RISING;
930 break;
931 case IRQ_TYPE_EDGE_FALLING:
932 irq_flags = RP1_INT_EDGE_FALLING;
933 break;
934 case IRQ_TYPE_EDGE_BOTH:
935 irq_flags = RP1_INT_EDGE_RISING | RP1_INT_EDGE_FALLING;
936 break;
937 case IRQ_TYPE_LEVEL_HIGH:
938 irq_flags = RP1_INT_LEVEL_HIGH;
939 break;
940 case IRQ_TYPE_LEVEL_LOW:
941 irq_flags = RP1_INT_LEVEL_LOW;
942 break;
943
944 default:
945 return -EINVAL;
946 }
947
948 /* Clear them all */
949 regmap_field_write(pin->gpio[RP1_GPIO_CTRL_INT_CLR], RP1_INT_MASK);
950
951 /* Set those that are needed */
952 regmap_field_write(pin->gpio[RP1_GPIO_CTRL_INT_SET], irq_flags);
953 pin->irq_type = type;
954
955 return 0;
956 }
957
rp1_gpio_irq_set_type(struct irq_data * data,unsigned int type)958 static int rp1_gpio_irq_set_type(struct irq_data *data, unsigned int type)
959 {
960 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
961 unsigned int gpio = irqd_to_hwirq(data);
962 struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
963 struct rp1_pinctrl *pc = gpiochip_get_data(chip);
964 int bank = pin->bank;
965 unsigned long flags;
966 int ret;
967
968 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
969
970 ret = rp1_irq_set_type(pin, type);
971 if (!ret) {
972 if (type & IRQ_TYPE_EDGE_BOTH)
973 irq_set_handler_locked(data, handle_edge_irq);
974 else
975 irq_set_handler_locked(data, handle_level_irq);
976 }
977
978 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
979
980 return ret;
981 }
982
rp1_gpio_irq_ack(struct irq_data * data)983 static void rp1_gpio_irq_ack(struct irq_data *data)
984 {
985 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
986 unsigned int gpio = irqd_to_hwirq(data);
987 struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
988
989 /* Clear any latched events */
990 regmap_field_write(pin->gpio[RP1_GPIO_CTRL_IRQRESET_SET], 1);
991 }
992
rp1_gpio_irq_set_affinity(struct irq_data * data,const struct cpumask * dest,bool force)993 static int rp1_gpio_irq_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force)
994 {
995 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
996 struct rp1_pinctrl *pc = gpiochip_get_data(chip);
997 const struct rp1_iobank_desc *bank;
998 struct irq_data *parent_data = NULL;
999 int i;
1000
1001 for (i = 0; i < 3; i++) {
1002 bank = &rp1_iobanks[i];
1003 if (data->hwirq >= bank->min_gpio &&
1004 data->hwirq < bank->min_gpio + bank->num_gpios) {
1005 parent_data = irq_get_irq_data(pc->irq[i]);
1006 break;
1007 }
1008 }
1009
1010 if (parent_data && parent_data->chip->irq_set_affinity)
1011 return parent_data->chip->irq_set_affinity(parent_data, dest, force);
1012
1013 return -EINVAL;
1014 }
1015
1016 static struct irq_chip rp1_gpio_irq_chip = {
1017 .name = MODULE_NAME,
1018 .irq_enable = rp1_gpio_irq_enable,
1019 .irq_disable = rp1_gpio_irq_disable,
1020 .irq_set_type = rp1_gpio_irq_set_type,
1021 .irq_ack = rp1_gpio_irq_ack,
1022 .irq_mask = rp1_gpio_irq_disable,
1023 .irq_unmask = rp1_gpio_irq_enable,
1024 .irq_set_affinity = rp1_gpio_irq_set_affinity,
1025 .flags = IRQCHIP_IMMUTABLE,
1026 GPIOCHIP_IRQ_RESOURCE_HELPERS,
1027 };
1028
rp1_pctl_get_groups_count(struct pinctrl_dev * pctldev)1029 static int rp1_pctl_get_groups_count(struct pinctrl_dev *pctldev)
1030 {
1031 return ARRAY_SIZE(rp1_gpio_groups) + ARRAY_SIZE(rp1_gpio_pins);
1032 }
1033
rp1_pctl_get_group_name(struct pinctrl_dev * pctldev,unsigned int selector)1034 static const char *rp1_pctl_get_group_name(struct pinctrl_dev *pctldev,
1035 unsigned int selector)
1036 {
1037 unsigned int ngroups = ARRAY_SIZE(rp1_gpio_groups);
1038
1039 if (selector < ngroups)
1040 return rp1_gpio_groups[selector].name;
1041
1042 return rp1_gpio_pins[selector - ngroups].name;
1043 }
1044
rp1_get_fsel_func(unsigned int pin,unsigned int fsel)1045 static enum funcs rp1_get_fsel_func(unsigned int pin, unsigned int fsel)
1046 {
1047 if (pin < RP1_NUM_GPIOS) {
1048 if (fsel < RP1_FSEL_COUNT)
1049 return rp1_gpio_pin_funcs[pin].funcs[fsel];
1050 else if (fsel == RP1_FSEL_NONE)
1051 return func_none;
1052 }
1053 return func_invalid;
1054 }
1055
rp1_pctl_get_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * num_pins)1056 static int rp1_pctl_get_group_pins(struct pinctrl_dev *pctldev,
1057 unsigned int selector,
1058 const unsigned int **pins,
1059 unsigned int *num_pins)
1060 {
1061 unsigned int ngroups = ARRAY_SIZE(rp1_gpio_groups);
1062
1063 if (selector < ngroups) {
1064 *pins = rp1_gpio_groups[selector].pins;
1065 *num_pins = rp1_gpio_groups[selector].npins;
1066 } else {
1067 *pins = &rp1_gpio_pins[selector - ngroups].number;
1068 *num_pins = 1;
1069 }
1070
1071 return 0;
1072 }
1073
rp1_pctl_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int offset)1074 static void rp1_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
1075 struct seq_file *s,
1076 unsigned int offset)
1077 {
1078 struct rp1_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1079 struct gpio_chip *chip = &pc->gpio_chip;
1080 struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1081 u32 fsel = rp1_get_fsel(pin);
1082 enum funcs func = rp1_get_fsel_func(offset, fsel);
1083 int value = rp1_get_value(pin);
1084 int irq = irq_find_mapping(chip->irq.domain, offset);
1085
1086 seq_printf(s, "function %s (%s) in %s; irq %d (%s)",
1087 rp1_func_names[fsel].name, rp1_func_names[func].name,
1088 value ? "hi" : "lo",
1089 irq, irq_type_names[pin->irq_type]);
1090 }
1091
rp1_pctl_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * maps,unsigned int num_maps)1092 static void rp1_pctl_dt_free_map(struct pinctrl_dev *pctldev,
1093 struct pinctrl_map *maps, unsigned int num_maps)
1094 {
1095 int i;
1096
1097 for (i = 0; i < num_maps; i++)
1098 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
1099 kfree(maps[i].data.configs.configs);
1100
1101 kfree(maps);
1102 }
1103
rp1_pctl_legacy_map_func(struct rp1_pinctrl * pc,struct device_node * np,u32 pin,u32 fnum,struct pinctrl_map * maps,unsigned int * num_maps)1104 static int rp1_pctl_legacy_map_func(struct rp1_pinctrl *pc,
1105 struct device_node *np, u32 pin, u32 fnum,
1106 struct pinctrl_map *maps,
1107 unsigned int *num_maps)
1108 {
1109 struct pinctrl_map *map = &maps[*num_maps];
1110 enum funcs func;
1111
1112 if (fnum >= ARRAY_SIZE(legacy_fsel_map[0])) {
1113 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
1114 return -EINVAL;
1115 }
1116
1117 if (pin < ARRAY_SIZE(legacy_fsel_map)) {
1118 func = legacy_fsel_map[pin][fnum];
1119 } else if (fnum < 2) {
1120 func = func_gpio;
1121 } else {
1122 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
1123 np, pin);
1124 return -EINVAL;
1125 }
1126
1127 map->type = PIN_MAP_TYPE_MUX_GROUP;
1128 map->data.mux.group = rp1_pctl_get_group_name(pc->pctl_dev,
1129 ARRAY_SIZE(rp1_gpio_groups)
1130 + pin);
1131 map->data.mux.function = rp1_func_names[func].name;
1132 (*num_maps)++;
1133
1134 return 0;
1135 }
1136
rp1_pctl_legacy_map_pull(struct rp1_pinctrl * pc,struct device_node * np,u32 pin,u32 pull,struct pinctrl_map * maps,unsigned int * num_maps)1137 static int rp1_pctl_legacy_map_pull(struct rp1_pinctrl *pc,
1138 struct device_node *np, u32 pin, u32 pull,
1139 struct pinctrl_map *maps,
1140 unsigned int *num_maps)
1141 {
1142 struct pinctrl_map *map = &maps[*num_maps];
1143 enum pin_config_param param;
1144 unsigned long *configs;
1145
1146 switch (pull) {
1147 case RP1_PUD_OFF:
1148 param = PIN_CONFIG_BIAS_DISABLE;
1149 break;
1150 case RP1_PUD_DOWN:
1151 param = PIN_CONFIG_BIAS_PULL_DOWN;
1152 break;
1153 case RP1_PUD_UP:
1154 param = PIN_CONFIG_BIAS_PULL_UP;
1155 break;
1156 default:
1157 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
1158 return -EINVAL;
1159 }
1160
1161 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
1162 if (!configs)
1163 return -ENOMEM;
1164
1165 configs[0] = pinconf_to_config_packed(param, 0);
1166 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
1167 map->data.configs.group_or_pin = rp1_gpio_pins[pin].name;
1168 map->data.configs.configs = configs;
1169 map->data.configs.num_configs = 1;
1170 (*num_maps)++;
1171
1172 return 0;
1173 }
1174
rp1_pctl_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps)1175 static int rp1_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
1176 struct device_node *np,
1177 struct pinctrl_map **map,
1178 unsigned int *num_maps)
1179 {
1180 struct rp1_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1181 struct property *pins, *funcs, *pulls;
1182 int num_pins, num_funcs, num_pulls, maps_per_pin;
1183 struct pinctrl_map *maps;
1184 unsigned long *configs = NULL;
1185 const char *function = NULL;
1186 unsigned int reserved_maps;
1187 int num_configs = 0;
1188 int i, err;
1189 u32 pin, func, pull;
1190
1191 /* Check for legacy pin declaration */
1192 pins = of_find_property(np, "brcm,pins", NULL);
1193
1194 if (!pins) /* Assume generic bindings in this node */
1195 return pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
1196
1197 funcs = of_find_property(np, "brcm,function", NULL);
1198 if (!funcs)
1199 of_property_read_string(np, "function", &function);
1200
1201 pulls = of_find_property(np, "brcm,pull", NULL);
1202 if (!pulls)
1203 pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs);
1204
1205 if (!function && !funcs && !num_configs && !pulls) {
1206 dev_err(pc->dev,
1207 "%pOF: no function, brcm,function, brcm,pull, etc.\n",
1208 np);
1209 return -EINVAL;
1210 }
1211
1212 num_pins = pins->length / 4;
1213 num_funcs = funcs ? (funcs->length / 4) : 0;
1214 num_pulls = pulls ? (pulls->length / 4) : 0;
1215
1216 if (num_funcs > 1 && num_funcs != num_pins) {
1217 dev_err(pc->dev,
1218 "%pOF: brcm,function must have 1 or %d entries\n",
1219 np, num_pins);
1220 return -EINVAL;
1221 }
1222
1223 if (num_pulls > 1 && num_pulls != num_pins) {
1224 dev_err(pc->dev,
1225 "%pOF: brcm,pull must have 1 or %d entries\n",
1226 np, num_pins);
1227 return -EINVAL;
1228 }
1229
1230 maps_per_pin = 0;
1231 if (function || num_funcs)
1232 maps_per_pin++;
1233 if (num_configs || num_pulls)
1234 maps_per_pin++;
1235 reserved_maps = num_pins * maps_per_pin;
1236 maps = kcalloc(reserved_maps, sizeof(*maps), GFP_KERNEL);
1237 if (!maps)
1238 return -ENOMEM;
1239
1240 *num_maps = 0;
1241
1242 for (i = 0; i < num_pins; i++) {
1243 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
1244 if (err)
1245 goto out;
1246 if (num_funcs) {
1247 err = of_property_read_u32_index(np, "brcm,function",
1248 (num_funcs > 1) ? i : 0,
1249 &func);
1250 if (err)
1251 goto out;
1252 err = rp1_pctl_legacy_map_func(pc, np, pin, func,
1253 maps, num_maps);
1254 } else if (function) {
1255 err = pinctrl_utils_add_map_mux(pctldev, &maps,
1256 &reserved_maps, num_maps,
1257 rp1_gpio_groups[pin].name,
1258 function);
1259 }
1260
1261 if (err)
1262 goto out;
1263
1264 if (num_pulls) {
1265 err = of_property_read_u32_index(np, "brcm,pull",
1266 (num_pulls > 1) ? i : 0,
1267 &pull);
1268 if (err)
1269 goto out;
1270 err = rp1_pctl_legacy_map_pull(pc, np, pin, pull,
1271 maps, num_maps);
1272 } else if (num_configs) {
1273 err = pinctrl_utils_add_map_configs(pctldev, &maps,
1274 &reserved_maps, num_maps,
1275 rp1_gpio_groups[pin].name,
1276 configs, num_configs,
1277 PIN_MAP_TYPE_CONFIGS_PIN);
1278 }
1279
1280 if (err)
1281 goto out;
1282 }
1283
1284 *map = maps;
1285
1286 return 0;
1287
1288 out:
1289 rp1_pctl_dt_free_map(pctldev, maps, reserved_maps);
1290 return err;
1291 }
1292
1293 static const struct pinctrl_ops rp1_pctl_ops = {
1294 .get_groups_count = rp1_pctl_get_groups_count,
1295 .get_group_name = rp1_pctl_get_group_name,
1296 .get_group_pins = rp1_pctl_get_group_pins,
1297 .pin_dbg_show = rp1_pctl_pin_dbg_show,
1298 .dt_node_to_map = rp1_pctl_dt_node_to_map,
1299 .dt_free_map = rp1_pctl_dt_free_map,
1300 };
1301
rp1_pmx_free(struct pinctrl_dev * pctldev,unsigned int offset)1302 static int rp1_pmx_free(struct pinctrl_dev *pctldev, unsigned int offset)
1303 {
1304 struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1305 u32 fsel = rp1_get_fsel(pin);
1306
1307 /* Return all pins to GPIO_IN, unless persist_gpio_outputs is set */
1308 if (persist_gpio_outputs && fsel == RP1_FSEL_GPIO)
1309 return 0;
1310
1311 rp1_set_dir(pin, RP1_DIR_INPUT);
1312 rp1_set_fsel(pin, RP1_FSEL_GPIO);
1313
1314 return 0;
1315 }
1316
rp1_pmx_get_functions_count(struct pinctrl_dev * pctldev)1317 static int rp1_pmx_get_functions_count(struct pinctrl_dev *pctldev)
1318 {
1319 return func_count;
1320 }
1321
rp1_pmx_get_function_name(struct pinctrl_dev * pctldev,unsigned int selector)1322 static const char *rp1_pmx_get_function_name(struct pinctrl_dev *pctldev,
1323 unsigned int selector)
1324 {
1325 return (selector < func_count) ? rp1_func_names[selector].name : NULL;
1326 }
1327
rp1_pmx_get_function_groups(struct pinctrl_dev * pctldev,unsigned int selector,const char * const ** groups,unsigned * const num_groups)1328 static int rp1_pmx_get_function_groups(struct pinctrl_dev *pctldev,
1329 unsigned int selector,
1330 const char * const **groups,
1331 unsigned * const num_groups)
1332 {
1333 *groups = rp1_func_names[selector].groups;
1334 *num_groups = rp1_func_names[selector].ngroups;
1335
1336 return 0;
1337 }
1338
rp1_pmx_set(struct pinctrl_dev * pctldev,unsigned int func_selector,unsigned int group_selector)1339 static int rp1_pmx_set(struct pinctrl_dev *pctldev, unsigned int func_selector,
1340 unsigned int group_selector)
1341 {
1342 struct rp1_pin_info *pin;
1343 const unsigned int *pins;
1344 const u8 *pin_funcs;
1345 unsigned int num_pins;
1346 int offset, fsel;
1347
1348 rp1_pctl_get_group_pins(pctldev, group_selector, &pins, &num_pins);
1349
1350 for (offset = 0; offset < num_pins; ++offset) {
1351 pin = rp1_get_pin_pctl(pctldev, pins[offset]);
1352 /* func_selector is an enum funcs, so needs translation */
1353 if (func_selector >= RP1_FSEL_COUNT) {
1354 /* Convert to an fsel number */
1355 pin_funcs = rp1_gpio_pin_funcs[pin->num].funcs;
1356 for (fsel = 0; fsel < RP1_FSEL_COUNT; fsel++) {
1357 if (pin_funcs[fsel] == func_selector)
1358 break;
1359 }
1360 } else {
1361 fsel = (int)func_selector;
1362 }
1363
1364 if (fsel >= RP1_FSEL_COUNT && fsel != RP1_FSEL_NONE)
1365 return -EINVAL;
1366
1367 rp1_set_fsel(pin, fsel);
1368 }
1369
1370 return 0;
1371 }
1372
rp1_pmx_gpio_disable_free(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)1373 static void rp1_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
1374 struct pinctrl_gpio_range *range,
1375 unsigned int offset)
1376 {
1377 (void)rp1_pmx_free(pctldev, offset);
1378 }
1379
rp1_pmx_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset,bool input)1380 static int rp1_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1381 struct pinctrl_gpio_range *range,
1382 unsigned int offset,
1383 bool input)
1384 {
1385 struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1386
1387 rp1_set_dir(pin, input);
1388 rp1_set_fsel(pin, RP1_FSEL_GPIO);
1389
1390 return 0;
1391 }
1392
1393 static const struct pinmux_ops rp1_pmx_ops = {
1394 .free = rp1_pmx_free,
1395 .get_functions_count = rp1_pmx_get_functions_count,
1396 .get_function_name = rp1_pmx_get_function_name,
1397 .get_function_groups = rp1_pmx_get_function_groups,
1398 .set_mux = rp1_pmx_set,
1399 .gpio_disable_free = rp1_pmx_gpio_disable_free,
1400 .gpio_set_direction = rp1_pmx_gpio_set_direction,
1401 };
1402
rp1_pull_config_set(struct rp1_pin_info * pin,unsigned int arg)1403 static void rp1_pull_config_set(struct rp1_pin_info *pin, unsigned int arg)
1404 {
1405 regmap_field_write(pin->pad[RP1_PAD_PULL], arg & 0x3);
1406 }
1407
rp1_pinconf_set(struct pinctrl_dev * pctldev,unsigned int offset,unsigned long * configs,unsigned int num_configs)1408 static int rp1_pinconf_set(struct pinctrl_dev *pctldev, unsigned int offset,
1409 unsigned long *configs, unsigned int num_configs)
1410 {
1411 struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1412 u32 param, arg;
1413 int i;
1414
1415 if (!pin)
1416 return -EINVAL;
1417
1418 for (i = 0; i < num_configs; i++) {
1419 param = pinconf_to_config_param(configs[i]);
1420 arg = pinconf_to_config_argument(configs[i]);
1421
1422 switch (param) {
1423 case PIN_CONFIG_BIAS_DISABLE:
1424 rp1_pull_config_set(pin, RP1_PUD_OFF);
1425 break;
1426
1427 case PIN_CONFIG_BIAS_PULL_DOWN:
1428 rp1_pull_config_set(pin, RP1_PUD_DOWN);
1429 break;
1430
1431 case PIN_CONFIG_BIAS_PULL_UP:
1432 rp1_pull_config_set(pin, RP1_PUD_UP);
1433 break;
1434
1435 case PIN_CONFIG_INPUT_ENABLE:
1436 rp1_input_enable(pin, arg);
1437 break;
1438
1439 case PIN_CONFIG_OUTPUT_ENABLE:
1440 rp1_output_enable(pin, arg);
1441 break;
1442
1443 case PIN_CONFIG_OUTPUT:
1444 rp1_set_value(pin, arg);
1445 rp1_set_dir(pin, RP1_DIR_OUTPUT);
1446 rp1_set_fsel(pin, RP1_FSEL_GPIO);
1447 break;
1448
1449 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1450 regmap_field_write(pin->pad[RP1_PAD_SCHMITT], !!arg);
1451 break;
1452
1453 case PIN_CONFIG_SLEW_RATE:
1454 regmap_field_write(pin->pad[RP1_PAD_SLEWFAST], !!arg);
1455 break;
1456
1457 case PIN_CONFIG_DRIVE_STRENGTH:
1458 switch (arg) {
1459 case 2:
1460 arg = RP1_PAD_DRIVE_2MA;
1461 break;
1462 case 4:
1463 arg = RP1_PAD_DRIVE_4MA;
1464 break;
1465 case 8:
1466 arg = RP1_PAD_DRIVE_8MA;
1467 break;
1468 case 12:
1469 arg = RP1_PAD_DRIVE_12MA;
1470 break;
1471 default:
1472 return -ENOTSUPP;
1473 }
1474 regmap_field_write(pin->pad[RP1_PAD_DRIVE], arg);
1475 break;
1476
1477 default:
1478 return -ENOTSUPP;
1479
1480 } /* switch param type */
1481 } /* for each config */
1482
1483 return 0;
1484 }
1485
rp1_pinconf_get(struct pinctrl_dev * pctldev,unsigned int offset,unsigned long * config)1486 static int rp1_pinconf_get(struct pinctrl_dev *pctldev, unsigned int offset,
1487 unsigned long *config)
1488 {
1489 struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1490 enum pin_config_param param = pinconf_to_config_param(*config);
1491 u32 padctrl;
1492 u32 arg;
1493
1494 if (!pin)
1495 return -EINVAL;
1496
1497 switch (param) {
1498 case PIN_CONFIG_INPUT_ENABLE:
1499 regmap_field_read(pin->pad[RP1_PAD_IN_ENABLE], &padctrl);
1500 arg = !!padctrl;
1501 break;
1502 case PIN_CONFIG_OUTPUT_ENABLE:
1503 regmap_field_read(pin->pad[RP1_PAD_OUT_DISABLE], &padctrl);
1504 arg = !padctrl;
1505 break;
1506 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1507 regmap_field_read(pin->pad[RP1_PAD_SCHMITT], &padctrl);
1508 arg = !!padctrl;
1509 break;
1510 case PIN_CONFIG_SLEW_RATE:
1511 regmap_field_read(pin->pad[RP1_PAD_SLEWFAST], &padctrl);
1512 arg = !!padctrl;
1513 break;
1514 case PIN_CONFIG_DRIVE_STRENGTH:
1515 regmap_field_read(pin->pad[RP1_PAD_DRIVE], &padctrl);
1516 switch (padctrl) {
1517 case RP1_PAD_DRIVE_2MA:
1518 arg = 2;
1519 break;
1520 case RP1_PAD_DRIVE_4MA:
1521 arg = 4;
1522 break;
1523 case RP1_PAD_DRIVE_8MA:
1524 arg = 8;
1525 break;
1526 case RP1_PAD_DRIVE_12MA:
1527 arg = 12;
1528 break;
1529 }
1530 break;
1531 case PIN_CONFIG_BIAS_DISABLE:
1532 regmap_field_read(pin->pad[RP1_PAD_PULL], &padctrl);
1533 arg = ((padctrl == RP1_PUD_OFF));
1534 break;
1535 case PIN_CONFIG_BIAS_PULL_DOWN:
1536 regmap_field_read(pin->pad[RP1_PAD_PULL], &padctrl);
1537 arg = ((padctrl == RP1_PUD_DOWN));
1538 break;
1539
1540 case PIN_CONFIG_BIAS_PULL_UP:
1541 regmap_field_read(pin->pad[RP1_PAD_PULL], &padctrl);
1542 arg = ((padctrl == RP1_PUD_UP));
1543 break;
1544 default:
1545 return -ENOTSUPP;
1546 }
1547
1548 *config = pinconf_to_config_packed(param, arg);
1549
1550 return 0;
1551 }
1552
rp1_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int selector,unsigned long * config)1553 static int rp1_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned int selector,
1554 unsigned long *config)
1555 {
1556 const unsigned int *pins;
1557 unsigned int npins;
1558 int ret;
1559
1560 ret = rp1_pctl_get_group_pins(pctldev, selector, &pins, &npins);
1561 if (ret < 0)
1562 return ret;
1563
1564 if (!npins)
1565 return -ENODEV;
1566
1567 ret = rp1_pinconf_get(pctldev, pins[0], config);
1568
1569 return ret;
1570 }
1571
rp1_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int selector,unsigned long * configs,unsigned int num_configs)1572 static int rp1_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned int selector,
1573 unsigned long *configs, unsigned int num_configs)
1574 {
1575 const unsigned int *pins;
1576 unsigned int npins;
1577 int ret, i;
1578
1579 ret = rp1_pctl_get_group_pins(pctldev, selector, &pins, &npins);
1580 if (ret < 0)
1581 return ret;
1582
1583 for (i = 0; i < npins; i++) {
1584 ret = rp1_pinconf_set(pctldev, pins[i], configs, num_configs);
1585 if (ret < 0)
1586 return ret;
1587 }
1588
1589 return 0;
1590 }
1591
1592 static const struct pinconf_ops rp1_pinconf_ops = {
1593 .is_generic = true,
1594 .pin_config_get = rp1_pinconf_get,
1595 .pin_config_set = rp1_pinconf_set,
1596 .pin_config_group_get = rp1_pinconf_group_get,
1597 .pin_config_group_set = rp1_pinconf_group_set,
1598 };
1599
1600 static struct pinctrl_desc rp1_pinctrl_desc = {
1601 .name = MODULE_NAME,
1602 .pins = rp1_gpio_pins,
1603 .npins = ARRAY_SIZE(rp1_gpio_pins),
1604 .pctlops = &rp1_pctl_ops,
1605 .pmxops = &rp1_pmx_ops,
1606 .confops = &rp1_pinconf_ops,
1607 .owner = THIS_MODULE,
1608 };
1609
1610 static struct pinctrl_gpio_range rp1_pinctrl_gpio_range = {
1611 .name = MODULE_NAME,
1612 .npins = RP1_NUM_GPIOS,
1613 };
1614
1615 static const struct of_device_id rp1_pinctrl_match[] = {
1616 {
1617 .compatible = "raspberrypi,rp1-gpio",
1618 .data = &rp1_pinconf_ops,
1619 },
1620 {},
1621 };
1622 MODULE_DEVICE_TABLE(of, rp1_pinctrl_match);
1623
1624 static struct rp1_pinctrl rp1_pinctrl_data = {};
1625
1626 static const struct regmap_config rp1_pinctrl_regmap_cfg = {
1627 .reg_bits = 32,
1628 .val_bits = 32,
1629 .reg_stride = 4,
1630 .fast_io = true,
1631 .name = "rp1-pinctrl",
1632 };
1633
rp1_gen_regfield(struct device * dev,const struct reg_field * array,size_t array_size,int reg_off,int pin_off,bool additive_offset,struct regmap * regmap,struct regmap_field * out[])1634 static int rp1_gen_regfield(struct device *dev,
1635 const struct reg_field *array,
1636 size_t array_size,
1637 int reg_off,
1638 int pin_off,
1639 bool additive_offset,
1640 struct regmap *regmap,
1641 struct regmap_field *out[])
1642 {
1643 struct reg_field regfield;
1644 int k;
1645
1646 for (k = 0; k < array_size; k++) {
1647 regfield = array[k];
1648 regfield.reg = (additive_offset ? regfield.reg : 0) + reg_off;
1649 if (pin_off >= 0) {
1650 regfield.lsb = pin_off;
1651 regfield.msb = regfield.lsb;
1652 }
1653 out[k] = devm_regmap_field_alloc(dev, regmap, regfield);
1654
1655 if (IS_ERR(out[k]))
1656 return PTR_ERR(out[k]);
1657 }
1658
1659 return 0;
1660 }
1661
rp1_pinctrl_probe(struct platform_device * pdev)1662 static int rp1_pinctrl_probe(struct platform_device *pdev)
1663 {
1664 struct regmap *gpio_regmap, *rio_regmap, *pads_regmap;
1665 struct rp1_pinctrl *pc = &rp1_pinctrl_data;
1666 struct device *dev = &pdev->dev;
1667 struct device_node *np = dev->of_node;
1668 struct gpio_irq_chip *girq;
1669 int err, i;
1670
1671 pc->dev = dev;
1672 pc->gpio_chip = rp1_gpio_chip;
1673 pc->gpio_chip.parent = dev;
1674
1675 pc->gpio_base = devm_platform_ioremap_resource(pdev, 0);
1676 if (IS_ERR(pc->gpio_base))
1677 return dev_err_probe(dev, PTR_ERR(pc->gpio_base), "could not get GPIO IO memory\n");
1678
1679 pc->rio_base = devm_platform_ioremap_resource(pdev, 1);
1680 if (IS_ERR(pc->rio_base))
1681 return dev_err_probe(dev, PTR_ERR(pc->rio_base), "could not get RIO IO memory\n");
1682
1683 pc->pads_base = devm_platform_ioremap_resource(pdev, 2);
1684 if (IS_ERR(pc->pads_base))
1685 return dev_err_probe(dev, PTR_ERR(pc->pads_base), "could not get PADS IO memory\n");
1686
1687 gpio_regmap = devm_regmap_init_mmio(dev, pc->gpio_base,
1688 &rp1_pinctrl_regmap_cfg);
1689 if (IS_ERR(gpio_regmap))
1690 return dev_err_probe(dev, PTR_ERR(gpio_regmap), "could not init GPIO regmap\n");
1691
1692 rio_regmap = devm_regmap_init_mmio(dev, pc->rio_base,
1693 &rp1_pinctrl_regmap_cfg);
1694 if (IS_ERR(rio_regmap))
1695 return dev_err_probe(dev, PTR_ERR(rio_regmap), "could not init RIO regmap\n");
1696
1697 pads_regmap = devm_regmap_init_mmio(dev, pc->pads_base,
1698 &rp1_pinctrl_regmap_cfg);
1699 if (IS_ERR(pads_regmap))
1700 return dev_err_probe(dev, PTR_ERR(pads_regmap), "could not init PADS regmap\n");
1701
1702 for (i = 0; i < RP1_NUM_BANKS; i++) {
1703 const struct rp1_iobank_desc *bank = &rp1_iobanks[i];
1704 int j;
1705
1706 for (j = 0; j < bank->num_gpios; j++) {
1707 struct rp1_pin_info *pin =
1708 &pc->pins[bank->min_gpio + j];
1709 int reg_off;
1710
1711 pin->num = bank->min_gpio + j;
1712 pin->bank = i;
1713 pin->offset = j;
1714
1715 reg_off = bank->gpio_offset + pin->offset *
1716 sizeof(u32) * 2;
1717 err = rp1_gen_regfield(dev,
1718 rp1_gpio_fields,
1719 ARRAY_SIZE(rp1_gpio_fields),
1720 reg_off,
1721 -1,
1722 true,
1723 gpio_regmap,
1724 pin->gpio);
1725
1726 if (err)
1727 return dev_err_probe(dev, err,
1728 "Unable to allocate regmap for gpio\n");
1729
1730 reg_off = bank->inte_offset;
1731 err = rp1_gen_regfield(dev,
1732 rp1_inte_fields,
1733 ARRAY_SIZE(rp1_inte_fields),
1734 reg_off,
1735 pin->offset,
1736 true,
1737 gpio_regmap,
1738 pin->inte);
1739
1740 if (err)
1741 return dev_err_probe(dev, err,
1742 "Unable to allocate regmap for inte\n");
1743
1744 reg_off = bank->rio_offset;
1745 err = rp1_gen_regfield(dev,
1746 rp1_rio_fields,
1747 ARRAY_SIZE(rp1_rio_fields),
1748 reg_off,
1749 pin->offset,
1750 true,
1751 rio_regmap,
1752 pin->rio);
1753
1754 if (err)
1755 return dev_err_probe(dev, err,
1756 "Unable to allocate regmap for rio\n");
1757
1758 reg_off = bank->pads_offset + pin->offset * sizeof(u32);
1759 err = rp1_gen_regfield(dev,
1760 rp1_pad_fields,
1761 ARRAY_SIZE(rp1_pad_fields),
1762 reg_off,
1763 -1,
1764 false,
1765 pads_regmap,
1766 pin->pad);
1767
1768 if (err)
1769 return dev_err_probe(dev, err,
1770 "Unable to allocate regmap for pad\n");
1771 }
1772
1773 raw_spin_lock_init(&pc->irq_lock[i]);
1774 }
1775
1776 pc->pctl_dev = devm_pinctrl_register(dev, &rp1_pinctrl_desc, pc);
1777 if (IS_ERR(pc->pctl_dev))
1778 return dev_err_probe(dev, PTR_ERR(pc->pctl_dev),
1779 "Could not register pin controller\n");
1780
1781 girq = &pc->gpio_chip.irq;
1782 girq->chip = &rp1_gpio_irq_chip;
1783 girq->parent_handler = rp1_gpio_irq_handler;
1784 girq->num_parents = RP1_NUM_BANKS;
1785 girq->parents = pc->irq;
1786 girq->default_type = IRQ_TYPE_NONE;
1787 girq->handler = handle_level_irq;
1788
1789 /*
1790 * Use the same handler for all groups: this is necessary
1791 * since we use one gpiochip to cover all lines - the
1792 * irq handler then needs to figure out which group and
1793 * bank that was firing the IRQ and look up the per-group
1794 * and bank data.
1795 */
1796 for (i = 0; i < RP1_NUM_BANKS; i++) {
1797 pc->irq[i] = irq_of_parse_and_map(np, i);
1798 if (!pc->irq[i]) {
1799 girq->num_parents = i;
1800 break;
1801 }
1802 }
1803
1804 platform_set_drvdata(pdev, pc);
1805
1806 err = devm_gpiochip_add_data(dev, &pc->gpio_chip, pc);
1807 if (err)
1808 return dev_err_probe(dev, err, "could not add GPIO chip\n");
1809
1810 pc->gpio_range = rp1_pinctrl_gpio_range;
1811 pc->gpio_range.base = pc->gpio_chip.base;
1812 pc->gpio_range.gc = &pc->gpio_chip;
1813 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1814
1815 return 0;
1816 }
1817
1818 static struct platform_driver rp1_pinctrl_driver = {
1819 .probe = rp1_pinctrl_probe,
1820 .driver = {
1821 .name = MODULE_NAME,
1822 .of_match_table = rp1_pinctrl_match,
1823 .suppress_bind_attrs = true,
1824 },
1825 };
1826 module_platform_driver(rp1_pinctrl_driver);
1827
1828 MODULE_AUTHOR("Phil Elwell <phil@raspberrypi.com>");
1829 MODULE_AUTHOR("Andrea della Porta <andrea.porta@suse.com>");
1830 MODULE_DESCRIPTION("RP1 pinctrl/gpio driver");
1831 MODULE_LICENSE("GPL");
1832