1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support 4 * 5 * Copyright (C) 2022 9elements GmbH 6 * Authors: Patrick Rudolph <patrick.rudolph@9elements.com> 7 * Naresh Solanki <Naresh.Solanki@9elements.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/bitmap.h> 12 #include <linux/cleanup.h> 13 #include <linux/dmi.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/module.h> 21 #include <linux/property.h> 22 #include <linux/regmap.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/seq_file.h> 25 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/pinctrl/pinconf.h> 28 #include <linux/pinctrl/pinconf-generic.h> 29 #include <linux/pinctrl/pinctrl.h> 30 #include <linux/pinctrl/pinmux.h> 31 32 /* Fast access registers */ 33 #define CY8C95X0_INPUT 0x00 34 #define CY8C95X0_OUTPUT 0x08 35 #define CY8C95X0_INTSTATUS 0x10 36 37 #define CY8C95X0_INPUT_(x) (CY8C95X0_INPUT + (x)) 38 #define CY8C95X0_OUTPUT_(x) (CY8C95X0_OUTPUT + (x)) 39 #define CY8C95X0_INTSTATUS_(x) (CY8C95X0_INTSTATUS + (x)) 40 41 /* Port Select configures the port */ 42 #define CY8C95X0_PORTSEL 0x18 43 /* Port settings, write PORTSEL first */ 44 #define CY8C95X0_INTMASK 0x19 45 #define CY8C95X0_SELPWM 0x1A 46 #define CY8C95X0_INVERT 0x1B 47 #define CY8C95X0_DIRECTION 0x1C 48 /* Drive mode register change state on writing '1' */ 49 #define CY8C95X0_DRV_PU 0x1D 50 #define CY8C95X0_DRV_PD 0x1E 51 #define CY8C95X0_DRV_ODH 0x1F 52 #define CY8C95X0_DRV_ODL 0x20 53 #define CY8C95X0_DRV_PP_FAST 0x21 54 #define CY8C95X0_DRV_PP_SLOW 0x22 55 #define CY8C95X0_DRV_HIZ 0x23 56 #define CY8C95X0_DEVID 0x2E 57 #define CY8C95X0_WATCHDOG 0x2F 58 #define CY8C95X0_COMMAND 0x30 59 60 #define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x)) 61 62 #define MAX_BANK 8 63 #define BANK_SZ 8 64 #define MAX_LINE (MAX_BANK * BANK_SZ) 65 #define MUXED_STRIDE 16 66 #define CY8C95X0_GPIO_MASK GENMASK(7, 0) 67 #define CY8C95X0_VIRTUAL 0x40 68 #define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \ 69 (CY8C95X0_VIRTUAL + (x) - CY8C95X0_PORTSEL + (p) * MUXED_STRIDE) 70 71 static const struct i2c_device_id cy8c95x0_id[] = { 72 { "cy8c9520", 20, }, 73 { "cy8c9540", 40, }, 74 { "cy8c9560", 60, }, 75 { } 76 }; 77 MODULE_DEVICE_TABLE(i2c, cy8c95x0_id); 78 79 #define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio)) 80 81 static const struct of_device_id cy8c95x0_dt_ids[] = { 82 { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), }, 83 { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), }, 84 { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), }, 85 { } 86 }; 87 MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids); 88 89 static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true }; 90 91 static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = { 92 { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, 93 { } 94 }; 95 96 static int cy8c95x0_acpi_get_irq(struct device *dev) 97 { 98 int ret; 99 100 ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios); 101 if (ret) 102 dev_warn(dev, "can't add GPIO ACPI mapping\n"); 103 104 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0); 105 if (ret < 0) 106 return ret; 107 108 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); 109 return ret; 110 } 111 112 static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = { 113 { 114 /* 115 * On Intel Galileo Gen 1 board the IRQ pin is provided 116 * as an absolute number instead of being relative. 117 * Since first controller (gpio-sch.c) and second 118 * (gpio-dwapb.c) are at the fixed bases, we may safely 119 * refer to the number in the global space to get an IRQ 120 * out of it. 121 */ 122 .matches = { 123 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 124 }, 125 }, 126 {} 127 }; 128 129 /** 130 * struct cy8c95x0_pinctrl - driver data 131 * @regmap: Device's regmap. Only direct access registers. 132 * @irq_lock: IRQ bus lock 133 * @i2c_lock: Mutex to hold while using the regmap 134 * @irq_mask: I/O bits affected by interrupts 135 * @irq_trig_raise: I/O bits affected by raising voltage level 136 * @irq_trig_fall: I/O bits affected by falling voltage level 137 * @irq_trig_low: I/O bits affected by a low voltage level 138 * @irq_trig_high: I/O bits affected by a high voltage level 139 * @push_pull: I/O bits configured as push pull driver 140 * @shiftmask: Mask used to compensate for Gport2 width 141 * @nport: Number of Gports in this chip 142 * @gpio_chip: gpiolib chip 143 * @driver_data: private driver data 144 * @dev: struct device 145 * @pctldev: pin controller device 146 * @pinctrl_desc: pin controller description 147 * @name: Chip controller name 148 * @tpin: Total number of pins 149 * @gpio_reset: GPIO line handler that can reset the IC 150 */ 151 struct cy8c95x0_pinctrl { 152 struct regmap *regmap; 153 struct mutex irq_lock; 154 struct mutex i2c_lock; 155 DECLARE_BITMAP(irq_mask, MAX_LINE); 156 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 157 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 158 DECLARE_BITMAP(irq_trig_low, MAX_LINE); 159 DECLARE_BITMAP(irq_trig_high, MAX_LINE); 160 DECLARE_BITMAP(push_pull, MAX_LINE); 161 DECLARE_BITMAP(shiftmask, MAX_LINE); 162 unsigned int nport; 163 struct gpio_chip gpio_chip; 164 unsigned long driver_data; 165 struct device *dev; 166 struct pinctrl_dev *pctldev; 167 struct pinctrl_desc pinctrl_desc; 168 char name[32]; 169 unsigned int tpin; 170 struct gpio_desc *gpio_reset; 171 }; 172 173 static const struct pinctrl_pin_desc cy8c9560_pins[] = { 174 PINCTRL_PIN(0, "gp00"), 175 PINCTRL_PIN(1, "gp01"), 176 PINCTRL_PIN(2, "gp02"), 177 PINCTRL_PIN(3, "gp03"), 178 PINCTRL_PIN(4, "gp04"), 179 PINCTRL_PIN(5, "gp05"), 180 PINCTRL_PIN(6, "gp06"), 181 PINCTRL_PIN(7, "gp07"), 182 183 PINCTRL_PIN(8, "gp10"), 184 PINCTRL_PIN(9, "gp11"), 185 PINCTRL_PIN(10, "gp12"), 186 PINCTRL_PIN(11, "gp13"), 187 PINCTRL_PIN(12, "gp14"), 188 PINCTRL_PIN(13, "gp15"), 189 PINCTRL_PIN(14, "gp16"), 190 PINCTRL_PIN(15, "gp17"), 191 192 PINCTRL_PIN(16, "gp20"), 193 PINCTRL_PIN(17, "gp21"), 194 PINCTRL_PIN(18, "gp22"), 195 PINCTRL_PIN(19, "gp23"), 196 197 PINCTRL_PIN(20, "gp30"), 198 PINCTRL_PIN(21, "gp31"), 199 PINCTRL_PIN(22, "gp32"), 200 PINCTRL_PIN(23, "gp33"), 201 PINCTRL_PIN(24, "gp34"), 202 PINCTRL_PIN(25, "gp35"), 203 PINCTRL_PIN(26, "gp36"), 204 PINCTRL_PIN(27, "gp37"), 205 206 PINCTRL_PIN(28, "gp40"), 207 PINCTRL_PIN(29, "gp41"), 208 PINCTRL_PIN(30, "gp42"), 209 PINCTRL_PIN(31, "gp43"), 210 PINCTRL_PIN(32, "gp44"), 211 PINCTRL_PIN(33, "gp45"), 212 PINCTRL_PIN(34, "gp46"), 213 PINCTRL_PIN(35, "gp47"), 214 215 PINCTRL_PIN(36, "gp50"), 216 PINCTRL_PIN(37, "gp51"), 217 PINCTRL_PIN(38, "gp52"), 218 PINCTRL_PIN(39, "gp53"), 219 PINCTRL_PIN(40, "gp54"), 220 PINCTRL_PIN(41, "gp55"), 221 PINCTRL_PIN(42, "gp56"), 222 PINCTRL_PIN(43, "gp57"), 223 224 PINCTRL_PIN(44, "gp60"), 225 PINCTRL_PIN(45, "gp61"), 226 PINCTRL_PIN(46, "gp62"), 227 PINCTRL_PIN(47, "gp63"), 228 PINCTRL_PIN(48, "gp64"), 229 PINCTRL_PIN(49, "gp65"), 230 PINCTRL_PIN(50, "gp66"), 231 PINCTRL_PIN(51, "gp67"), 232 233 PINCTRL_PIN(52, "gp70"), 234 PINCTRL_PIN(53, "gp71"), 235 PINCTRL_PIN(54, "gp72"), 236 PINCTRL_PIN(55, "gp73"), 237 PINCTRL_PIN(56, "gp74"), 238 PINCTRL_PIN(57, "gp75"), 239 PINCTRL_PIN(58, "gp76"), 240 PINCTRL_PIN(59, "gp77"), 241 }; 242 243 static const char * const cy8c95x0_groups[] = { 244 "gp00", 245 "gp01", 246 "gp02", 247 "gp03", 248 "gp04", 249 "gp05", 250 "gp06", 251 "gp07", 252 253 "gp10", 254 "gp11", 255 "gp12", 256 "gp13", 257 "gp14", 258 "gp15", 259 "gp16", 260 "gp17", 261 262 "gp20", 263 "gp21", 264 "gp22", 265 "gp23", 266 267 "gp30", 268 "gp31", 269 "gp32", 270 "gp33", 271 "gp34", 272 "gp35", 273 "gp36", 274 "gp37", 275 276 "gp40", 277 "gp41", 278 "gp42", 279 "gp43", 280 "gp44", 281 "gp45", 282 "gp46", 283 "gp47", 284 285 "gp50", 286 "gp51", 287 "gp52", 288 "gp53", 289 "gp54", 290 "gp55", 291 "gp56", 292 "gp57", 293 294 "gp60", 295 "gp61", 296 "gp62", 297 "gp63", 298 "gp64", 299 "gp65", 300 "gp66", 301 "gp67", 302 303 "gp70", 304 "gp71", 305 "gp72", 306 "gp73", 307 "gp74", 308 "gp75", 309 "gp76", 310 "gp77", 311 }; 312 313 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, 314 unsigned int pin, bool input); 315 316 static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin) 317 { 318 /* Account for GPORT2 which only has 4 bits */ 319 return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ; 320 } 321 322 static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin) 323 { 324 /* Account for GPORT2 which only has 4 bits */ 325 return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ); 326 } 327 328 static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg) 329 { 330 /* 331 * Only 12 registers are present per port (see Table 6 in the datasheet). 332 */ 333 if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) >= 12) 334 return false; 335 336 switch (reg) { 337 case 0x24 ... 0x27: 338 case 0x31 ... 0x3f: 339 return false; 340 default: 341 return true; 342 } 343 } 344 345 static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg) 346 { 347 /* 348 * Only 12 registers are present per port (see Table 6 in the datasheet). 349 */ 350 if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) >= 12) 351 return false; 352 353 switch (reg) { 354 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): 355 return false; 356 case CY8C95X0_DEVID: 357 return false; 358 case 0x24 ... 0x27: 359 case 0x31 ... 0x3f: 360 return false; 361 default: 362 return true; 363 } 364 } 365 366 static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg) 367 { 368 switch (reg) { 369 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): 370 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): 371 case CY8C95X0_INTMASK: 372 case CY8C95X0_SELPWM: 373 case CY8C95X0_INVERT: 374 case CY8C95X0_DIRECTION: 375 case CY8C95X0_DRV_PU: 376 case CY8C95X0_DRV_PD: 377 case CY8C95X0_DRV_ODH: 378 case CY8C95X0_DRV_ODL: 379 case CY8C95X0_DRV_PP_FAST: 380 case CY8C95X0_DRV_PP_SLOW: 381 case CY8C95X0_DRV_HIZ: 382 return true; 383 default: 384 return false; 385 } 386 } 387 388 static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg) 389 { 390 switch (reg) { 391 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): 392 return true; 393 default: 394 return false; 395 } 396 } 397 398 static bool cy8c95x0_muxed_register(unsigned int reg) 399 { 400 switch (reg) { 401 case CY8C95X0_INTMASK: 402 case CY8C95X0_SELPWM: 403 case CY8C95X0_INVERT: 404 case CY8C95X0_DIRECTION: 405 case CY8C95X0_DRV_PU: 406 case CY8C95X0_DRV_PD: 407 case CY8C95X0_DRV_ODH: 408 case CY8C95X0_DRV_ODL: 409 case CY8C95X0_DRV_PP_FAST: 410 case CY8C95X0_DRV_PP_SLOW: 411 case CY8C95X0_DRV_HIZ: 412 return true; 413 default: 414 return false; 415 } 416 } 417 418 static bool cy8c95x0_wc_register(unsigned int reg) 419 { 420 switch (reg) { 421 case CY8C95X0_DRV_PU: 422 case CY8C95X0_DRV_PD: 423 case CY8C95X0_DRV_ODH: 424 case CY8C95X0_DRV_ODL: 425 case CY8C95X0_DRV_PP_FAST: 426 case CY8C95X0_DRV_PP_SLOW: 427 case CY8C95X0_DRV_HIZ: 428 return true; 429 default: 430 return false; 431 } 432 } 433 434 static bool cy8c95x0_quick_path_register(unsigned int reg) 435 { 436 switch (reg) { 437 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): 438 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): 439 case CY8C95X0_OUTPUT_(0) ... CY8C95X0_OUTPUT_(7): 440 return true; 441 default: 442 return false; 443 } 444 } 445 446 static const struct regmap_range_cfg cy8c95x0_ranges[] = { 447 { 448 .range_min = CY8C95X0_VIRTUAL, 449 .range_max = 0, /* Updated at runtime */ 450 .selector_reg = CY8C95X0_PORTSEL, 451 .selector_mask = 0x07, 452 .selector_shift = 0x0, 453 .window_start = CY8C95X0_PORTSEL, 454 .window_len = MUXED_STRIDE, 455 } 456 }; 457 458 static const struct regmap_config cy8c9520_i2c_regmap = { 459 .reg_bits = 8, 460 .val_bits = 8, 461 462 .readable_reg = cy8c95x0_readable_register, 463 .writeable_reg = cy8c95x0_writeable_register, 464 .volatile_reg = cy8c95x0_volatile_register, 465 .precious_reg = cy8c95x0_precious_register, 466 467 .cache_type = REGCACHE_MAPLE, 468 .ranges = NULL, /* Updated at runtime */ 469 .num_ranges = 1, 470 .max_register = 0, /* Updated at runtime */ 471 .num_reg_defaults_raw = 0, /* Updated at runtime */ 472 .use_single_read = true, /* Workaround for regcache bug */ 473 #if IS_ENABLED(CONFIG_DEBUG_PINCTRL) 474 .disable_locking = false, 475 #else 476 .disable_locking = true, 477 #endif 478 }; 479 480 static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip, 481 unsigned int reg, 482 unsigned int port, 483 unsigned int mask, 484 unsigned int val, 485 bool *change, bool async, 486 bool force) 487 { 488 int ret, off, i; 489 490 /* Caller should never modify PORTSEL directly */ 491 if (reg == CY8C95X0_PORTSEL) 492 return -EINVAL; 493 494 /* Registers behind the PORTSEL mux have their own range in regmap */ 495 if (cy8c95x0_muxed_register(reg)) { 496 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port); 497 } else { 498 /* Quick path direct access registers honor the port argument */ 499 if (cy8c95x0_quick_path_register(reg)) 500 off = reg + port; 501 else 502 off = reg; 503 } 504 guard(mutex)(&chip->i2c_lock); 505 506 ret = regmap_update_bits_base(chip->regmap, off, mask, val, change, async, force); 507 if (ret < 0) 508 return ret; 509 510 /* Mimic what hardware does and update the cache when a WC bit is written. 511 * Allows to mark the registers as non-volatile and reduces I/O cycles. 512 */ 513 if (cy8c95x0_wc_register(reg) && (mask & val)) { 514 /* Writing a 1 clears set bits in the other drive mode registers */ 515 regcache_cache_only(chip->regmap, true); 516 for (i = CY8C95X0_DRV_PU; i <= CY8C95X0_DRV_HIZ; i++) { 517 if (i == reg) 518 continue; 519 520 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port); 521 regmap_clear_bits(chip->regmap, off, mask & val); 522 } 523 regcache_cache_only(chip->regmap, false); 524 } 525 526 return ret; 527 } 528 529 /** 530 * cy8c95x0_regmap_write_bits() - writes a register using the regmap cache 531 * @chip: The pinctrl to work on 532 * @reg: The register to write to. Can be direct access or muxed register. 533 * MUST NOT be the PORTSEL register. 534 * @port: The port to be used for muxed registers or quick path direct access 535 * registers. Otherwise unused. 536 * @mask: Bitmask to change 537 * @val: New value for bitmask 538 * 539 * This function handles the register writes to the direct access registers and 540 * the muxed registers while caching all register accesses, internally handling 541 * the correct state of the PORTSEL register and protecting the access to muxed 542 * registers. 543 * The caller must only use this function to change registers behind the PORTSEL mux. 544 * 545 * Return: 0 for successful request, else a corresponding error value 546 */ 547 static int cy8c95x0_regmap_write_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg, 548 unsigned int port, unsigned int mask, unsigned int val) 549 { 550 return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, true); 551 } 552 553 /** 554 * cy8c95x0_regmap_update_bits() - updates a register using the regmap cache 555 * @chip: The pinctrl to work on 556 * @reg: The register to write to. Can be direct access or muxed register. 557 * MUST NOT be the PORTSEL register. 558 * @port: The port to be used for muxed registers or quick path direct access 559 * registers. Otherwise unused. 560 * @mask: Bitmask to change 561 * @val: New value for bitmask 562 * 563 * This function handles the register updates to the direct access registers and 564 * the muxed registers while caching all register accesses, internally handling 565 * the correct state of the PORTSEL register and protecting the access to muxed 566 * registers. 567 * The caller must only use this function to change registers behind the PORTSEL mux. 568 * 569 * Return: 0 for successful request, else a corresponding error value 570 */ 571 static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg, 572 unsigned int port, unsigned int mask, unsigned int val) 573 { 574 return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, false); 575 } 576 577 /** 578 * cy8c95x0_regmap_read() - reads a register using the regmap cache 579 * @chip: The pinctrl to work on 580 * @reg: The register to read from. Can be direct access or muxed register. 581 * @port: The port to be used for muxed registers or quick path direct access 582 * registers. Otherwise unused. 583 * @read_val: Value read from hardware or cache 584 * 585 * This function handles the register reads from the direct access registers and 586 * the muxed registers while caching all register accesses, internally handling 587 * the correct state of the PORTSEL register and protecting the access to muxed 588 * registers. 589 * The caller must only use this function to read registers behind the PORTSEL mux. 590 * 591 * Return: 0 for successful request, else a corresponding error value 592 */ 593 static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg, 594 unsigned int port, unsigned int *read_val) 595 { 596 int off, ret; 597 598 /* Registers behind the PORTSEL mux have their own range in regmap */ 599 if (cy8c95x0_muxed_register(reg)) { 600 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port); 601 } else { 602 /* Quick path direct access registers honor the port argument */ 603 if (cy8c95x0_quick_path_register(reg)) 604 off = reg + port; 605 else 606 off = reg; 607 } 608 guard(mutex)(&chip->i2c_lock); 609 610 ret = regmap_read(chip->regmap, off, read_val); 611 612 return ret; 613 } 614 615 static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, 616 unsigned long *val, unsigned long *mask) 617 { 618 DECLARE_BITMAP(tmask, MAX_LINE); 619 DECLARE_BITMAP(tval, MAX_LINE); 620 int write_val; 621 u8 bits; 622 int ret; 623 624 /* Add the 4 bit gap of Gport2 */ 625 bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); 626 bitmap_shift_left(tmask, tmask, 4, MAX_LINE); 627 bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3); 628 629 bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE); 630 bitmap_shift_left(tval, tval, 4, MAX_LINE); 631 bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); 632 633 for (unsigned int i = 0; i < chip->nport; i++) { 634 /* Skip over unused banks */ 635 bits = bitmap_get_value8(tmask, i * BANK_SZ); 636 if (!bits) 637 continue; 638 639 write_val = bitmap_get_value8(tval, i * BANK_SZ); 640 641 ret = cy8c95x0_regmap_update_bits(chip, reg, i, bits, write_val); 642 if (ret < 0) { 643 dev_err(chip->dev, "failed writing register %d, port %u: err %d\n", reg, i, ret); 644 return ret; 645 } 646 } 647 648 return 0; 649 } 650 651 static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, 652 unsigned long *val, unsigned long *mask) 653 { 654 DECLARE_BITMAP(tmask, MAX_LINE); 655 DECLARE_BITMAP(tval, MAX_LINE); 656 DECLARE_BITMAP(tmp, MAX_LINE); 657 int read_val; 658 u8 bits; 659 int ret; 660 661 /* Add the 4 bit gap of Gport2 */ 662 bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); 663 bitmap_shift_left(tmask, tmask, 4, MAX_LINE); 664 bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3); 665 666 bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE); 667 bitmap_shift_left(tval, tval, 4, MAX_LINE); 668 bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); 669 670 for (unsigned int i = 0; i < chip->nport; i++) { 671 /* Skip over unused banks */ 672 bits = bitmap_get_value8(tmask, i * BANK_SZ); 673 if (!bits) 674 continue; 675 676 ret = cy8c95x0_regmap_read(chip, reg, i, &read_val); 677 if (ret < 0) { 678 dev_err(chip->dev, "failed reading register %d, port %u: err %d\n", reg, i, ret); 679 return ret; 680 } 681 682 read_val &= bits; 683 read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits; 684 bitmap_set_value8(tval, read_val, i * BANK_SZ); 685 } 686 687 /* Fill the 4 bit gap of Gport2 */ 688 bitmap_shift_right(tmp, tval, 4, MAX_LINE); 689 bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE); 690 691 return 0; 692 } 693 694 static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off) 695 { 696 return pinctrl_gpio_direction_input(gc, off); 697 } 698 699 static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc, 700 unsigned int off, int val) 701 { 702 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 703 u8 port = cypress_get_port(chip, off); 704 u8 bit = cypress_get_pin_mask(chip, off); 705 int ret; 706 707 /* Set output level */ 708 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0); 709 if (ret) 710 return ret; 711 712 return pinctrl_gpio_direction_output(gc, off); 713 } 714 715 static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off) 716 { 717 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 718 u8 port = cypress_get_port(chip, off); 719 u8 bit = cypress_get_pin_mask(chip, off); 720 u32 reg_val; 721 int ret; 722 723 ret = cy8c95x0_regmap_read(chip, CY8C95X0_INPUT, port, ®_val); 724 if (ret < 0) { 725 /* 726 * NOTE: 727 * Diagnostic already emitted; that's all we should 728 * do unless gpio_*_value_cansleep() calls become different 729 * from their nonsleeping siblings (and report faults). 730 */ 731 return 0; 732 } 733 734 return !!(reg_val & bit); 735 } 736 737 static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off, 738 int val) 739 { 740 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 741 u8 port = cypress_get_port(chip, off); 742 u8 bit = cypress_get_pin_mask(chip, off); 743 744 cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0); 745 } 746 747 static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off) 748 { 749 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 750 u8 port = cypress_get_port(chip, off); 751 u8 bit = cypress_get_pin_mask(chip, off); 752 u32 reg_val; 753 int ret; 754 755 ret = cy8c95x0_regmap_read(chip, CY8C95X0_DIRECTION, port, ®_val); 756 if (ret < 0) 757 return ret; 758 759 if (reg_val & bit) 760 return GPIO_LINE_DIRECTION_IN; 761 762 return GPIO_LINE_DIRECTION_OUT; 763 } 764 765 static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, 766 unsigned int off, 767 unsigned long *config) 768 { 769 enum pin_config_param param = pinconf_to_config_param(*config); 770 u8 port = cypress_get_port(chip, off); 771 u8 bit = cypress_get_pin_mask(chip, off); 772 unsigned int reg; 773 u32 reg_val; 774 u16 arg = 0; 775 int ret; 776 777 switch (param) { 778 case PIN_CONFIG_BIAS_PULL_UP: 779 reg = CY8C95X0_DRV_PU; 780 break; 781 case PIN_CONFIG_BIAS_PULL_DOWN: 782 reg = CY8C95X0_DRV_PD; 783 break; 784 case PIN_CONFIG_BIAS_DISABLE: 785 reg = CY8C95X0_DRV_HIZ; 786 break; 787 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 788 reg = CY8C95X0_DRV_ODL; 789 break; 790 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 791 reg = CY8C95X0_DRV_ODH; 792 break; 793 case PIN_CONFIG_DRIVE_PUSH_PULL: 794 reg = CY8C95X0_DRV_PP_FAST; 795 break; 796 case PIN_CONFIG_INPUT_ENABLE: 797 reg = CY8C95X0_DIRECTION; 798 break; 799 case PIN_CONFIG_MODE_PWM: 800 reg = CY8C95X0_SELPWM; 801 break; 802 case PIN_CONFIG_OUTPUT: 803 reg = CY8C95X0_OUTPUT; 804 break; 805 case PIN_CONFIG_OUTPUT_ENABLE: 806 reg = CY8C95X0_DIRECTION; 807 break; 808 809 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 810 case PIN_CONFIG_BIAS_BUS_HOLD: 811 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 812 case PIN_CONFIG_DRIVE_STRENGTH: 813 case PIN_CONFIG_DRIVE_STRENGTH_UA: 814 case PIN_CONFIG_INPUT_DEBOUNCE: 815 case PIN_CONFIG_INPUT_SCHMITT: 816 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 817 case PIN_CONFIG_MODE_LOW_POWER: 818 case PIN_CONFIG_PERSIST_STATE: 819 case PIN_CONFIG_POWER_SOURCE: 820 case PIN_CONFIG_SKEW_DELAY: 821 case PIN_CONFIG_SLEEP_HARDWARE_STATE: 822 case PIN_CONFIG_SLEW_RATE: 823 default: 824 return -ENOTSUPP; 825 } 826 /* 827 * Writing 1 to one of the drive mode registers will automatically 828 * clear conflicting set bits in the other drive mode registers. 829 */ 830 ret = cy8c95x0_regmap_read(chip, reg, port, ®_val); 831 if (ret < 0) 832 return ret; 833 834 if (reg_val & bit) 835 arg = 1; 836 if (param == PIN_CONFIG_OUTPUT_ENABLE) 837 arg = !arg; 838 839 *config = pinconf_to_config_packed(param, (u16)arg); 840 return 0; 841 } 842 843 static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip, 844 unsigned int off, 845 unsigned long config) 846 { 847 u8 port = cypress_get_port(chip, off); 848 u8 bit = cypress_get_pin_mask(chip, off); 849 unsigned long param = pinconf_to_config_param(config); 850 unsigned long arg = pinconf_to_config_argument(config); 851 unsigned int reg; 852 853 switch (param) { 854 case PIN_CONFIG_BIAS_PULL_UP: 855 __clear_bit(off, chip->push_pull); 856 reg = CY8C95X0_DRV_PU; 857 break; 858 case PIN_CONFIG_BIAS_PULL_DOWN: 859 __clear_bit(off, chip->push_pull); 860 reg = CY8C95X0_DRV_PD; 861 break; 862 case PIN_CONFIG_BIAS_DISABLE: 863 __clear_bit(off, chip->push_pull); 864 reg = CY8C95X0_DRV_HIZ; 865 break; 866 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 867 __clear_bit(off, chip->push_pull); 868 reg = CY8C95X0_DRV_ODL; 869 break; 870 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 871 __clear_bit(off, chip->push_pull); 872 reg = CY8C95X0_DRV_ODH; 873 break; 874 case PIN_CONFIG_DRIVE_PUSH_PULL: 875 __set_bit(off, chip->push_pull); 876 reg = CY8C95X0_DRV_PP_FAST; 877 break; 878 case PIN_CONFIG_MODE_PWM: 879 reg = CY8C95X0_SELPWM; 880 break; 881 case PIN_CONFIG_OUTPUT_ENABLE: 882 return cy8c95x0_pinmux_direction(chip, off, !arg); 883 case PIN_CONFIG_INPUT_ENABLE: 884 return cy8c95x0_pinmux_direction(chip, off, arg); 885 default: 886 return -ENOTSUPP; 887 } 888 /* 889 * Writing 1 to one of the drive mode registers will automatically 890 * clear conflicting set bits in the other drive mode registers. 891 */ 892 return cy8c95x0_regmap_write_bits(chip, reg, port, bit, bit); 893 } 894 895 static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc, 896 unsigned long *mask, unsigned long *bits) 897 { 898 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 899 900 return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask); 901 } 902 903 static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc, 904 unsigned long *mask, unsigned long *bits) 905 { 906 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 907 908 cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask); 909 } 910 911 static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc) 912 { 913 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 914 struct device *dev = chip->dev; 915 int ret; 916 917 ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin); 918 if (ret) 919 dev_err(dev, "failed to add GPIO pin range\n"); 920 921 return ret; 922 } 923 924 static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip) 925 { 926 struct gpio_chip *gc = &chip->gpio_chip; 927 928 gc->request = gpiochip_generic_request; 929 gc->free = gpiochip_generic_free; 930 gc->direction_input = cy8c95x0_gpio_direction_input; 931 gc->direction_output = cy8c95x0_gpio_direction_output; 932 gc->get = cy8c95x0_gpio_get_value; 933 gc->set = cy8c95x0_gpio_set_value; 934 gc->get_direction = cy8c95x0_gpio_get_direction; 935 gc->get_multiple = cy8c95x0_gpio_get_multiple; 936 gc->set_multiple = cy8c95x0_gpio_set_multiple; 937 gc->set_config = gpiochip_generic_config; 938 gc->can_sleep = true; 939 gc->add_pin_ranges = cy8c95x0_add_pin_ranges; 940 941 gc->base = -1; 942 gc->ngpio = chip->tpin; 943 944 gc->parent = chip->dev; 945 gc->owner = THIS_MODULE; 946 gc->names = NULL; 947 948 gc->label = dev_name(chip->dev); 949 950 return devm_gpiochip_add_data(chip->dev, gc, chip); 951 } 952 953 static void cy8c95x0_irq_mask(struct irq_data *d) 954 { 955 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 956 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 957 irq_hw_number_t hwirq = irqd_to_hwirq(d); 958 959 set_bit(hwirq, chip->irq_mask); 960 gpiochip_disable_irq(gc, hwirq); 961 } 962 963 static void cy8c95x0_irq_unmask(struct irq_data *d) 964 { 965 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 966 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 967 irq_hw_number_t hwirq = irqd_to_hwirq(d); 968 969 gpiochip_enable_irq(gc, hwirq); 970 clear_bit(hwirq, chip->irq_mask); 971 } 972 973 static void cy8c95x0_irq_bus_lock(struct irq_data *d) 974 { 975 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 976 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 977 978 mutex_lock(&chip->irq_lock); 979 } 980 981 static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d) 982 { 983 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 984 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 985 DECLARE_BITMAP(ones, MAX_LINE); 986 DECLARE_BITMAP(irq_mask, MAX_LINE); 987 DECLARE_BITMAP(reg_direction, MAX_LINE); 988 989 bitmap_fill(ones, MAX_LINE); 990 991 cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones); 992 993 /* Switch direction to input if needed */ 994 cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask); 995 bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE); 996 bitmap_complement(irq_mask, irq_mask, MAX_LINE); 997 998 /* Look for any newly setup interrupt */ 999 cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask); 1000 1001 mutex_unlock(&chip->irq_lock); 1002 } 1003 1004 static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type) 1005 { 1006 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1007 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 1008 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1009 unsigned int trig_type; 1010 1011 switch (type) { 1012 case IRQ_TYPE_EDGE_RISING: 1013 case IRQ_TYPE_EDGE_FALLING: 1014 case IRQ_TYPE_EDGE_BOTH: 1015 trig_type = type; 1016 break; 1017 case IRQ_TYPE_LEVEL_HIGH: 1018 trig_type = IRQ_TYPE_EDGE_RISING; 1019 break; 1020 case IRQ_TYPE_LEVEL_LOW: 1021 trig_type = IRQ_TYPE_EDGE_FALLING; 1022 break; 1023 default: 1024 dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type); 1025 return -EINVAL; 1026 } 1027 1028 assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING); 1029 assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING); 1030 assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW); 1031 assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH); 1032 1033 return 0; 1034 } 1035 1036 static void cy8c95x0_irq_shutdown(struct irq_data *d) 1037 { 1038 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1039 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 1040 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1041 1042 clear_bit(hwirq, chip->irq_trig_raise); 1043 clear_bit(hwirq, chip->irq_trig_fall); 1044 clear_bit(hwirq, chip->irq_trig_low); 1045 clear_bit(hwirq, chip->irq_trig_high); 1046 } 1047 1048 static const struct irq_chip cy8c95x0_irqchip = { 1049 .name = "cy8c95x0-irq", 1050 .irq_mask = cy8c95x0_irq_mask, 1051 .irq_unmask = cy8c95x0_irq_unmask, 1052 .irq_bus_lock = cy8c95x0_irq_bus_lock, 1053 .irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock, 1054 .irq_set_type = cy8c95x0_irq_set_type, 1055 .irq_shutdown = cy8c95x0_irq_shutdown, 1056 .flags = IRQCHIP_IMMUTABLE, 1057 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1058 }; 1059 1060 static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending) 1061 { 1062 DECLARE_BITMAP(ones, MAX_LINE); 1063 DECLARE_BITMAP(cur_stat, MAX_LINE); 1064 DECLARE_BITMAP(new_stat, MAX_LINE); 1065 DECLARE_BITMAP(trigger, MAX_LINE); 1066 1067 bitmap_fill(ones, MAX_LINE); 1068 1069 /* Read the current interrupt status from the device */ 1070 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones)) 1071 return false; 1072 1073 /* Check latched inputs */ 1074 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger)) 1075 return false; 1076 1077 /* Apply filter for rising/falling edge selection */ 1078 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, 1079 cur_stat, MAX_LINE); 1080 1081 bitmap_and(pending, new_stat, trigger, MAX_LINE); 1082 1083 return !bitmap_empty(pending, MAX_LINE); 1084 } 1085 1086 static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid) 1087 { 1088 struct cy8c95x0_pinctrl *chip = devid; 1089 struct gpio_chip *gc = &chip->gpio_chip; 1090 DECLARE_BITMAP(pending, MAX_LINE); 1091 int nested_irq, level; 1092 bool ret; 1093 1094 ret = cy8c95x0_irq_pending(chip, pending); 1095 if (!ret) 1096 return IRQ_RETVAL(0); 1097 1098 ret = 0; 1099 for_each_set_bit(level, pending, MAX_LINE) { 1100 /* Already accounted for 4bit gap in GPort2 */ 1101 nested_irq = irq_find_mapping(gc->irq.domain, level); 1102 1103 if (unlikely(nested_irq <= 0)) { 1104 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); 1105 continue; 1106 } 1107 1108 if (test_bit(level, chip->irq_trig_low)) 1109 while (!cy8c95x0_gpio_get_value(gc, level)) 1110 handle_nested_irq(nested_irq); 1111 else if (test_bit(level, chip->irq_trig_high)) 1112 while (cy8c95x0_gpio_get_value(gc, level)) 1113 handle_nested_irq(nested_irq); 1114 else 1115 handle_nested_irq(nested_irq); 1116 1117 ret = 1; 1118 } 1119 1120 return IRQ_RETVAL(ret); 1121 } 1122 1123 static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 1124 { 1125 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1126 1127 return chip->tpin; 1128 } 1129 1130 static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 1131 unsigned int group) 1132 { 1133 return cy8c95x0_groups[group]; 1134 } 1135 1136 static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 1137 unsigned int group, 1138 const unsigned int **pins, 1139 unsigned int *num_pins) 1140 { 1141 *pins = &cy8c9560_pins[group].number; 1142 *num_pins = 1; 1143 return 0; 1144 } 1145 1146 static const char *cy8c95x0_get_fname(unsigned int selector) 1147 { 1148 if (selector == 0) 1149 return "gpio"; 1150 else 1151 return "pwm"; 1152 } 1153 1154 static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 1155 unsigned int pin) 1156 { 1157 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1158 DECLARE_BITMAP(mask, MAX_LINE); 1159 DECLARE_BITMAP(pwm, MAX_LINE); 1160 1161 bitmap_zero(mask, MAX_LINE); 1162 __set_bit(pin, mask); 1163 1164 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_SELPWM, pwm, mask)) { 1165 seq_puts(s, "not available"); 1166 return; 1167 } 1168 1169 seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm))); 1170 } 1171 1172 static const struct pinctrl_ops cy8c95x0_pinctrl_ops = { 1173 .get_groups_count = cy8c95x0_pinctrl_get_groups_count, 1174 .get_group_name = cy8c95x0_pinctrl_get_group_name, 1175 .get_group_pins = cy8c95x0_pinctrl_get_group_pins, 1176 #ifdef CONFIG_OF 1177 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1178 .dt_free_map = pinconf_generic_dt_free_map, 1179 #endif 1180 .pin_dbg_show = cy8c95x0_pin_dbg_show, 1181 }; 1182 1183 static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector) 1184 { 1185 return cy8c95x0_get_fname(selector); 1186 } 1187 1188 static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev) 1189 { 1190 return 2; 1191 } 1192 1193 static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, 1194 const char * const **groups, 1195 unsigned int * const num_groups) 1196 { 1197 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1198 1199 *groups = cy8c95x0_groups; 1200 *num_groups = chip->tpin; 1201 return 0; 1202 } 1203 1204 static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode) 1205 { 1206 u8 port = cypress_get_port(chip, off); 1207 u8 bit = cypress_get_pin_mask(chip, off); 1208 1209 return cy8c95x0_regmap_write_bits(chip, CY8C95X0_SELPWM, port, bit, mode ? bit : 0); 1210 } 1211 1212 static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip, 1213 unsigned int selector, unsigned int group) 1214 { 1215 u8 port = cypress_get_port(chip, group); 1216 u8 bit = cypress_get_pin_mask(chip, group); 1217 int ret; 1218 1219 ret = cy8c95x0_set_mode(chip, group, selector); 1220 if (ret < 0) 1221 return ret; 1222 1223 if (selector == 0) 1224 return 0; 1225 1226 /* Set direction to output & set output to 1 so that PWM can work */ 1227 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, bit); 1228 if (ret < 0) 1229 return ret; 1230 1231 return cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, bit); 1232 } 1233 1234 static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, 1235 unsigned int group) 1236 { 1237 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1238 1239 return cy8c95x0_pinmux_mode(chip, selector, group); 1240 } 1241 1242 static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev, 1243 struct pinctrl_gpio_range *range, 1244 unsigned int pin) 1245 { 1246 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1247 1248 return cy8c95x0_set_mode(chip, pin, false); 1249 } 1250 1251 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, 1252 unsigned int pin, bool input) 1253 { 1254 u8 port = cypress_get_port(chip, pin); 1255 u8 bit = cypress_get_pin_mask(chip, pin); 1256 int ret; 1257 1258 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, input ? bit : 0); 1259 if (ret) 1260 return ret; 1261 1262 /* 1263 * Disable driving the pin by forcing it to HighZ. Only setting 1264 * the direction register isn't sufficient in Push-Pull mode. 1265 */ 1266 if (input && test_bit(pin, chip->push_pull)) { 1267 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bit); 1268 if (ret) 1269 return ret; 1270 1271 __clear_bit(pin, chip->push_pull); 1272 } 1273 1274 return 0; 1275 } 1276 1277 static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev, 1278 struct pinctrl_gpio_range *range, 1279 unsigned int pin, bool input) 1280 { 1281 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1282 1283 return cy8c95x0_pinmux_direction(chip, pin, input); 1284 } 1285 1286 static const struct pinmux_ops cy8c95x0_pmxops = { 1287 .get_functions_count = cy8c95x0_get_functions_count, 1288 .get_function_name = cy8c95x0_get_function_name, 1289 .get_function_groups = cy8c95x0_get_function_groups, 1290 .set_mux = cy8c95x0_set_mux, 1291 .gpio_request_enable = cy8c95x0_gpio_request_enable, 1292 .gpio_set_direction = cy8c95x0_gpio_set_direction, 1293 .strict = true, 1294 }; 1295 1296 static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 1297 unsigned long *config) 1298 { 1299 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1300 1301 return cy8c95x0_gpio_get_pincfg(chip, pin, config); 1302 } 1303 1304 static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1305 unsigned long *configs, unsigned int num_configs) 1306 { 1307 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1308 int ret = 0; 1309 int i; 1310 1311 for (i = 0; i < num_configs; i++) { 1312 ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]); 1313 if (ret) 1314 return ret; 1315 } 1316 1317 return ret; 1318 } 1319 1320 static const struct pinconf_ops cy8c95x0_pinconf_ops = { 1321 .pin_config_get = cy8c95x0_pinconf_get, 1322 .pin_config_set = cy8c95x0_pinconf_set, 1323 .is_generic = true, 1324 }; 1325 1326 static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq) 1327 { 1328 struct gpio_irq_chip *girq = &chip->gpio_chip.irq; 1329 DECLARE_BITMAP(pending_irqs, MAX_LINE); 1330 int ret; 1331 1332 mutex_init(&chip->irq_lock); 1333 1334 bitmap_zero(pending_irqs, MAX_LINE); 1335 1336 /* Read IRQ status register to clear all pending interrupts */ 1337 ret = cy8c95x0_irq_pending(chip, pending_irqs); 1338 if (ret) { 1339 dev_err(chip->dev, "failed to clear irq status register\n"); 1340 return ret; 1341 } 1342 1343 /* Mask all interrupts */ 1344 bitmap_fill(chip->irq_mask, MAX_LINE); 1345 1346 gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip); 1347 1348 /* This will let us handle the parent IRQ in the driver */ 1349 girq->parent_handler = NULL; 1350 girq->num_parents = 0; 1351 girq->parents = NULL; 1352 girq->default_type = IRQ_TYPE_NONE; 1353 girq->handler = handle_simple_irq; 1354 girq->threaded = true; 1355 1356 ret = devm_request_threaded_irq(chip->dev, irq, 1357 NULL, cy8c95x0_irq_handler, 1358 IRQF_ONESHOT | IRQF_SHARED, 1359 dev_name(chip->dev), chip); 1360 if (ret) { 1361 dev_err(chip->dev, "failed to request irq %d\n", irq); 1362 return ret; 1363 } 1364 dev_info(chip->dev, "Registered threaded IRQ\n"); 1365 1366 return 0; 1367 } 1368 1369 static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip) 1370 { 1371 struct pinctrl_desc *pd = &chip->pinctrl_desc; 1372 1373 pd->pctlops = &cy8c95x0_pinctrl_ops; 1374 pd->confops = &cy8c95x0_pinconf_ops; 1375 pd->pmxops = &cy8c95x0_pmxops; 1376 pd->name = dev_name(chip->dev); 1377 pd->pins = cy8c9560_pins; 1378 pd->npins = chip->tpin; 1379 pd->owner = THIS_MODULE; 1380 1381 chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip); 1382 if (IS_ERR(chip->pctldev)) 1383 return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev), 1384 "can't register controller\n"); 1385 1386 return 0; 1387 } 1388 1389 static int cy8c95x0_detect(struct i2c_client *client, 1390 struct i2c_board_info *info) 1391 { 1392 struct i2c_adapter *adapter = client->adapter; 1393 int ret; 1394 const char *name; 1395 1396 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1397 return -ENODEV; 1398 1399 ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID); 1400 if (ret < 0) 1401 return ret; 1402 switch (ret & GENMASK(7, 4)) { 1403 case 0x20: 1404 name = cy8c95x0_id[0].name; 1405 break; 1406 case 0x40: 1407 name = cy8c95x0_id[1].name; 1408 break; 1409 case 0x60: 1410 name = cy8c95x0_id[2].name; 1411 break; 1412 default: 1413 return -ENODEV; 1414 } 1415 1416 dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr); 1417 strscpy(info->type, name); 1418 1419 return 0; 1420 } 1421 1422 static int cy8c95x0_probe(struct i2c_client *client) 1423 { 1424 struct device *dev = &client->dev; 1425 struct cy8c95x0_pinctrl *chip; 1426 struct regmap_config regmap_conf; 1427 struct regmap_range_cfg regmap_range_conf; 1428 int ret; 1429 1430 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 1431 if (!chip) 1432 return -ENOMEM; 1433 1434 chip->dev = dev; 1435 1436 /* Set the device type */ 1437 chip->driver_data = (uintptr_t)i2c_get_match_data(client); 1438 if (!chip->driver_data) 1439 return -ENODEV; 1440 1441 chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK; 1442 chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ); 1443 1444 memcpy(®map_range_conf, &cy8c95x0_ranges[0], sizeof(regmap_range_conf)); 1445 1446 switch (chip->tpin) { 1447 case 20: 1448 strscpy(chip->name, cy8c95x0_id[0].name); 1449 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE - 1; 1450 break; 1451 case 40: 1452 strscpy(chip->name, cy8c95x0_id[1].name); 1453 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE - 1; 1454 break; 1455 case 60: 1456 strscpy(chip->name, cy8c95x0_id[2].name); 1457 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE - 1; 1458 break; 1459 default: 1460 return -ENODEV; 1461 } 1462 1463 ret = devm_regulator_get_enable(dev, "vdd"); 1464 if (ret) 1465 return dev_err_probe(dev, ret, "failed to enable regulator vdd\n"); 1466 1467 /* bring the chip out of reset if reset pin is provided */ 1468 chip->gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1469 if (IS_ERR(chip->gpio_reset)) 1470 return dev_err_probe(dev, PTR_ERR(chip->gpio_reset), "Failed to get GPIO 'reset'\n"); 1471 gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET"); 1472 if (chip->gpio_reset) { 1473 fsleep(1000); 1474 gpiod_set_value_cansleep(chip->gpio_reset, 0); 1475 fsleep(250000); 1476 } 1477 1478 /* Regmap for direct and paged registers */ 1479 memcpy(®map_conf, &cy8c9520_i2c_regmap, sizeof(regmap_conf)); 1480 regmap_conf.ranges = ®map_range_conf; 1481 regmap_conf.max_register = regmap_range_conf.range_max; 1482 regmap_conf.num_reg_defaults_raw = regmap_range_conf.range_max; 1483 1484 chip->regmap = devm_regmap_init_i2c(client, ®map_conf); 1485 if (IS_ERR(chip->regmap)) 1486 return PTR_ERR(chip->regmap); 1487 1488 bitmap_zero(chip->push_pull, MAX_LINE); 1489 bitmap_zero(chip->shiftmask, MAX_LINE); 1490 bitmap_set(chip->shiftmask, 0, 20); 1491 mutex_init(&chip->i2c_lock); 1492 1493 if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) { 1494 ret = cy8c95x0_acpi_get_irq(&client->dev); 1495 if (ret > 0) 1496 client->irq = ret; 1497 } 1498 1499 if (client->irq) { 1500 ret = cy8c95x0_irq_setup(chip, client->irq); 1501 if (ret) 1502 return ret; 1503 } 1504 1505 ret = cy8c95x0_setup_pinctrl(chip); 1506 if (ret) 1507 return ret; 1508 1509 return cy8c95x0_setup_gpiochip(chip); 1510 } 1511 1512 static const struct acpi_device_id cy8c95x0_acpi_ids[] = { 1513 { "INT3490", 40, }, 1514 { } 1515 }; 1516 MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids); 1517 1518 static struct i2c_driver cy8c95x0_driver = { 1519 .driver = { 1520 .name = "cy8c95x0-pinctrl", 1521 .of_match_table = cy8c95x0_dt_ids, 1522 .acpi_match_table = cy8c95x0_acpi_ids, 1523 }, 1524 .probe = cy8c95x0_probe, 1525 .id_table = cy8c95x0_id, 1526 .detect = cy8c95x0_detect, 1527 }; 1528 module_i2c_driver(cy8c95x0_driver); 1529 1530 MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>"); 1531 MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>"); 1532 MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0"); 1533 MODULE_LICENSE("GPL"); 1534