1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support 4 * 5 * Copyright (C) 2022 9elements GmbH 6 * Authors: Patrick Rudolph <patrick.rudolph@9elements.com> 7 * Naresh Solanki <Naresh.Solanki@9elements.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/bitmap.h> 12 #include <linux/cleanup.h> 13 #include <linux/dmi.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/module.h> 21 #include <linux/property.h> 22 #include <linux/regmap.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/seq_file.h> 25 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/pinctrl/pinconf.h> 28 #include <linux/pinctrl/pinconf-generic.h> 29 #include <linux/pinctrl/pinctrl.h> 30 #include <linux/pinctrl/pinmux.h> 31 32 /* Fast access registers */ 33 #define CY8C95X0_INPUT 0x00 34 #define CY8C95X0_OUTPUT 0x08 35 #define CY8C95X0_INTSTATUS 0x10 36 37 #define CY8C95X0_INPUT_(x) (CY8C95X0_INPUT + (x)) 38 #define CY8C95X0_OUTPUT_(x) (CY8C95X0_OUTPUT + (x)) 39 #define CY8C95X0_INTSTATUS_(x) (CY8C95X0_INTSTATUS + (x)) 40 41 /* Port Select configures the port */ 42 #define CY8C95X0_PORTSEL 0x18 43 44 /* Port settings, write PORTSEL first */ 45 #define CY8C95X0_INTMASK 0x19 46 #define CY8C95X0_SELPWM 0x1A 47 #define CY8C95X0_INVERT 0x1B 48 #define CY8C95X0_DIRECTION 0x1C 49 /* Drive mode register change state on writing '1' */ 50 #define CY8C95X0_DRV_PU 0x1D 51 #define CY8C95X0_DRV_PD 0x1E 52 #define CY8C95X0_DRV_ODH 0x1F 53 #define CY8C95X0_DRV_ODL 0x20 54 #define CY8C95X0_DRV_PP_FAST 0x21 55 #define CY8C95X0_DRV_PP_SLOW 0x22 56 #define CY8C95X0_DRV_HIZ 0x23 57 58 /* Internal device configuration */ 59 #define CY8C95X0_ENABLE_WDE 0x2D 60 #define CY8C95X0_DEVID 0x2E 61 #define CY8C95X0_WATCHDOG 0x2F 62 #define CY8C95X0_COMMAND 0x30 63 64 #define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x)) 65 66 #define MAX_BANK 8 67 #define BANK_SZ 8 68 #define MAX_LINE (MAX_BANK * BANK_SZ) 69 #define MUXED_STRIDE 16 70 #define CY8C95X0_GPIO_MASK GENMASK(7, 0) 71 #define CY8C95X0_VIRTUAL 0x40 72 #define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \ 73 (CY8C95X0_VIRTUAL + (x) - CY8C95X0_PORTSEL + (p) * MUXED_STRIDE) 74 75 static const struct i2c_device_id cy8c95x0_id[] = { 76 { "cy8c9520", 20, }, 77 { "cy8c9540", 40, }, 78 { "cy8c9560", 60, }, 79 { } 80 }; 81 MODULE_DEVICE_TABLE(i2c, cy8c95x0_id); 82 83 #define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio)) 84 85 static const struct of_device_id cy8c95x0_dt_ids[] = { 86 { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), }, 87 { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), }, 88 { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), }, 89 { } 90 }; 91 MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids); 92 93 static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true }; 94 95 static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = { 96 { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, 97 { } 98 }; 99 100 static int cy8c95x0_acpi_get_irq(struct device *dev) 101 { 102 int ret; 103 104 ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios); 105 if (ret) 106 dev_warn(dev, "can't add GPIO ACPI mapping\n"); 107 108 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0); 109 if (ret < 0) 110 return ret; 111 112 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); 113 return ret; 114 } 115 116 static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = { 117 { 118 /* 119 * On Intel Galileo Gen 1 board the IRQ pin is provided 120 * as an absolute number instead of being relative. 121 * Since first controller (gpio-sch.c) and second 122 * (gpio-dwapb.c) are at the fixed bases, we may safely 123 * refer to the number in the global space to get an IRQ 124 * out of it. 125 */ 126 .matches = { 127 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 128 }, 129 }, 130 {} 131 }; 132 133 /** 134 * struct cy8c95x0_pinctrl - driver data 135 * @regmap: Device's regmap. Only direct access registers. 136 * @irq_lock: IRQ bus lock 137 * @i2c_lock: Mutex to hold while using the regmap 138 * @irq_mask: I/O bits affected by interrupts 139 * @irq_trig_raise: I/O bits affected by raising voltage level 140 * @irq_trig_fall: I/O bits affected by falling voltage level 141 * @irq_trig_low: I/O bits affected by a low voltage level 142 * @irq_trig_high: I/O bits affected by a high voltage level 143 * @push_pull: I/O bits configured as push pull driver 144 * @map: Mask used to compensate for Gport2 width 145 * @nport: Number of Gports in this chip 146 * @gpio_chip: gpiolib chip 147 * @driver_data: private driver data 148 * @dev: struct device 149 * @pctldev: pin controller device 150 * @pinctrl_desc: pin controller description 151 * @name: Chip controller name 152 * @tpin: Total number of pins 153 * @gpio_reset: GPIO line handler that can reset the IC 154 */ 155 struct cy8c95x0_pinctrl { 156 struct regmap *regmap; 157 struct mutex irq_lock; 158 struct mutex i2c_lock; 159 DECLARE_BITMAP(irq_mask, MAX_LINE); 160 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 161 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 162 DECLARE_BITMAP(irq_trig_low, MAX_LINE); 163 DECLARE_BITMAP(irq_trig_high, MAX_LINE); 164 DECLARE_BITMAP(push_pull, MAX_LINE); 165 DECLARE_BITMAP(map, MAX_LINE); 166 unsigned int nport; 167 struct gpio_chip gpio_chip; 168 unsigned long driver_data; 169 struct device *dev; 170 struct pinctrl_dev *pctldev; 171 struct pinctrl_desc pinctrl_desc; 172 char name[32]; 173 unsigned int tpin; 174 struct gpio_desc *gpio_reset; 175 }; 176 177 static const struct pinctrl_pin_desc cy8c9560_pins[] = { 178 PINCTRL_PIN(0, "gp00"), 179 PINCTRL_PIN(1, "gp01"), 180 PINCTRL_PIN(2, "gp02"), 181 PINCTRL_PIN(3, "gp03"), 182 PINCTRL_PIN(4, "gp04"), 183 PINCTRL_PIN(5, "gp05"), 184 PINCTRL_PIN(6, "gp06"), 185 PINCTRL_PIN(7, "gp07"), 186 187 PINCTRL_PIN(8, "gp10"), 188 PINCTRL_PIN(9, "gp11"), 189 PINCTRL_PIN(10, "gp12"), 190 PINCTRL_PIN(11, "gp13"), 191 PINCTRL_PIN(12, "gp14"), 192 PINCTRL_PIN(13, "gp15"), 193 PINCTRL_PIN(14, "gp16"), 194 PINCTRL_PIN(15, "gp17"), 195 196 PINCTRL_PIN(16, "gp20"), 197 PINCTRL_PIN(17, "gp21"), 198 PINCTRL_PIN(18, "gp22"), 199 PINCTRL_PIN(19, "gp23"), 200 201 PINCTRL_PIN(20, "gp30"), 202 PINCTRL_PIN(21, "gp31"), 203 PINCTRL_PIN(22, "gp32"), 204 PINCTRL_PIN(23, "gp33"), 205 PINCTRL_PIN(24, "gp34"), 206 PINCTRL_PIN(25, "gp35"), 207 PINCTRL_PIN(26, "gp36"), 208 PINCTRL_PIN(27, "gp37"), 209 210 PINCTRL_PIN(28, "gp40"), 211 PINCTRL_PIN(29, "gp41"), 212 PINCTRL_PIN(30, "gp42"), 213 PINCTRL_PIN(31, "gp43"), 214 PINCTRL_PIN(32, "gp44"), 215 PINCTRL_PIN(33, "gp45"), 216 PINCTRL_PIN(34, "gp46"), 217 PINCTRL_PIN(35, "gp47"), 218 219 PINCTRL_PIN(36, "gp50"), 220 PINCTRL_PIN(37, "gp51"), 221 PINCTRL_PIN(38, "gp52"), 222 PINCTRL_PIN(39, "gp53"), 223 PINCTRL_PIN(40, "gp54"), 224 PINCTRL_PIN(41, "gp55"), 225 PINCTRL_PIN(42, "gp56"), 226 PINCTRL_PIN(43, "gp57"), 227 228 PINCTRL_PIN(44, "gp60"), 229 PINCTRL_PIN(45, "gp61"), 230 PINCTRL_PIN(46, "gp62"), 231 PINCTRL_PIN(47, "gp63"), 232 PINCTRL_PIN(48, "gp64"), 233 PINCTRL_PIN(49, "gp65"), 234 PINCTRL_PIN(50, "gp66"), 235 PINCTRL_PIN(51, "gp67"), 236 237 PINCTRL_PIN(52, "gp70"), 238 PINCTRL_PIN(53, "gp71"), 239 PINCTRL_PIN(54, "gp72"), 240 PINCTRL_PIN(55, "gp73"), 241 PINCTRL_PIN(56, "gp74"), 242 PINCTRL_PIN(57, "gp75"), 243 PINCTRL_PIN(58, "gp76"), 244 PINCTRL_PIN(59, "gp77"), 245 }; 246 247 static const char * const cy8c95x0_groups[] = { 248 "gp00", 249 "gp01", 250 "gp02", 251 "gp03", 252 "gp04", 253 "gp05", 254 "gp06", 255 "gp07", 256 257 "gp10", 258 "gp11", 259 "gp12", 260 "gp13", 261 "gp14", 262 "gp15", 263 "gp16", 264 "gp17", 265 266 "gp20", 267 "gp21", 268 "gp22", 269 "gp23", 270 271 "gp30", 272 "gp31", 273 "gp32", 274 "gp33", 275 "gp34", 276 "gp35", 277 "gp36", 278 "gp37", 279 280 "gp40", 281 "gp41", 282 "gp42", 283 "gp43", 284 "gp44", 285 "gp45", 286 "gp46", 287 "gp47", 288 289 "gp50", 290 "gp51", 291 "gp52", 292 "gp53", 293 "gp54", 294 "gp55", 295 "gp56", 296 "gp57", 297 298 "gp60", 299 "gp61", 300 "gp62", 301 "gp63", 302 "gp64", 303 "gp65", 304 "gp66", 305 "gp67", 306 307 "gp70", 308 "gp71", 309 "gp72", 310 "gp73", 311 "gp74", 312 "gp75", 313 "gp76", 314 "gp77", 315 }; 316 317 static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin) 318 { 319 /* Account for GPORT2 which only has 4 bits */ 320 return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ; 321 } 322 323 static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin) 324 { 325 /* Account for GPORT2 which only has 4 bits */ 326 return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ); 327 } 328 329 static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg) 330 { 331 /* 332 * Only 12 registers are present per port (see Table 6 in the datasheet). 333 */ 334 if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) >= 12) 335 return false; 336 337 switch (reg) { 338 case 0x24 ... 0x27: 339 case 0x31 ... 0x3f: 340 return false; 341 default: 342 return true; 343 } 344 } 345 346 static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg) 347 { 348 /* 349 * Only 12 registers are present per port (see Table 6 in the datasheet). 350 */ 351 if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) >= 12) 352 return false; 353 354 switch (reg) { 355 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): 356 return false; 357 case CY8C95X0_DEVID: 358 return false; 359 case 0x24 ... 0x27: 360 case 0x31 ... 0x3f: 361 return false; 362 default: 363 return true; 364 } 365 } 366 367 static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg) 368 { 369 switch (reg) { 370 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): 371 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): 372 case CY8C95X0_INTMASK: 373 case CY8C95X0_SELPWM: 374 case CY8C95X0_INVERT: 375 case CY8C95X0_DIRECTION: 376 case CY8C95X0_DRV_PU: 377 case CY8C95X0_DRV_PD: 378 case CY8C95X0_DRV_ODH: 379 case CY8C95X0_DRV_ODL: 380 case CY8C95X0_DRV_PP_FAST: 381 case CY8C95X0_DRV_PP_SLOW: 382 case CY8C95X0_DRV_HIZ: 383 return true; 384 default: 385 return false; 386 } 387 } 388 389 static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg) 390 { 391 switch (reg) { 392 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): 393 return true; 394 default: 395 return false; 396 } 397 } 398 399 static bool cy8c95x0_muxed_register(unsigned int reg) 400 { 401 switch (reg) { 402 case CY8C95X0_INTMASK: 403 case CY8C95X0_SELPWM: 404 case CY8C95X0_INVERT: 405 case CY8C95X0_DIRECTION: 406 case CY8C95X0_DRV_PU: 407 case CY8C95X0_DRV_PD: 408 case CY8C95X0_DRV_ODH: 409 case CY8C95X0_DRV_ODL: 410 case CY8C95X0_DRV_PP_FAST: 411 case CY8C95X0_DRV_PP_SLOW: 412 case CY8C95X0_DRV_HIZ: 413 return true; 414 default: 415 return false; 416 } 417 } 418 419 static bool cy8c95x0_wc_register(unsigned int reg) 420 { 421 switch (reg) { 422 case CY8C95X0_DRV_PU: 423 case CY8C95X0_DRV_PD: 424 case CY8C95X0_DRV_ODH: 425 case CY8C95X0_DRV_ODL: 426 case CY8C95X0_DRV_PP_FAST: 427 case CY8C95X0_DRV_PP_SLOW: 428 case CY8C95X0_DRV_HIZ: 429 return true; 430 default: 431 return false; 432 } 433 } 434 435 static bool cy8c95x0_quick_path_register(unsigned int reg) 436 { 437 switch (reg) { 438 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): 439 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): 440 case CY8C95X0_OUTPUT_(0) ... CY8C95X0_OUTPUT_(7): 441 return true; 442 default: 443 return false; 444 } 445 } 446 447 static const struct regmap_range_cfg cy8c95x0_ranges[] = { 448 { 449 .range_min = CY8C95X0_VIRTUAL, 450 .range_max = 0, /* Updated at runtime */ 451 .selector_reg = CY8C95X0_PORTSEL, 452 .selector_mask = 0x07, 453 .selector_shift = 0x0, 454 .window_start = CY8C95X0_PORTSEL, 455 .window_len = MUXED_STRIDE, 456 } 457 }; 458 459 static const struct regmap_config cy8c9520_i2c_regmap = { 460 .reg_bits = 8, 461 .val_bits = 8, 462 463 .readable_reg = cy8c95x0_readable_register, 464 .writeable_reg = cy8c95x0_writeable_register, 465 .volatile_reg = cy8c95x0_volatile_register, 466 .precious_reg = cy8c95x0_precious_register, 467 468 .cache_type = REGCACHE_MAPLE, 469 .ranges = NULL, /* Updated at runtime */ 470 .num_ranges = 1, 471 .max_register = 0, /* Updated at runtime */ 472 .num_reg_defaults_raw = 0, /* Updated at runtime */ 473 .use_single_read = true, /* Workaround for regcache bug */ 474 #if IS_ENABLED(CONFIG_DEBUG_PINCTRL) 475 .disable_locking = false, 476 #else 477 .disable_locking = true, 478 #endif 479 }; 480 481 /* Caller should never modify PORTSEL directly */ 482 static int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip, 483 unsigned int reg, unsigned int port, 484 unsigned int mask, unsigned int val, 485 bool *change, bool async, bool force) 486 { 487 int ret, off, i; 488 489 /* Registers behind the PORTSEL mux have their own range in regmap */ 490 if (cy8c95x0_muxed_register(reg)) { 491 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port); 492 } else { 493 /* Quick path direct access registers honor the port argument */ 494 if (cy8c95x0_quick_path_register(reg)) 495 off = reg + port; 496 else 497 off = reg; 498 } 499 guard(mutex)(&chip->i2c_lock); 500 501 ret = regmap_update_bits_base(chip->regmap, off, mask, val, change, async, force); 502 if (ret < 0) 503 return ret; 504 505 /* 506 * Mimic what hardware does and update the cache when a WC bit is written. 507 * Allows to mark the registers as non-volatile and reduces I/O cycles. 508 */ 509 if (cy8c95x0_wc_register(reg) && (mask & val)) { 510 /* Writing a 1 clears set bits in the other drive mode registers */ 511 regcache_cache_only(chip->regmap, true); 512 for (i = CY8C95X0_DRV_PU; i <= CY8C95X0_DRV_HIZ; i++) { 513 if (i == reg) 514 continue; 515 516 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port); 517 regmap_clear_bits(chip->regmap, off, mask & val); 518 } 519 regcache_cache_only(chip->regmap, false); 520 } 521 522 return 0; 523 } 524 525 /** 526 * cy8c95x0_regmap_write_bits() - writes a register using the regmap cache 527 * @chip: The pinctrl to work on 528 * @reg: The register to write to. Can be direct access or muxed register. 529 * MUST NOT be the PORTSEL register. 530 * @port: The port to be used for muxed registers or quick path direct access 531 * registers. Otherwise unused. 532 * @mask: Bitmask to change 533 * @val: New value for bitmask 534 * 535 * This function handles the register writes to the direct access registers and 536 * the muxed registers while caching all register accesses, internally handling 537 * the correct state of the PORTSEL register and protecting the access to muxed 538 * registers. 539 * The caller must only use this function to change registers behind the PORTSEL mux. 540 * 541 * Return: 0 for successful request, else a corresponding error value 542 */ 543 static int cy8c95x0_regmap_write_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg, 544 unsigned int port, unsigned int mask, unsigned int val) 545 { 546 return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, true); 547 } 548 549 /** 550 * cy8c95x0_regmap_update_bits() - updates a register using the regmap cache 551 * @chip: The pinctrl to work on 552 * @reg: The register to write to. Can be direct access or muxed register. 553 * MUST NOT be the PORTSEL register. 554 * @port: The port to be used for muxed registers or quick path direct access 555 * registers. Otherwise unused. 556 * @mask: Bitmask to change 557 * @val: New value for bitmask 558 * 559 * This function handles the register updates to the direct access registers and 560 * the muxed registers while caching all register accesses, internally handling 561 * the correct state of the PORTSEL register and protecting the access to muxed 562 * registers. 563 * The caller must only use this function to change registers behind the PORTSEL mux. 564 * 565 * Return: 0 for successful request, else a corresponding error value 566 */ 567 static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg, 568 unsigned int port, unsigned int mask, unsigned int val) 569 { 570 return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, false); 571 } 572 573 /** 574 * cy8c95x0_regmap_read_bits() - reads a register using the regmap cache 575 * @chip: The pinctrl to work on 576 * @reg: The register to read from. Can be direct access or muxed register. 577 * @port: The port to be used for muxed registers or quick path direct access 578 * registers. Otherwise unused. 579 * @mask: Bitmask to apply 580 * @val: Value read from hardware or cache 581 * 582 * This function handles the register reads from the direct access registers and 583 * the muxed registers while caching all register accesses, internally handling 584 * the correct state of the PORTSEL register and protecting the access to muxed 585 * registers. 586 * The caller must only use this function to read registers behind the PORTSEL mux. 587 * 588 * Return: 0 for successful request, else a corresponding error value 589 */ 590 static int cy8c95x0_regmap_read_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg, 591 unsigned int port, unsigned int mask, unsigned int *val) 592 { 593 unsigned int off; 594 unsigned int tmp; 595 int ret; 596 597 /* Registers behind the PORTSEL mux have their own range in regmap */ 598 if (cy8c95x0_muxed_register(reg)) { 599 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port); 600 } else { 601 /* Quick path direct access registers honor the port argument */ 602 if (cy8c95x0_quick_path_register(reg)) 603 off = reg + port; 604 else 605 off = reg; 606 } 607 608 scoped_guard(mutex, &chip->i2c_lock) 609 ret = regmap_read(chip->regmap, off, &tmp); 610 if (ret) 611 return ret; 612 613 *val = tmp & mask; 614 return 0; 615 } 616 617 static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, 618 unsigned long *val, unsigned long *mask) 619 { 620 DECLARE_BITMAP(tmask, MAX_LINE); 621 DECLARE_BITMAP(tval, MAX_LINE); 622 unsigned long bits, offset; 623 int write_val; 624 int ret; 625 626 /* Add the 4 bit gap of Gport2 */ 627 bitmap_scatter(tmask, mask, chip->map, MAX_LINE); 628 bitmap_scatter(tval, val, chip->map, MAX_LINE); 629 630 for_each_set_clump8(offset, bits, tmask, chip->tpin) { 631 unsigned int i = offset / 8; 632 633 write_val = bitmap_get_value8(tval, offset); 634 635 ret = cy8c95x0_regmap_update_bits(chip, reg, i, bits, write_val); 636 if (ret < 0) { 637 dev_err(chip->dev, "failed writing register %d, port %u: err %d\n", reg, i, ret); 638 return ret; 639 } 640 } 641 642 return 0; 643 } 644 645 static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, 646 unsigned long *val, unsigned long *mask) 647 { 648 DECLARE_BITMAP(tmask, MAX_LINE); 649 DECLARE_BITMAP(tval, MAX_LINE); 650 unsigned long bits, offset; 651 unsigned int read_val; 652 int ret; 653 654 /* Add the 4 bit gap of Gport2 */ 655 bitmap_scatter(tmask, mask, chip->map, MAX_LINE); 656 bitmap_scatter(tval, val, chip->map, MAX_LINE); 657 658 for_each_set_clump8(offset, bits, tmask, chip->tpin) { 659 unsigned int i = offset / 8; 660 661 ret = cy8c95x0_regmap_read_bits(chip, reg, i, bits, &read_val); 662 if (ret < 0) { 663 dev_err(chip->dev, "failed reading register %d, port %u: err %d\n", reg, i, ret); 664 return ret; 665 } 666 667 read_val |= bitmap_get_value8(tval, offset) & ~bits; 668 bitmap_set_value8(tval, read_val, offset); 669 } 670 671 /* Fill the 4 bit gap of Gport2 */ 672 bitmap_gather(val, tval, chip->map, MAX_LINE); 673 674 return 0; 675 } 676 677 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, unsigned int pin, bool input) 678 { 679 u8 port = cypress_get_port(chip, pin); 680 u8 bit = cypress_get_pin_mask(chip, pin); 681 int ret; 682 683 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, input ? bit : 0); 684 if (ret) 685 return ret; 686 687 /* 688 * Disable driving the pin by forcing it to HighZ. Only setting 689 * the direction register isn't sufficient in Push-Pull mode. 690 */ 691 if (input && test_bit(pin, chip->push_pull)) { 692 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bit); 693 if (ret) 694 return ret; 695 696 __clear_bit(pin, chip->push_pull); 697 } 698 699 return 0; 700 } 701 702 static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off) 703 { 704 return pinctrl_gpio_direction_input(gc, off); 705 } 706 707 static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc, 708 unsigned int off, int val) 709 { 710 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 711 u8 port = cypress_get_port(chip, off); 712 u8 bit = cypress_get_pin_mask(chip, off); 713 int ret; 714 715 /* Set output level */ 716 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0); 717 if (ret) 718 return ret; 719 720 return pinctrl_gpio_direction_output(gc, off); 721 } 722 723 static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off) 724 { 725 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 726 u8 port = cypress_get_port(chip, off); 727 u8 bit = cypress_get_pin_mask(chip, off); 728 unsigned int reg_val; 729 int ret; 730 731 ret = cy8c95x0_regmap_read_bits(chip, CY8C95X0_INPUT, port, bit, ®_val); 732 if (ret < 0) { 733 /* 734 * NOTE: 735 * Diagnostic already emitted; that's all we should 736 * do unless gpio_*_value_cansleep() calls become different 737 * from their nonsleeping siblings (and report faults). 738 */ 739 return 0; 740 } 741 742 return reg_val ? 1 : 0; 743 } 744 745 static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off, 746 int val) 747 { 748 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 749 u8 port = cypress_get_port(chip, off); 750 u8 bit = cypress_get_pin_mask(chip, off); 751 752 cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0); 753 } 754 755 static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off) 756 { 757 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 758 u8 port = cypress_get_port(chip, off); 759 u8 bit = cypress_get_pin_mask(chip, off); 760 unsigned int reg_val; 761 int ret; 762 763 ret = cy8c95x0_regmap_read_bits(chip, CY8C95X0_DIRECTION, port, bit, ®_val); 764 if (ret < 0) 765 return ret; 766 767 if (reg_val) 768 return GPIO_LINE_DIRECTION_IN; 769 770 return GPIO_LINE_DIRECTION_OUT; 771 } 772 773 static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, 774 unsigned int off, 775 unsigned long *config) 776 { 777 enum pin_config_param param = pinconf_to_config_param(*config); 778 u8 port = cypress_get_port(chip, off); 779 u8 bit = cypress_get_pin_mask(chip, off); 780 unsigned int reg_val; 781 unsigned int reg; 782 u16 arg = 0; 783 int ret; 784 785 switch (param) { 786 case PIN_CONFIG_BIAS_PULL_UP: 787 reg = CY8C95X0_DRV_PU; 788 break; 789 case PIN_CONFIG_BIAS_PULL_DOWN: 790 reg = CY8C95X0_DRV_PD; 791 break; 792 case PIN_CONFIG_BIAS_DISABLE: 793 reg = CY8C95X0_DRV_HIZ; 794 break; 795 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 796 reg = CY8C95X0_DRV_ODL; 797 break; 798 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 799 reg = CY8C95X0_DRV_ODH; 800 break; 801 case PIN_CONFIG_DRIVE_PUSH_PULL: 802 reg = CY8C95X0_DRV_PP_FAST; 803 break; 804 case PIN_CONFIG_INPUT_ENABLE: 805 reg = CY8C95X0_DIRECTION; 806 break; 807 case PIN_CONFIG_MODE_PWM: 808 reg = CY8C95X0_SELPWM; 809 break; 810 case PIN_CONFIG_OUTPUT: 811 reg = CY8C95X0_OUTPUT; 812 break; 813 case PIN_CONFIG_OUTPUT_ENABLE: 814 reg = CY8C95X0_DIRECTION; 815 break; 816 817 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 818 case PIN_CONFIG_BIAS_BUS_HOLD: 819 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 820 case PIN_CONFIG_DRIVE_STRENGTH: 821 case PIN_CONFIG_DRIVE_STRENGTH_UA: 822 case PIN_CONFIG_INPUT_DEBOUNCE: 823 case PIN_CONFIG_INPUT_SCHMITT: 824 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 825 case PIN_CONFIG_MODE_LOW_POWER: 826 case PIN_CONFIG_PERSIST_STATE: 827 case PIN_CONFIG_POWER_SOURCE: 828 case PIN_CONFIG_SKEW_DELAY: 829 case PIN_CONFIG_SLEEP_HARDWARE_STATE: 830 case PIN_CONFIG_SLEW_RATE: 831 default: 832 return -ENOTSUPP; 833 } 834 /* 835 * Writing 1 to one of the drive mode registers will automatically 836 * clear conflicting set bits in the other drive mode registers. 837 */ 838 ret = cy8c95x0_regmap_read_bits(chip, reg, port, bit, ®_val); 839 if (ret < 0) 840 return ret; 841 842 if (reg_val) 843 arg = 1; 844 if (param == PIN_CONFIG_OUTPUT_ENABLE) 845 arg = !arg; 846 847 *config = pinconf_to_config_packed(param, arg); 848 return 0; 849 } 850 851 static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip, 852 unsigned int off, 853 unsigned long config) 854 { 855 u8 port = cypress_get_port(chip, off); 856 u8 bit = cypress_get_pin_mask(chip, off); 857 unsigned long param = pinconf_to_config_param(config); 858 unsigned long arg = pinconf_to_config_argument(config); 859 unsigned int reg; 860 861 switch (param) { 862 case PIN_CONFIG_BIAS_PULL_UP: 863 __clear_bit(off, chip->push_pull); 864 reg = CY8C95X0_DRV_PU; 865 break; 866 case PIN_CONFIG_BIAS_PULL_DOWN: 867 __clear_bit(off, chip->push_pull); 868 reg = CY8C95X0_DRV_PD; 869 break; 870 case PIN_CONFIG_BIAS_DISABLE: 871 __clear_bit(off, chip->push_pull); 872 reg = CY8C95X0_DRV_HIZ; 873 break; 874 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 875 __clear_bit(off, chip->push_pull); 876 reg = CY8C95X0_DRV_ODL; 877 break; 878 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 879 __clear_bit(off, chip->push_pull); 880 reg = CY8C95X0_DRV_ODH; 881 break; 882 case PIN_CONFIG_DRIVE_PUSH_PULL: 883 __set_bit(off, chip->push_pull); 884 reg = CY8C95X0_DRV_PP_FAST; 885 break; 886 case PIN_CONFIG_MODE_PWM: 887 reg = CY8C95X0_SELPWM; 888 break; 889 case PIN_CONFIG_OUTPUT_ENABLE: 890 return cy8c95x0_pinmux_direction(chip, off, !arg); 891 case PIN_CONFIG_INPUT_ENABLE: 892 return cy8c95x0_pinmux_direction(chip, off, arg); 893 default: 894 return -ENOTSUPP; 895 } 896 /* 897 * Writing 1 to one of the drive mode registers will automatically 898 * clear conflicting set bits in the other drive mode registers. 899 */ 900 return cy8c95x0_regmap_write_bits(chip, reg, port, bit, bit); 901 } 902 903 static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc, 904 unsigned long *mask, unsigned long *bits) 905 { 906 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 907 908 return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask); 909 } 910 911 static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc, 912 unsigned long *mask, unsigned long *bits) 913 { 914 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 915 916 cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask); 917 } 918 919 static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc) 920 { 921 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 922 struct device *dev = chip->dev; 923 int ret; 924 925 ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin); 926 if (ret) 927 dev_err(dev, "failed to add GPIO pin range\n"); 928 929 return ret; 930 } 931 932 static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip) 933 { 934 struct gpio_chip *gc = &chip->gpio_chip; 935 936 gc->request = gpiochip_generic_request; 937 gc->free = gpiochip_generic_free; 938 gc->direction_input = cy8c95x0_gpio_direction_input; 939 gc->direction_output = cy8c95x0_gpio_direction_output; 940 gc->get = cy8c95x0_gpio_get_value; 941 gc->set = cy8c95x0_gpio_set_value; 942 gc->get_direction = cy8c95x0_gpio_get_direction; 943 gc->get_multiple = cy8c95x0_gpio_get_multiple; 944 gc->set_multiple = cy8c95x0_gpio_set_multiple; 945 gc->set_config = gpiochip_generic_config; 946 gc->can_sleep = true; 947 gc->add_pin_ranges = cy8c95x0_add_pin_ranges; 948 949 gc->base = -1; 950 gc->ngpio = chip->tpin; 951 952 gc->parent = chip->dev; 953 gc->owner = THIS_MODULE; 954 gc->names = NULL; 955 956 gc->label = dev_name(chip->dev); 957 958 return devm_gpiochip_add_data(chip->dev, gc, chip); 959 } 960 961 static void cy8c95x0_irq_mask(struct irq_data *d) 962 { 963 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 964 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 965 irq_hw_number_t hwirq = irqd_to_hwirq(d); 966 967 set_bit(hwirq, chip->irq_mask); 968 gpiochip_disable_irq(gc, hwirq); 969 } 970 971 static void cy8c95x0_irq_unmask(struct irq_data *d) 972 { 973 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 974 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 975 irq_hw_number_t hwirq = irqd_to_hwirq(d); 976 977 gpiochip_enable_irq(gc, hwirq); 978 clear_bit(hwirq, chip->irq_mask); 979 } 980 981 static void cy8c95x0_irq_bus_lock(struct irq_data *d) 982 { 983 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 984 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 985 986 mutex_lock(&chip->irq_lock); 987 } 988 989 static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d) 990 { 991 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 992 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 993 DECLARE_BITMAP(ones, MAX_LINE); 994 DECLARE_BITMAP(irq_mask, MAX_LINE); 995 DECLARE_BITMAP(reg_direction, MAX_LINE); 996 997 bitmap_fill(ones, MAX_LINE); 998 999 cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones); 1000 1001 /* Switch direction to input if needed */ 1002 cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask); 1003 bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE); 1004 bitmap_complement(irq_mask, irq_mask, MAX_LINE); 1005 1006 /* Look for any newly setup interrupt */ 1007 cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask); 1008 1009 mutex_unlock(&chip->irq_lock); 1010 } 1011 1012 static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type) 1013 { 1014 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1015 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 1016 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1017 unsigned int trig_type; 1018 1019 switch (type) { 1020 case IRQ_TYPE_EDGE_RISING: 1021 case IRQ_TYPE_EDGE_FALLING: 1022 case IRQ_TYPE_EDGE_BOTH: 1023 trig_type = type; 1024 break; 1025 case IRQ_TYPE_LEVEL_HIGH: 1026 trig_type = IRQ_TYPE_EDGE_RISING; 1027 break; 1028 case IRQ_TYPE_LEVEL_LOW: 1029 trig_type = IRQ_TYPE_EDGE_FALLING; 1030 break; 1031 default: 1032 dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type); 1033 return -EINVAL; 1034 } 1035 1036 assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING); 1037 assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING); 1038 assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW); 1039 assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH); 1040 1041 return 0; 1042 } 1043 1044 static void cy8c95x0_irq_shutdown(struct irq_data *d) 1045 { 1046 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1047 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 1048 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1049 1050 clear_bit(hwirq, chip->irq_trig_raise); 1051 clear_bit(hwirq, chip->irq_trig_fall); 1052 clear_bit(hwirq, chip->irq_trig_low); 1053 clear_bit(hwirq, chip->irq_trig_high); 1054 } 1055 1056 static const struct irq_chip cy8c95x0_irqchip = { 1057 .name = "cy8c95x0-irq", 1058 .irq_mask = cy8c95x0_irq_mask, 1059 .irq_unmask = cy8c95x0_irq_unmask, 1060 .irq_bus_lock = cy8c95x0_irq_bus_lock, 1061 .irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock, 1062 .irq_set_type = cy8c95x0_irq_set_type, 1063 .irq_shutdown = cy8c95x0_irq_shutdown, 1064 .flags = IRQCHIP_IMMUTABLE, 1065 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1066 }; 1067 1068 static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending) 1069 { 1070 DECLARE_BITMAP(ones, MAX_LINE); 1071 DECLARE_BITMAP(cur_stat, MAX_LINE); 1072 DECLARE_BITMAP(new_stat, MAX_LINE); 1073 DECLARE_BITMAP(trigger, MAX_LINE); 1074 1075 bitmap_fill(ones, MAX_LINE); 1076 1077 /* Read the current interrupt status from the device */ 1078 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones)) 1079 return false; 1080 1081 /* Check latched inputs */ 1082 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger)) 1083 return false; 1084 1085 /* Apply filter for rising/falling edge selection */ 1086 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, 1087 cur_stat, MAX_LINE); 1088 1089 bitmap_and(pending, new_stat, trigger, MAX_LINE); 1090 1091 return !bitmap_empty(pending, MAX_LINE); 1092 } 1093 1094 static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid) 1095 { 1096 struct cy8c95x0_pinctrl *chip = devid; 1097 struct gpio_chip *gc = &chip->gpio_chip; 1098 DECLARE_BITMAP(pending, MAX_LINE); 1099 int nested_irq, level; 1100 bool ret; 1101 1102 ret = cy8c95x0_irq_pending(chip, pending); 1103 if (!ret) 1104 return IRQ_RETVAL(0); 1105 1106 ret = false; 1107 for_each_set_bit(level, pending, MAX_LINE) { 1108 /* Already accounted for 4bit gap in GPort2 */ 1109 nested_irq = irq_find_mapping(gc->irq.domain, level); 1110 1111 if (unlikely(nested_irq <= 0)) { 1112 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); 1113 continue; 1114 } 1115 1116 if (test_bit(level, chip->irq_trig_low)) 1117 while (!cy8c95x0_gpio_get_value(gc, level)) 1118 handle_nested_irq(nested_irq); 1119 else if (test_bit(level, chip->irq_trig_high)) 1120 while (cy8c95x0_gpio_get_value(gc, level)) 1121 handle_nested_irq(nested_irq); 1122 else 1123 handle_nested_irq(nested_irq); 1124 1125 ret = true; 1126 } 1127 1128 return IRQ_RETVAL(ret); 1129 } 1130 1131 static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 1132 { 1133 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1134 1135 return chip->tpin; 1136 } 1137 1138 static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 1139 unsigned int group) 1140 { 1141 return cy8c95x0_groups[group]; 1142 } 1143 1144 static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 1145 unsigned int group, 1146 const unsigned int **pins, 1147 unsigned int *num_pins) 1148 { 1149 *pins = &cy8c9560_pins[group].number; 1150 *num_pins = 1; 1151 return 0; 1152 } 1153 1154 static const char *cy8c95x0_get_fname(unsigned int selector) 1155 { 1156 if (selector == 0) 1157 return "gpio"; 1158 else 1159 return "pwm"; 1160 } 1161 1162 static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 1163 unsigned int pin) 1164 { 1165 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1166 DECLARE_BITMAP(mask, MAX_LINE); 1167 DECLARE_BITMAP(pwm, MAX_LINE); 1168 1169 bitmap_zero(mask, MAX_LINE); 1170 __set_bit(pin, mask); 1171 1172 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_SELPWM, pwm, mask)) { 1173 seq_puts(s, "not available"); 1174 return; 1175 } 1176 1177 seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm))); 1178 } 1179 1180 static const struct pinctrl_ops cy8c95x0_pinctrl_ops = { 1181 .get_groups_count = cy8c95x0_pinctrl_get_groups_count, 1182 .get_group_name = cy8c95x0_pinctrl_get_group_name, 1183 .get_group_pins = cy8c95x0_pinctrl_get_group_pins, 1184 #ifdef CONFIG_OF 1185 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1186 .dt_free_map = pinconf_generic_dt_free_map, 1187 #endif 1188 .pin_dbg_show = cy8c95x0_pin_dbg_show, 1189 }; 1190 1191 static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector) 1192 { 1193 return cy8c95x0_get_fname(selector); 1194 } 1195 1196 static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev) 1197 { 1198 return 2; 1199 } 1200 1201 static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, 1202 const char * const **groups, 1203 unsigned int * const num_groups) 1204 { 1205 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1206 1207 *groups = cy8c95x0_groups; 1208 *num_groups = chip->tpin; 1209 return 0; 1210 } 1211 1212 static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode) 1213 { 1214 u8 port = cypress_get_port(chip, off); 1215 u8 bit = cypress_get_pin_mask(chip, off); 1216 1217 return cy8c95x0_regmap_write_bits(chip, CY8C95X0_SELPWM, port, bit, mode ? bit : 0); 1218 } 1219 1220 static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip, 1221 unsigned int selector, unsigned int group) 1222 { 1223 u8 port = cypress_get_port(chip, group); 1224 u8 bit = cypress_get_pin_mask(chip, group); 1225 int ret; 1226 1227 ret = cy8c95x0_set_mode(chip, group, selector); 1228 if (ret < 0) 1229 return ret; 1230 1231 if (selector == 0) 1232 return 0; 1233 1234 /* Set direction to output & set output to 1 so that PWM can work */ 1235 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, bit); 1236 if (ret < 0) 1237 return ret; 1238 1239 return cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, bit); 1240 } 1241 1242 static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, 1243 unsigned int group) 1244 { 1245 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1246 1247 return cy8c95x0_pinmux_mode(chip, selector, group); 1248 } 1249 1250 static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev, 1251 struct pinctrl_gpio_range *range, 1252 unsigned int pin) 1253 { 1254 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1255 1256 return cy8c95x0_set_mode(chip, pin, false); 1257 } 1258 1259 static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev, 1260 struct pinctrl_gpio_range *range, 1261 unsigned int pin, bool input) 1262 { 1263 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1264 1265 return cy8c95x0_pinmux_direction(chip, pin, input); 1266 } 1267 1268 static const struct pinmux_ops cy8c95x0_pmxops = { 1269 .get_functions_count = cy8c95x0_get_functions_count, 1270 .get_function_name = cy8c95x0_get_function_name, 1271 .get_function_groups = cy8c95x0_get_function_groups, 1272 .set_mux = cy8c95x0_set_mux, 1273 .gpio_request_enable = cy8c95x0_gpio_request_enable, 1274 .gpio_set_direction = cy8c95x0_gpio_set_direction, 1275 .strict = true, 1276 }; 1277 1278 static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 1279 unsigned long *config) 1280 { 1281 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1282 1283 return cy8c95x0_gpio_get_pincfg(chip, pin, config); 1284 } 1285 1286 static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1287 unsigned long *configs, unsigned int num_configs) 1288 { 1289 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1290 int ret; 1291 int i; 1292 1293 for (i = 0; i < num_configs; i++) { 1294 ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]); 1295 if (ret) 1296 return ret; 1297 } 1298 1299 return 0; 1300 } 1301 1302 static const struct pinconf_ops cy8c95x0_pinconf_ops = { 1303 .pin_config_get = cy8c95x0_pinconf_get, 1304 .pin_config_set = cy8c95x0_pinconf_set, 1305 .is_generic = true, 1306 }; 1307 1308 static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq) 1309 { 1310 struct gpio_irq_chip *girq = &chip->gpio_chip.irq; 1311 DECLARE_BITMAP(pending_irqs, MAX_LINE); 1312 int ret; 1313 1314 mutex_init(&chip->irq_lock); 1315 1316 bitmap_zero(pending_irqs, MAX_LINE); 1317 1318 /* Read IRQ status register to clear all pending interrupts */ 1319 ret = cy8c95x0_irq_pending(chip, pending_irqs); 1320 if (ret) { 1321 dev_err(chip->dev, "failed to clear irq status register\n"); 1322 return ret; 1323 } 1324 1325 /* Mask all interrupts */ 1326 bitmap_fill(chip->irq_mask, MAX_LINE); 1327 1328 gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip); 1329 1330 /* This will let us handle the parent IRQ in the driver */ 1331 girq->parent_handler = NULL; 1332 girq->num_parents = 0; 1333 girq->parents = NULL; 1334 girq->default_type = IRQ_TYPE_NONE; 1335 girq->handler = handle_simple_irq; 1336 girq->threaded = true; 1337 1338 ret = devm_request_threaded_irq(chip->dev, irq, 1339 NULL, cy8c95x0_irq_handler, 1340 IRQF_ONESHOT | IRQF_SHARED, 1341 dev_name(chip->dev), chip); 1342 if (ret) { 1343 dev_err(chip->dev, "failed to request irq %d\n", irq); 1344 return ret; 1345 } 1346 dev_info(chip->dev, "Registered threaded IRQ\n"); 1347 1348 return 0; 1349 } 1350 1351 static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip) 1352 { 1353 struct pinctrl_desc *pd = &chip->pinctrl_desc; 1354 1355 pd->pctlops = &cy8c95x0_pinctrl_ops; 1356 pd->confops = &cy8c95x0_pinconf_ops; 1357 pd->pmxops = &cy8c95x0_pmxops; 1358 pd->name = dev_name(chip->dev); 1359 pd->pins = cy8c9560_pins; 1360 pd->npins = chip->tpin; 1361 pd->owner = THIS_MODULE; 1362 1363 chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip); 1364 if (IS_ERR(chip->pctldev)) 1365 return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev), 1366 "can't register controller\n"); 1367 1368 return 0; 1369 } 1370 1371 static int cy8c95x0_detect(struct i2c_client *client, 1372 struct i2c_board_info *info) 1373 { 1374 struct i2c_adapter *adapter = client->adapter; 1375 int ret; 1376 const char *name; 1377 1378 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1379 return -ENODEV; 1380 1381 ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID); 1382 if (ret < 0) 1383 return ret; 1384 switch (ret & GENMASK(7, 4)) { 1385 case 0x20: 1386 name = cy8c95x0_id[0].name; 1387 break; 1388 case 0x40: 1389 name = cy8c95x0_id[1].name; 1390 break; 1391 case 0x60: 1392 name = cy8c95x0_id[2].name; 1393 break; 1394 default: 1395 return -ENODEV; 1396 } 1397 1398 dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr); 1399 strscpy(info->type, name); 1400 1401 return 0; 1402 } 1403 1404 static int cy8c95x0_probe(struct i2c_client *client) 1405 { 1406 struct device *dev = &client->dev; 1407 struct cy8c95x0_pinctrl *chip; 1408 struct regmap_config regmap_conf; 1409 struct regmap_range_cfg regmap_range_conf; 1410 int ret; 1411 1412 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 1413 if (!chip) 1414 return -ENOMEM; 1415 1416 chip->dev = dev; 1417 1418 /* Set the device type */ 1419 chip->driver_data = (uintptr_t)i2c_get_match_data(client); 1420 if (!chip->driver_data) 1421 return -ENODEV; 1422 1423 chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK; 1424 chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ); 1425 1426 memcpy(®map_range_conf, &cy8c95x0_ranges[0], sizeof(regmap_range_conf)); 1427 1428 switch (chip->tpin) { 1429 case 20: 1430 strscpy(chip->name, cy8c95x0_id[0].name); 1431 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE - 1; 1432 break; 1433 case 40: 1434 strscpy(chip->name, cy8c95x0_id[1].name); 1435 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE - 1; 1436 break; 1437 case 60: 1438 strscpy(chip->name, cy8c95x0_id[2].name); 1439 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE - 1; 1440 break; 1441 default: 1442 return -ENODEV; 1443 } 1444 1445 ret = devm_regulator_get_enable(dev, "vdd"); 1446 if (ret) 1447 return dev_err_probe(dev, ret, "failed to enable regulator vdd\n"); 1448 1449 /* bring the chip out of reset if reset pin is provided */ 1450 chip->gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1451 if (IS_ERR(chip->gpio_reset)) 1452 return dev_err_probe(dev, PTR_ERR(chip->gpio_reset), "Failed to get GPIO 'reset'\n"); 1453 gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET"); 1454 if (chip->gpio_reset) { 1455 fsleep(1000); 1456 gpiod_set_value_cansleep(chip->gpio_reset, 0); 1457 fsleep(250000); 1458 } 1459 1460 /* Regmap for direct and paged registers */ 1461 memcpy(®map_conf, &cy8c9520_i2c_regmap, sizeof(regmap_conf)); 1462 regmap_conf.ranges = ®map_range_conf; 1463 regmap_conf.max_register = regmap_range_conf.range_max; 1464 regmap_conf.num_reg_defaults_raw = regmap_range_conf.range_max; 1465 1466 chip->regmap = devm_regmap_init_i2c(client, ®map_conf); 1467 if (IS_ERR(chip->regmap)) 1468 return PTR_ERR(chip->regmap); 1469 1470 bitmap_zero(chip->push_pull, MAX_LINE); 1471 1472 /* Setup HW pins mapping */ 1473 bitmap_fill(chip->map, MAX_LINE); 1474 bitmap_clear(chip->map, 20, 4); 1475 1476 mutex_init(&chip->i2c_lock); 1477 1478 if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) { 1479 ret = cy8c95x0_acpi_get_irq(&client->dev); 1480 if (ret > 0) 1481 client->irq = ret; 1482 } 1483 1484 if (client->irq) { 1485 ret = cy8c95x0_irq_setup(chip, client->irq); 1486 if (ret) 1487 return ret; 1488 } 1489 1490 ret = cy8c95x0_setup_pinctrl(chip); 1491 if (ret) 1492 return ret; 1493 1494 return cy8c95x0_setup_gpiochip(chip); 1495 } 1496 1497 static const struct acpi_device_id cy8c95x0_acpi_ids[] = { 1498 { "INT3490", 40, }, 1499 { } 1500 }; 1501 MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids); 1502 1503 static struct i2c_driver cy8c95x0_driver = { 1504 .driver = { 1505 .name = "cy8c95x0-pinctrl", 1506 .of_match_table = cy8c95x0_dt_ids, 1507 .acpi_match_table = cy8c95x0_acpi_ids, 1508 }, 1509 .probe = cy8c95x0_probe, 1510 .id_table = cy8c95x0_id, 1511 .detect = cy8c95x0_detect, 1512 }; 1513 module_i2c_driver(cy8c95x0_driver); 1514 1515 MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>"); 1516 MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>"); 1517 MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0"); 1518 MODULE_LICENSE("GPL"); 1519