1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2024 Amlogic, Inc. All rights reserved. 4 * Author: Xianwei Zhao <xianwei.zhao@amlogic.com> 5 */ 6 7 #include <linux/err.h> 8 #include <linux/gpio/driver.h> 9 #include <linux/init.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/seq_file.h> 17 #include <linux/slab.h> 18 #include <linux/string_helpers.h> 19 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <dt-bindings/pinctrl/amlogic,pinctrl.h> 25 26 #include "../core.h" 27 #include "../pinconf.h" 28 29 #define gpio_chip_to_bank(chip) \ 30 container_of(chip, struct aml_gpio_bank, gpio_chip) 31 32 #define AML_REG_PULLEN 0 33 #define AML_REG_PULL 1 34 #define AML_REG_DIR 2 35 #define AML_REG_OUT 3 36 #define AML_REG_IN 4 37 #define AML_REG_DS 5 38 #define AML_NUM_REG 6 39 40 enum aml_pinconf_drv { 41 PINCONF_DRV_500UA, 42 PINCONF_DRV_2500UA, 43 PINCONF_DRV_3000UA, 44 PINCONF_DRV_4000UA, 45 }; 46 47 struct aml_pio_control { 48 u32 gpio_offset; 49 u32 reg_offset[AML_NUM_REG]; 50 u32 bit_offset[AML_NUM_REG]; 51 }; 52 53 struct aml_reg_bit { 54 u32 bank_id; 55 u32 reg_offs[AML_NUM_REG]; 56 u32 bit_offs[AML_NUM_REG]; 57 }; 58 59 struct aml_pctl_data { 60 unsigned int number; 61 struct aml_reg_bit rb_offs[]; 62 }; 63 64 struct aml_pmx_func { 65 const char *name; 66 const char **groups; 67 unsigned int ngroups; 68 }; 69 70 struct aml_pctl_group { 71 const char *name; 72 unsigned int npins; 73 unsigned int *pins; 74 unsigned int *func; 75 }; 76 77 struct aml_gpio_bank { 78 struct gpio_chip gpio_chip; 79 struct aml_pio_control pc; 80 u32 bank_id; 81 unsigned int pin_base; 82 struct regmap *reg_mux; 83 struct regmap *reg_gpio; 84 struct regmap *reg_ds; 85 }; 86 87 struct aml_pinctrl { 88 struct device *dev; 89 struct pinctrl_dev *pctl; 90 struct aml_gpio_bank *banks; 91 int nbanks; 92 struct aml_pmx_func *functions; 93 int nfunctions; 94 struct aml_pctl_group *groups; 95 int ngroups; 96 97 const struct aml_pctl_data *data; 98 }; 99 100 static const unsigned int aml_bit_strides[AML_NUM_REG] = { 101 1, 1, 1, 1, 1, 2 102 }; 103 104 static const unsigned int aml_def_regoffs[AML_NUM_REG] = { 105 3, 4, 2, 1, 0, 7 106 }; 107 108 static const char *aml_bank_name[31] = { 109 "GPIOA", "GPIOB", "GPIOC", "GPIOD", "GPIOE", "GPIOF", "GPIOG", 110 "GPIOH", "GPIOI", "GPIOJ", "GPIOK", "GPIOL", "GPIOM", "GPION", 111 "GPIOO", "GPIOP", "GPIOQ", "GPIOR", "GPIOS", "GPIOT", "GPIOU", 112 "GPIOV", "GPIOW", "GPIOX", "GPIOY", "GPIOZ", "GPIODV", "GPIOAO", 113 "GPIOCC", "TEST_N", "ANALOG" 114 }; 115 116 static int aml_pmx_calc_reg_and_offset(struct pinctrl_gpio_range *range, 117 unsigned int pin, unsigned int *reg, 118 unsigned int *offset) 119 { 120 unsigned int shift; 121 122 shift = (pin - range->pin_base) << 2; 123 *reg = (shift / 32) * 4; 124 *offset = shift % 32; 125 126 return 0; 127 } 128 129 static int aml_pctl_set_function(struct aml_pinctrl *info, 130 struct pinctrl_gpio_range *range, 131 int pin_id, int func) 132 { 133 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 134 int reg; 135 int offset; 136 137 if (!bank->reg_mux) 138 return 0; 139 140 aml_pmx_calc_reg_and_offset(range, pin_id, ®, &offset); 141 return regmap_update_bits(bank->reg_mux, reg, 142 0xf << offset, (func & 0xf) << offset); 143 } 144 145 static int aml_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 146 { 147 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 148 149 return info->nfunctions; 150 } 151 152 static const char *aml_pmx_get_fname(struct pinctrl_dev *pctldev, 153 unsigned int selector) 154 { 155 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 156 157 return info->functions[selector].name; 158 } 159 160 static int aml_pmx_get_groups(struct pinctrl_dev *pctldev, 161 unsigned int selector, 162 const char * const **grps, 163 unsigned * const ngrps) 164 { 165 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 166 167 *grps = info->functions[selector].groups; 168 *ngrps = info->functions[selector].ngroups; 169 170 return 0; 171 } 172 173 static int aml_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned int fselector, 174 unsigned int group_id) 175 { 176 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 177 struct aml_pctl_group *group = &info->groups[group_id]; 178 struct pinctrl_gpio_range *range; 179 int i; 180 181 for (i = 0; i < group->npins; i++) { 182 range = pinctrl_find_gpio_range_from_pin(pctldev, group->pins[i]); 183 aml_pctl_set_function(info, range, group->pins[i], group->func[i]); 184 } 185 186 return 0; 187 } 188 189 static int aml_pmx_request_gpio(struct pinctrl_dev *pctldev, 190 struct pinctrl_gpio_range *range, 191 unsigned int pin) 192 { 193 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 194 195 return aml_pctl_set_function(info, range, pin, 0); 196 } 197 198 static const struct pinmux_ops aml_pmx_ops = { 199 .set_mux = aml_pmx_set_mux, 200 .get_functions_count = aml_pmx_get_funcs_count, 201 .get_function_name = aml_pmx_get_fname, 202 .get_function_groups = aml_pmx_get_groups, 203 .gpio_request_enable = aml_pmx_request_gpio, 204 }; 205 206 static int aml_calc_reg_and_bit(struct pinctrl_gpio_range *range, 207 unsigned int pin, 208 unsigned int reg_type, 209 unsigned int *reg, unsigned int *bit) 210 { 211 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 212 213 *bit = (pin - range->pin_base) * aml_bit_strides[reg_type] 214 + bank->pc.bit_offset[reg_type]; 215 *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; 216 *bit &= 0x1f; 217 218 return 0; 219 } 220 221 static int aml_pinconf_get_pull(struct aml_pinctrl *info, unsigned int pin) 222 { 223 struct pinctrl_gpio_range *range = 224 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 225 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 226 unsigned int reg, bit, val; 227 int ret, conf; 228 229 aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); 230 231 ret = regmap_read(bank->reg_gpio, reg, &val); 232 if (ret) 233 return ret; 234 235 if (!(val & BIT(bit))) { 236 conf = PIN_CONFIG_BIAS_DISABLE; 237 } else { 238 aml_calc_reg_and_bit(range, pin, AML_REG_PULL, ®, &bit); 239 240 ret = regmap_read(bank->reg_gpio, reg, &val); 241 if (ret) 242 return ret; 243 244 if (val & BIT(bit)) 245 conf = PIN_CONFIG_BIAS_PULL_UP; 246 else 247 conf = PIN_CONFIG_BIAS_PULL_DOWN; 248 } 249 250 return conf; 251 } 252 253 static int aml_pinconf_get_drive_strength(struct aml_pinctrl *info, 254 unsigned int pin, 255 u16 *drive_strength_ua) 256 { 257 struct pinctrl_gpio_range *range = 258 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 259 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 260 unsigned int reg, bit; 261 unsigned int val; 262 int ret; 263 264 if (!bank->reg_ds) 265 return -EOPNOTSUPP; 266 267 aml_calc_reg_and_bit(range, pin, AML_REG_DS, ®, &bit); 268 ret = regmap_read(bank->reg_ds, reg, &val); 269 if (ret) 270 return ret; 271 272 switch ((val >> bit) & 0x3) { 273 case PINCONF_DRV_500UA: 274 *drive_strength_ua = 500; 275 break; 276 case PINCONF_DRV_2500UA: 277 *drive_strength_ua = 2500; 278 break; 279 case PINCONF_DRV_3000UA: 280 *drive_strength_ua = 3000; 281 break; 282 case PINCONF_DRV_4000UA: 283 *drive_strength_ua = 4000; 284 break; 285 default: 286 return -EINVAL; 287 } 288 289 return 0; 290 } 291 292 static int aml_pinconf_get_gpio_bit(struct aml_pinctrl *info, 293 unsigned int pin, 294 unsigned int reg_type) 295 { 296 struct pinctrl_gpio_range *range = 297 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 298 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 299 unsigned int reg, bit, val; 300 int ret; 301 302 aml_calc_reg_and_bit(range, pin, reg_type, ®, &bit); 303 ret = regmap_read(bank->reg_gpio, reg, &val); 304 if (ret) 305 return ret; 306 307 return BIT(bit) & val ? 1 : 0; 308 } 309 310 static int aml_pinconf_get_output(struct aml_pinctrl *info, 311 unsigned int pin) 312 { 313 int ret = aml_pinconf_get_gpio_bit(info, pin, AML_REG_DIR); 314 315 if (ret < 0) 316 return ret; 317 318 return !ret; 319 } 320 321 static int aml_pinconf_get_drive(struct aml_pinctrl *info, 322 unsigned int pin) 323 { 324 return aml_pinconf_get_gpio_bit(info, pin, AML_REG_OUT); 325 } 326 327 static int aml_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, 328 unsigned long *config) 329 { 330 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); 331 enum pin_config_param param = pinconf_to_config_param(*config); 332 u16 arg; 333 int ret; 334 335 switch (param) { 336 case PIN_CONFIG_BIAS_DISABLE: 337 case PIN_CONFIG_BIAS_PULL_DOWN: 338 case PIN_CONFIG_BIAS_PULL_UP: 339 if (aml_pinconf_get_pull(info, pin) == param) 340 arg = 1; 341 else 342 return -EINVAL; 343 break; 344 case PIN_CONFIG_DRIVE_STRENGTH_UA: 345 ret = aml_pinconf_get_drive_strength(info, pin, &arg); 346 if (ret) 347 return ret; 348 break; 349 case PIN_CONFIG_OUTPUT_ENABLE: 350 ret = aml_pinconf_get_output(info, pin); 351 if (ret <= 0) 352 return -EINVAL; 353 arg = 1; 354 break; 355 case PIN_CONFIG_OUTPUT: 356 ret = aml_pinconf_get_output(info, pin); 357 if (ret <= 0) 358 return -EINVAL; 359 360 ret = aml_pinconf_get_drive(info, pin); 361 if (ret < 0) 362 return -EINVAL; 363 364 arg = ret; 365 break; 366 367 default: 368 return -ENOTSUPP; 369 } 370 371 *config = pinconf_to_config_packed(param, arg); 372 dev_dbg(info->dev, "pinconf for pin %u is %lu\n", pin, *config); 373 374 return 0; 375 } 376 377 static int aml_pinconf_disable_bias(struct aml_pinctrl *info, 378 unsigned int pin) 379 { 380 struct pinctrl_gpio_range *range = 381 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 382 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 383 unsigned int reg, bit = 0; 384 385 aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); 386 387 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); 388 } 389 390 static int aml_pinconf_enable_bias(struct aml_pinctrl *info, unsigned int pin, 391 bool pull_up) 392 { 393 struct pinctrl_gpio_range *range = 394 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 395 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 396 unsigned int reg, bit, val = 0; 397 int ret; 398 399 aml_calc_reg_and_bit(range, pin, AML_REG_PULL, ®, &bit); 400 if (pull_up) 401 val = BIT(bit); 402 403 ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), val); 404 if (ret) 405 return ret; 406 407 aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); 408 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit)); 409 } 410 411 static int aml_pinconf_set_drive_strength(struct aml_pinctrl *info, 412 unsigned int pin, 413 u16 drive_strength_ua) 414 { 415 struct pinctrl_gpio_range *range = 416 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 417 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 418 unsigned int reg, bit, ds_val; 419 420 if (!bank->reg_ds) { 421 dev_err(info->dev, "drive-strength not supported\n"); 422 return -EOPNOTSUPP; 423 } 424 425 aml_calc_reg_and_bit(range, pin, AML_REG_DS, ®, &bit); 426 427 if (drive_strength_ua <= 500) { 428 ds_val = PINCONF_DRV_500UA; 429 } else if (drive_strength_ua <= 2500) { 430 ds_val = PINCONF_DRV_2500UA; 431 } else if (drive_strength_ua <= 3000) { 432 ds_val = PINCONF_DRV_3000UA; 433 } else if (drive_strength_ua <= 4000) { 434 ds_val = PINCONF_DRV_4000UA; 435 } else { 436 dev_warn_once(info->dev, 437 "pin %u: invalid drive-strength : %d , default to 4mA\n", 438 pin, drive_strength_ua); 439 ds_val = PINCONF_DRV_4000UA; 440 } 441 442 return regmap_update_bits(bank->reg_ds, reg, 0x3 << bit, ds_val << bit); 443 } 444 445 static int aml_pinconf_set_gpio_bit(struct aml_pinctrl *info, 446 unsigned int pin, 447 unsigned int reg_type, 448 bool arg) 449 { 450 struct pinctrl_gpio_range *range = 451 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 452 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 453 unsigned int reg, bit; 454 455 aml_calc_reg_and_bit(range, pin, reg_type, ®, &bit); 456 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 457 arg ? BIT(bit) : 0); 458 } 459 460 static int aml_pinconf_set_output(struct aml_pinctrl *info, 461 unsigned int pin, 462 bool out) 463 { 464 return aml_pinconf_set_gpio_bit(info, pin, AML_REG_DIR, !out); 465 } 466 467 static int aml_pinconf_set_drive(struct aml_pinctrl *info, 468 unsigned int pin, 469 bool high) 470 { 471 return aml_pinconf_set_gpio_bit(info, pin, AML_REG_OUT, high); 472 } 473 474 static int aml_pinconf_set_output_drive(struct aml_pinctrl *info, 475 unsigned int pin, 476 bool high) 477 { 478 int ret; 479 480 ret = aml_pinconf_set_output(info, pin, true); 481 if (ret) 482 return ret; 483 484 return aml_pinconf_set_drive(info, pin, high); 485 } 486 487 static int aml_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, 488 unsigned long *configs, unsigned int num_configs) 489 { 490 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); 491 enum pin_config_param param; 492 unsigned int arg = 0; 493 int i, ret; 494 495 for (i = 0; i < num_configs; i++) { 496 param = pinconf_to_config_param(configs[i]); 497 498 switch (param) { 499 case PIN_CONFIG_DRIVE_STRENGTH_UA: 500 case PIN_CONFIG_OUTPUT_ENABLE: 501 case PIN_CONFIG_OUTPUT: 502 arg = pinconf_to_config_argument(configs[i]); 503 break; 504 505 default: 506 break; 507 } 508 509 switch (param) { 510 case PIN_CONFIG_BIAS_DISABLE: 511 ret = aml_pinconf_disable_bias(info, pin); 512 break; 513 case PIN_CONFIG_BIAS_PULL_UP: 514 ret = aml_pinconf_enable_bias(info, pin, true); 515 break; 516 case PIN_CONFIG_BIAS_PULL_DOWN: 517 ret = aml_pinconf_enable_bias(info, pin, false); 518 break; 519 case PIN_CONFIG_DRIVE_STRENGTH_UA: 520 ret = aml_pinconf_set_drive_strength(info, pin, arg); 521 break; 522 case PIN_CONFIG_OUTPUT_ENABLE: 523 ret = aml_pinconf_set_output(info, pin, arg); 524 break; 525 case PIN_CONFIG_OUTPUT: 526 ret = aml_pinconf_set_output_drive(info, pin, arg); 527 break; 528 default: 529 ret = -ENOTSUPP; 530 } 531 532 if (ret) 533 return ret; 534 } 535 536 return 0; 537 } 538 539 static int aml_pinconf_group_set(struct pinctrl_dev *pcdev, 540 unsigned int num_group, 541 unsigned long *configs, 542 unsigned int num_configs) 543 { 544 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); 545 int i; 546 547 for (i = 0; i < info->groups[num_group].npins; i++) { 548 aml_pinconf_set(pcdev, info->groups[num_group].pins[i], configs, 549 num_configs); 550 } 551 552 return 0; 553 } 554 555 static int aml_pinconf_group_get(struct pinctrl_dev *pcdev, 556 unsigned int group, unsigned long *config) 557 { 558 return -EOPNOTSUPP; 559 } 560 561 static const struct pinconf_ops aml_pinconf_ops = { 562 .pin_config_get = aml_pinconf_get, 563 .pin_config_set = aml_pinconf_set, 564 .pin_config_group_get = aml_pinconf_group_get, 565 .pin_config_group_set = aml_pinconf_group_set, 566 .is_generic = true, 567 }; 568 569 static int aml_get_groups_count(struct pinctrl_dev *pctldev) 570 { 571 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 572 573 return info->ngroups; 574 } 575 576 static const char *aml_get_group_name(struct pinctrl_dev *pctldev, 577 unsigned int selector) 578 { 579 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 580 581 return info->groups[selector].name; 582 } 583 584 static int aml_get_group_pins(struct pinctrl_dev *pctldev, 585 unsigned int selector, const unsigned int **pins, 586 unsigned int *npins) 587 { 588 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 589 590 if (selector >= info->ngroups) 591 return -EINVAL; 592 593 *pins = info->groups[selector].pins; 594 *npins = info->groups[selector].npins; 595 596 return 0; 597 } 598 599 static inline const struct aml_pctl_group * 600 aml_pctl_find_group_by_name(const struct aml_pinctrl *info, 601 const char *name) 602 { 603 int i; 604 605 for (i = 0; i < info->ngroups; i++) { 606 if (!strcmp(info->groups[i].name, name)) 607 return &info->groups[i]; 608 } 609 610 return NULL; 611 } 612 613 static void aml_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, 614 unsigned int offset) 615 { 616 seq_printf(s, " %s", dev_name(pcdev->dev)); 617 } 618 619 static const struct pinctrl_ops aml_pctrl_ops = { 620 .get_groups_count = aml_get_groups_count, 621 .get_group_name = aml_get_group_name, 622 .get_group_pins = aml_get_group_pins, 623 .dt_node_to_map = pinconf_generic_dt_node_to_map_pinmux, 624 .dt_free_map = pinconf_generic_dt_free_map, 625 .pin_dbg_show = aml_pin_dbg_show, 626 }; 627 628 static int aml_pctl_parse_functions(struct device_node *np, 629 struct aml_pinctrl *info, u32 index, 630 int *grp_index) 631 { 632 struct device *dev = info->dev; 633 struct aml_pmx_func *func; 634 struct aml_pctl_group *grp; 635 int ret, i; 636 637 func = &info->functions[index]; 638 func->name = np->name; 639 func->ngroups = of_get_child_count(np); 640 if (func->ngroups == 0) 641 return dev_err_probe(dev, -EINVAL, "No groups defined\n"); 642 643 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); 644 if (!func->groups) 645 return -ENOMEM; 646 647 i = 0; 648 for_each_child_of_node_scoped(np, child) { 649 func->groups[i++] = child->name; 650 grp = &info->groups[*grp_index]; 651 grp->name = child->name; 652 *grp_index += 1; 653 ret = pinconf_generic_parse_dt_pinmux(child, dev, &grp->pins, 654 &grp->func, &grp->npins); 655 if (ret) { 656 dev_err(dev, "function :%s, groups:%s fail\n", func->name, child->name); 657 return ret; 658 } 659 } 660 dev_dbg(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); 661 662 return 0; 663 } 664 665 static u32 aml_bank_pins(struct device_node *np) 666 { 667 struct of_phandle_args of_args; 668 669 if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 670 0, &of_args)) 671 return 0; 672 else 673 return of_args.args[2]; 674 } 675 676 static int aml_bank_number(struct device_node *np) 677 { 678 struct of_phandle_args of_args; 679 680 if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 681 0, &of_args)) 682 return -EINVAL; 683 else 684 return of_args.args[1] >> 8; 685 } 686 687 static unsigned int aml_count_pins(struct device_node *np) 688 { 689 struct device_node *child; 690 unsigned int pins = 0; 691 692 for_each_child_of_node(np, child) { 693 if (of_property_read_bool(child, "gpio-controller")) 694 pins += aml_bank_pins(child); 695 } 696 697 return pins; 698 } 699 700 /* 701 * A pinctrl device contains two types of nodes. The one named GPIO 702 * bank which includes gpio-controller property. The other one named 703 * function which includes one or more pin groups. The pin group 704 * include pinmux property(global index in pinctrl dev, and mux vlaue 705 * in mux reg) and pin configuration properties. 706 */ 707 static void aml_pctl_dt_child_count(struct aml_pinctrl *info, 708 struct device_node *np) 709 { 710 struct device_node *child; 711 712 for_each_child_of_node(np, child) { 713 if (of_property_read_bool(child, "gpio-controller")) { 714 info->nbanks++; 715 } else { 716 info->nfunctions++; 717 info->ngroups += of_get_child_count(child); 718 } 719 } 720 } 721 722 static struct regmap *aml_map_resource(struct device *dev, unsigned int id, 723 struct device_node *node, char *name) 724 { 725 struct resource res; 726 void __iomem *base; 727 int i; 728 729 struct regmap_config aml_regmap_config = { 730 .reg_bits = 32, 731 .val_bits = 32, 732 .reg_stride = 4, 733 }; 734 735 i = of_property_match_string(node, "reg-names", name); 736 if (i < 0) 737 return NULL; 738 if (of_address_to_resource(node, i, &res)) 739 return NULL; 740 base = devm_ioremap_resource(dev, &res); 741 if (IS_ERR(base)) 742 return ERR_CAST(base); 743 744 aml_regmap_config.max_register = resource_size(&res) - 4; 745 aml_regmap_config.name = devm_kasprintf(dev, GFP_KERNEL, 746 "%s-%s", aml_bank_name[id], name); 747 if (!aml_regmap_config.name) 748 return ERR_PTR(-ENOMEM); 749 750 return devm_regmap_init_mmio(dev, base, &aml_regmap_config); 751 } 752 753 static inline int aml_gpio_calc_reg_and_bit(struct aml_gpio_bank *bank, 754 unsigned int reg_type, 755 unsigned int gpio, 756 unsigned int *reg, 757 unsigned int *bit) 758 { 759 *bit = gpio * aml_bit_strides[reg_type] + bank->pc.bit_offset[reg_type]; 760 *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; 761 *bit &= 0x1f; 762 763 return 0; 764 } 765 766 static int aml_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) 767 { 768 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 769 unsigned int bit, reg, val; 770 int ret; 771 772 aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); 773 774 ret = regmap_read(bank->reg_gpio, reg, &val); 775 if (ret) 776 return ret; 777 778 return BIT(bit) & val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; 779 } 780 781 static int aml_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) 782 { 783 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 784 unsigned int bit, reg; 785 786 aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); 787 788 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit)); 789 } 790 791 static int aml_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, 792 int value) 793 { 794 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 795 unsigned int bit, reg; 796 int ret; 797 798 aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); 799 ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); 800 if (ret < 0) 801 return ret; 802 803 aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); 804 805 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 806 value ? BIT(bit) : 0); 807 } 808 809 static void aml_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) 810 { 811 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 812 unsigned int bit, reg; 813 814 aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); 815 816 regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 817 value ? BIT(bit) : 0); 818 } 819 820 static int aml_gpio_get(struct gpio_chip *chip, unsigned int gpio) 821 { 822 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 823 unsigned int reg, bit, val; 824 825 aml_gpio_calc_reg_and_bit(bank, AML_REG_IN, gpio, ®, &bit); 826 regmap_read(bank->reg_gpio, reg, &val); 827 828 return !!(val & BIT(bit)); 829 } 830 831 static const struct gpio_chip aml_gpio_template = { 832 .request = gpiochip_generic_request, 833 .free = gpiochip_generic_free, 834 .set_config = gpiochip_generic_config, 835 .set = aml_gpio_set, 836 .get = aml_gpio_get, 837 .direction_input = aml_gpio_direction_input, 838 .direction_output = aml_gpio_direction_output, 839 .get_direction = aml_gpio_get_direction, 840 .can_sleep = false, 841 }; 842 843 static void init_bank_register_bit(struct aml_pinctrl *info, 844 struct aml_gpio_bank *bank) 845 { 846 const struct aml_pctl_data *data = info->data; 847 const struct aml_reg_bit *aml_rb; 848 bool def_offs = true; 849 int i; 850 851 if (data) { 852 for (i = 0; i < data->number; i++) { 853 aml_rb = &data->rb_offs[i]; 854 if (bank->bank_id == aml_rb->bank_id) { 855 def_offs = false; 856 break; 857 } 858 } 859 } 860 861 if (def_offs) { 862 for (i = 0; i < AML_NUM_REG; i++) { 863 bank->pc.reg_offset[i] = aml_def_regoffs[i]; 864 bank->pc.bit_offset[i] = 0; 865 } 866 } else { 867 for (i = 0; i < AML_NUM_REG; i++) { 868 bank->pc.reg_offset[i] = aml_rb->reg_offs[i]; 869 bank->pc.bit_offset[i] = aml_rb->bit_offs[i]; 870 } 871 } 872 } 873 874 static int aml_gpiolib_register_bank(struct aml_pinctrl *info, 875 int bank_nr, struct device_node *np) 876 { 877 struct aml_gpio_bank *bank = &info->banks[bank_nr]; 878 struct device *dev = info->dev; 879 int ret = 0; 880 881 ret = aml_bank_number(np); 882 if (ret < 0) { 883 dev_err(dev, "get num=%d bank identity fail\n", bank_nr); 884 return -EINVAL; 885 } 886 bank->bank_id = ret; 887 888 bank->reg_mux = aml_map_resource(dev, bank->bank_id, np, "mux"); 889 if (IS_ERR_OR_NULL(bank->reg_mux)) { 890 if (bank->bank_id == AMLOGIC_GPIO_TEST_N || 891 bank->bank_id == AMLOGIC_GPIO_ANALOG) 892 bank->reg_mux = NULL; 893 else 894 return dev_err_probe(dev, bank->reg_mux ? PTR_ERR(bank->reg_mux) : -ENOENT, 895 "mux registers not found\n"); 896 } 897 898 bank->reg_gpio = aml_map_resource(dev, bank->bank_id, np, "gpio"); 899 if (IS_ERR_OR_NULL(bank->reg_gpio)) 900 return dev_err_probe(dev, bank->reg_gpio ? PTR_ERR(bank->reg_gpio) : -ENOENT, 901 "gpio registers not found\n"); 902 903 bank->reg_ds = aml_map_resource(dev, bank->bank_id, np, "ds"); 904 if (IS_ERR_OR_NULL(bank->reg_ds)) { 905 dev_dbg(info->dev, "ds registers not found - skipping\n"); 906 bank->reg_ds = bank->reg_gpio; 907 } 908 909 bank->gpio_chip = aml_gpio_template; 910 bank->gpio_chip.base = -1; 911 bank->gpio_chip.ngpio = aml_bank_pins(np); 912 bank->gpio_chip.fwnode = of_fwnode_handle(np); 913 bank->gpio_chip.parent = dev; 914 915 init_bank_register_bit(info, bank); 916 bank->gpio_chip.label = aml_bank_name[bank->bank_id]; 917 918 bank->pin_base = bank->bank_id << 8; 919 920 return 0; 921 } 922 923 static int aml_pctl_probe_dt(struct platform_device *pdev, 924 struct pinctrl_desc *pctl_desc, 925 struct aml_pinctrl *info) 926 { 927 struct device *dev = &pdev->dev; 928 struct pinctrl_pin_desc *pdesc; 929 struct device_node *np = dev->of_node; 930 int grp_index = 0; 931 int i = 0, j = 0, k = 0, bank; 932 int ret = 0; 933 934 aml_pctl_dt_child_count(info, np); 935 if (!info->nbanks) 936 return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); 937 938 dev_dbg(dev, "nbanks = %d\n", info->nbanks); 939 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); 940 dev_dbg(dev, "ngroups = %d\n", info->ngroups); 941 942 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 943 944 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); 945 946 info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); 947 948 if (!info->functions || !info->groups || !info->banks) 949 return -ENOMEM; 950 951 info->data = (struct aml_pctl_data *)of_device_get_match_data(dev); 952 953 pctl_desc->npins = aml_count_pins(np); 954 955 pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); 956 if (!pdesc) 957 return -ENOMEM; 958 959 pctl_desc->pins = pdesc; 960 961 bank = 0; 962 for_each_child_of_node_scoped(np, child) { 963 if (of_property_read_bool(child, "gpio-controller")) { 964 const char *bank_name = NULL; 965 char **pin_names; 966 967 ret = aml_gpiolib_register_bank(info, bank, child); 968 if (ret) 969 return ret; 970 971 k = info->banks[bank].pin_base; 972 bank_name = info->banks[bank].gpio_chip.label; 973 974 pin_names = devm_kasprintf_strarray(dev, bank_name, 975 info->banks[bank].gpio_chip.ngpio); 976 if (IS_ERR(pin_names)) 977 return PTR_ERR(pin_names); 978 979 for (j = 0; j < info->banks[bank].gpio_chip.ngpio; j++, k++) { 980 pdesc->number = k; 981 pdesc->name = pin_names[j]; 982 pdesc++; 983 } 984 bank++; 985 } else { 986 ret = aml_pctl_parse_functions(child, info, 987 i++, &grp_index); 988 if (ret) 989 return ret; 990 } 991 } 992 993 return 0; 994 } 995 996 static int aml_pctl_probe(struct platform_device *pdev) 997 { 998 struct device *dev = &pdev->dev; 999 struct aml_pinctrl *info; 1000 struct pinctrl_desc *pctl_desc; 1001 int ret, i; 1002 1003 pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL); 1004 if (!pctl_desc) 1005 return -ENOMEM; 1006 1007 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1008 if (!info) 1009 return -ENOMEM; 1010 1011 info->dev = dev; 1012 platform_set_drvdata(pdev, info); 1013 ret = aml_pctl_probe_dt(pdev, pctl_desc, info); 1014 if (ret) 1015 return ret; 1016 1017 pctl_desc->owner = THIS_MODULE; 1018 pctl_desc->pctlops = &aml_pctrl_ops; 1019 pctl_desc->pmxops = &aml_pmx_ops; 1020 pctl_desc->confops = &aml_pinconf_ops; 1021 pctl_desc->name = dev_name(dev); 1022 1023 info->pctl = devm_pinctrl_register(dev, pctl_desc, info); 1024 if (IS_ERR(info->pctl)) 1025 return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); 1026 1027 for (i = 0; i < info->nbanks; i++) { 1028 ret = gpiochip_add_data(&info->banks[i].gpio_chip, &info->banks[i]); 1029 if (ret) 1030 return dev_err_probe(dev, ret, "Failed to add gpiochip(%d)!\n", i); 1031 } 1032 1033 return 0; 1034 } 1035 1036 static const struct of_device_id aml_pctl_of_match[] = { 1037 { .compatible = "amlogic,pinctrl-a4", }, 1038 { /* sentinel */ } 1039 }; 1040 MODULE_DEVICE_TABLE(of, aml_pctl_dt_match); 1041 1042 static struct platform_driver aml_pctl_driver = { 1043 .driver = { 1044 .name = "amlogic-pinctrl", 1045 .of_match_table = aml_pctl_of_match, 1046 }, 1047 .probe = aml_pctl_probe, 1048 }; 1049 module_platform_driver(aml_pctl_driver); 1050 1051 MODULE_AUTHOR("Xianwei Zhao <xianwei.zhao@amlogic.com>"); 1052 MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic SoC"); 1053 MODULE_LICENSE("Dual BSD/GPL"); 1054