1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (C) 2013-2017 Broadcom 3 4 #include <linux/err.h> 5 #include <linux/init.h> 6 #include <linux/io.h> 7 #include <linux/of.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 #include <linux/seq_file.h> 11 #include <linux/slab.h> 12 13 #include <linux/pinctrl/pinconf-generic.h> 14 #include <linux/pinctrl/pinconf.h> 15 #include <linux/pinctrl/pinctrl.h> 16 #include <linux/pinctrl/pinmux.h> 17 18 #include "../core.h" 19 #include "../pinctrl-utils.h" 20 21 /* BCM281XX Pin Control Registers Definitions */ 22 23 /* Function Select bits are the same for all pin control registers */ 24 #define BCM281XX_PIN_REG_F_SEL_MASK 0x0700 25 #define BCM281XX_PIN_REG_F_SEL_SHIFT 8 26 27 /* Standard pin register */ 28 #define BCM281XX_STD_PIN_REG_DRV_STR_MASK 0x0007 29 #define BCM281XX_STD_PIN_REG_DRV_STR_SHIFT 0 30 #define BCM281XX_STD_PIN_REG_INPUT_DIS_MASK 0x0008 31 #define BCM281XX_STD_PIN_REG_INPUT_DIS_SHIFT 3 32 #define BCM281XX_STD_PIN_REG_SLEW_MASK 0x0010 33 #define BCM281XX_STD_PIN_REG_SLEW_SHIFT 4 34 #define BCM281XX_STD_PIN_REG_PULL_UP_MASK 0x0020 35 #define BCM281XX_STD_PIN_REG_PULL_UP_SHIFT 5 36 #define BCM281XX_STD_PIN_REG_PULL_DN_MASK 0x0040 37 #define BCM281XX_STD_PIN_REG_PULL_DN_SHIFT 6 38 #define BCM281XX_STD_PIN_REG_HYST_MASK 0x0080 39 #define BCM281XX_STD_PIN_REG_HYST_SHIFT 7 40 41 /* I2C pin register */ 42 #define BCM281XX_I2C_PIN_REG_INPUT_DIS_MASK 0x0004 43 #define BCM281XX_I2C_PIN_REG_INPUT_DIS_SHIFT 2 44 #define BCM281XX_I2C_PIN_REG_SLEW_MASK 0x0008 45 #define BCM281XX_I2C_PIN_REG_SLEW_SHIFT 3 46 #define BCM281XX_I2C_PIN_REG_PULL_UP_STR_MASK 0x0070 47 #define BCM281XX_I2C_PIN_REG_PULL_UP_STR_SHIFT 4 48 49 /* HDMI pin register */ 50 #define BCM281XX_HDMI_PIN_REG_INPUT_DIS_MASK 0x0008 51 #define BCM281XX_HDMI_PIN_REG_INPUT_DIS_SHIFT 3 52 #define BCM281XX_HDMI_PIN_REG_MODE_MASK 0x0010 53 #define BCM281XX_HDMI_PIN_REG_MODE_SHIFT 4 54 55 /* 56 * bcm281xx_pin_type - types of pin register 57 */ 58 enum bcm281xx_pin_type { 59 BCM281XX_PIN_TYPE_UNKNOWN = 0, 60 BCM281XX_PIN_TYPE_STD, 61 BCM281XX_PIN_TYPE_I2C, 62 BCM281XX_PIN_TYPE_HDMI, 63 }; 64 65 static enum bcm281xx_pin_type std_pin = BCM281XX_PIN_TYPE_STD; 66 static enum bcm281xx_pin_type i2c_pin = BCM281XX_PIN_TYPE_I2C; 67 static enum bcm281xx_pin_type hdmi_pin = BCM281XX_PIN_TYPE_HDMI; 68 69 /* 70 * bcm281xx_pin_function- define pin function 71 */ 72 struct bcm281xx_pin_function { 73 const char *name; 74 const char * const *groups; 75 const unsigned int ngroups; 76 }; 77 78 /* 79 * Device types (used in bcm281xx_pinctrl_desc to differentiate 80 * the two device types from each other) 81 */ 82 enum bcm281xx_pinctrl_type { 83 BCM281XX_PINCTRL_TYPE, 84 }; 85 86 /* 87 * bcm281xx_pinctrl_info - description of a pinctrl device supported 88 * by this driver, intended to be used as a provider of OF match data. 89 */ 90 struct bcm281xx_pinctrl_info { 91 enum bcm281xx_pinctrl_type device_type; 92 93 /* List of all pins */ 94 const struct pinctrl_pin_desc *pins; 95 unsigned int npins; 96 97 const struct bcm281xx_pin_function *functions; 98 unsigned int nfunctions; 99 100 const struct regmap_config *regmap_config; 101 }; 102 103 /* 104 * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data 105 * @reg_base - base of pinctrl registers 106 */ 107 struct bcm281xx_pinctrl_data { 108 struct device *dev; 109 void __iomem *reg_base; 110 111 struct regmap *regmap; 112 const struct bcm281xx_pinctrl_info *info; 113 }; 114 115 /* 116 * Pin number definition. The order here must be the same as defined in the 117 * PADCTRLREG block in the RDB. 118 */ 119 #define BCM281XX_PIN_ADCSYNC 0 120 #define BCM281XX_PIN_BAT_RM 1 121 #define BCM281XX_PIN_BSC1_SCL 2 122 #define BCM281XX_PIN_BSC1_SDA 3 123 #define BCM281XX_PIN_BSC2_SCL 4 124 #define BCM281XX_PIN_BSC2_SDA 5 125 #define BCM281XX_PIN_CLASSGPWR 6 126 #define BCM281XX_PIN_CLK_CX8 7 127 #define BCM281XX_PIN_CLKOUT_0 8 128 #define BCM281XX_PIN_CLKOUT_1 9 129 #define BCM281XX_PIN_CLKOUT_2 10 130 #define BCM281XX_PIN_CLKOUT_3 11 131 #define BCM281XX_PIN_CLKREQ_IN_0 12 132 #define BCM281XX_PIN_CLKREQ_IN_1 13 133 #define BCM281XX_PIN_CWS_SYS_REQ1 14 134 #define BCM281XX_PIN_CWS_SYS_REQ2 15 135 #define BCM281XX_PIN_CWS_SYS_REQ3 16 136 #define BCM281XX_PIN_DIGMIC1_CLK 17 137 #define BCM281XX_PIN_DIGMIC1_DQ 18 138 #define BCM281XX_PIN_DIGMIC2_CLK 19 139 #define BCM281XX_PIN_DIGMIC2_DQ 20 140 #define BCM281XX_PIN_GPEN13 21 141 #define BCM281XX_PIN_GPEN14 22 142 #define BCM281XX_PIN_GPEN15 23 143 #define BCM281XX_PIN_GPIO00 24 144 #define BCM281XX_PIN_GPIO01 25 145 #define BCM281XX_PIN_GPIO02 26 146 #define BCM281XX_PIN_GPIO03 27 147 #define BCM281XX_PIN_GPIO04 28 148 #define BCM281XX_PIN_GPIO05 29 149 #define BCM281XX_PIN_GPIO06 30 150 #define BCM281XX_PIN_GPIO07 31 151 #define BCM281XX_PIN_GPIO08 32 152 #define BCM281XX_PIN_GPIO09 33 153 #define BCM281XX_PIN_GPIO10 34 154 #define BCM281XX_PIN_GPIO11 35 155 #define BCM281XX_PIN_GPIO12 36 156 #define BCM281XX_PIN_GPIO13 37 157 #define BCM281XX_PIN_GPIO14 38 158 #define BCM281XX_PIN_GPS_PABLANK 39 159 #define BCM281XX_PIN_GPS_TMARK 40 160 #define BCM281XX_PIN_HDMI_SCL 41 161 #define BCM281XX_PIN_HDMI_SDA 42 162 #define BCM281XX_PIN_IC_DM 43 163 #define BCM281XX_PIN_IC_DP 44 164 #define BCM281XX_PIN_KP_COL_IP_0 45 165 #define BCM281XX_PIN_KP_COL_IP_1 46 166 #define BCM281XX_PIN_KP_COL_IP_2 47 167 #define BCM281XX_PIN_KP_COL_IP_3 48 168 #define BCM281XX_PIN_KP_ROW_OP_0 49 169 #define BCM281XX_PIN_KP_ROW_OP_1 50 170 #define BCM281XX_PIN_KP_ROW_OP_2 51 171 #define BCM281XX_PIN_KP_ROW_OP_3 52 172 #define BCM281XX_PIN_LCD_B_0 53 173 #define BCM281XX_PIN_LCD_B_1 54 174 #define BCM281XX_PIN_LCD_B_2 55 175 #define BCM281XX_PIN_LCD_B_3 56 176 #define BCM281XX_PIN_LCD_B_4 57 177 #define BCM281XX_PIN_LCD_B_5 58 178 #define BCM281XX_PIN_LCD_B_6 59 179 #define BCM281XX_PIN_LCD_B_7 60 180 #define BCM281XX_PIN_LCD_G_0 61 181 #define BCM281XX_PIN_LCD_G_1 62 182 #define BCM281XX_PIN_LCD_G_2 63 183 #define BCM281XX_PIN_LCD_G_3 64 184 #define BCM281XX_PIN_LCD_G_4 65 185 #define BCM281XX_PIN_LCD_G_5 66 186 #define BCM281XX_PIN_LCD_G_6 67 187 #define BCM281XX_PIN_LCD_G_7 68 188 #define BCM281XX_PIN_LCD_HSYNC 69 189 #define BCM281XX_PIN_LCD_OE 70 190 #define BCM281XX_PIN_LCD_PCLK 71 191 #define BCM281XX_PIN_LCD_R_0 72 192 #define BCM281XX_PIN_LCD_R_1 73 193 #define BCM281XX_PIN_LCD_R_2 74 194 #define BCM281XX_PIN_LCD_R_3 75 195 #define BCM281XX_PIN_LCD_R_4 76 196 #define BCM281XX_PIN_LCD_R_5 77 197 #define BCM281XX_PIN_LCD_R_6 78 198 #define BCM281XX_PIN_LCD_R_7 79 199 #define BCM281XX_PIN_LCD_VSYNC 80 200 #define BCM281XX_PIN_MDMGPIO0 81 201 #define BCM281XX_PIN_MDMGPIO1 82 202 #define BCM281XX_PIN_MDMGPIO2 83 203 #define BCM281XX_PIN_MDMGPIO3 84 204 #define BCM281XX_PIN_MDMGPIO4 85 205 #define BCM281XX_PIN_MDMGPIO5 86 206 #define BCM281XX_PIN_MDMGPIO6 87 207 #define BCM281XX_PIN_MDMGPIO7 88 208 #define BCM281XX_PIN_MDMGPIO8 89 209 #define BCM281XX_PIN_MPHI_DATA_0 90 210 #define BCM281XX_PIN_MPHI_DATA_1 91 211 #define BCM281XX_PIN_MPHI_DATA_2 92 212 #define BCM281XX_PIN_MPHI_DATA_3 93 213 #define BCM281XX_PIN_MPHI_DATA_4 94 214 #define BCM281XX_PIN_MPHI_DATA_5 95 215 #define BCM281XX_PIN_MPHI_DATA_6 96 216 #define BCM281XX_PIN_MPHI_DATA_7 97 217 #define BCM281XX_PIN_MPHI_DATA_8 98 218 #define BCM281XX_PIN_MPHI_DATA_9 99 219 #define BCM281XX_PIN_MPHI_DATA_10 100 220 #define BCM281XX_PIN_MPHI_DATA_11 101 221 #define BCM281XX_PIN_MPHI_DATA_12 102 222 #define BCM281XX_PIN_MPHI_DATA_13 103 223 #define BCM281XX_PIN_MPHI_DATA_14 104 224 #define BCM281XX_PIN_MPHI_DATA_15 105 225 #define BCM281XX_PIN_MPHI_HA0 106 226 #define BCM281XX_PIN_MPHI_HAT0 107 227 #define BCM281XX_PIN_MPHI_HAT1 108 228 #define BCM281XX_PIN_MPHI_HCE0_N 109 229 #define BCM281XX_PIN_MPHI_HCE1_N 110 230 #define BCM281XX_PIN_MPHI_HRD_N 111 231 #define BCM281XX_PIN_MPHI_HWR_N 112 232 #define BCM281XX_PIN_MPHI_RUN0 113 233 #define BCM281XX_PIN_MPHI_RUN1 114 234 #define BCM281XX_PIN_MTX_SCAN_CLK 115 235 #define BCM281XX_PIN_MTX_SCAN_DATA 116 236 #define BCM281XX_PIN_NAND_AD_0 117 237 #define BCM281XX_PIN_NAND_AD_1 118 238 #define BCM281XX_PIN_NAND_AD_2 119 239 #define BCM281XX_PIN_NAND_AD_3 120 240 #define BCM281XX_PIN_NAND_AD_4 121 241 #define BCM281XX_PIN_NAND_AD_5 122 242 #define BCM281XX_PIN_NAND_AD_6 123 243 #define BCM281XX_PIN_NAND_AD_7 124 244 #define BCM281XX_PIN_NAND_ALE 125 245 #define BCM281XX_PIN_NAND_CEN_0 126 246 #define BCM281XX_PIN_NAND_CEN_1 127 247 #define BCM281XX_PIN_NAND_CLE 128 248 #define BCM281XX_PIN_NAND_OEN 129 249 #define BCM281XX_PIN_NAND_RDY_0 130 250 #define BCM281XX_PIN_NAND_RDY_1 131 251 #define BCM281XX_PIN_NAND_WEN 132 252 #define BCM281XX_PIN_NAND_WP 133 253 #define BCM281XX_PIN_PC1 134 254 #define BCM281XX_PIN_PC2 135 255 #define BCM281XX_PIN_PMU_INT 136 256 #define BCM281XX_PIN_PMU_SCL 137 257 #define BCM281XX_PIN_PMU_SDA 138 258 #define BCM281XX_PIN_RFST2G_MTSLOTEN3G 139 259 #define BCM281XX_PIN_RGMII_0_RX_CTL 140 260 #define BCM281XX_PIN_RGMII_0_RXC 141 261 #define BCM281XX_PIN_RGMII_0_RXD_0 142 262 #define BCM281XX_PIN_RGMII_0_RXD_1 143 263 #define BCM281XX_PIN_RGMII_0_RXD_2 144 264 #define BCM281XX_PIN_RGMII_0_RXD_3 145 265 #define BCM281XX_PIN_RGMII_0_TX_CTL 146 266 #define BCM281XX_PIN_RGMII_0_TXC 147 267 #define BCM281XX_PIN_RGMII_0_TXD_0 148 268 #define BCM281XX_PIN_RGMII_0_TXD_1 149 269 #define BCM281XX_PIN_RGMII_0_TXD_2 150 270 #define BCM281XX_PIN_RGMII_0_TXD_3 151 271 #define BCM281XX_PIN_RGMII_1_RX_CTL 152 272 #define BCM281XX_PIN_RGMII_1_RXC 153 273 #define BCM281XX_PIN_RGMII_1_RXD_0 154 274 #define BCM281XX_PIN_RGMII_1_RXD_1 155 275 #define BCM281XX_PIN_RGMII_1_RXD_2 156 276 #define BCM281XX_PIN_RGMII_1_RXD_3 157 277 #define BCM281XX_PIN_RGMII_1_TX_CTL 158 278 #define BCM281XX_PIN_RGMII_1_TXC 159 279 #define BCM281XX_PIN_RGMII_1_TXD_0 160 280 #define BCM281XX_PIN_RGMII_1_TXD_1 161 281 #define BCM281XX_PIN_RGMII_1_TXD_2 162 282 #define BCM281XX_PIN_RGMII_1_TXD_3 163 283 #define BCM281XX_PIN_RGMII_GPIO_0 164 284 #define BCM281XX_PIN_RGMII_GPIO_1 165 285 #define BCM281XX_PIN_RGMII_GPIO_2 166 286 #define BCM281XX_PIN_RGMII_GPIO_3 167 287 #define BCM281XX_PIN_RTXDATA2G_TXDATA3G1 168 288 #define BCM281XX_PIN_RTXEN2G_TXDATA3G2 169 289 #define BCM281XX_PIN_RXDATA3G0 170 290 #define BCM281XX_PIN_RXDATA3G1 171 291 #define BCM281XX_PIN_RXDATA3G2 172 292 #define BCM281XX_PIN_SDIO1_CLK 173 293 #define BCM281XX_PIN_SDIO1_CMD 174 294 #define BCM281XX_PIN_SDIO1_DATA_0 175 295 #define BCM281XX_PIN_SDIO1_DATA_1 176 296 #define BCM281XX_PIN_SDIO1_DATA_2 177 297 #define BCM281XX_PIN_SDIO1_DATA_3 178 298 #define BCM281XX_PIN_SDIO4_CLK 179 299 #define BCM281XX_PIN_SDIO4_CMD 180 300 #define BCM281XX_PIN_SDIO4_DATA_0 181 301 #define BCM281XX_PIN_SDIO4_DATA_1 182 302 #define BCM281XX_PIN_SDIO4_DATA_2 183 303 #define BCM281XX_PIN_SDIO4_DATA_3 184 304 #define BCM281XX_PIN_SIM_CLK 185 305 #define BCM281XX_PIN_SIM_DATA 186 306 #define BCM281XX_PIN_SIM_DET 187 307 #define BCM281XX_PIN_SIM_RESETN 188 308 #define BCM281XX_PIN_SIM2_CLK 189 309 #define BCM281XX_PIN_SIM2_DATA 190 310 #define BCM281XX_PIN_SIM2_DET 191 311 #define BCM281XX_PIN_SIM2_RESETN 192 312 #define BCM281XX_PIN_SRI_C 193 313 #define BCM281XX_PIN_SRI_D 194 314 #define BCM281XX_PIN_SRI_E 195 315 #define BCM281XX_PIN_SSP_EXTCLK 196 316 #define BCM281XX_PIN_SSP0_CLK 197 317 #define BCM281XX_PIN_SSP0_FS 198 318 #define BCM281XX_PIN_SSP0_RXD 199 319 #define BCM281XX_PIN_SSP0_TXD 200 320 #define BCM281XX_PIN_SSP2_CLK 201 321 #define BCM281XX_PIN_SSP2_FS_0 202 322 #define BCM281XX_PIN_SSP2_FS_1 203 323 #define BCM281XX_PIN_SSP2_FS_2 204 324 #define BCM281XX_PIN_SSP2_FS_3 205 325 #define BCM281XX_PIN_SSP2_RXD_0 206 326 #define BCM281XX_PIN_SSP2_RXD_1 207 327 #define BCM281XX_PIN_SSP2_TXD_0 208 328 #define BCM281XX_PIN_SSP2_TXD_1 209 329 #define BCM281XX_PIN_SSP3_CLK 210 330 #define BCM281XX_PIN_SSP3_FS 211 331 #define BCM281XX_PIN_SSP3_RXD 212 332 #define BCM281XX_PIN_SSP3_TXD 213 333 #define BCM281XX_PIN_SSP4_CLK 214 334 #define BCM281XX_PIN_SSP4_FS 215 335 #define BCM281XX_PIN_SSP4_RXD 216 336 #define BCM281XX_PIN_SSP4_TXD 217 337 #define BCM281XX_PIN_SSP5_CLK 218 338 #define BCM281XX_PIN_SSP5_FS 219 339 #define BCM281XX_PIN_SSP5_RXD 220 340 #define BCM281XX_PIN_SSP5_TXD 221 341 #define BCM281XX_PIN_SSP6_CLK 222 342 #define BCM281XX_PIN_SSP6_FS 223 343 #define BCM281XX_PIN_SSP6_RXD 224 344 #define BCM281XX_PIN_SSP6_TXD 225 345 #define BCM281XX_PIN_STAT_1 226 346 #define BCM281XX_PIN_STAT_2 227 347 #define BCM281XX_PIN_SYSCLKEN 228 348 #define BCM281XX_PIN_TRACECLK 229 349 #define BCM281XX_PIN_TRACEDT00 230 350 #define BCM281XX_PIN_TRACEDT01 231 351 #define BCM281XX_PIN_TRACEDT02 232 352 #define BCM281XX_PIN_TRACEDT03 233 353 #define BCM281XX_PIN_TRACEDT04 234 354 #define BCM281XX_PIN_TRACEDT05 235 355 #define BCM281XX_PIN_TRACEDT06 236 356 #define BCM281XX_PIN_TRACEDT07 237 357 #define BCM281XX_PIN_TRACEDT08 238 358 #define BCM281XX_PIN_TRACEDT09 239 359 #define BCM281XX_PIN_TRACEDT10 240 360 #define BCM281XX_PIN_TRACEDT11 241 361 #define BCM281XX_PIN_TRACEDT12 242 362 #define BCM281XX_PIN_TRACEDT13 243 363 #define BCM281XX_PIN_TRACEDT14 244 364 #define BCM281XX_PIN_TRACEDT15 245 365 #define BCM281XX_PIN_TXDATA3G0 246 366 #define BCM281XX_PIN_TXPWRIND 247 367 #define BCM281XX_PIN_UARTB1_UCTS 248 368 #define BCM281XX_PIN_UARTB1_URTS 249 369 #define BCM281XX_PIN_UARTB1_URXD 250 370 #define BCM281XX_PIN_UARTB1_UTXD 251 371 #define BCM281XX_PIN_UARTB2_URXD 252 372 #define BCM281XX_PIN_UARTB2_UTXD 253 373 #define BCM281XX_PIN_UARTB3_UCTS 254 374 #define BCM281XX_PIN_UARTB3_URTS 255 375 #define BCM281XX_PIN_UARTB3_URXD 256 376 #define BCM281XX_PIN_UARTB3_UTXD 257 377 #define BCM281XX_PIN_UARTB4_UCTS 258 378 #define BCM281XX_PIN_UARTB4_URTS 259 379 #define BCM281XX_PIN_UARTB4_URXD 260 380 #define BCM281XX_PIN_UARTB4_UTXD 261 381 #define BCM281XX_PIN_VC_CAM1_SCL 262 382 #define BCM281XX_PIN_VC_CAM1_SDA 263 383 #define BCM281XX_PIN_VC_CAM2_SCL 264 384 #define BCM281XX_PIN_VC_CAM2_SDA 265 385 #define BCM281XX_PIN_VC_CAM3_SCL 266 386 #define BCM281XX_PIN_VC_CAM3_SDA 267 387 388 #define BCM281XX_PIN_DESC(a, b, c) \ 389 { .number = a, .name = b, .drv_data = &c##_pin } 390 391 /* 392 * Pin description definition. The order here must be the same as defined in 393 * the PADCTRLREG block in the RDB, since the pin number is used as an index 394 * into this array. 395 */ 396 static const struct pinctrl_pin_desc bcm281xx_pinctrl_pins[] = { 397 BCM281XX_PIN_DESC(BCM281XX_PIN_ADCSYNC, "adcsync", std), 398 BCM281XX_PIN_DESC(BCM281XX_PIN_BAT_RM, "bat_rm", std), 399 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SCL, "bsc1_scl", i2c), 400 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SDA, "bsc1_sda", i2c), 401 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SCL, "bsc2_scl", i2c), 402 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SDA, "bsc2_sda", i2c), 403 BCM281XX_PIN_DESC(BCM281XX_PIN_CLASSGPWR, "classgpwr", std), 404 BCM281XX_PIN_DESC(BCM281XX_PIN_CLK_CX8, "clk_cx8", std), 405 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_0, "clkout_0", std), 406 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_1, "clkout_1", std), 407 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_2, "clkout_2", std), 408 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_3, "clkout_3", std), 409 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_0, "clkreq_in_0", std), 410 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_1, "clkreq_in_1", std), 411 BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ1, "cws_sys_req1", std), 412 BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ2, "cws_sys_req2", std), 413 BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ3, "cws_sys_req3", std), 414 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_CLK, "digmic1_clk", std), 415 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_DQ, "digmic1_dq", std), 416 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_CLK, "digmic2_clk", std), 417 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_DQ, "digmic2_dq", std), 418 BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN13, "gpen13", std), 419 BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN14, "gpen14", std), 420 BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN15, "gpen15", std), 421 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO00, "gpio00", std), 422 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO01, "gpio01", std), 423 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO02, "gpio02", std), 424 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO03, "gpio03", std), 425 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO04, "gpio04", std), 426 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO05, "gpio05", std), 427 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO06, "gpio06", std), 428 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO07, "gpio07", std), 429 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO08, "gpio08", std), 430 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO09, "gpio09", std), 431 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO10, "gpio10", std), 432 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO11, "gpio11", std), 433 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO12, "gpio12", std), 434 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO13, "gpio13", std), 435 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO14, "gpio14", std), 436 BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_PABLANK, "gps_pablank", std), 437 BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_TMARK, "gps_tmark", std), 438 BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SCL, "hdmi_scl", hdmi), 439 BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SDA, "hdmi_sda", hdmi), 440 BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DM, "ic_dm", std), 441 BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DP, "ic_dp", std), 442 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_0, "kp_col_ip_0", std), 443 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_1, "kp_col_ip_1", std), 444 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_2, "kp_col_ip_2", std), 445 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_3, "kp_col_ip_3", std), 446 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_0, "kp_row_op_0", std), 447 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_1, "kp_row_op_1", std), 448 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_2, "kp_row_op_2", std), 449 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_3, "kp_row_op_3", std), 450 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_0, "lcd_b_0", std), 451 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_1, "lcd_b_1", std), 452 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_2, "lcd_b_2", std), 453 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_3, "lcd_b_3", std), 454 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_4, "lcd_b_4", std), 455 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_5, "lcd_b_5", std), 456 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_6, "lcd_b_6", std), 457 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_7, "lcd_b_7", std), 458 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_0, "lcd_g_0", std), 459 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_1, "lcd_g_1", std), 460 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_2, "lcd_g_2", std), 461 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_3, "lcd_g_3", std), 462 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_4, "lcd_g_4", std), 463 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_5, "lcd_g_5", std), 464 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_6, "lcd_g_6", std), 465 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_7, "lcd_g_7", std), 466 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_HSYNC, "lcd_hsync", std), 467 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_OE, "lcd_oe", std), 468 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_PCLK, "lcd_pclk", std), 469 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_0, "lcd_r_0", std), 470 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_1, "lcd_r_1", std), 471 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_2, "lcd_r_2", std), 472 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_3, "lcd_r_3", std), 473 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_4, "lcd_r_4", std), 474 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_5, "lcd_r_5", std), 475 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_6, "lcd_r_6", std), 476 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_7, "lcd_r_7", std), 477 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_VSYNC, "lcd_vsync", std), 478 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO0, "mdmgpio0", std), 479 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO1, "mdmgpio1", std), 480 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO2, "mdmgpio2", std), 481 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO3, "mdmgpio3", std), 482 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO4, "mdmgpio4", std), 483 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO5, "mdmgpio5", std), 484 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO6, "mdmgpio6", std), 485 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO7, "mdmgpio7", std), 486 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO8, "mdmgpio8", std), 487 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_0, "mphi_data_0", std), 488 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_1, "mphi_data_1", std), 489 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_2, "mphi_data_2", std), 490 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_3, "mphi_data_3", std), 491 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_4, "mphi_data_4", std), 492 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_5, "mphi_data_5", std), 493 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_6, "mphi_data_6", std), 494 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_7, "mphi_data_7", std), 495 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_8, "mphi_data_8", std), 496 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_9, "mphi_data_9", std), 497 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_10, "mphi_data_10", std), 498 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_11, "mphi_data_11", std), 499 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_12, "mphi_data_12", std), 500 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_13, "mphi_data_13", std), 501 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_14, "mphi_data_14", std), 502 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_15, "mphi_data_15", std), 503 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HA0, "mphi_ha0", std), 504 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT0, "mphi_hat0", std), 505 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT1, "mphi_hat1", std), 506 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE0_N, "mphi_hce0_n", std), 507 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE1_N, "mphi_hce1_n", std), 508 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HRD_N, "mphi_hrd_n", std), 509 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HWR_N, "mphi_hwr_n", std), 510 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN0, "mphi_run0", std), 511 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN1, "mphi_run1", std), 512 BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std), 513 BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_DATA, "mtx_scan_data", std), 514 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_0, "nand_ad_0", std), 515 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_1, "nand_ad_1", std), 516 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_2, "nand_ad_2", std), 517 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_3, "nand_ad_3", std), 518 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_4, "nand_ad_4", std), 519 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_5, "nand_ad_5", std), 520 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_6, "nand_ad_6", std), 521 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_7, "nand_ad_7", std), 522 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_ALE, "nand_ale", std), 523 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_0, "nand_cen_0", std), 524 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_1, "nand_cen_1", std), 525 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CLE, "nand_cle", std), 526 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_OEN, "nand_oen", std), 527 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_0, "nand_rdy_0", std), 528 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_1, "nand_rdy_1", std), 529 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WEN, "nand_wen", std), 530 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WP, "nand_wp", std), 531 BCM281XX_PIN_DESC(BCM281XX_PIN_PC1, "pc1", std), 532 BCM281XX_PIN_DESC(BCM281XX_PIN_PC2, "pc2", std), 533 BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_INT, "pmu_int", std), 534 BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SCL, "pmu_scl", i2c), 535 BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SDA, "pmu_sda", i2c), 536 BCM281XX_PIN_DESC(BCM281XX_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g", 537 std), 538 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std), 539 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXC, "rgmii_0_rxc", std), 540 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std), 541 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std), 542 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std), 543 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std), 544 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std), 545 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXC, "rgmii_0_txc", std), 546 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std), 547 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std), 548 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std), 549 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std), 550 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std), 551 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXC, "rgmii_1_rxc", std), 552 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std), 553 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std), 554 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std), 555 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std), 556 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std), 557 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXC, "rgmii_1_txc", std), 558 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std), 559 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std), 560 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std), 561 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std), 562 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std), 563 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std), 564 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std), 565 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std), 566 BCM281XX_PIN_DESC(BCM281XX_PIN_RTXDATA2G_TXDATA3G1, 567 "rtxdata2g_txdata3g1", std), 568 BCM281XX_PIN_DESC(BCM281XX_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2", 569 std), 570 BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G0, "rxdata3g0", std), 571 BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G1, "rxdata3g1", std), 572 BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G2, "rxdata3g2", std), 573 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CLK, "sdio1_clk", std), 574 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CMD, "sdio1_cmd", std), 575 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_0, "sdio1_data_0", std), 576 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_1, "sdio1_data_1", std), 577 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_2, "sdio1_data_2", std), 578 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_3, "sdio1_data_3", std), 579 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CLK, "sdio4_clk", std), 580 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CMD, "sdio4_cmd", std), 581 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_0, "sdio4_data_0", std), 582 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_1, "sdio4_data_1", std), 583 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_2, "sdio4_data_2", std), 584 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_3, "sdio4_data_3", std), 585 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_CLK, "sim_clk", std), 586 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DATA, "sim_data", std), 587 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DET, "sim_det", std), 588 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_RESETN, "sim_resetn", std), 589 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_CLK, "sim2_clk", std), 590 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DATA, "sim2_data", std), 591 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DET, "sim2_det", std), 592 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_RESETN, "sim2_resetn", std), 593 BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_C, "sri_c", std), 594 BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_D, "sri_d", std), 595 BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_E, "sri_e", std), 596 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP_EXTCLK, "ssp_extclk", std), 597 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_CLK, "ssp0_clk", std), 598 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_FS, "ssp0_fs", std), 599 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_RXD, "ssp0_rxd", std), 600 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_TXD, "ssp0_txd", std), 601 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_CLK, "ssp2_clk", std), 602 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_0, "ssp2_fs_0", std), 603 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_1, "ssp2_fs_1", std), 604 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_2, "ssp2_fs_2", std), 605 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_3, "ssp2_fs_3", std), 606 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_0, "ssp2_rxd_0", std), 607 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_1, "ssp2_rxd_1", std), 608 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_0, "ssp2_txd_0", std), 609 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_1, "ssp2_txd_1", std), 610 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_CLK, "ssp3_clk", std), 611 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_FS, "ssp3_fs", std), 612 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_RXD, "ssp3_rxd", std), 613 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_TXD, "ssp3_txd", std), 614 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_CLK, "ssp4_clk", std), 615 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_FS, "ssp4_fs", std), 616 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_RXD, "ssp4_rxd", std), 617 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_TXD, "ssp4_txd", std), 618 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_CLK, "ssp5_clk", std), 619 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_FS, "ssp5_fs", std), 620 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_RXD, "ssp5_rxd", std), 621 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_TXD, "ssp5_txd", std), 622 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_CLK, "ssp6_clk", std), 623 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_FS, "ssp6_fs", std), 624 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_RXD, "ssp6_rxd", std), 625 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_TXD, "ssp6_txd", std), 626 BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_1, "stat_1", std), 627 BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_2, "stat_2", std), 628 BCM281XX_PIN_DESC(BCM281XX_PIN_SYSCLKEN, "sysclken", std), 629 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACECLK, "traceclk", std), 630 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT00, "tracedt00", std), 631 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT01, "tracedt01", std), 632 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT02, "tracedt02", std), 633 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT03, "tracedt03", std), 634 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT04, "tracedt04", std), 635 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT05, "tracedt05", std), 636 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT06, "tracedt06", std), 637 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT07, "tracedt07", std), 638 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT08, "tracedt08", std), 639 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT09, "tracedt09", std), 640 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT10, "tracedt10", std), 641 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT11, "tracedt11", std), 642 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT12, "tracedt12", std), 643 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT13, "tracedt13", std), 644 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT14, "tracedt14", std), 645 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT15, "tracedt15", std), 646 BCM281XX_PIN_DESC(BCM281XX_PIN_TXDATA3G0, "txdata3g0", std), 647 BCM281XX_PIN_DESC(BCM281XX_PIN_TXPWRIND, "txpwrind", std), 648 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UCTS, "uartb1_ucts", std), 649 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URTS, "uartb1_urts", std), 650 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URXD, "uartb1_urxd", std), 651 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UTXD, "uartb1_utxd", std), 652 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_URXD, "uartb2_urxd", std), 653 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_UTXD, "uartb2_utxd", std), 654 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UCTS, "uartb3_ucts", std), 655 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URTS, "uartb3_urts", std), 656 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URXD, "uartb3_urxd", std), 657 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UTXD, "uartb3_utxd", std), 658 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UCTS, "uartb4_ucts", std), 659 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URTS, "uartb4_urts", std), 660 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URXD, "uartb4_urxd", std), 661 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UTXD, "uartb4_utxd", std), 662 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c), 663 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c), 664 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c), 665 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c), 666 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c), 667 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c), 668 }; 669 670 static const char * const bcm281xx_alt_groups[] = { 671 "adcsync", 672 "bat_rm", 673 "bsc1_scl", 674 "bsc1_sda", 675 "bsc2_scl", 676 "bsc2_sda", 677 "classgpwr", 678 "clk_cx8", 679 "clkout_0", 680 "clkout_1", 681 "clkout_2", 682 "clkout_3", 683 "clkreq_in_0", 684 "clkreq_in_1", 685 "cws_sys_req1", 686 "cws_sys_req2", 687 "cws_sys_req3", 688 "digmic1_clk", 689 "digmic1_dq", 690 "digmic2_clk", 691 "digmic2_dq", 692 "gpen13", 693 "gpen14", 694 "gpen15", 695 "gpio00", 696 "gpio01", 697 "gpio02", 698 "gpio03", 699 "gpio04", 700 "gpio05", 701 "gpio06", 702 "gpio07", 703 "gpio08", 704 "gpio09", 705 "gpio10", 706 "gpio11", 707 "gpio12", 708 "gpio13", 709 "gpio14", 710 "gps_pablank", 711 "gps_tmark", 712 "hdmi_scl", 713 "hdmi_sda", 714 "ic_dm", 715 "ic_dp", 716 "kp_col_ip_0", 717 "kp_col_ip_1", 718 "kp_col_ip_2", 719 "kp_col_ip_3", 720 "kp_row_op_0", 721 "kp_row_op_1", 722 "kp_row_op_2", 723 "kp_row_op_3", 724 "lcd_b_0", 725 "lcd_b_1", 726 "lcd_b_2", 727 "lcd_b_3", 728 "lcd_b_4", 729 "lcd_b_5", 730 "lcd_b_6", 731 "lcd_b_7", 732 "lcd_g_0", 733 "lcd_g_1", 734 "lcd_g_2", 735 "lcd_g_3", 736 "lcd_g_4", 737 "lcd_g_5", 738 "lcd_g_6", 739 "lcd_g_7", 740 "lcd_hsync", 741 "lcd_oe", 742 "lcd_pclk", 743 "lcd_r_0", 744 "lcd_r_1", 745 "lcd_r_2", 746 "lcd_r_3", 747 "lcd_r_4", 748 "lcd_r_5", 749 "lcd_r_6", 750 "lcd_r_7", 751 "lcd_vsync", 752 "mdmgpio0", 753 "mdmgpio1", 754 "mdmgpio2", 755 "mdmgpio3", 756 "mdmgpio4", 757 "mdmgpio5", 758 "mdmgpio6", 759 "mdmgpio7", 760 "mdmgpio8", 761 "mphi_data_0", 762 "mphi_data_1", 763 "mphi_data_2", 764 "mphi_data_3", 765 "mphi_data_4", 766 "mphi_data_5", 767 "mphi_data_6", 768 "mphi_data_7", 769 "mphi_data_8", 770 "mphi_data_9", 771 "mphi_data_10", 772 "mphi_data_11", 773 "mphi_data_12", 774 "mphi_data_13", 775 "mphi_data_14", 776 "mphi_data_15", 777 "mphi_ha0", 778 "mphi_hat0", 779 "mphi_hat1", 780 "mphi_hce0_n", 781 "mphi_hce1_n", 782 "mphi_hrd_n", 783 "mphi_hwr_n", 784 "mphi_run0", 785 "mphi_run1", 786 "mtx_scan_clk", 787 "mtx_scan_data", 788 "nand_ad_0", 789 "nand_ad_1", 790 "nand_ad_2", 791 "nand_ad_3", 792 "nand_ad_4", 793 "nand_ad_5", 794 "nand_ad_6", 795 "nand_ad_7", 796 "nand_ale", 797 "nand_cen_0", 798 "nand_cen_1", 799 "nand_cle", 800 "nand_oen", 801 "nand_rdy_0", 802 "nand_rdy_1", 803 "nand_wen", 804 "nand_wp", 805 "pc1", 806 "pc2", 807 "pmu_int", 808 "pmu_scl", 809 "pmu_sda", 810 "rfst2g_mtsloten3g", 811 "rgmii_0_rx_ctl", 812 "rgmii_0_rxc", 813 "rgmii_0_rxd_0", 814 "rgmii_0_rxd_1", 815 "rgmii_0_rxd_2", 816 "rgmii_0_rxd_3", 817 "rgmii_0_tx_ctl", 818 "rgmii_0_txc", 819 "rgmii_0_txd_0", 820 "rgmii_0_txd_1", 821 "rgmii_0_txd_2", 822 "rgmii_0_txd_3", 823 "rgmii_1_rx_ctl", 824 "rgmii_1_rxc", 825 "rgmii_1_rxd_0", 826 "rgmii_1_rxd_1", 827 "rgmii_1_rxd_2", 828 "rgmii_1_rxd_3", 829 "rgmii_1_tx_ctl", 830 "rgmii_1_txc", 831 "rgmii_1_txd_0", 832 "rgmii_1_txd_1", 833 "rgmii_1_txd_2", 834 "rgmii_1_txd_3", 835 "rgmii_gpio_0", 836 "rgmii_gpio_1", 837 "rgmii_gpio_2", 838 "rgmii_gpio_3", 839 "rtxdata2g_txdata3g1", 840 "rtxen2g_txdata3g2", 841 "rxdata3g0", 842 "rxdata3g1", 843 "rxdata3g2", 844 "sdio1_clk", 845 "sdio1_cmd", 846 "sdio1_data_0", 847 "sdio1_data_1", 848 "sdio1_data_2", 849 "sdio1_data_3", 850 "sdio4_clk", 851 "sdio4_cmd", 852 "sdio4_data_0", 853 "sdio4_data_1", 854 "sdio4_data_2", 855 "sdio4_data_3", 856 "sim_clk", 857 "sim_data", 858 "sim_det", 859 "sim_resetn", 860 "sim2_clk", 861 "sim2_data", 862 "sim2_det", 863 "sim2_resetn", 864 "sri_c", 865 "sri_d", 866 "sri_e", 867 "ssp_extclk", 868 "ssp0_clk", 869 "ssp0_fs", 870 "ssp0_rxd", 871 "ssp0_txd", 872 "ssp2_clk", 873 "ssp2_fs_0", 874 "ssp2_fs_1", 875 "ssp2_fs_2", 876 "ssp2_fs_3", 877 "ssp2_rxd_0", 878 "ssp2_rxd_1", 879 "ssp2_txd_0", 880 "ssp2_txd_1", 881 "ssp3_clk", 882 "ssp3_fs", 883 "ssp3_rxd", 884 "ssp3_txd", 885 "ssp4_clk", 886 "ssp4_fs", 887 "ssp4_rxd", 888 "ssp4_txd", 889 "ssp5_clk", 890 "ssp5_fs", 891 "ssp5_rxd", 892 "ssp5_txd", 893 "ssp6_clk", 894 "ssp6_fs", 895 "ssp6_rxd", 896 "ssp6_txd", 897 "stat_1", 898 "stat_2", 899 "sysclken", 900 "traceclk", 901 "tracedt00", 902 "tracedt01", 903 "tracedt02", 904 "tracedt03", 905 "tracedt04", 906 "tracedt05", 907 "tracedt06", 908 "tracedt07", 909 "tracedt08", 910 "tracedt09", 911 "tracedt10", 912 "tracedt11", 913 "tracedt12", 914 "tracedt13", 915 "tracedt14", 916 "tracedt15", 917 "txdata3g0", 918 "txpwrind", 919 "uartb1_ucts", 920 "uartb1_urts", 921 "uartb1_urxd", 922 "uartb1_utxd", 923 "uartb2_urxd", 924 "uartb2_utxd", 925 "uartb3_ucts", 926 "uartb3_urts", 927 "uartb3_urxd", 928 "uartb3_utxd", 929 "uartb4_ucts", 930 "uartb4_urts", 931 "uartb4_urxd", 932 "uartb4_utxd", 933 "vc_cam1_scl", 934 "vc_cam1_sda", 935 "vc_cam2_scl", 936 "vc_cam2_sda", 937 "vc_cam3_scl", 938 "vc_cam3_sda", 939 }; 940 941 /* Every pin can implement all ALT1-ALT4 functions */ 942 #define BCM281XX_PIN_FUNCTION(fcn_name) \ 943 { \ 944 .name = #fcn_name, \ 945 .groups = bcm281xx_alt_groups, \ 946 .ngroups = ARRAY_SIZE(bcm281xx_alt_groups), \ 947 } 948 949 static const struct bcm281xx_pin_function bcm281xx_functions[] = { 950 BCM281XX_PIN_FUNCTION(alt1), 951 BCM281XX_PIN_FUNCTION(alt2), 952 BCM281XX_PIN_FUNCTION(alt3), 953 BCM281XX_PIN_FUNCTION(alt4), 954 }; 955 956 static const struct regmap_config bcm281xx_pinctrl_regmap_config = { 957 .reg_bits = 32, 958 .reg_stride = 4, 959 .val_bits = 32, 960 .max_register = BCM281XX_PIN_VC_CAM3_SDA * 4, 961 }; 962 963 static const struct bcm281xx_pinctrl_info bcm281xx_pinctrl = { 964 .device_type = BCM281XX_PINCTRL_TYPE, 965 966 .pins = bcm281xx_pinctrl_pins, 967 .npins = ARRAY_SIZE(bcm281xx_pinctrl_pins), 968 .functions = bcm281xx_functions, 969 .nfunctions = ARRAY_SIZE(bcm281xx_functions), 970 971 .regmap_config = &bcm281xx_pinctrl_regmap_config, 972 }; 973 974 static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev, 975 unsigned int pin) 976 { 977 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); 978 979 if (pin >= pdata->info->npins) 980 return BCM281XX_PIN_TYPE_UNKNOWN; 981 982 return *(enum bcm281xx_pin_type *)(pdata->info->pins[pin].drv_data); 983 } 984 985 #define BCM281XX_PIN_SHIFT(type, param) \ 986 (BCM281XX_ ## type ## _PIN_REG_ ## param ## _SHIFT) 987 988 #define BCM281XX_PIN_MASK(type, param) \ 989 (BCM281XX_ ## type ## _PIN_REG_ ## param ## _MASK) 990 991 /* 992 * This helper function is used to build up the value and mask used to write to 993 * a pin register, but does not actually write to the register. 994 */ 995 static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask, 996 u32 param_val, u32 param_shift, 997 u32 param_mask) 998 { 999 *reg_val &= ~param_mask; 1000 *reg_val |= (param_val << param_shift) & param_mask; 1001 *reg_mask |= param_mask; 1002 } 1003 1004 static int bcm281xx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 1005 { 1006 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); 1007 1008 return pdata->info->npins; 1009 } 1010 1011 static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 1012 unsigned int group) 1013 { 1014 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); 1015 1016 return pdata->info->pins[group].name; 1017 } 1018 1019 static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 1020 unsigned int group, 1021 const unsigned **pins, 1022 unsigned int *num_pins) 1023 { 1024 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); 1025 1026 *pins = &pdata->info->pins[group].number; 1027 *num_pins = 1; 1028 1029 return 0; 1030 } 1031 1032 static void bcm281xx_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, 1033 struct seq_file *s, 1034 unsigned int offset) 1035 { 1036 seq_printf(s, " %s", dev_name(pctldev->dev)); 1037 } 1038 1039 static const struct pinctrl_ops bcm281xx_pinctrl_ops = { 1040 .get_groups_count = bcm281xx_pinctrl_get_groups_count, 1041 .get_group_name = bcm281xx_pinctrl_get_group_name, 1042 .get_group_pins = bcm281xx_pinctrl_get_group_pins, 1043 .pin_dbg_show = bcm281xx_pinctrl_pin_dbg_show, 1044 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1045 .dt_free_map = pinctrl_utils_free_map, 1046 }; 1047 1048 static int bcm281xx_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev) 1049 { 1050 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); 1051 1052 return pdata->info->nfunctions; 1053 } 1054 1055 static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev, 1056 unsigned int function) 1057 { 1058 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); 1059 1060 return pdata->info->functions[function].name; 1061 } 1062 1063 static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev, 1064 unsigned int function, 1065 const char * const **groups, 1066 unsigned int * const num_groups) 1067 { 1068 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); 1069 1070 *groups = pdata->info->functions[function].groups; 1071 *num_groups = pdata->info->functions[function].ngroups; 1072 1073 return 0; 1074 } 1075 1076 static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev, 1077 unsigned int function, 1078 unsigned int group) 1079 { 1080 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); 1081 const struct bcm281xx_pin_function *f = &pdata->info->functions[function]; 1082 unsigned int pin = pdata->info->pins[group].number; 1083 u32 offset = 4 * pin; 1084 int rc = 0; 1085 1086 dev_dbg(pctldev->dev, 1087 "%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n", 1088 __func__, f->name, function, pdata->info->pins[group].name, 1089 pin, offset); 1090 1091 rc = regmap_update_bits(pdata->regmap, offset, 1092 BCM281XX_PIN_REG_F_SEL_MASK, 1093 function << BCM281XX_PIN_REG_F_SEL_SHIFT); 1094 if (rc) 1095 dev_err(pctldev->dev, 1096 "Error updating register for pin %s (%d).\n", 1097 pdata->info->pins[group].name, pin); 1098 1099 return rc; 1100 } 1101 1102 static const struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = { 1103 .get_functions_count = bcm281xx_pinctrl_get_fcns_count, 1104 .get_function_name = bcm281xx_pinctrl_get_fcn_name, 1105 .get_function_groups = bcm281xx_pinctrl_get_fcn_groups, 1106 .set_mux = bcm281xx_pinmux_set, 1107 }; 1108 1109 static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev, 1110 unsigned int pin, 1111 unsigned long *config) 1112 { 1113 return -ENOTSUPP; 1114 } 1115 1116 1117 /* Goes through the configs and update register val/mask */ 1118 static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev, 1119 unsigned int pin, 1120 unsigned long *configs, 1121 unsigned int num_configs, 1122 u32 *val, 1123 u32 *mask) 1124 { 1125 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); 1126 int i; 1127 enum pin_config_param param; 1128 u32 arg; 1129 1130 for (i = 0; i < num_configs; i++) { 1131 param = pinconf_to_config_param(configs[i]); 1132 arg = pinconf_to_config_argument(configs[i]); 1133 1134 switch (param) { 1135 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1136 arg = (arg >= 1 ? 1 : 0); 1137 bcm281xx_pin_update(val, mask, arg, 1138 BCM281XX_PIN_SHIFT(STD, HYST), 1139 BCM281XX_PIN_MASK(STD, HYST)); 1140 break; 1141 /* 1142 * The pin bias can only be one of pull-up, pull-down, or 1143 * disable. The user does not need to specify a value for the 1144 * property, and the default value from pinconf-generic is 1145 * ignored. 1146 */ 1147 case PIN_CONFIG_BIAS_DISABLE: 1148 bcm281xx_pin_update(val, mask, 0, 1149 BCM281XX_PIN_SHIFT(STD, PULL_UP), 1150 BCM281XX_PIN_MASK(STD, PULL_UP)); 1151 bcm281xx_pin_update(val, mask, 0, 1152 BCM281XX_PIN_SHIFT(STD, PULL_DN), 1153 BCM281XX_PIN_MASK(STD, PULL_DN)); 1154 break; 1155 1156 case PIN_CONFIG_BIAS_PULL_UP: 1157 bcm281xx_pin_update(val, mask, 1, 1158 BCM281XX_PIN_SHIFT(STD, PULL_UP), 1159 BCM281XX_PIN_MASK(STD, PULL_UP)); 1160 bcm281xx_pin_update(val, mask, 0, 1161 BCM281XX_PIN_SHIFT(STD, PULL_DN), 1162 BCM281XX_PIN_MASK(STD, PULL_DN)); 1163 break; 1164 1165 case PIN_CONFIG_BIAS_PULL_DOWN: 1166 bcm281xx_pin_update(val, mask, 0, 1167 BCM281XX_PIN_SHIFT(STD, PULL_UP), 1168 BCM281XX_PIN_MASK(STD, PULL_UP)); 1169 bcm281xx_pin_update(val, mask, 1, 1170 BCM281XX_PIN_SHIFT(STD, PULL_DN), 1171 BCM281XX_PIN_MASK(STD, PULL_DN)); 1172 break; 1173 1174 case PIN_CONFIG_SLEW_RATE: 1175 arg = (arg >= 1 ? 1 : 0); 1176 bcm281xx_pin_update(val, mask, arg, 1177 BCM281XX_PIN_SHIFT(STD, SLEW), 1178 BCM281XX_PIN_MASK(STD, SLEW)); 1179 break; 1180 1181 case PIN_CONFIG_INPUT_ENABLE: 1182 /* inversed since register is for input _disable_ */ 1183 arg = (arg >= 1 ? 0 : 1); 1184 bcm281xx_pin_update(val, mask, arg, 1185 BCM281XX_PIN_SHIFT(STD, INPUT_DIS), 1186 BCM281XX_PIN_MASK(STD, INPUT_DIS)); 1187 break; 1188 1189 case PIN_CONFIG_DRIVE_STRENGTH: 1190 /* Valid range is 2-16 mA, even numbers only */ 1191 if ((arg < 2) || (arg > 16) || (arg % 2)) { 1192 dev_err(pctldev->dev, 1193 "Invalid Drive Strength value (%d) for " 1194 "pin %s (%d). Valid values are " 1195 "(2..16) mA, even numbers only.\n", 1196 arg, pdata->info->pins[pin].name, pin); 1197 return -EINVAL; 1198 } 1199 bcm281xx_pin_update(val, mask, (arg/2)-1, 1200 BCM281XX_PIN_SHIFT(STD, DRV_STR), 1201 BCM281XX_PIN_MASK(STD, DRV_STR)); 1202 break; 1203 1204 default: 1205 dev_err(pctldev->dev, 1206 "Unrecognized pin config %d for pin %s (%d).\n", 1207 param, pdata->info->pins[pin].name, pin); 1208 return -EINVAL; 1209 1210 } /* switch config */ 1211 } /* for each config */ 1212 1213 return 0; 1214 } 1215 1216 /* 1217 * The pull-up strength for an I2C pin is represented by bits 4-6 in the 1218 * register with the following mapping: 1219 * 0b000: No pull-up 1220 * 0b001: 1200 Ohm 1221 * 0b010: 1800 Ohm 1222 * 0b011: 720 Ohm 1223 * 0b100: 2700 Ohm 1224 * 0b101: 831 Ohm 1225 * 0b110: 1080 Ohm 1226 * 0b111: 568 Ohm 1227 * This array maps pull-up strength in Ohms to register values (1+index). 1228 */ 1229 static const u16 bcm281xx_pullup_map[] = { 1230 1200, 1800, 720, 2700, 831, 1080, 568 1231 }; 1232 1233 /* Goes through the configs and update register val/mask */ 1234 static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev, 1235 unsigned int pin, 1236 unsigned long *configs, 1237 unsigned int num_configs, 1238 u32 *val, 1239 u32 *mask) 1240 { 1241 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); 1242 int i, j; 1243 enum pin_config_param param; 1244 u32 arg; 1245 1246 for (i = 0; i < num_configs; i++) { 1247 param = pinconf_to_config_param(configs[i]); 1248 arg = pinconf_to_config_argument(configs[i]); 1249 1250 switch (param) { 1251 case PIN_CONFIG_BIAS_PULL_UP: 1252 for (j = 0; j < ARRAY_SIZE(bcm281xx_pullup_map); j++) 1253 if (bcm281xx_pullup_map[j] == arg) 1254 break; 1255 1256 if (j == ARRAY_SIZE(bcm281xx_pullup_map)) { 1257 dev_err(pctldev->dev, 1258 "Invalid pull-up value (%d) for pin %s " 1259 "(%d). Valid values are 568, 720, 831, " 1260 "1080, 1200, 1800, 2700 Ohms.\n", 1261 arg, pdata->info->pins[pin].name, pin); 1262 return -EINVAL; 1263 } 1264 1265 bcm281xx_pin_update(val, mask, j+1, 1266 BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR), 1267 BCM281XX_PIN_MASK(I2C, PULL_UP_STR)); 1268 break; 1269 1270 case PIN_CONFIG_BIAS_DISABLE: 1271 bcm281xx_pin_update(val, mask, 0, 1272 BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR), 1273 BCM281XX_PIN_MASK(I2C, PULL_UP_STR)); 1274 break; 1275 1276 case PIN_CONFIG_SLEW_RATE: 1277 arg = (arg >= 1 ? 1 : 0); 1278 bcm281xx_pin_update(val, mask, arg, 1279 BCM281XX_PIN_SHIFT(I2C, SLEW), 1280 BCM281XX_PIN_MASK(I2C, SLEW)); 1281 break; 1282 1283 case PIN_CONFIG_INPUT_ENABLE: 1284 /* inversed since register is for input _disable_ */ 1285 arg = (arg >= 1 ? 0 : 1); 1286 bcm281xx_pin_update(val, mask, arg, 1287 BCM281XX_PIN_SHIFT(I2C, INPUT_DIS), 1288 BCM281XX_PIN_MASK(I2C, INPUT_DIS)); 1289 break; 1290 1291 default: 1292 dev_err(pctldev->dev, 1293 "Unrecognized pin config %d for pin %s (%d).\n", 1294 param, pdata->info->pins[pin].name, pin); 1295 return -EINVAL; 1296 1297 } /* switch config */ 1298 } /* for each config */ 1299 1300 return 0; 1301 } 1302 1303 /* Goes through the configs and update register val/mask */ 1304 static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev, 1305 unsigned int pin, 1306 unsigned long *configs, 1307 unsigned int num_configs, 1308 u32 *val, 1309 u32 *mask) 1310 { 1311 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); 1312 int i; 1313 enum pin_config_param param; 1314 u32 arg; 1315 1316 for (i = 0; i < num_configs; i++) { 1317 param = pinconf_to_config_param(configs[i]); 1318 arg = pinconf_to_config_argument(configs[i]); 1319 1320 switch (param) { 1321 case PIN_CONFIG_SLEW_RATE: 1322 arg = (arg >= 1 ? 1 : 0); 1323 bcm281xx_pin_update(val, mask, arg, 1324 BCM281XX_PIN_SHIFT(HDMI, MODE), 1325 BCM281XX_PIN_MASK(HDMI, MODE)); 1326 break; 1327 1328 case PIN_CONFIG_INPUT_ENABLE: 1329 /* inversed since register is for input _disable_ */ 1330 arg = (arg >= 1 ? 0 : 1); 1331 bcm281xx_pin_update(val, mask, arg, 1332 BCM281XX_PIN_SHIFT(HDMI, INPUT_DIS), 1333 BCM281XX_PIN_MASK(HDMI, INPUT_DIS)); 1334 break; 1335 1336 default: 1337 dev_err(pctldev->dev, 1338 "Unrecognized pin config %d for pin %s (%d).\n", 1339 param, pdata->info->pins[pin].name, pin); 1340 return -EINVAL; 1341 1342 } /* switch config */ 1343 } /* for each config */ 1344 1345 return 0; 1346 } 1347 1348 static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, 1349 unsigned int pin, 1350 unsigned long *configs, 1351 unsigned int num_configs) 1352 { 1353 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); 1354 enum bcm281xx_pin_type pin_type; 1355 u32 offset = 4 * pin; 1356 u32 cfg_val, cfg_mask; 1357 int rc; 1358 1359 cfg_val = 0; 1360 cfg_mask = 0; 1361 pin_type = pin_type_get(pctldev, pin); 1362 1363 /* Different pins have different configuration options */ 1364 switch (pin_type) { 1365 case BCM281XX_PIN_TYPE_STD: 1366 rc = bcm281xx_std_pin_update(pctldev, pin, configs, 1367 num_configs, &cfg_val, &cfg_mask); 1368 break; 1369 1370 case BCM281XX_PIN_TYPE_I2C: 1371 rc = bcm281xx_i2c_pin_update(pctldev, pin, configs, 1372 num_configs, &cfg_val, &cfg_mask); 1373 break; 1374 1375 case BCM281XX_PIN_TYPE_HDMI: 1376 rc = bcm281xx_hdmi_pin_update(pctldev, pin, configs, 1377 num_configs, &cfg_val, &cfg_mask); 1378 break; 1379 1380 default: 1381 dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n", 1382 pdata->info->pins[pin].name, pin); 1383 return -EINVAL; 1384 1385 } /* switch pin type */ 1386 1387 if (rc) 1388 return rc; 1389 1390 dev_dbg(pctldev->dev, 1391 "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n", 1392 __func__, pdata->info->pins[pin].name, pin, cfg_val, cfg_mask); 1393 1394 rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val); 1395 if (rc) { 1396 dev_err(pctldev->dev, 1397 "Error updating register for pin %s (%d).\n", 1398 pdata->info->pins[pin].name, pin); 1399 return rc; 1400 } 1401 1402 return 0; 1403 } 1404 1405 static const struct pinconf_ops bcm281xx_pinctrl_pinconf_ops = { 1406 .pin_config_get = bcm281xx_pinctrl_pin_config_get, 1407 .pin_config_set = bcm281xx_pinctrl_pin_config_set, 1408 }; 1409 1410 static struct pinctrl_desc bcm281xx_pinctrl_desc = { 1411 /* name, pins, npins members initialized in probe function */ 1412 .pctlops = &bcm281xx_pinctrl_ops, 1413 .pmxops = &bcm281xx_pinctrl_pinmux_ops, 1414 .confops = &bcm281xx_pinctrl_pinconf_ops, 1415 .owner = THIS_MODULE, 1416 }; 1417 1418 static struct bcm281xx_pinctrl_data bcm281xx_pinctrl_pdata; 1419 1420 static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) 1421 { 1422 struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl_pdata; 1423 struct pinctrl_dev *pctl; 1424 1425 /* Set device pointer in platform data */ 1426 pdata->dev = &pdev->dev; 1427 1428 /* Get the data to use from OF match */ 1429 pdata->info = of_device_get_match_data(&pdev->dev); 1430 if (!pdata->info) { 1431 dev_err(&pdev->dev, "Failed to get data from OF match\n"); 1432 return -ENODEV; 1433 } 1434 1435 /* So far We can assume there is only 1 bank of registers */ 1436 pdata->reg_base = devm_platform_ioremap_resource(pdev, 0); 1437 if (IS_ERR(pdata->reg_base)) { 1438 dev_err(&pdev->dev, "Failed to ioremap MEM resource\n"); 1439 return PTR_ERR(pdata->reg_base); 1440 } 1441 1442 /* Initialize the dynamic part of pinctrl_desc */ 1443 pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base, 1444 pdata->info->regmap_config); 1445 if (IS_ERR(pdata->regmap)) { 1446 dev_err(&pdev->dev, "Regmap MMIO init failed.\n"); 1447 return -ENODEV; 1448 } 1449 1450 bcm281xx_pinctrl_desc.name = dev_name(&pdev->dev); 1451 bcm281xx_pinctrl_desc.pins = pdata->info->pins; 1452 bcm281xx_pinctrl_desc.npins = pdata->info->npins; 1453 1454 pctl = devm_pinctrl_register(&pdev->dev, &bcm281xx_pinctrl_desc, pdata); 1455 if (IS_ERR(pctl)) { 1456 dev_err(&pdev->dev, "Failed to register pinctrl\n"); 1457 return PTR_ERR(pctl); 1458 } 1459 1460 platform_set_drvdata(pdev, pdata); 1461 1462 return 0; 1463 } 1464 1465 static const struct of_device_id bcm281xx_pinctrl_of_match[] = { 1466 { .compatible = "brcm,bcm11351-pinctrl", .data = &bcm281xx_pinctrl }, 1467 { }, 1468 }; 1469 1470 static struct platform_driver bcm281xx_pinctrl_driver = { 1471 .driver = { 1472 .name = "bcm281xx-pinctrl", 1473 .of_match_table = bcm281xx_pinctrl_of_match, 1474 }, 1475 }; 1476 builtin_platform_driver_probe(bcm281xx_pinctrl_driver, bcm281xx_pinctrl_probe); 1477