1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/pcie.h> 18 #include <linux/phy/phy.h> 19 #include <linux/platform_device.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/reset.h> 23 #include <linux/slab.h> 24 25 #include <dt-bindings/phy/phy-qcom-qmp.h> 26 27 #include "phy-qcom-qmp-common.h" 28 29 #include "phy-qcom-qmp.h" 30 #include "phy-qcom-qmp-pcs-misc-v3.h" 31 #include "phy-qcom-qmp-pcs-pcie-v4.h" 32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h" 33 #include "phy-qcom-qmp-pcs-pcie-v5.h" 34 #include "phy-qcom-qmp-pcs-pcie-v5_20.h" 35 #include "phy-qcom-qmp-pcs-pcie-v6.h" 36 #include "phy-qcom-qmp-pcs-pcie-v6_20.h" 37 #include "phy-qcom-qmp-pcs-pcie-v6_30.h" 38 #include "phy-qcom-qmp-pcs-v6_30.h" 39 #include "phy-qcom-qmp-pcie-qhp.h" 40 41 #define PHY_INIT_COMPLETE_TIMEOUT 10000 42 43 /* set of registers with offsets different per-PHY */ 44 enum qphy_reg_layout { 45 /* PCS registers */ 46 QPHY_SW_RESET, 47 QPHY_START_CTRL, 48 QPHY_PCS_STATUS, 49 QPHY_PCS_POWER_DOWN_CONTROL, 50 /* Keep last to ensure regs_layout arrays are properly initialized */ 51 QPHY_LAYOUT_SIZE 52 }; 53 54 static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { 55 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, 56 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, 57 [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS, 58 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, 59 }; 60 61 static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { 62 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 63 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 64 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 65 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 66 }; 67 68 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 69 [QPHY_SW_RESET] = 0x00, 70 [QPHY_START_CTRL] = 0x08, 71 [QPHY_PCS_STATUS] = 0x2ac, 72 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 73 }; 74 75 static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { 76 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 77 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 78 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 79 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 80 }; 81 82 static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { 83 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 84 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 85 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 86 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 87 }; 88 89 static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { 90 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 91 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 92 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 93 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 94 }; 95 96 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 97 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 98 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 99 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 100 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 101 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 102 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 103 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 104 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 105 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 106 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 107 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 108 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 109 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 110 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 111 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 112 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 113 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 114 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 119 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 139 }; 140 141 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 142 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 143 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 144 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 145 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 146 }; 147 148 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 149 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 150 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 151 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 152 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 153 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 154 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 155 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 156 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 157 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 158 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 159 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 160 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 161 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 162 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 163 }; 164 165 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 166 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 167 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 168 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 169 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 170 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 171 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 172 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 173 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 174 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 175 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 176 }; 177 178 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 179 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 180 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 181 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 182 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 183 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 184 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 185 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 186 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 187 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 188 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 189 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 190 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 191 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 192 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 193 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 194 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 195 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 196 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 197 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 198 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 199 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 200 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 201 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 202 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 203 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 204 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 205 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 206 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 207 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 208 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 209 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 210 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 211 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 212 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 213 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 214 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 215 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 216 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 217 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 218 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 219 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 220 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 221 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 222 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 223 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 224 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 225 }; 226 227 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 228 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 229 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 230 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 231 }; 232 233 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 234 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 235 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 236 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 237 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 238 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 239 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 240 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 241 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 242 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 243 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 244 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 245 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 246 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 247 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 248 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 249 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 264 }; 265 266 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 267 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 268 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 269 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 270 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 271 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 272 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 273 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 274 }; 275 276 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 277 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 278 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 279 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 280 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 281 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 282 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 283 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 284 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 285 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 286 }; 287 288 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 289 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 290 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 291 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 292 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 293 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 294 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 295 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 296 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 297 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 298 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 299 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 300 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 301 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 302 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 303 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 304 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 305 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 306 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 307 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 308 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 309 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 310 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 311 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 312 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 313 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 314 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 315 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 316 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 317 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 318 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 319 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 320 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 321 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 322 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 323 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 324 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 325 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 326 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 327 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 328 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 329 }; 330 331 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 332 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 333 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 334 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 335 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 336 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), 337 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 338 }; 339 340 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 341 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 342 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 343 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 344 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 345 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 346 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 347 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 348 }; 349 350 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 351 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 352 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 353 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 354 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 355 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 356 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 357 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 358 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 359 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 360 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 361 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 362 }; 363 364 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 365 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 366 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 367 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 368 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 369 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 370 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 371 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 372 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 373 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 374 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 375 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 376 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 377 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 378 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 379 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 380 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 381 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 382 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 383 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 384 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 385 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 386 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 387 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 388 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 389 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 390 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 391 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 392 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 393 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 394 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 395 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 396 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 397 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 398 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 399 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 400 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 401 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 402 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 403 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 404 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 405 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 406 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 407 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 408 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 409 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 410 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 411 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 412 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 413 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 414 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 415 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 416 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 417 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 418 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 419 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 420 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 421 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 422 }; 423 424 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 425 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 426 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 427 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 428 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 429 }; 430 431 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 432 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 433 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 434 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 435 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 436 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 437 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 438 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 439 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 440 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 441 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 442 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 443 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 444 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 445 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 446 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 447 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 448 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 449 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 462 }; 463 464 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 465 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 466 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 467 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 468 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 469 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 470 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 471 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 472 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 473 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 474 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 475 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 476 }; 477 478 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { 479 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 480 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 481 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 482 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 483 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 490 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 491 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 492 }; 493 494 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] = { 495 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 496 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 497 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 498 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 499 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 500 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 501 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 502 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 503 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 504 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 505 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 506 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 507 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 508 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 509 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 510 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 511 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 512 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 513 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 514 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 515 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 516 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 517 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 518 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 519 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00), 520 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 521 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 522 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 523 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 524 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 525 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a), 526 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 527 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 528 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 529 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 530 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a), 531 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 532 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 533 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 534 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 535 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 536 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 537 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 538 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 539 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 540 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 541 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00), 542 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 543 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 544 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 545 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 546 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 547 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 548 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01), 549 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 550 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 551 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00), 552 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00), 553 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 554 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 555 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 556 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 557 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 558 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 559 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 560 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89), 561 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), 562 }; 563 564 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = { 565 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 566 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 567 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 568 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 569 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 570 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 571 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 572 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 573 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 574 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 575 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 576 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 577 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 578 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 579 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 580 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 581 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 582 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 583 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 584 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 585 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 586 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 587 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 588 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 589 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00), 590 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 591 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 592 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 593 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 594 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 595 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a), 596 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 597 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 598 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 599 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 600 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a), 601 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 602 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 603 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 604 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 605 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 606 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 607 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 608 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 609 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 610 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 611 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00), 612 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 613 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 614 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 615 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 616 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 617 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 618 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01), 619 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 620 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 621 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00), 622 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00), 623 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 624 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 625 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 626 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 627 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 628 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 629 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 630 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89), 631 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), 632 }; 633 634 static const struct qmp_phy_init_tbl ipq9574_pcie_rx_tbl[] = { 635 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 636 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 637 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 638 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 639 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 640 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 641 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 642 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 643 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 644 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 645 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 646 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x73), 647 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x80), 648 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 649 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 650 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 651 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 652 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 653 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x00), 654 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x02), 660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 665 }; 666 667 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_tbl[] = { 668 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 669 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 670 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 671 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 672 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 673 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 674 }; 675 676 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_misc_tbl[] = { 677 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 678 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 679 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 680 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 681 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 682 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 683 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x14), 684 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x10), 685 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0b), 686 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 687 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 688 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 689 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 690 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 691 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 692 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 693 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x06), 694 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03), 695 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 696 }; 697 698 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_tbl[] = { 699 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 700 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 701 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 702 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 703 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 704 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 705 }; 706 707 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = { 708 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 709 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 710 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 711 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 712 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 713 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 714 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14), 715 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10), 716 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b), 717 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00), 718 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58), 719 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 720 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00), 721 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 722 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19), 723 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 724 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49), 725 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a), 726 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02), 727 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03), 728 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 729 }; 730 731 static const struct qmp_phy_init_tbl qcs615_pcie_serdes_tbl[] = { 732 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 733 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 734 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 735 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 736 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 737 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 738 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 739 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 740 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 741 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 742 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 743 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 744 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 745 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 746 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x9), 747 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x4), 748 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 749 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 750 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 751 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 752 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 753 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xd), 754 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x04), 755 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x35), 756 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 757 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 758 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x4), 759 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 760 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x30), 761 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 762 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 763 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 764 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 765 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 766 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 767 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 768 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 769 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 770 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 771 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 772 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 773 }; 774 775 static const struct qmp_phy_init_tbl qcs615_pcie_rx_tbl[] = { 776 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 777 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 778 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 779 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 780 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 781 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 782 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 783 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4), 784 }; 785 786 static const struct qmp_phy_init_tbl qcs615_pcie_tx_tbl[] = { 787 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 788 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 789 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 790 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 791 }; 792 793 static const struct qmp_phy_init_tbl qcs615_pcie_pcs_tbl[] = { 794 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 795 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 796 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 797 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 798 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 799 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 800 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 801 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 802 QMP_PHY_INIT_CFG(QPHY_V2_PCS_SIGDET_CNTRL, 0x7), 803 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 804 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 805 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 806 }; 807 808 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 809 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 810 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 811 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 812 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 813 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 814 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 815 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 816 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 817 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 818 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 819 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 820 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 821 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 822 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 823 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 824 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 825 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 826 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 827 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 828 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 829 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 830 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 831 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 832 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 833 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 834 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 835 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 836 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 837 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 838 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 839 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 840 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 841 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 842 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 843 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 844 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 845 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 846 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 847 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 848 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 849 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 850 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 851 }; 852 853 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 854 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 855 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 856 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 857 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 858 }; 859 860 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 861 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 862 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 863 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 864 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 865 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 866 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 867 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 868 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 869 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 870 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 871 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 872 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 873 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 874 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 875 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 876 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 877 }; 878 879 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 880 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 881 882 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 883 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 884 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 885 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 886 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 887 888 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 889 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 890 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 891 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 892 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 893 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 894 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 895 896 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 897 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 898 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 899 900 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 901 }; 902 903 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 904 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 905 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 906 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 907 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 908 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 909 }; 910 911 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 912 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 913 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 914 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 915 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 916 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 917 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 918 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 919 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 920 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 921 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 922 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 923 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 924 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 925 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 926 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 927 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 928 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 929 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 930 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 931 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 932 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 933 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 934 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 935 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 936 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 937 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 938 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 939 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 940 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 941 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 942 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 943 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 944 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 945 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 946 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 947 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 948 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 949 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 950 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 951 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 952 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 953 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 954 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 955 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 956 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 957 }; 958 959 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 960 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 961 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 962 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 963 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 964 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 965 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 966 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 967 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 968 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 969 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 970 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 971 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 972 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 973 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 974 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 975 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 976 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 977 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 978 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 979 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 980 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 981 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 982 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 983 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 984 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 985 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 986 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 987 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 988 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 989 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 990 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 991 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 992 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 993 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 994 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 995 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 996 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 997 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 998 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 999 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 1000 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 1001 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 1002 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 1003 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 1004 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 1005 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 1006 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 1007 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 1008 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 1009 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 1010 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 1011 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 1012 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 1013 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 1014 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 1015 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 1016 }; 1017 1018 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 1019 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 1020 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 1021 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 1022 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 1023 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 1024 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 1025 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 1026 }; 1027 1028 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 1029 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 1030 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 1031 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 1032 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1033 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 1034 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 1035 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 1036 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 1037 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1038 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1039 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 1040 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 1041 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 1042 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 1043 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 1044 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 1045 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 1046 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 1048 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 1049 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 1050 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 1051 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1052 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1053 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1054 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1055 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1056 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1057 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1058 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1059 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1060 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1061 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1062 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 1063 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1064 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1065 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1066 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1067 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1068 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1069 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1070 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1071 }; 1072 1073 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 1074 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1075 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 1076 }; 1077 1078 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 1079 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 1080 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 1081 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 1082 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 1083 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 1084 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 1085 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 1086 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1087 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1088 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 1089 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 1090 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 1091 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 1092 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 1093 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 1094 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 1095 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 1096 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 1097 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 1098 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 1099 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 1100 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 1101 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 1102 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 1103 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 1104 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 1105 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 1106 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 1107 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1108 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1109 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1110 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 1111 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1112 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 1113 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1114 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 1115 }; 1116 1117 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 1118 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1119 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1120 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 1121 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1122 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 1123 }; 1124 1125 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 1126 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1127 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1128 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1129 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1130 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1131 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1132 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1133 }; 1134 1135 static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = { 1136 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1138 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1139 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1140 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1141 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1142 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1143 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1146 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1147 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1148 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1149 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1150 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1151 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1154 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1155 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1156 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1157 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1158 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1162 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1163 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1164 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1165 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1166 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1167 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1168 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1169 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1170 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1171 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1172 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9), 1173 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1174 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94), 1175 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1176 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1177 }; 1178 1179 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 1180 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1181 }; 1182 1183 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = { 1184 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1185 }; 1186 1187 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = { 1188 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 1189 }; 1190 1191 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = { 1192 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1193 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1194 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1195 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1196 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1197 }; 1198 1199 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = { 1200 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1201 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1202 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1203 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1204 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1205 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1206 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1207 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1208 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1209 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1210 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1211 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1212 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1213 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1214 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1215 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1216 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1217 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1218 }; 1219 1220 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = { 1221 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1222 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1223 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1224 }; 1225 1226 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1227 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1228 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1229 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1230 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1231 }; 1232 1233 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = { 1234 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 1235 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 1236 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 1237 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1238 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1239 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1240 }; 1241 1242 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = { 1243 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1244 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1245 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 1246 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 1247 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1248 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1249 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1250 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1251 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1252 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1253 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1254 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1255 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1256 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1257 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1258 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1259 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1260 }; 1261 1262 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = { 1263 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1264 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88), 1265 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1266 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f), 1267 }; 1268 1269 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1270 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 1271 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1272 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1273 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1274 }; 1275 1276 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = { 1277 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 1278 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1279 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 1280 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1281 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1282 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1283 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 1284 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 1285 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 1286 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 1287 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 1288 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 1289 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 1290 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 1291 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1292 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1293 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1294 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1295 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1296 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 1297 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 1298 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1299 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 1300 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 1301 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1302 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1303 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1304 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1305 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1306 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1307 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 1308 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), 1309 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 1310 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 1311 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1312 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 1313 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 1314 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1315 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1316 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 1317 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1318 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 1319 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 1320 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 1321 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 1322 }; 1323 1324 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl[] = { 1325 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c), 1326 }; 1327 1328 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 1329 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 1330 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88), 1331 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), 1332 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), 1333 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4), 1334 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 1335 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 1336 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 1337 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32), 1338 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 1339 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 1340 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1341 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1342 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1343 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1344 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1345 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1346 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1347 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1348 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1349 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), 1350 }; 1351 1352 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = { 1353 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1354 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), 1355 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 1356 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10), 1357 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 1358 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 1359 }; 1360 1361 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = { 1362 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), 1363 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), 1364 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 1365 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 1366 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 1367 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 1368 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00), 1369 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15), 1370 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01), 1371 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01), 1372 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45), 1373 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a, 1), 1374 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b, 2), 1375 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), 1376 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 1377 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1378 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 1379 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 1380 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, 1), 1381 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38, 2), 1382 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39), 1383 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), 1384 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), 1385 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 1386 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 1387 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), 1388 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 1389 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 1390 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xe4), 1391 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xa4), 1392 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 1393 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 1394 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b), 1395 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 1396 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 1397 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), 1398 }; 1399 1400 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = { 1401 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), 1402 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), 1403 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), 1404 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), 1405 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), 1406 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), 1407 }; 1408 1409 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1410 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 1411 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), 1412 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), 1413 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), 1414 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), 1415 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), 1416 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), 1417 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), 1418 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), 1419 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), 1420 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), 1421 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x18), 1422 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0x7a), 1423 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0x8a), 1424 }; 1425 1426 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_serdes_tbl[] = { 1427 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 1428 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1429 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 1430 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1431 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1432 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x08), 1433 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x04), 1434 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0d), 1435 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 1436 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 1437 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 1438 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 1439 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 1440 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 1441 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1442 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1443 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1444 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1445 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1446 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 1447 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 1448 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1449 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 1450 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 1451 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1452 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1453 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1454 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1455 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1456 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1457 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 1458 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c), 1459 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 1460 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 1461 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1462 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 1463 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 1464 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1465 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1466 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 1467 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 1468 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 1469 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 1470 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 1471 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 1472 }; 1473 1474 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl[] = { 1475 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 1476 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), 1477 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88), 1478 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), 1479 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), 1480 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), 1481 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 1482 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 1483 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 1484 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38), 1485 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 1486 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 1487 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1488 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1489 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1490 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1491 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1492 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1493 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1494 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1495 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1496 }; 1497 1498 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_txz_tbl[] = { 1499 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1500 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x05), 1501 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 1502 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10), 1503 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 1504 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 1505 }; 1506 1507 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rxz_tbl[] = { 1508 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), 1509 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), 1510 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 1511 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 1512 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 1513 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 1514 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00), 1515 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15), 1516 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45), 1517 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0c), 1518 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), 1519 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 1520 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1521 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 1522 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 1523 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1524 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39), 1525 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd4), 1526 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0x23), 1527 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 1528 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 1529 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x38), 1530 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 1531 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 1532 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x1c), 1533 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xe4), 1534 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 1535 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 1536 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x69), 1537 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 1538 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 1539 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), 1540 }; 1541 1542 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rx_tbl[] = { 1543 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, BIT(0)), 1544 }; 1545 1546 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_tbl[] = { 1547 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_LOCK_DETECT_CONFIG2, 0x00), 1548 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_G3S2_PRE_GAIN, 0x2e), 1549 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_RX_SIGDET_LVL, 0x99), 1550 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_ALIGN_DETECT_CONFIG7, 0x00), 1551 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG4, 0x00), 1552 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG5, 0x22), 1553 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG, 0x04), 1554 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG2, 0x02), 1555 }; 1556 1557 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl[] = { 1558 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 1559 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_OSC_DTCT_ACTIONS, 0x00), 1560 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_EQ_CONFIG1, 0x16), 1561 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_EQ_CONFIG5, 0x02), 1562 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_PRE_GAIN, 0x2e), 1563 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG1, 0x03), 1564 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG3, 0x28), 1565 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG5, 0x18), 1566 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_FOM_EQ_CONFIG5, 0x7a), 1567 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_FOM_EQ_CONFIG5, 0x8a), 1568 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_RXEQEVAL_TIME, 0x27), 1569 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_RXEQEVAL_TIME, 0x27), 1570 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_TX_RX_CONFIG, 0xc0), 1571 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_POWER_STATE_CONFIG2, 0x1d), 1572 }; 1573 1574 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 1575 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 1576 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 1577 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 1578 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1579 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 1580 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 1581 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 1582 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 1583 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1584 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1585 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 1586 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 1587 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 1588 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 1589 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 1590 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 1591 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 1592 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 1593 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 1594 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 1595 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 1596 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 1597 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1598 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1599 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1600 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1601 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1602 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1603 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1604 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1605 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1606 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1607 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1608 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1609 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1610 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1611 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1612 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1613 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1614 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1615 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1616 }; 1617 1618 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 1619 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 1620 }; 1621 1622 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 1623 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1624 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 1625 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1626 }; 1627 1628 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 1629 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1630 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 1631 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 1632 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1633 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1634 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 1635 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 1636 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 1637 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1638 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 1639 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1640 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1641 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 1642 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 1643 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 1644 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 1645 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 1646 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 1647 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 1648 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 1649 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 1650 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 1651 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 1652 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 1653 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 1654 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 1656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 1657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 1658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 1659 }; 1660 1661 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 1662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 1663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 1664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1665 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 1666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 1667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 1668 }; 1669 1670 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 1671 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1672 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 1673 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 1674 }; 1675 1676 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 1677 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1678 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 1679 }; 1680 1681 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 1682 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1683 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1684 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1685 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 1686 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1687 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1688 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1689 }; 1690 1691 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1692 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1693 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 1694 }; 1695 1696 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 1697 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 1698 }; 1699 1700 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 1701 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 1702 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 1703 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 1704 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1705 }; 1706 1707 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 1708 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 1709 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 1710 }; 1711 1712 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1713 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 1714 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1715 }; 1716 1717 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 1718 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 1719 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1720 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 1721 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 1722 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1723 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 1724 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1725 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 1726 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1727 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1728 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1729 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1730 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1731 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1732 }; 1733 1734 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = { 1735 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1736 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1737 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1738 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce), 1739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b), 1740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a), 1744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10), 1745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 1752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04), 1753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d), 1754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a), 1755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a), 1756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3), 1757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0), 1758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05), 1759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55), 1760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55), 1761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05), 1762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 1763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8), 1766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20), 1767 }; 1768 1769 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = { 1770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 1771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 1772 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 1773 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 1774 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 1775 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 1776 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 1777 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 1778 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 1779 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 1780 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 1781 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 1782 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 1783 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 1784 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 1785 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 1786 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1787 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1788 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1789 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1790 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1791 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 1792 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 1793 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 1794 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 1795 }; 1796 1797 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 1798 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 1799 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 1800 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 1801 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 1802 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 1803 }; 1804 1805 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 1806 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 1807 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 1808 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 1809 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 1810 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 1811 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 1812 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 1813 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1814 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 1815 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 1816 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 1817 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 1818 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 1819 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 1820 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 1821 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 1822 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 1823 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 1824 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 1825 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 1826 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 1827 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 1828 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1829 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1830 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1831 }; 1832 1833 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1834 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1835 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1836 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1837 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1838 }; 1839 1840 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1841 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1842 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1843 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1844 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1845 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1846 }; 1847 1848 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = { 1849 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1850 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1851 }; 1852 1853 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_lane1_tbl[] = { 1854 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1855 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1856 }; 1857 1858 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_serdes_tbl[] = { 1859 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1860 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1861 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1862 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1863 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1864 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1865 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1866 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1867 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1868 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1869 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1870 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1871 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1872 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1873 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1874 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1875 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1876 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1877 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1878 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1879 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1880 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1881 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1882 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1883 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1884 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1885 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1886 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1887 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1888 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1889 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1890 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1891 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE_CONTD, 0x00), 1892 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1893 }; 1894 1895 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_tx_tbl[] = { 1896 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1897 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1898 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x00), 1899 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_VMODE_CTRL1, 0x00), 1900 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_PI_QEC_CTRL, 0x00), 1901 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1902 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1903 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RCV_DETECT_LVL_2, 0x12), 1904 }; 1905 1906 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_rx_tbl[] = { 1907 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1908 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_1, 0x06), 1909 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_2, 0x06), 1910 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1, 0x3e), 1911 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2, 0x1e), 1912 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1913 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1914 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1, 0x02), 1915 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2, 0x1d), 1916 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x44), 1917 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL2, 0x00), 1918 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 1919 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1920 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x74), 1921 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 1922 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_ENABLES, 0x1c), 1923 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_CNTRL, 0x03), 1924 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 1925 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x04), 1926 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1927 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1928 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1929 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x64), 1930 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1931 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1932 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1933 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DCC_CTRL1, 0x0c), 1934 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1935 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1936 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1937 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1938 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1939 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1940 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1941 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1942 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1943 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1944 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1945 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1946 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1947 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1948 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1949 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1950 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE2, 0x00), 1951 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1952 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1953 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1954 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1955 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xac), 1956 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1957 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1958 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x07), 1959 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1960 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 1961 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc5), 1962 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xee), 1963 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1964 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1965 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1966 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1967 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1968 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_EN_TIMER, 0x28), 1969 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1970 }; 1971 1972 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_tbl[] = { 1973 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 1974 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0xaa), 1975 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG2, 0x0d), 1976 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 1977 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 1978 }; 1979 1980 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = { 1981 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1982 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1983 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1984 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d), 1985 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1986 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1987 }; 1988 1989 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_lane1_tbl[] = { 1990 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1991 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1992 }; 1993 1994 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = { 1995 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1996 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1997 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1998 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1999 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 2000 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 2001 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 2002 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 2003 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2004 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 2005 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 2006 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 2007 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 2008 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 2009 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 2010 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 2011 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 2012 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 2013 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 2014 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 2015 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 2016 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 2017 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 2018 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 2019 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 2020 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 2021 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 2022 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 2023 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 2024 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 2025 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 2026 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 2027 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 2028 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 2029 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 2030 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 2031 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2032 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2033 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 2034 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 2035 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 2036 }; 2037 2038 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 2039 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 2040 }; 2041 2042 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 2043 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 2044 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 2045 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 2046 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 2047 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 2048 }; 2049 2050 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = { 2051 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 2052 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 2053 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 2054 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 2055 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 2056 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 2057 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 2058 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 2059 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 2060 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 2061 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 2062 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 2063 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2064 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 2065 }; 2066 2067 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = { 2068 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 2069 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 2070 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 2071 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 2072 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 2073 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 2074 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 2075 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 2076 }; 2077 2078 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = { 2079 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 2080 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 2081 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 2082 }; 2083 2084 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 2085 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2086 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 2087 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 2088 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2089 }; 2090 2091 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = { 2092 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 2093 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 2094 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 2095 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 2096 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 2097 }; 2098 2099 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = { 2100 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 2101 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 2102 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 2103 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 2104 }; 2105 2106 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = { 2107 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 2108 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 2109 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 2110 }; 2111 2112 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = { 2113 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 2114 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 2115 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 2116 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 2117 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 2118 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 2119 }; 2120 2121 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = { 2122 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f), 2123 }; 2124 2125 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 2126 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 2127 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 2128 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 2129 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 2130 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2131 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 2132 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 2133 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 2134 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 2135 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 2136 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 2137 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2138 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 2139 }; 2140 2141 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = { 2142 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 2143 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 2144 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2145 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2146 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 2147 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 2148 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 2149 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 2150 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 2151 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 2152 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 2153 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 2154 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 2155 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 2156 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 2157 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 2158 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 2159 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 2160 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 2161 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 2162 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 2163 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 2164 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 2165 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 2166 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 2167 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 2168 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 2169 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 2170 }; 2171 2172 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 2173 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 2174 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 2175 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 2176 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 2177 }; 2178 2179 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 2180 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 2181 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2182 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 2183 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 2184 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 2185 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 2186 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 2187 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 2188 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 2189 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 2190 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 2191 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 2192 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 2193 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 2194 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 2195 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 2196 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 2197 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 2198 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 2199 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 2200 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 2201 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 2202 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 2203 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 2204 2205 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 2206 2207 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2208 2209 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2210 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2211 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2212 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2213 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2214 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2215 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2216 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2217 2218 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 2219 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 2220 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 2221 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2222 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 2223 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 2224 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 2225 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 2226 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 2227 }; 2228 2229 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 2230 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 2231 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 2232 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 2233 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99), 2234 }; 2235 2236 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 2237 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 2238 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 2239 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 2240 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 2241 }; 2242 2243 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { 2244 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2245 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2246 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00), 2247 }; 2248 2249 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = { 2250 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 2251 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 2252 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 2253 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 2254 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 2255 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 2256 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 2257 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 2258 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 2259 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 2260 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 2261 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 2262 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 2263 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 2264 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 2265 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 2266 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 2267 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 2268 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 2269 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 2270 }; 2271 2272 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = { 2273 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 2274 }; 2275 2276 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = { 2277 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 2278 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 2279 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 2280 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 2281 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 2282 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93), 2283 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 2284 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 2285 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 2286 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 2287 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 2288 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 2289 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 2290 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 2291 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 2292 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 2293 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 2294 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 2295 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), 2296 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 2297 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 2298 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 2299 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 2300 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 2301 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34), 2302 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 2303 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 2304 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 2305 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 2306 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 2307 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 2308 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 2309 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 2310 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 2311 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 2312 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 2313 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), 2314 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 2315 }; 2316 2317 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = { 2318 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15), 2319 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 2320 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02), 2321 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 2322 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18), 2323 }; 2324 2325 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = { 2326 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2327 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11), 2328 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), 2329 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf), 2330 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7), 2331 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea), 2332 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), 2333 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 2334 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 2335 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a), 2336 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89), 2337 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 2338 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94), 2339 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b), 2340 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a), 2341 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89), 2342 QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00), 2343 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09), 2344 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05), 2345 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 2346 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 2347 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 2348 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c), 2349 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 2350 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 2351 }; 2352 2353 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = { 2354 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05), 2355 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77), 2356 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b), 2357 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f), 2358 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c), 2359 }; 2360 2361 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 2362 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e), 2363 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27), 2364 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 2365 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 2366 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2367 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2368 }; 2369 2370 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = { 2371 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 2372 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 2373 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 2374 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 2375 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 2376 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 2377 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 2378 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 2379 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 2380 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 2381 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 2382 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 2383 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 2384 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 2385 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 2386 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 2387 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 2388 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 2389 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 2390 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 2391 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 2392 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 2393 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 2394 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 2395 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 2396 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 2397 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 2398 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 2399 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 2400 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 2401 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 2402 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), 2403 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 2404 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 2405 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 2406 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 2407 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 2408 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 2409 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 2410 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 2411 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 2412 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 2413 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 2414 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 2415 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 2416 }; 2417 2418 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 2419 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 2420 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00), 2421 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), 2422 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), 2423 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), 2424 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 2425 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 2426 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 2427 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38), 2428 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 2429 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 2430 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2431 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2432 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2433 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2434 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2435 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2436 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2437 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2438 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2439 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), 2440 }; 2441 2442 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = { 2443 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 2444 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), 2445 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 2446 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00), 2447 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 2448 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 2449 }; 2450 2451 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = { 2452 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), 2453 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 2454 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), 2455 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 2456 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 2457 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 2458 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c), 2459 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), 2460 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), 2461 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), 2462 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 2463 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2464 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 2465 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 2466 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 2467 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 2468 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), 2469 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), 2470 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 2471 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 2472 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), 2473 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 2474 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 2475 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb), 2476 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb), 2477 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0), 2478 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 2479 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78), 2480 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 2481 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 2482 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), 2483 }; 2484 2485 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = { 2486 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 2487 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), 2488 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), 2489 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), 2490 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), 2491 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), 2492 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), 2493 }; 2494 2495 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 2496 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 2497 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), 2498 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), 2499 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), 2500 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), 2501 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), 2502 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), 2503 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), 2504 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), 2505 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), 2506 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), 2507 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f), 2508 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2), 2509 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2), 2510 }; 2511 2512 static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = { 2513 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a), 2514 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 2515 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 2516 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 2517 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82), 2518 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), 2519 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), 2520 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 2521 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2522 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 2523 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 2524 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2525 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3), 2526 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3), 2527 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00), 2528 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 2529 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06), 2530 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 2531 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 2532 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23), 2533 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b), 2534 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 2535 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 2536 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43), 2537 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 2538 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 2539 }; 2540 2541 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = { 2542 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 2543 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 2544 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 2545 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 2546 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2547 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 2548 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 2549 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 2550 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 2551 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 2552 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 2553 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 2554 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2555 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 2556 }; 2557 2558 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl[] = { 2559 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 2560 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 2561 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 2562 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2563 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2564 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 2565 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 2566 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 2567 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 2568 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 2569 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 2570 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 2571 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 2572 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 2573 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 2574 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 2575 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 2576 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 2577 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 2578 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 2579 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 2580 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 2581 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 2582 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 2583 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 2584 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 2585 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 2586 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 2587 }; 2588 2589 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rx_alt_tbl[] = { 2590 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 2591 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2592 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9a), 2593 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0), 2594 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92), 2595 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0), 2596 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42), 2597 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x99), 2598 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 2599 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a), 2600 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb), 2601 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92), 2602 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec), 2603 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43), 2604 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd), 2605 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 2606 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3), 2607 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8), 2608 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec), 2609 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6), 2610 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83), 2611 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5), 2612 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e), 2613 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 2614 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 2615 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 2616 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00), 2617 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2618 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2619 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2620 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2621 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2622 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2623 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2624 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2625 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2626 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 2627 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 2628 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08), 2629 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04), 2630 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04), 2631 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08), 2632 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2633 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c), 2634 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 2635 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 2636 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05), 2637 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 2638 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 2639 }; 2640 2641 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_tx_tbl[] = { 2642 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 2643 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 2644 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 2645 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 2646 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x0f), 2647 }; 2648 2649 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_misc_tbl[] = { 2650 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 2651 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 2652 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 2653 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 2654 }; 2655 2656 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl[] = { 2657 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 2658 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2659 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2660 }; 2661 2662 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl[] = { 2663 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 2664 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 2665 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 2666 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66), 2667 }; 2668 2669 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = { 2670 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 2671 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 2672 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00), 2673 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2674 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 2675 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05), 2676 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 2677 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2678 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c), 2679 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 2680 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2681 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2682 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2683 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2684 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2685 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2686 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2687 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2688 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2689 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 2690 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x99), 2691 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0), 2692 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92), 2693 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0), 2694 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42), 2695 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00), 2696 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20), 2697 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a), 2698 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xb6), 2699 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92), 2700 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xf0), 2701 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43), 2702 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd), 2703 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 2704 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3), 2705 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf6), 2706 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xee), 2707 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd2), 2708 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83), 2709 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf9), 2710 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x3d), 2711 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 2712 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 2713 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 2714 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08), 2715 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04), 2716 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 2717 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04), 2718 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08), 2719 }; 2720 2721 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl[] = { 2722 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 2723 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 2724 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 2725 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66), 2726 }; 2727 2728 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = { 2729 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 2730 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 2731 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 2732 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 2733 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 2734 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 2735 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2736 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 2737 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 2738 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 2739 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 2740 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 2741 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 2742 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 2743 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2744 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 2745 }; 2746 2747 2748 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[] = { 2749 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 2750 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 2751 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 2752 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2753 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2754 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 2755 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 2756 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 2757 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 2758 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 2759 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 2760 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 2761 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 2762 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 2763 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 2764 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 2765 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 2766 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 2767 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 2768 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 2769 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 2770 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 2771 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 2772 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 2773 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 2774 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 2775 }; 2776 2777 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl[] = { 2778 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 2779 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 2780 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 2781 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 2782 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 2783 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 2784 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 2785 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 2786 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 2787 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 2788 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 2789 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 2790 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 2791 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2792 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 2793 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 2794 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 2795 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 2796 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 2797 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 2798 }; 2799 2800 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] = { 2801 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_MX_CTRL7, 0x00), 2802 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_SW_CTRL7, 0x00), 2803 }; 2804 2805 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl[] = { 2806 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 2807 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), 2808 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), 2809 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xff), 2810 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06), 2811 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 2812 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06), 2813 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 2814 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 2815 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 2816 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 2817 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 2818 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 2819 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 2820 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 2821 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 2822 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 2823 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), 2824 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), 2825 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 2826 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 2827 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x14), 2828 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x34), 2829 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 2830 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 2831 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 2832 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea), 2833 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02), 2834 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 2835 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 2836 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 2837 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 2838 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 2839 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 2840 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 2841 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 2842 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), 2843 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 2844 }; 2845 2846 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl[] = { 2847 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_SW_CTRL2, 0x01), 2848 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_MX_CTRL2, 0x01), 2849 }; 2850 2851 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_tx_tbl[] = { 2852 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_BIST_MODE_LANENO, 0x00, 2), 2853 }; 2854 2855 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl[] = { 2856 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 2857 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G3S2_PRE_GAIN, 0x2e), 2858 }; 2859 2860 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl[] = { 2861 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x00), 2862 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x06), 2863 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x07), 2864 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 2865 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x28), 2866 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x28), 2867 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x0d), 2868 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x0d), 2869 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x00), 2870 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x00), 2871 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), 2872 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff), 2873 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 2874 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0xff), 2875 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x09), 2876 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x19), 2877 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x14), 2878 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 2879 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x03), 2880 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 2881 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE1, 0x03), 2882 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 2883 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 2884 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 2885 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 2886 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 2887 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 2888 }; 2889 2890 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl[] = { 2891 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 2892 }; 2893 2894 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl[] = { 2895 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e), 2896 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x14), 2897 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 2898 }; 2899 2900 struct qmp_pcie_offsets { 2901 u16 serdes; 2902 u16 pcs; 2903 u16 pcs_misc; 2904 u16 pcs_lane1; 2905 u16 tx; 2906 u16 rx; 2907 u16 tx2; 2908 u16 rx2; 2909 u16 txz; 2910 u16 rxz; 2911 u16 ln_shrd; 2912 }; 2913 2914 struct qmp_phy_cfg_tbls { 2915 const struct qmp_phy_init_tbl *serdes; 2916 int serdes_num; 2917 const struct qmp_phy_init_tbl *tx; 2918 int tx_num; 2919 const struct qmp_phy_init_tbl *rx; 2920 int rx_num; 2921 const struct qmp_phy_init_tbl *txz; 2922 int txz_num; 2923 const struct qmp_phy_init_tbl *rxz; 2924 int rxz_num; 2925 const struct qmp_phy_init_tbl *pcs; 2926 int pcs_num; 2927 const struct qmp_phy_init_tbl *pcs_misc; 2928 int pcs_misc_num; 2929 const struct qmp_phy_init_tbl *pcs_lane1; 2930 int pcs_lane1_num; 2931 const struct qmp_phy_init_tbl *ln_shrd; 2932 int ln_shrd_num; 2933 }; 2934 2935 /* struct qmp_phy_cfg - per-PHY initialization config */ 2936 struct qmp_phy_cfg { 2937 int lanes; 2938 2939 const struct qmp_pcie_offsets *offsets; 2940 2941 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 2942 const struct qmp_phy_cfg_tbls tbls; 2943 /* 2944 * Additional init sequences for PHY blocks, providing additional 2945 * register programming. They are used for providing separate sequences 2946 * for the Root Complex and End Point use cases. 2947 * 2948 * If EP mode is not supported, both tables can be left unset. 2949 */ 2950 const struct qmp_phy_cfg_tbls *tbls_rc; 2951 const struct qmp_phy_cfg_tbls *tbls_ep; 2952 2953 const struct qmp_phy_init_tbl *serdes_4ln_tbl; 2954 int serdes_4ln_num; 2955 2956 /* resets to be requested */ 2957 const char * const *reset_list; 2958 int num_resets; 2959 /* regulators to be requested */ 2960 const char * const *vreg_list; 2961 int num_vregs; 2962 2963 /* array of registers with different offsets */ 2964 const unsigned int *regs; 2965 2966 unsigned int pwrdn_ctrl; 2967 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 2968 unsigned int phy_status; 2969 2970 bool skip_start_delay; 2971 2972 bool has_nocsr_reset; 2973 2974 /* QMP PHY pipe clock interface rate */ 2975 unsigned long pipe_clock_rate; 2976 2977 /* QMP PHY AUX clock interface rate */ 2978 unsigned long aux_clock_rate; 2979 }; 2980 2981 struct qmp_pcie { 2982 struct device *dev; 2983 2984 const struct qmp_phy_cfg *cfg; 2985 bool tcsr_4ln_config; 2986 2987 void __iomem *serdes; 2988 void __iomem *pcs; 2989 void __iomem *pcs_misc; 2990 void __iomem *pcs_lane1; 2991 void __iomem *tx; 2992 void __iomem *rx; 2993 void __iomem *tx2; 2994 void __iomem *rx2; 2995 void __iomem *txz; 2996 void __iomem *rxz; 2997 void __iomem *ln_shrd; 2998 2999 void __iomem *port_b; 3000 3001 struct clk_bulk_data *clks; 3002 struct clk_bulk_data pipe_clks[2]; 3003 int num_pipe_clks; 3004 3005 struct reset_control_bulk_data *resets; 3006 struct reset_control *nocsr_reset; 3007 struct regulator_bulk_data *vregs; 3008 3009 struct phy *phy; 3010 int mode; 3011 3012 struct clk_fixed_rate pipe_clk_fixed; 3013 struct clk_fixed_rate aux_clk_fixed; 3014 }; 3015 3016 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 3017 { 3018 u32 reg; 3019 3020 reg = readl(base + offset); 3021 reg |= val; 3022 writel(reg, base + offset); 3023 3024 /* ensure that above write is through */ 3025 readl(base + offset); 3026 } 3027 3028 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 3029 { 3030 u32 reg; 3031 3032 reg = readl(base + offset); 3033 reg &= ~val; 3034 writel(reg, base + offset); 3035 3036 /* ensure that above write is through */ 3037 readl(base + offset); 3038 } 3039 3040 /* list of clocks required by phy */ 3041 static const char * const qmp_pciephy_clk_l[] = { 3042 "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", 3043 }; 3044 3045 /* list of regulators */ 3046 static const char * const qmp_phy_vreg_l[] = { 3047 "vdda-phy", "vdda-pll", 3048 }; 3049 3050 static const char * const sm8550_qmp_phy_vreg_l[] = { 3051 "vdda-phy", "vdda-pll", "vdda-qref", 3052 }; 3053 3054 /* list of resets */ 3055 static const char * const ipq8074_pciephy_reset_l[] = { 3056 "phy", "common", 3057 }; 3058 3059 static const char * const sdm845_pciephy_reset_l[] = { 3060 "phy", 3061 }; 3062 3063 static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = { 3064 .serdes = 0, 3065 .pcs = 0x1800, 3066 .tx = 0x0800, 3067 /* no .rx for QHP */ 3068 }; 3069 3070 static const struct qmp_pcie_offsets qmp_pcie_offsets_v2 = { 3071 .serdes = 0, 3072 .pcs = 0x0800, 3073 .tx = 0x0200, 3074 .rx = 0x0400, 3075 }; 3076 3077 static const struct qmp_pcie_offsets qmp_pcie_offsets_v3 = { 3078 .serdes = 0, 3079 .pcs = 0x0800, 3080 .pcs_misc = 0x0600, 3081 .tx = 0x0200, 3082 .rx = 0x0400, 3083 }; 3084 3085 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = { 3086 .serdes = 0, 3087 .pcs = 0x0800, 3088 .pcs_misc = 0x0c00, 3089 .tx = 0x0200, 3090 .rx = 0x0400, 3091 }; 3092 3093 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = { 3094 .serdes = 0, 3095 .pcs = 0x0a00, 3096 .pcs_misc = 0x0e00, 3097 .tx = 0x0200, 3098 .rx = 0x0400, 3099 .tx2 = 0x0600, 3100 .rx2 = 0x0800, 3101 }; 3102 3103 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = { 3104 .serdes = 0x1000, 3105 .pcs = 0x1200, 3106 .pcs_misc = 0x1600, 3107 .pcs_lane1 = 0x1e00, 3108 .tx = 0x0000, 3109 .rx = 0x0200, 3110 .tx2 = 0x0800, 3111 .rx2 = 0x0a00, 3112 }; 3113 3114 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { 3115 .serdes = 0, 3116 .pcs = 0x0200, 3117 .pcs_misc = 0x0600, 3118 .tx = 0x0e00, 3119 .rx = 0x1000, 3120 .tx2 = 0x1600, 3121 .rx2 = 0x1800, 3122 }; 3123 3124 static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = { 3125 .serdes = 0, 3126 .pcs = 0x1000, 3127 .pcs_misc = 0x1400, 3128 .tx = 0x0200, 3129 .rx = 0x0400, 3130 .tx2 = 0x0600, 3131 .rx2 = 0x0800, 3132 }; 3133 3134 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = { 3135 .serdes = 0x1000, 3136 .pcs = 0x1200, 3137 .pcs_misc = 0x1400, 3138 .pcs_lane1 = 0x1e00, 3139 .tx = 0x0000, 3140 .rx = 0x0200, 3141 .tx2 = 0x0800, 3142 .rx2 = 0x0a00, 3143 }; 3144 3145 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = { 3146 .serdes = 0x2000, 3147 .pcs = 0x2200, 3148 .pcs_misc = 0x2400, 3149 .tx = 0x0, 3150 .rx = 0x0200, 3151 .tx2 = 0x3800, 3152 .rx2 = 0x3a00, 3153 }; 3154 3155 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = { 3156 .serdes = 0x1000, 3157 .pcs = 0x1200, 3158 .pcs_misc = 0x1400, 3159 .tx = 0x0000, 3160 .rx = 0x0200, 3161 .tx2 = 0x0800, 3162 .rx2 = 0x0a00, 3163 .ln_shrd = 0x0e00, 3164 }; 3165 3166 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_30 = { 3167 .serdes = 0x8800, 3168 .pcs = 0x9000, 3169 .pcs_misc = 0x9800, 3170 .tx = 0x0000, 3171 .rx = 0x0200, 3172 .txz = 0xe000, 3173 .rxz = 0xe200, 3174 .ln_shrd = 0x8000, 3175 }; 3176 3177 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 3178 .lanes = 1, 3179 3180 .offsets = &qmp_pcie_offsets_v2, 3181 3182 .tbls = { 3183 .serdes = ipq8074_pcie_serdes_tbl, 3184 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 3185 .tx = ipq8074_pcie_tx_tbl, 3186 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 3187 .rx = ipq8074_pcie_rx_tbl, 3188 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 3189 .pcs = ipq8074_pcie_pcs_tbl, 3190 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 3191 }, 3192 .reset_list = ipq8074_pciephy_reset_l, 3193 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3194 .vreg_list = NULL, 3195 .num_vregs = 0, 3196 .regs = pciephy_v2_regs_layout, 3197 3198 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3199 .phy_status = PHYSTATUS, 3200 }; 3201 3202 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 3203 .lanes = 1, 3204 3205 .offsets = &qmp_pcie_offsets_v4x1, 3206 3207 .tbls = { 3208 .serdes = ipq8074_pcie_gen3_serdes_tbl, 3209 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 3210 .tx = ipq8074_pcie_gen3_tx_tbl, 3211 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 3212 .rx = ipq8074_pcie_gen3_rx_tbl, 3213 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 3214 .pcs = ipq8074_pcie_gen3_pcs_tbl, 3215 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 3216 .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl, 3217 .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl), 3218 }, 3219 .reset_list = ipq8074_pciephy_reset_l, 3220 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3221 .vreg_list = NULL, 3222 .num_vregs = 0, 3223 .regs = pciephy_v4_regs_layout, 3224 3225 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3226 .phy_status = PHYSTATUS, 3227 3228 .pipe_clock_rate = 250000000, 3229 }; 3230 3231 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 3232 .lanes = 1, 3233 3234 .offsets = &qmp_pcie_offsets_v4x1, 3235 3236 .tbls = { 3237 .serdes = ipq6018_pcie_serdes_tbl, 3238 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 3239 .tx = ipq6018_pcie_tx_tbl, 3240 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 3241 .rx = ipq6018_pcie_rx_tbl, 3242 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 3243 .pcs = ipq6018_pcie_pcs_tbl, 3244 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 3245 .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 3246 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 3247 }, 3248 .reset_list = ipq8074_pciephy_reset_l, 3249 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3250 .vreg_list = NULL, 3251 .num_vregs = 0, 3252 .regs = pciephy_v4_regs_layout, 3253 3254 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3255 .phy_status = PHYSTATUS, 3256 }; 3257 3258 static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg = { 3259 .lanes = 1, 3260 3261 .offsets = &qmp_pcie_offsets_v4x1, 3262 3263 .tbls = { 3264 .serdes = ipq9574_gen3x1_pcie_serdes_tbl, 3265 .serdes_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl), 3266 .tx = ipq8074_pcie_gen3_tx_tbl, 3267 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 3268 .rx = ipq9574_pcie_rx_tbl, 3269 .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl), 3270 .pcs = ipq9574_gen3x1_pcie_pcs_tbl, 3271 .pcs_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl), 3272 .pcs_misc = ipq9574_gen3x1_pcie_pcs_misc_tbl, 3273 .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl), 3274 }, 3275 .reset_list = ipq8074_pciephy_reset_l, 3276 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3277 .vreg_list = NULL, 3278 .num_vregs = 0, 3279 .regs = pciephy_v4_regs_layout, 3280 3281 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3282 .phy_status = PHYSTATUS, 3283 .pipe_clock_rate = 250000000, 3284 }; 3285 3286 static const struct qmp_phy_cfg ipq9574_gen3x2_pciephy_cfg = { 3287 .lanes = 2, 3288 3289 .offsets = &qmp_pcie_offsets_ipq9574, 3290 3291 .tbls = { 3292 .serdes = ipq9574_gen3x2_pcie_serdes_tbl, 3293 .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl), 3294 .tx = ipq8074_pcie_gen3_tx_tbl, 3295 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 3296 .rx = ipq9574_pcie_rx_tbl, 3297 .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl), 3298 .pcs = ipq9574_gen3x2_pcie_pcs_tbl, 3299 .pcs_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_tbl), 3300 .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl, 3301 .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl), 3302 }, 3303 .reset_list = ipq8074_pciephy_reset_l, 3304 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3305 .vreg_list = NULL, 3306 .num_vregs = 0, 3307 .regs = pciephy_v5_regs_layout, 3308 3309 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3310 .phy_status = PHYSTATUS, 3311 .pipe_clock_rate = 250000000, 3312 }; 3313 3314 static const struct qmp_phy_cfg qcs615_pciephy_cfg = { 3315 .lanes = 1, 3316 3317 .offsets = &qmp_pcie_offsets_v2, 3318 3319 .tbls = { 3320 .serdes = qcs615_pcie_serdes_tbl, 3321 .serdes_num = ARRAY_SIZE(qcs615_pcie_serdes_tbl), 3322 .tx = qcs615_pcie_tx_tbl, 3323 .tx_num = ARRAY_SIZE(qcs615_pcie_tx_tbl), 3324 .rx = qcs615_pcie_rx_tbl, 3325 .rx_num = ARRAY_SIZE(qcs615_pcie_rx_tbl), 3326 .pcs = qcs615_pcie_pcs_tbl, 3327 .pcs_num = ARRAY_SIZE(qcs615_pcie_pcs_tbl), 3328 }, 3329 .reset_list = sdm845_pciephy_reset_l, 3330 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3331 .vreg_list = qmp_phy_vreg_l, 3332 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3333 .regs = pciephy_v2_regs_layout, 3334 3335 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3336 .phy_status = PHYSTATUS, 3337 }; 3338 3339 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 3340 .lanes = 1, 3341 3342 .offsets = &qmp_pcie_offsets_v3, 3343 3344 .tbls = { 3345 .serdes = sdm845_qmp_pcie_serdes_tbl, 3346 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 3347 .tx = sdm845_qmp_pcie_tx_tbl, 3348 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 3349 .rx = sdm845_qmp_pcie_rx_tbl, 3350 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 3351 .pcs = sdm845_qmp_pcie_pcs_tbl, 3352 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 3353 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 3354 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 3355 }, 3356 .reset_list = sdm845_pciephy_reset_l, 3357 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3358 .vreg_list = qmp_phy_vreg_l, 3359 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3360 .regs = pciephy_v3_regs_layout, 3361 3362 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3363 .phy_status = PHYSTATUS, 3364 }; 3365 3366 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 3367 .lanes = 1, 3368 3369 .offsets = &qmp_pcie_offsets_qhp, 3370 3371 .tbls = { 3372 .serdes = sdm845_qhp_pcie_serdes_tbl, 3373 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 3374 .tx = sdm845_qhp_pcie_tx_tbl, 3375 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 3376 .pcs = sdm845_qhp_pcie_pcs_tbl, 3377 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 3378 }, 3379 .reset_list = sdm845_pciephy_reset_l, 3380 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3381 .vreg_list = qmp_phy_vreg_l, 3382 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3383 .regs = sdm845_qhp_pciephy_regs_layout, 3384 3385 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3386 .phy_status = PHYSTATUS, 3387 }; 3388 3389 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 3390 .lanes = 1, 3391 3392 .offsets = &qmp_pcie_offsets_v4x1, 3393 3394 .tbls = { 3395 .serdes = sm8250_qmp_pcie_serdes_tbl, 3396 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 3397 .tx = sm8250_qmp_pcie_tx_tbl, 3398 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 3399 .rx = sm8250_qmp_pcie_rx_tbl, 3400 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 3401 .pcs = sm8250_qmp_pcie_pcs_tbl, 3402 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 3403 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 3404 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 3405 }, 3406 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3407 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 3408 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 3409 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 3410 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 3411 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 3412 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 3413 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 3414 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 3415 }, 3416 .reset_list = sdm845_pciephy_reset_l, 3417 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3418 .vreg_list = qmp_phy_vreg_l, 3419 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3420 .regs = pciephy_v4_regs_layout, 3421 3422 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3423 .phy_status = PHYSTATUS, 3424 }; 3425 3426 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 3427 .lanes = 2, 3428 3429 .offsets = &qmp_pcie_offsets_v4x2, 3430 3431 .tbls = { 3432 .serdes = sm8250_qmp_pcie_serdes_tbl, 3433 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 3434 .tx = sm8250_qmp_pcie_tx_tbl, 3435 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 3436 .rx = sm8250_qmp_pcie_rx_tbl, 3437 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 3438 .pcs = sm8250_qmp_pcie_pcs_tbl, 3439 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 3440 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 3441 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 3442 }, 3443 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3444 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 3445 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 3446 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 3447 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 3448 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 3449 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 3450 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 3451 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 3452 }, 3453 .reset_list = sdm845_pciephy_reset_l, 3454 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3455 .vreg_list = qmp_phy_vreg_l, 3456 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3457 .regs = pciephy_v4_regs_layout, 3458 3459 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3460 .phy_status = PHYSTATUS, 3461 }; 3462 3463 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 3464 .lanes = 1, 3465 3466 .offsets = &qmp_pcie_offsets_v3, 3467 3468 .tbls = { 3469 .serdes = msm8998_pcie_serdes_tbl, 3470 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 3471 .tx = msm8998_pcie_tx_tbl, 3472 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 3473 .rx = msm8998_pcie_rx_tbl, 3474 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 3475 .pcs = msm8998_pcie_pcs_tbl, 3476 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 3477 }, 3478 .reset_list = ipq8074_pciephy_reset_l, 3479 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3480 .vreg_list = qmp_phy_vreg_l, 3481 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3482 .regs = pciephy_v3_regs_layout, 3483 3484 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3485 .phy_status = PHYSTATUS, 3486 3487 .skip_start_delay = true, 3488 }; 3489 3490 static const struct qmp_phy_cfg sar2130p_qmp_gen3x2_pciephy_cfg = { 3491 .lanes = 2, 3492 3493 .offsets = &qmp_pcie_offsets_v5, 3494 3495 .tbls = { 3496 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, 3497 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), 3498 .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, 3499 .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), 3500 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, 3501 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), 3502 .pcs_lane1 = sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl, 3503 .pcs_lane1_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl), 3504 }, 3505 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3506 .serdes = sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl, 3507 .serdes_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl), 3508 .tx = sar2130p_qmp_gen3x2_pcie_rc_tx_tbl, 3509 .tx_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_tx_tbl), 3510 .pcs = sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl, 3511 .pcs_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl), 3512 .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, 3513 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), 3514 }, 3515 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 3516 .serdes = sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl, 3517 .serdes_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl), 3518 .pcs = sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl, 3519 .pcs_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl), 3520 .pcs_misc = sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl, 3521 .pcs_misc_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl), 3522 }, 3523 .reset_list = sdm845_pciephy_reset_l, 3524 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3525 .vreg_list = qmp_phy_vreg_l, 3526 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3527 .regs = pciephy_v5_regs_layout, 3528 3529 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3530 .phy_status = PHYSTATUS, 3531 }; 3532 3533 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 3534 .lanes = 2, 3535 3536 .offsets = &qmp_pcie_offsets_v4x2, 3537 3538 .tbls = { 3539 .serdes = sc8180x_qmp_pcie_serdes_tbl, 3540 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 3541 .tx = sc8180x_qmp_pcie_tx_tbl, 3542 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 3543 .rx = sc8180x_qmp_pcie_rx_tbl, 3544 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 3545 .pcs = sc8180x_qmp_pcie_pcs_tbl, 3546 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 3547 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 3548 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 3549 }, 3550 .reset_list = sdm845_pciephy_reset_l, 3551 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3552 .vreg_list = qmp_phy_vreg_l, 3553 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3554 .regs = pciephy_v4_regs_layout, 3555 3556 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3557 .phy_status = PHYSTATUS, 3558 }; 3559 3560 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { 3561 .lanes = 1, 3562 3563 .offsets = &qmp_pcie_offsets_v5, 3564 3565 .tbls = { 3566 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 3567 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 3568 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl, 3569 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl), 3570 .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl, 3571 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl), 3572 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl, 3573 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl), 3574 .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl, 3575 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl), 3576 }, 3577 3578 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3579 .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl, 3580 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl), 3581 }, 3582 3583 .reset_list = sdm845_pciephy_reset_l, 3584 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3585 .vreg_list = qmp_phy_vreg_l, 3586 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3587 .regs = pciephy_v5_regs_layout, 3588 3589 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3590 .phy_status = PHYSTATUS, 3591 }; 3592 3593 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { 3594 .lanes = 2, 3595 3596 .offsets = &qmp_pcie_offsets_v5, 3597 3598 .tbls = { 3599 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 3600 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 3601 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 3602 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 3603 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 3604 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 3605 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 3606 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 3607 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 3608 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 3609 }, 3610 3611 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3612 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 3613 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 3614 }, 3615 3616 .reset_list = sdm845_pciephy_reset_l, 3617 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3618 .vreg_list = qmp_phy_vreg_l, 3619 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3620 .regs = pciephy_v5_regs_layout, 3621 3622 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3623 .phy_status = PHYSTATUS, 3624 }; 3625 3626 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { 3627 .lanes = 4, 3628 3629 .offsets = &qmp_pcie_offsets_v5, 3630 3631 .tbls = { 3632 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 3633 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 3634 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 3635 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 3636 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 3637 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 3638 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 3639 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 3640 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 3641 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 3642 }, 3643 3644 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3645 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 3646 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 3647 }, 3648 3649 .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl, 3650 .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl), 3651 3652 .reset_list = sdm845_pciephy_reset_l, 3653 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3654 .vreg_list = qmp_phy_vreg_l, 3655 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3656 .regs = pciephy_v5_regs_layout, 3657 3658 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3659 .phy_status = PHYSTATUS, 3660 }; 3661 3662 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 3663 .lanes = 2, 3664 3665 .offsets = &qmp_pcie_offsets_v4_20, 3666 3667 .tbls = { 3668 .serdes = sdx55_qmp_pcie_serdes_tbl, 3669 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 3670 .tx = sdx55_qmp_pcie_tx_tbl, 3671 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 3672 .rx = sdx55_qmp_pcie_rx_tbl, 3673 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 3674 .pcs = sdx55_qmp_pcie_pcs_tbl, 3675 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 3676 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 3677 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 3678 }, 3679 3680 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3681 .serdes = sdx55_qmp_pcie_rc_serdes_tbl, 3682 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl), 3683 .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl, 3684 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl), 3685 }, 3686 3687 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 3688 .serdes = sdx55_qmp_pcie_ep_serdes_tbl, 3689 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), 3690 .pcs_lane1 = sdx55_qmp_pcie_ep_pcs_lane1_tbl, 3691 .pcs_lane1_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_lane1_tbl), 3692 }, 3693 3694 .reset_list = sdm845_pciephy_reset_l, 3695 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3696 .vreg_list = qmp_phy_vreg_l, 3697 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3698 .regs = pciephy_v4_regs_layout, 3699 3700 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3701 .phy_status = PHYSTATUS_4_20, 3702 }; 3703 3704 static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = { 3705 .lanes = 1, 3706 3707 .offsets = &qmp_pcie_offsets_v5, 3708 3709 .tbls = { 3710 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 3711 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 3712 .tx = sm8350_qmp_gen3x1_pcie_tx_tbl, 3713 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl), 3714 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 3715 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 3716 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 3717 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 3718 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 3719 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 3720 }, 3721 3722 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3723 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, 3724 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), 3725 .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl, 3726 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl), 3727 }, 3728 3729 .reset_list = sdm845_pciephy_reset_l, 3730 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3731 .vreg_list = qmp_phy_vreg_l, 3732 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3733 .regs = pciephy_v5_regs_layout, 3734 3735 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3736 .phy_status = PHYSTATUS, 3737 }; 3738 3739 static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = { 3740 .lanes = 2, 3741 3742 .offsets = &qmp_pcie_offsets_v5, 3743 3744 .tbls = { 3745 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 3746 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 3747 .tx = sm8350_qmp_gen3x2_pcie_tx_tbl, 3748 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl), 3749 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 3750 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 3751 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 3752 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 3753 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 3754 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 3755 }, 3756 3757 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3758 .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl, 3759 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl), 3760 .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl, 3761 .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl), 3762 }, 3763 3764 .reset_list = sdm845_pciephy_reset_l, 3765 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3766 .vreg_list = qmp_phy_vreg_l, 3767 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3768 .regs = pciephy_v5_regs_layout, 3769 3770 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3771 .phy_status = PHYSTATUS, 3772 }; 3773 3774 static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = { 3775 .lanes = 2, 3776 3777 .offsets = &qmp_pcie_offsets_v6_20, 3778 3779 .tbls = { 3780 .serdes = sdx65_qmp_pcie_serdes_tbl, 3781 .serdes_num = ARRAY_SIZE(sdx65_qmp_pcie_serdes_tbl), 3782 .tx = sdx65_qmp_pcie_tx_tbl, 3783 .tx_num = ARRAY_SIZE(sdx65_qmp_pcie_tx_tbl), 3784 .rx = sdx65_qmp_pcie_rx_tbl, 3785 .rx_num = ARRAY_SIZE(sdx65_qmp_pcie_rx_tbl), 3786 .pcs = sdx65_qmp_pcie_pcs_tbl, 3787 .pcs_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl), 3788 .pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl, 3789 .pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl), 3790 .pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl, 3791 .pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl), 3792 }, 3793 .reset_list = sdm845_pciephy_reset_l, 3794 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3795 .vreg_list = qmp_phy_vreg_l, 3796 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3797 .regs = pciephy_v6_regs_layout, 3798 3799 .pwrdn_ctrl = SW_PWRDN, 3800 .phy_status = PHYSTATUS_4_20, 3801 }; 3802 3803 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 3804 .lanes = 1, 3805 3806 .offsets = &qmp_pcie_offsets_v5, 3807 3808 .tbls = { 3809 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 3810 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 3811 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 3812 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 3813 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 3814 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 3815 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 3816 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 3817 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 3818 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 3819 }, 3820 3821 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3822 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, 3823 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), 3824 .rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl, 3825 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl), 3826 }, 3827 3828 .reset_list = sdm845_pciephy_reset_l, 3829 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3830 .vreg_list = qmp_phy_vreg_l, 3831 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3832 .regs = pciephy_v5_regs_layout, 3833 3834 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3835 .phy_status = PHYSTATUS, 3836 }; 3837 3838 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 3839 .lanes = 2, 3840 3841 .offsets = &qmp_pcie_offsets_v5_20, 3842 3843 .tbls = { 3844 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 3845 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 3846 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 3847 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 3848 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 3849 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 3850 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 3851 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 3852 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 3853 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 3854 }, 3855 3856 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3857 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, 3858 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), 3859 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, 3860 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), 3861 }, 3862 3863 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 3864 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, 3865 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), 3866 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 3867 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 3868 }, 3869 3870 .reset_list = sdm845_pciephy_reset_l, 3871 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3872 .vreg_list = qmp_phy_vreg_l, 3873 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3874 .regs = pciephy_v5_regs_layout, 3875 3876 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3877 .phy_status = PHYSTATUS_4_20, 3878 3879 /* 20MHz PHY AUX Clock */ 3880 .aux_clock_rate = 20000000, 3881 }; 3882 3883 static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = { 3884 .lanes = 2, 3885 3886 .offsets = &qmp_pcie_offsets_v5, 3887 3888 .tbls = { 3889 .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl, 3890 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), 3891 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, 3892 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), 3893 .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, 3894 .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), 3895 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, 3896 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), 3897 .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, 3898 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), 3899 }, 3900 .reset_list = sdm845_pciephy_reset_l, 3901 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3902 .vreg_list = qmp_phy_vreg_l, 3903 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3904 .regs = pciephy_v5_regs_layout, 3905 3906 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3907 .phy_status = PHYSTATUS, 3908 }; 3909 3910 static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { 3911 .lanes = 2, 3912 3913 .offsets = &qmp_pcie_offsets_v6_20, 3914 3915 .tbls = { 3916 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, 3917 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), 3918 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, 3919 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), 3920 .rx = sm8550_qmp_gen4x2_pcie_rx_tbl, 3921 .rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl), 3922 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, 3923 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), 3924 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, 3925 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), 3926 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, 3927 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), 3928 }, 3929 .reset_list = sdm845_pciephy_reset_l, 3930 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3931 .vreg_list = sm8550_qmp_phy_vreg_l, 3932 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 3933 .regs = pciephy_v6_regs_layout, 3934 3935 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3936 .phy_status = PHYSTATUS_4_20, 3937 .has_nocsr_reset = true, 3938 3939 /* 20MHz PHY AUX Clock */ 3940 .aux_clock_rate = 20000000, 3941 }; 3942 3943 static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = { 3944 .lanes = 2, 3945 3946 .offsets = &qmp_pcie_offsets_v6_20, 3947 3948 .tbls = { 3949 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, 3950 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), 3951 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, 3952 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), 3953 .rx = sm8650_qmp_gen4x2_pcie_rx_tbl, 3954 .rx_num = ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl), 3955 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, 3956 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), 3957 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, 3958 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), 3959 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, 3960 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), 3961 }, 3962 .reset_list = sdm845_pciephy_reset_l, 3963 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3964 .vreg_list = sm8550_qmp_phy_vreg_l, 3965 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 3966 .regs = pciephy_v6_regs_layout, 3967 3968 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3969 .phy_status = PHYSTATUS_4_20, 3970 .has_nocsr_reset = true, 3971 3972 /* 20MHz PHY AUX Clock */ 3973 .aux_clock_rate = 20000000, 3974 }; 3975 3976 static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = { 3977 .lanes = 2, 3978 .offsets = &qmp_pcie_offsets_v5_20, 3979 3980 .tbls = { 3981 .serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl, 3982 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl), 3983 .tx = sa8775p_qmp_gen4_pcie_tx_tbl, 3984 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl), 3985 .rx = sa8775p_qmp_gen4x2_pcie_rx_alt_tbl, 3986 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rx_alt_tbl), 3987 .pcs = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl, 3988 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl), 3989 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, 3990 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), 3991 .pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl, 3992 .pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl), 3993 }, 3994 3995 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3996 .serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl, 3997 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl), 3998 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl, 3999 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), 4000 }, 4001 4002 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 4003 .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl, 4004 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl), 4005 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 4006 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 4007 .pcs = sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl, 4008 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl), 4009 }, 4010 4011 .reset_list = sdm845_pciephy_reset_l, 4012 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4013 .vreg_list = qmp_phy_vreg_l, 4014 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4015 .regs = pciephy_v5_regs_layout, 4016 4017 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4018 .phy_status = PHYSTATUS_4_20, 4019 }; 4020 4021 static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = { 4022 .lanes = 4, 4023 .offsets = &qmp_pcie_offsets_v5_30, 4024 4025 .tbls = { 4026 .serdes = sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl, 4027 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl), 4028 .tx = sa8775p_qmp_gen4_pcie_tx_tbl, 4029 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl), 4030 .rx = sa8775p_qmp_gen4x4_pcie_rx_alt_tbl, 4031 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rx_alt_tbl), 4032 .pcs = sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl, 4033 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl), 4034 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, 4035 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), 4036 }, 4037 4038 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 4039 .serdes = sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl, 4040 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl), 4041 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl, 4042 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), 4043 }, 4044 4045 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 4046 .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl, 4047 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl), 4048 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 4049 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 4050 }, 4051 4052 .reset_list = sdm845_pciephy_reset_l, 4053 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4054 .vreg_list = qmp_phy_vreg_l, 4055 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4056 .regs = pciephy_v5_regs_layout, 4057 4058 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4059 .phy_status = PHYSTATUS_4_20, 4060 }; 4061 4062 static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { 4063 .lanes = 2, 4064 4065 .offsets = &qmp_pcie_offsets_v6_20, 4066 4067 .tbls = { 4068 .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl, 4069 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl), 4070 .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl, 4071 .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl), 4072 .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl, 4073 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl), 4074 .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl, 4075 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl), 4076 .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl, 4077 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl), 4078 .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl, 4079 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl), 4080 }, 4081 4082 .reset_list = sdm845_pciephy_reset_l, 4083 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4084 .vreg_list = qmp_phy_vreg_l, 4085 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4086 .regs = pciephy_v6_regs_layout, 4087 4088 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4089 .phy_status = PHYSTATUS_4_20, 4090 .has_nocsr_reset = true, 4091 }; 4092 4093 static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = { 4094 .lanes = 4, 4095 4096 .offsets = &qmp_pcie_offsets_v6_20, 4097 4098 .tbls = { 4099 .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl, 4100 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl), 4101 .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl, 4102 .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl), 4103 .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl, 4104 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl), 4105 .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl, 4106 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl), 4107 .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl, 4108 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl), 4109 .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl, 4110 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl), 4111 }, 4112 4113 .serdes_4ln_tbl = x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl, 4114 .serdes_4ln_num = ARRAY_SIZE(x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl), 4115 4116 .reset_list = sdm845_pciephy_reset_l, 4117 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4118 .vreg_list = qmp_phy_vreg_l, 4119 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4120 .regs = pciephy_v6_regs_layout, 4121 4122 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4123 .phy_status = PHYSTATUS_4_20, 4124 .has_nocsr_reset = true, 4125 }; 4126 4127 static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = { 4128 .lanes = 8, 4129 4130 .offsets = &qmp_pcie_offsets_v6_30, 4131 .tbls = { 4132 .serdes = x1e80100_qmp_gen4x8_pcie_serdes_tbl, 4133 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_serdes_tbl), 4134 .rx = x1e80100_qmp_gen4x8_pcie_rx_tbl, 4135 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rx_tbl), 4136 .txz = x1e80100_qmp_gen4x8_pcie_txz_tbl, 4137 .txz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_txz_tbl), 4138 .rxz = x1e80100_qmp_gen4x8_pcie_rxz_tbl, 4139 .rxz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rxz_tbl), 4140 .pcs = x1e80100_qmp_gen4x8_pcie_pcs_tbl, 4141 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_tbl), 4142 .pcs_misc = x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl, 4143 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl), 4144 .ln_shrd = x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl, 4145 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl), 4146 }, 4147 4148 .reset_list = sdm845_pciephy_reset_l, 4149 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4150 .vreg_list = sm8550_qmp_phy_vreg_l, 4151 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 4152 .regs = pciephy_v6_regs_layout, 4153 4154 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4155 .phy_status = PHYSTATUS_4_20, 4156 .has_nocsr_reset = true, 4157 }; 4158 4159 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 4160 { 4161 const struct qmp_phy_cfg *cfg = qmp->cfg; 4162 const struct qmp_pcie_offsets *offs = cfg->offsets; 4163 void __iomem *serdes, *tx3, *rx3, *tx4, *rx4, *pcs, *pcs_misc, *ln_shrd; 4164 4165 serdes = qmp->port_b + offs->serdes; 4166 tx3 = qmp->port_b + offs->tx; 4167 rx3 = qmp->port_b + offs->rx; 4168 tx4 = qmp->port_b + offs->tx2; 4169 rx4 = qmp->port_b + offs->rx2; 4170 pcs = qmp->port_b + offs->pcs; 4171 pcs_misc = qmp->port_b + offs->pcs_misc; 4172 ln_shrd = qmp->port_b + offs->ln_shrd; 4173 4174 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); 4175 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); 4176 4177 qmp_configure_lane(qmp->dev, tx3, tbls->tx, tbls->tx_num, 1); 4178 qmp_configure_lane(qmp->dev, rx3, tbls->rx, tbls->rx_num, 1); 4179 4180 qmp_configure_lane(qmp->dev, tx4, tbls->tx, tbls->tx_num, 2); 4181 qmp_configure_lane(qmp->dev, rx4, tbls->rx, tbls->rx_num, 2); 4182 4183 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); 4184 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 4185 4186 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); 4187 } 4188 4189 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 4190 { 4191 const struct qmp_phy_cfg *cfg = qmp->cfg; 4192 void __iomem *serdes = qmp->serdes; 4193 void __iomem *tx = qmp->tx; 4194 void __iomem *rx = qmp->rx; 4195 void __iomem *tx2 = qmp->tx2; 4196 void __iomem *rx2 = qmp->rx2; 4197 void __iomem *pcs = qmp->pcs; 4198 void __iomem *pcs_misc = qmp->pcs_misc; 4199 void __iomem *pcs_lane1 = qmp->pcs_lane1; 4200 void __iomem *ln_shrd = qmp->ln_shrd; 4201 4202 if (!tbls) 4203 return; 4204 4205 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); 4206 4207 /* 4208 * Tx/Rx registers that require different settings than 4209 * txz/rxz must be programmed after txz/rxz. 4210 */ 4211 qmp_configure(qmp->dev, qmp->txz, tbls->txz, tbls->txz_num); 4212 qmp_configure(qmp->dev, qmp->rxz, tbls->rxz, tbls->rxz_num); 4213 4214 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1); 4215 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1); 4216 4217 if (cfg->lanes >= 2) { 4218 qmp_configure_lane(qmp->dev, tx2, tbls->tx, tbls->tx_num, 2); 4219 qmp_configure_lane(qmp->dev, rx2, tbls->rx, tbls->rx_num, 2); 4220 } 4221 4222 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); 4223 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 4224 qmp_configure(qmp->dev, pcs_lane1, tbls->pcs_lane1, tbls->pcs_lane1_num); 4225 4226 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 4227 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, 4228 cfg->serdes_4ln_num); 4229 qmp_pcie_init_port_b(qmp, tbls); 4230 } 4231 4232 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); 4233 } 4234 4235 static int qmp_pcie_init(struct phy *phy) 4236 { 4237 struct qmp_pcie *qmp = phy_get_drvdata(phy); 4238 const struct qmp_phy_cfg *cfg = qmp->cfg; 4239 int ret; 4240 4241 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 4242 if (ret) { 4243 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 4244 return ret; 4245 } 4246 4247 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 4248 if (ret) { 4249 dev_err(qmp->dev, "reset assert failed\n"); 4250 goto err_disable_regulators; 4251 } 4252 4253 ret = reset_control_assert(qmp->nocsr_reset); 4254 if (ret) { 4255 dev_err(qmp->dev, "no-csr reset assert failed\n"); 4256 goto err_assert_reset; 4257 } 4258 4259 usleep_range(200, 300); 4260 4261 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 4262 if (ret) { 4263 dev_err(qmp->dev, "reset deassert failed\n"); 4264 goto err_assert_reset; 4265 } 4266 4267 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); 4268 if (ret) 4269 goto err_assert_reset; 4270 4271 return 0; 4272 4273 err_assert_reset: 4274 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 4275 err_disable_regulators: 4276 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 4277 4278 return ret; 4279 } 4280 4281 static int qmp_pcie_exit(struct phy *phy) 4282 { 4283 struct qmp_pcie *qmp = phy_get_drvdata(phy); 4284 const struct qmp_phy_cfg *cfg = qmp->cfg; 4285 4286 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 4287 4288 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); 4289 4290 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 4291 4292 return 0; 4293 } 4294 4295 static int qmp_pcie_power_on(struct phy *phy) 4296 { 4297 struct qmp_pcie *qmp = phy_get_drvdata(phy); 4298 const struct qmp_phy_cfg *cfg = qmp->cfg; 4299 const struct qmp_phy_cfg_tbls *mode_tbls; 4300 void __iomem *pcs = qmp->pcs; 4301 void __iomem *status; 4302 unsigned int mask, val; 4303 int ret; 4304 4305 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 4306 cfg->pwrdn_ctrl); 4307 4308 if (qmp->mode == PHY_MODE_PCIE_RC) 4309 mode_tbls = cfg->tbls_rc; 4310 else 4311 mode_tbls = cfg->tbls_ep; 4312 4313 qmp_pcie_init_registers(qmp, &cfg->tbls); 4314 qmp_pcie_init_registers(qmp, mode_tbls); 4315 4316 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); 4317 if (ret) 4318 return ret; 4319 4320 ret = reset_control_deassert(qmp->nocsr_reset); 4321 if (ret) { 4322 dev_err(qmp->dev, "no-csr reset deassert failed\n"); 4323 goto err_disable_pipe_clk; 4324 } 4325 4326 /* Pull PHY out of reset state */ 4327 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 4328 4329 /* start SerDes and Phy-Coding-Sublayer */ 4330 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 4331 4332 if (!cfg->skip_start_delay) 4333 usleep_range(1000, 1200); 4334 4335 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 4336 mask = cfg->phy_status; 4337 ret = readl_poll_timeout(status, val, !(val & mask), 200, 4338 PHY_INIT_COMPLETE_TIMEOUT); 4339 if (ret) { 4340 dev_err(qmp->dev, "phy initialization timed-out\n"); 4341 goto err_disable_pipe_clk; 4342 } 4343 4344 return 0; 4345 4346 err_disable_pipe_clk: 4347 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 4348 4349 return ret; 4350 } 4351 4352 static int qmp_pcie_power_off(struct phy *phy) 4353 { 4354 struct qmp_pcie *qmp = phy_get_drvdata(phy); 4355 const struct qmp_phy_cfg *cfg = qmp->cfg; 4356 4357 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 4358 4359 /* PHY reset */ 4360 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 4361 4362 /* stop SerDes and Phy-Coding-Sublayer */ 4363 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 4364 SERDES_START | PCS_START); 4365 4366 /* Put PHY into POWER DOWN state: active low */ 4367 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 4368 cfg->pwrdn_ctrl); 4369 4370 return 0; 4371 } 4372 4373 static int qmp_pcie_enable(struct phy *phy) 4374 { 4375 int ret; 4376 4377 ret = qmp_pcie_init(phy); 4378 if (ret) 4379 return ret; 4380 4381 ret = qmp_pcie_power_on(phy); 4382 if (ret) 4383 qmp_pcie_exit(phy); 4384 4385 return ret; 4386 } 4387 4388 static int qmp_pcie_disable(struct phy *phy) 4389 { 4390 int ret; 4391 4392 ret = qmp_pcie_power_off(phy); 4393 if (ret) 4394 return ret; 4395 4396 return qmp_pcie_exit(phy); 4397 } 4398 4399 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 4400 { 4401 struct qmp_pcie *qmp = phy_get_drvdata(phy); 4402 4403 switch (submode) { 4404 case PHY_MODE_PCIE_RC: 4405 case PHY_MODE_PCIE_EP: 4406 qmp->mode = submode; 4407 break; 4408 default: 4409 dev_err(&phy->dev, "Unsupported submode %d\n", submode); 4410 return -EINVAL; 4411 } 4412 4413 return 0; 4414 } 4415 4416 static const struct phy_ops qmp_pcie_phy_ops = { 4417 .power_on = qmp_pcie_enable, 4418 .power_off = qmp_pcie_disable, 4419 .set_mode = qmp_pcie_set_mode, 4420 .owner = THIS_MODULE, 4421 }; 4422 4423 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) 4424 { 4425 const struct qmp_phy_cfg *cfg = qmp->cfg; 4426 struct device *dev = qmp->dev; 4427 int num = cfg->num_vregs; 4428 int i; 4429 4430 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 4431 if (!qmp->vregs) 4432 return -ENOMEM; 4433 4434 for (i = 0; i < num; i++) 4435 qmp->vregs[i].supply = cfg->vreg_list[i]; 4436 4437 return devm_regulator_bulk_get(dev, num, qmp->vregs); 4438 } 4439 4440 static int qmp_pcie_reset_init(struct qmp_pcie *qmp) 4441 { 4442 const struct qmp_phy_cfg *cfg = qmp->cfg; 4443 struct device *dev = qmp->dev; 4444 int i; 4445 int ret; 4446 4447 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 4448 sizeof(*qmp->resets), GFP_KERNEL); 4449 if (!qmp->resets) 4450 return -ENOMEM; 4451 4452 for (i = 0; i < cfg->num_resets; i++) 4453 qmp->resets[i].id = cfg->reset_list[i]; 4454 4455 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 4456 if (ret) 4457 return dev_err_probe(dev, ret, "failed to get resets\n"); 4458 4459 if (cfg->has_nocsr_reset) { 4460 qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr"); 4461 if (IS_ERR(qmp->nocsr_reset)) 4462 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), 4463 "failed to get no-csr reset\n"); 4464 } 4465 4466 return 0; 4467 } 4468 4469 static int qmp_pcie_clk_init(struct qmp_pcie *qmp) 4470 { 4471 struct device *dev = qmp->dev; 4472 int num = ARRAY_SIZE(qmp_pciephy_clk_l); 4473 int i; 4474 4475 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 4476 if (!qmp->clks) 4477 return -ENOMEM; 4478 4479 for (i = 0; i < num; i++) 4480 qmp->clks[i].id = qmp_pciephy_clk_l[i]; 4481 4482 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 4483 } 4484 4485 static void phy_clk_release_provider(void *res) 4486 { 4487 of_clk_del_provider(res); 4488 } 4489 4490 /* 4491 * Register a fixed rate pipe clock. 4492 * 4493 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 4494 * controls it. The <s>_pipe_clk coming out of the GCC is requested 4495 * by the PHY driver for its operations. 4496 * We register the <s>_pipe_clksrc here. The gcc driver takes care 4497 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 4498 * Below picture shows this relationship. 4499 * 4500 * +---------------+ 4501 * | PHY block |<<---------------------------------------+ 4502 * | | | 4503 * | +-------+ | +-----+ | 4504 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 4505 * clk | +-------+ | +-----+ 4506 * +---------------+ 4507 */ 4508 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) 4509 { 4510 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 4511 struct clk_init_data init = { }; 4512 int ret; 4513 4514 ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name); 4515 if (ret) { 4516 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 4517 return ret; 4518 } 4519 4520 init.ops = &clk_fixed_rate_ops; 4521 4522 /* 4523 * Controllers using QMP PHY-s use 125MHz pipe clock interface 4524 * unless other frequency is specified in the PHY config. 4525 */ 4526 if (qmp->cfg->pipe_clock_rate) 4527 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; 4528 else 4529 fixed->fixed_rate = 125000000; 4530 4531 fixed->hw.init = &init; 4532 4533 return devm_clk_hw_register(qmp->dev, &fixed->hw); 4534 } 4535 4536 /* 4537 * Register a fixed rate PHY aux clock. 4538 * 4539 * The <s>_phy_aux_clksrc generated by PHY goes to the GCC that gate 4540 * controls it. The <s>_phy_aux_clk coming out of the GCC is requested 4541 * by the PHY driver for its operations. 4542 * We register the <s>_phy_aux_clksrc here. The gcc driver takes care 4543 * of assigning this <s>_phy_aux_clksrc as parent to <s>_phy_aux_clk. 4544 * Below picture shows this relationship. 4545 * 4546 * +---------------+ 4547 * | PHY block |<<---------------------------------------------+ 4548 * | | | 4549 * | +-------+ | +-----+ | 4550 * I/P---^-->| PLL |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+ 4551 * clk | +-------+ | +-----+ 4552 * +---------------+ 4553 */ 4554 static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np) 4555 { 4556 struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed; 4557 struct clk_init_data init = { }; 4558 char name[64]; 4559 4560 snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev)); 4561 4562 init.name = name; 4563 init.ops = &clk_fixed_rate_ops; 4564 4565 fixed->fixed_rate = qmp->cfg->aux_clock_rate; 4566 fixed->hw.init = &init; 4567 4568 return devm_clk_hw_register(qmp->dev, &fixed->hw); 4569 } 4570 4571 static struct clk_hw *qmp_pcie_clk_hw_get(struct of_phandle_args *clkspec, void *data) 4572 { 4573 struct qmp_pcie *qmp = data; 4574 4575 /* Support legacy bindings */ 4576 if (!clkspec->args_count) 4577 return &qmp->pipe_clk_fixed.hw; 4578 4579 switch (clkspec->args[0]) { 4580 case QMP_PCIE_PIPE_CLK: 4581 return &qmp->pipe_clk_fixed.hw; 4582 case QMP_PCIE_PHY_AUX_CLK: 4583 return &qmp->aux_clk_fixed.hw; 4584 } 4585 4586 return ERR_PTR(-EINVAL); 4587 } 4588 4589 static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np) 4590 { 4591 int ret; 4592 4593 ret = phy_pipe_clk_register(qmp, np); 4594 if (ret) 4595 return ret; 4596 4597 if (qmp->cfg->aux_clock_rate) { 4598 ret = phy_aux_clk_register(qmp, np); 4599 if (ret) 4600 return ret; 4601 4602 ret = of_clk_add_hw_provider(np, qmp_pcie_clk_hw_get, qmp); 4603 if (ret) 4604 return ret; 4605 } else { 4606 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw); 4607 if (ret) 4608 return ret; 4609 } 4610 4611 /* 4612 * Roll a devm action because the clock provider is the child node, but 4613 * the child node is not actually a device. 4614 */ 4615 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 4616 } 4617 4618 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np) 4619 { 4620 struct platform_device *pdev = to_platform_device(qmp->dev); 4621 const struct qmp_phy_cfg *cfg = qmp->cfg; 4622 struct device *dev = qmp->dev; 4623 struct clk *clk; 4624 4625 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 4626 if (IS_ERR(qmp->serdes)) 4627 return PTR_ERR(qmp->serdes); 4628 4629 /* 4630 * Get memory resources for the PHY: 4631 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 4632 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 4633 * For single lane PHYs: pcs_misc (optional) -> 3. 4634 */ 4635 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 4636 if (IS_ERR(qmp->tx)) 4637 return PTR_ERR(qmp->tx); 4638 4639 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 4640 qmp->rx = qmp->tx; 4641 else 4642 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 4643 if (IS_ERR(qmp->rx)) 4644 return PTR_ERR(qmp->rx); 4645 4646 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 4647 if (IS_ERR(qmp->pcs)) 4648 return PTR_ERR(qmp->pcs); 4649 4650 if (cfg->lanes >= 2) { 4651 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 4652 if (IS_ERR(qmp->tx2)) 4653 return PTR_ERR(qmp->tx2); 4654 4655 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 4656 if (IS_ERR(qmp->rx2)) 4657 return PTR_ERR(qmp->rx2); 4658 4659 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 4660 } else { 4661 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 4662 } 4663 4664 if (IS_ERR(qmp->pcs_misc) && 4665 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 4666 qmp->pcs_misc = qmp->pcs + 0x400; 4667 4668 if (IS_ERR(qmp->pcs_misc)) { 4669 if (cfg->tbls.pcs_misc || 4670 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || 4671 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { 4672 return PTR_ERR(qmp->pcs_misc); 4673 } 4674 } 4675 4676 /* 4677 * For all platforms where legacy bindings existed, PCS_LANE1 was 4678 * mapped as a part of the PCS_MISC region. 4679 */ 4680 if (!IS_ERR(qmp->pcs_misc) && cfg->offsets->pcs_lane1 != 0) 4681 qmp->pcs_lane1 = qmp->pcs_misc + 4682 (cfg->offsets->pcs_lane1 - cfg->offsets->pcs_misc); 4683 4684 clk = devm_get_clk_from_child(dev, np, NULL); 4685 if (IS_ERR(clk)) { 4686 return dev_err_probe(dev, PTR_ERR(clk), 4687 "failed to get pipe clock\n"); 4688 } 4689 4690 qmp->num_pipe_clks = 1; 4691 qmp->pipe_clks[0].id = "pipe"; 4692 qmp->pipe_clks[0].clk = clk; 4693 4694 return 0; 4695 } 4696 4697 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp) 4698 { 4699 struct regmap *tcsr; 4700 unsigned int args[2]; 4701 int ret; 4702 4703 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, 4704 "qcom,4ln-config-sel", 4705 ARRAY_SIZE(args), args); 4706 if (IS_ERR(tcsr)) { 4707 ret = PTR_ERR(tcsr); 4708 if (ret == -ENOENT) 4709 return 0; 4710 4711 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); 4712 return ret; 4713 } 4714 4715 ret = regmap_test_bits(tcsr, args[0], BIT(args[1])); 4716 if (ret < 0) { 4717 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); 4718 return ret; 4719 } 4720 4721 qmp->tcsr_4ln_config = ret; 4722 4723 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); 4724 4725 return 0; 4726 } 4727 4728 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) 4729 { 4730 struct platform_device *pdev = to_platform_device(qmp->dev); 4731 const struct qmp_phy_cfg *cfg = qmp->cfg; 4732 const struct qmp_pcie_offsets *offs = cfg->offsets; 4733 struct device *dev = qmp->dev; 4734 void __iomem *base; 4735 int ret; 4736 4737 if (!offs) 4738 return -EINVAL; 4739 4740 ret = qmp_pcie_get_4ln_config(qmp); 4741 if (ret) 4742 return ret; 4743 4744 base = devm_platform_ioremap_resource(pdev, 0); 4745 if (IS_ERR(base)) 4746 return PTR_ERR(base); 4747 4748 qmp->serdes = base + offs->serdes; 4749 qmp->pcs = base + offs->pcs; 4750 qmp->pcs_misc = base + offs->pcs_misc; 4751 qmp->pcs_lane1 = base + offs->pcs_lane1; 4752 qmp->tx = base + offs->tx; 4753 qmp->rx = base + offs->rx; 4754 4755 if (cfg->lanes >= 2) { 4756 qmp->tx2 = base + offs->tx2; 4757 qmp->rx2 = base + offs->rx2; 4758 } 4759 4760 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 4761 qmp->port_b = devm_platform_ioremap_resource(pdev, 1); 4762 if (IS_ERR(qmp->port_b)) 4763 return PTR_ERR(qmp->port_b); 4764 } 4765 4766 qmp->txz = base + offs->txz; 4767 qmp->rxz = base + offs->rxz; 4768 4769 if (cfg->tbls.ln_shrd) 4770 qmp->ln_shrd = base + offs->ln_shrd; 4771 4772 qmp->num_pipe_clks = 2; 4773 qmp->pipe_clks[0].id = "pipe"; 4774 qmp->pipe_clks[1].id = "pipediv2"; 4775 4776 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks); 4777 if (ret) 4778 return ret; 4779 4780 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1); 4781 if (ret) 4782 return ret; 4783 4784 return 0; 4785 } 4786 4787 static int qmp_pcie_probe(struct platform_device *pdev) 4788 { 4789 struct device *dev = &pdev->dev; 4790 struct phy_provider *phy_provider; 4791 struct device_node *np; 4792 struct qmp_pcie *qmp; 4793 int ret; 4794 4795 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 4796 if (!qmp) 4797 return -ENOMEM; 4798 4799 qmp->dev = dev; 4800 4801 qmp->cfg = of_device_get_match_data(dev); 4802 if (!qmp->cfg) 4803 return -EINVAL; 4804 4805 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); 4806 WARN_ON_ONCE(!qmp->cfg->phy_status); 4807 4808 ret = qmp_pcie_clk_init(qmp); 4809 if (ret) 4810 return ret; 4811 4812 ret = qmp_pcie_reset_init(qmp); 4813 if (ret) 4814 return ret; 4815 4816 ret = qmp_pcie_vreg_init(qmp); 4817 if (ret) 4818 return ret; 4819 4820 /* Check for legacy binding with child node. */ 4821 np = of_get_next_available_child(dev->of_node, NULL); 4822 if (np) { 4823 ret = qmp_pcie_parse_dt_legacy(qmp, np); 4824 } else { 4825 np = of_node_get(dev->of_node); 4826 ret = qmp_pcie_parse_dt(qmp); 4827 } 4828 if (ret) 4829 goto err_node_put; 4830 4831 ret = qmp_pcie_register_clocks(qmp, np); 4832 if (ret) 4833 goto err_node_put; 4834 4835 qmp->mode = PHY_MODE_PCIE_RC; 4836 4837 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); 4838 if (IS_ERR(qmp->phy)) { 4839 ret = PTR_ERR(qmp->phy); 4840 dev_err(dev, "failed to create PHY: %d\n", ret); 4841 goto err_node_put; 4842 } 4843 4844 phy_set_drvdata(qmp->phy, qmp); 4845 4846 of_node_put(np); 4847 4848 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 4849 4850 return PTR_ERR_OR_ZERO(phy_provider); 4851 4852 err_node_put: 4853 of_node_put(np); 4854 return ret; 4855 } 4856 4857 static const struct of_device_id qmp_pcie_of_match_table[] = { 4858 { 4859 .compatible = "qcom,ipq6018-qmp-pcie-phy", 4860 .data = &ipq6018_pciephy_cfg, 4861 }, { 4862 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 4863 .data = &ipq8074_pciephy_gen3_cfg, 4864 }, { 4865 .compatible = "qcom,ipq8074-qmp-pcie-phy", 4866 .data = &ipq8074_pciephy_cfg, 4867 }, { 4868 .compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy", 4869 .data = &ipq9574_gen3x1_pciephy_cfg, 4870 }, { 4871 .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy", 4872 .data = &ipq9574_gen3x2_pciephy_cfg, 4873 }, { 4874 .compatible = "qcom,msm8998-qmp-pcie-phy", 4875 .data = &msm8998_pciephy_cfg, 4876 }, { 4877 .compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy", 4878 .data = &qcs615_pciephy_cfg, 4879 }, { 4880 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy", 4881 .data = &sa8775p_qmp_gen4x2_pciephy_cfg, 4882 }, { 4883 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy", 4884 .data = &sa8775p_qmp_gen4x4_pciephy_cfg, 4885 }, { 4886 .compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy", 4887 .data = &sar2130p_qmp_gen3x2_pciephy_cfg, 4888 }, { 4889 .compatible = "qcom,sc8180x-qmp-pcie-phy", 4890 .data = &sc8180x_pciephy_cfg, 4891 }, { 4892 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy", 4893 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg, 4894 }, { 4895 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy", 4896 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg, 4897 }, { 4898 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy", 4899 .data = &sc8280xp_qmp_gen3x4_pciephy_cfg, 4900 }, { 4901 .compatible = "qcom,sdm845-qhp-pcie-phy", 4902 .data = &sdm845_qhp_pciephy_cfg, 4903 }, { 4904 .compatible = "qcom,sdm845-qmp-pcie-phy", 4905 .data = &sdm845_qmp_pciephy_cfg, 4906 }, { 4907 .compatible = "qcom,sdx55-qmp-pcie-phy", 4908 .data = &sdx55_qmp_pciephy_cfg, 4909 }, { 4910 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy", 4911 .data = &sdx65_qmp_pciephy_cfg, 4912 }, { 4913 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy", 4914 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 4915 }, { 4916 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy", 4917 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 4918 }, { 4919 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 4920 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 4921 }, { 4922 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 4923 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 4924 }, { 4925 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 4926 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 4927 }, { 4928 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy", 4929 .data = &sm8350_qmp_gen3x1_pciephy_cfg, 4930 }, { 4931 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy", 4932 .data = &sm8350_qmp_gen3x2_pciephy_cfg, 4933 }, { 4934 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 4935 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 4936 }, { 4937 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 4938 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 4939 }, { 4940 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy", 4941 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 4942 }, { 4943 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy", 4944 .data = &sm8550_qmp_gen4x2_pciephy_cfg, 4945 }, { 4946 .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy", 4947 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 4948 }, { 4949 .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy", 4950 .data = &sm8650_qmp_gen4x2_pciephy_cfg, 4951 }, { 4952 .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy", 4953 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 4954 }, { 4955 .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy", 4956 .data = &x1e80100_qmp_gen4x2_pciephy_cfg, 4957 }, { 4958 .compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy", 4959 .data = &x1e80100_qmp_gen4x4_pciephy_cfg, 4960 }, { 4961 .compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy", 4962 .data = &x1e80100_qmp_gen4x8_pciephy_cfg, 4963 }, 4964 { }, 4965 }; 4966 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 4967 4968 static struct platform_driver qmp_pcie_driver = { 4969 .probe = qmp_pcie_probe, 4970 .driver = { 4971 .name = "qcom-qmp-pcie-phy", 4972 .of_match_table = qmp_pcie_of_match_table, 4973 }, 4974 }; 4975 4976 module_platform_driver(qmp_pcie_driver); 4977 4978 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 4979 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 4980 MODULE_LICENSE("GPL v2"); 4981