1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * pci-j721e - PCIe controller driver for TI's J721E SoCs 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/container_of.h> 12 #include <linux/delay.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/io.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/pci.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regmap.h> 24 25 #include "../../pci.h" 26 #include "pcie-cadence.h" 27 28 #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie) 29 30 #define ENABLE_REG_SYS_2 0x108 31 #define ENABLE_CLR_REG_SYS_2 0x308 32 #define STATUS_REG_SYS_2 0x508 33 #define STATUS_CLR_REG_SYS_2 0x708 34 #define LINK_DOWN BIT(1) 35 #define J7200_LINK_DOWN BIT(10) 36 37 #define J721E_PCIE_USER_CMD_STATUS 0x4 38 #define LINK_TRAINING_ENABLE BIT(0) 39 40 #define J721E_PCIE_USER_LINKSTATUS 0x14 41 #define LINK_STATUS GENMASK(1, 0) 42 43 enum link_status { 44 NO_RECEIVERS_DETECTED, 45 LINK_TRAINING_IN_PROGRESS, 46 LINK_UP_DL_IN_PROGRESS, 47 LINK_UP_DL_COMPLETED, 48 }; 49 50 #define J721E_MODE_RC BIT(7) 51 #define LANE_COUNT(n) ((n) << 8) 52 53 #define ACSPCIE_PAD_DISABLE_MASK GENMASK(1, 0) 54 #define GENERATION_SEL_MASK GENMASK(1, 0) 55 56 struct j721e_pcie { 57 struct cdns_pcie *cdns_pcie; 58 struct clk *refclk; 59 u32 mode; 60 u32 num_lanes; 61 u32 max_lanes; 62 struct gpio_desc *reset_gpio; 63 void __iomem *user_cfg_base; 64 void __iomem *intd_cfg_base; 65 u32 linkdown_irq_regfield; 66 }; 67 68 enum j721e_pcie_mode { 69 PCI_MODE_RC, 70 PCI_MODE_EP, 71 }; 72 73 struct j721e_pcie_data { 74 enum j721e_pcie_mode mode; 75 unsigned int quirk_retrain_flag:1; 76 unsigned int quirk_detect_quiet_flag:1; 77 unsigned int quirk_disable_flr:1; 78 u32 linkdown_irq_regfield; 79 unsigned int byte_access_allowed:1; 80 unsigned int max_lanes; 81 }; 82 83 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) 84 { 85 return readl(pcie->user_cfg_base + offset); 86 } 87 88 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, 89 u32 value) 90 { 91 writel(value, pcie->user_cfg_base + offset); 92 } 93 94 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) 95 { 96 return readl(pcie->intd_cfg_base + offset); 97 } 98 99 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, 100 u32 value) 101 { 102 writel(value, pcie->intd_cfg_base + offset); 103 } 104 105 static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv) 106 { 107 struct j721e_pcie *pcie = priv; 108 struct device *dev = pcie->cdns_pcie->dev; 109 u32 reg; 110 111 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2); 112 if (!(reg & pcie->linkdown_irq_regfield)) 113 return IRQ_NONE; 114 115 dev_err(dev, "LINK DOWN!\n"); 116 117 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield); 118 return IRQ_HANDLED; 119 } 120 121 static void j721e_pcie_disable_link_irq(struct j721e_pcie *pcie) 122 { 123 u32 reg; 124 125 reg = j721e_pcie_intd_readl(pcie, ENABLE_CLR_REG_SYS_2); 126 reg |= pcie->linkdown_irq_regfield; 127 j721e_pcie_intd_writel(pcie, ENABLE_CLR_REG_SYS_2, reg); 128 } 129 130 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie) 131 { 132 u32 reg; 133 134 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2); 135 reg |= pcie->linkdown_irq_regfield; 136 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg); 137 } 138 139 static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie) 140 { 141 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 142 u32 reg; 143 144 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); 145 reg |= LINK_TRAINING_ENABLE; 146 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); 147 148 return 0; 149 } 150 151 static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie) 152 { 153 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 154 u32 reg; 155 156 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); 157 reg &= ~LINK_TRAINING_ENABLE; 158 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); 159 } 160 161 static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie) 162 { 163 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 164 u32 reg; 165 166 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS); 167 return (reg & LINK_STATUS) == LINK_UP_DL_COMPLETED; 168 } 169 170 static const struct cdns_pcie_ops j721e_pcie_ops = { 171 .start_link = j721e_pcie_start_link, 172 .stop_link = j721e_pcie_stop_link, 173 .link_up = j721e_pcie_link_up, 174 }; 175 176 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon, 177 unsigned int offset) 178 { 179 struct device *dev = pcie->cdns_pcie->dev; 180 u32 mask = J721E_MODE_RC; 181 u32 mode = pcie->mode; 182 u32 val = 0; 183 int ret = 0; 184 185 if (mode == PCI_MODE_RC) 186 val = J721E_MODE_RC; 187 188 ret = regmap_update_bits(syscon, offset, mask, val); 189 if (ret) 190 dev_err(dev, "failed to set pcie mode\n"); 191 192 return ret; 193 } 194 195 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, 196 struct regmap *syscon, unsigned int offset) 197 { 198 struct device *dev = pcie->cdns_pcie->dev; 199 struct device_node *np = dev->of_node; 200 int link_speed; 201 u32 val = 0; 202 int ret; 203 204 link_speed = of_pci_get_max_link_speed(np); 205 if (link_speed < 2) 206 link_speed = 2; 207 208 val = link_speed - 1; 209 ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val); 210 if (ret) 211 dev_err(dev, "failed to set link speed\n"); 212 213 return ret; 214 } 215 216 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, 217 struct regmap *syscon, unsigned int offset) 218 { 219 struct device *dev = pcie->cdns_pcie->dev; 220 u32 lanes = pcie->num_lanes; 221 u32 mask = BIT(8); 222 u32 val = 0; 223 int ret; 224 225 if (pcie->max_lanes == 4) 226 mask = GENMASK(9, 8); 227 228 val = LANE_COUNT(lanes - 1); 229 ret = regmap_update_bits(syscon, offset, mask, val); 230 if (ret) 231 dev_err(dev, "failed to set link count\n"); 232 233 return ret; 234 } 235 236 static int j721e_enable_acspcie_refclk(struct j721e_pcie *pcie, 237 struct regmap *syscon) 238 { 239 struct device *dev = pcie->cdns_pcie->dev; 240 struct device_node *node = dev->of_node; 241 u32 mask = ACSPCIE_PAD_DISABLE_MASK; 242 struct of_phandle_args args; 243 u32 val; 244 int ret; 245 246 ret = of_parse_phandle_with_fixed_args(node, 247 "ti,syscon-acspcie-proxy-ctrl", 248 1, 0, &args); 249 if (ret) { 250 dev_err(dev, 251 "ti,syscon-acspcie-proxy-ctrl has invalid arguments\n"); 252 return ret; 253 } 254 255 /* Clear PAD IO disable bits to enable refclk output */ 256 val = ~(args.args[0]); 257 ret = regmap_update_bits(syscon, 0, mask, val); 258 if (ret) { 259 dev_err(dev, "failed to enable ACSPCIE refclk: %d\n", ret); 260 return ret; 261 } 262 263 return 0; 264 } 265 266 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) 267 { 268 struct device *dev = pcie->cdns_pcie->dev; 269 struct device_node *node = dev->of_node; 270 struct of_phandle_args args; 271 unsigned int offset = 0; 272 struct regmap *syscon; 273 int ret; 274 275 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl"); 276 if (IS_ERR(syscon)) { 277 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n"); 278 return PTR_ERR(syscon); 279 } 280 281 /* Do not error out to maintain old DT compatibility */ 282 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1, 283 0, &args); 284 if (!ret) 285 offset = args.args[0]; 286 287 ret = j721e_pcie_set_mode(pcie, syscon, offset); 288 if (ret < 0) { 289 dev_err(dev, "Failed to set pci mode\n"); 290 return ret; 291 } 292 293 ret = j721e_pcie_set_link_speed(pcie, syscon, offset); 294 if (ret < 0) { 295 dev_err(dev, "Failed to set link speed\n"); 296 return ret; 297 } 298 299 ret = j721e_pcie_set_lane_count(pcie, syscon, offset); 300 if (ret < 0) { 301 dev_err(dev, "Failed to set num-lanes\n"); 302 return ret; 303 } 304 305 /* Enable ACSPCIE refclk output if the optional property exists */ 306 syscon = syscon_regmap_lookup_by_phandle_optional(node, 307 "ti,syscon-acspcie-proxy-ctrl"); 308 if (!syscon) 309 return 0; 310 311 return j721e_enable_acspcie_refclk(pcie, syscon); 312 } 313 314 static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 315 int where, int size, u32 *value) 316 { 317 if (pci_is_root_bus(bus)) 318 return pci_generic_config_read32(bus, devfn, where, size, 319 value); 320 321 return pci_generic_config_read(bus, devfn, where, size, value); 322 } 323 324 static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn, 325 int where, int size, u32 value) 326 { 327 if (pci_is_root_bus(bus)) 328 return pci_generic_config_write32(bus, devfn, where, size, 329 value); 330 331 return pci_generic_config_write(bus, devfn, where, size, value); 332 } 333 334 static struct pci_ops cdns_ti_pcie_host_ops = { 335 .map_bus = cdns_pci_map_bus, 336 .read = cdns_ti_pcie_config_read, 337 .write = cdns_ti_pcie_config_write, 338 }; 339 340 static const struct j721e_pcie_data j721e_pcie_rc_data = { 341 .mode = PCI_MODE_RC, 342 .quirk_retrain_flag = true, 343 .byte_access_allowed = false, 344 .linkdown_irq_regfield = LINK_DOWN, 345 .max_lanes = 2, 346 }; 347 348 static const struct j721e_pcie_data j721e_pcie_ep_data = { 349 .mode = PCI_MODE_EP, 350 .linkdown_irq_regfield = LINK_DOWN, 351 .max_lanes = 2, 352 }; 353 354 static const struct j721e_pcie_data j7200_pcie_rc_data = { 355 .mode = PCI_MODE_RC, 356 .quirk_detect_quiet_flag = true, 357 .linkdown_irq_regfield = J7200_LINK_DOWN, 358 .byte_access_allowed = true, 359 .max_lanes = 2, 360 }; 361 362 static const struct j721e_pcie_data j7200_pcie_ep_data = { 363 .mode = PCI_MODE_EP, 364 .quirk_detect_quiet_flag = true, 365 .linkdown_irq_regfield = J7200_LINK_DOWN, 366 .quirk_disable_flr = true, 367 .max_lanes = 2, 368 }; 369 370 static const struct j721e_pcie_data am64_pcie_rc_data = { 371 .mode = PCI_MODE_RC, 372 .linkdown_irq_regfield = J7200_LINK_DOWN, 373 .byte_access_allowed = true, 374 .max_lanes = 1, 375 }; 376 377 static const struct j721e_pcie_data am64_pcie_ep_data = { 378 .mode = PCI_MODE_EP, 379 .linkdown_irq_regfield = J7200_LINK_DOWN, 380 .max_lanes = 1, 381 }; 382 383 static const struct j721e_pcie_data j784s4_pcie_rc_data = { 384 .mode = PCI_MODE_RC, 385 .quirk_retrain_flag = true, 386 .byte_access_allowed = false, 387 .linkdown_irq_regfield = J7200_LINK_DOWN, 388 .max_lanes = 4, 389 }; 390 391 static const struct j721e_pcie_data j784s4_pcie_ep_data = { 392 .mode = PCI_MODE_EP, 393 .linkdown_irq_regfield = J7200_LINK_DOWN, 394 .max_lanes = 4, 395 }; 396 397 static const struct j721e_pcie_data j722s_pcie_rc_data = { 398 .mode = PCI_MODE_RC, 399 .linkdown_irq_regfield = J7200_LINK_DOWN, 400 .byte_access_allowed = true, 401 .max_lanes = 1, 402 }; 403 404 static const struct of_device_id of_j721e_pcie_match[] = { 405 { 406 .compatible = "ti,j721e-pcie-host", 407 .data = &j721e_pcie_rc_data, 408 }, 409 { 410 .compatible = "ti,j721e-pcie-ep", 411 .data = &j721e_pcie_ep_data, 412 }, 413 { 414 .compatible = "ti,j7200-pcie-host", 415 .data = &j7200_pcie_rc_data, 416 }, 417 { 418 .compatible = "ti,j7200-pcie-ep", 419 .data = &j7200_pcie_ep_data, 420 }, 421 { 422 .compatible = "ti,am64-pcie-host", 423 .data = &am64_pcie_rc_data, 424 }, 425 { 426 .compatible = "ti,am64-pcie-ep", 427 .data = &am64_pcie_ep_data, 428 }, 429 { 430 .compatible = "ti,j784s4-pcie-host", 431 .data = &j784s4_pcie_rc_data, 432 }, 433 { 434 .compatible = "ti,j784s4-pcie-ep", 435 .data = &j784s4_pcie_ep_data, 436 }, 437 { 438 .compatible = "ti,j722s-pcie-host", 439 .data = &j722s_pcie_rc_data, 440 }, 441 {}, 442 }; 443 444 static int j721e_pcie_probe(struct platform_device *pdev) 445 { 446 struct device *dev = &pdev->dev; 447 struct device_node *node = dev->of_node; 448 struct pci_host_bridge *bridge; 449 const struct j721e_pcie_data *data; 450 struct cdns_pcie *cdns_pcie; 451 struct j721e_pcie *pcie; 452 struct cdns_pcie_rc *rc = NULL; 453 struct cdns_pcie_ep *ep = NULL; 454 struct gpio_desc *gpiod; 455 void __iomem *base; 456 struct clk *clk; 457 u32 num_lanes; 458 u32 mode; 459 int ret; 460 int irq; 461 462 data = of_device_get_match_data(dev); 463 if (!data) 464 return -EINVAL; 465 466 mode = (u32)data->mode; 467 468 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 469 if (!pcie) 470 return -ENOMEM; 471 472 switch (mode) { 473 case PCI_MODE_RC: 474 if (!IS_ENABLED(CONFIG_PCI_J721E_HOST)) 475 return -ENODEV; 476 477 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); 478 if (!bridge) 479 return -ENOMEM; 480 481 if (!data->byte_access_allowed) 482 bridge->ops = &cdns_ti_pcie_host_ops; 483 rc = pci_host_bridge_priv(bridge); 484 rc->quirk_retrain_flag = data->quirk_retrain_flag; 485 rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; 486 487 cdns_pcie = &rc->pcie; 488 cdns_pcie->dev = dev; 489 cdns_pcie->ops = &j721e_pcie_ops; 490 pcie->cdns_pcie = cdns_pcie; 491 break; 492 case PCI_MODE_EP: 493 if (!IS_ENABLED(CONFIG_PCI_J721E_EP)) 494 return -ENODEV; 495 496 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); 497 if (!ep) 498 return -ENOMEM; 499 500 ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; 501 ep->quirk_disable_flr = data->quirk_disable_flr; 502 503 cdns_pcie = &ep->pcie; 504 cdns_pcie->dev = dev; 505 cdns_pcie->ops = &j721e_pcie_ops; 506 pcie->cdns_pcie = cdns_pcie; 507 break; 508 default: 509 dev_err(dev, "INVALID device type %d\n", mode); 510 return 0; 511 } 512 513 pcie->mode = mode; 514 pcie->linkdown_irq_regfield = data->linkdown_irq_regfield; 515 516 base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg"); 517 if (IS_ERR(base)) 518 return PTR_ERR(base); 519 pcie->intd_cfg_base = base; 520 521 base = devm_platform_ioremap_resource_byname(pdev, "user_cfg"); 522 if (IS_ERR(base)) 523 return PTR_ERR(base); 524 pcie->user_cfg_base = base; 525 526 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 527 if (ret || num_lanes > data->max_lanes) { 528 dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n"); 529 num_lanes = 1; 530 } 531 532 pcie->num_lanes = num_lanes; 533 pcie->max_lanes = data->max_lanes; 534 535 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) 536 return -EINVAL; 537 538 irq = platform_get_irq_byname(pdev, "link_state"); 539 if (irq < 0) 540 return irq; 541 542 dev_set_drvdata(dev, pcie); 543 pm_runtime_enable(dev); 544 ret = pm_runtime_get_sync(dev); 545 if (ret < 0) { 546 dev_err_probe(dev, ret, "pm_runtime_get_sync failed\n"); 547 goto err_get_sync; 548 } 549 550 ret = j721e_pcie_ctrl_init(pcie); 551 if (ret < 0) { 552 dev_err_probe(dev, ret, "pm_runtime_get_sync failed\n"); 553 goto err_get_sync; 554 } 555 556 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0, 557 "j721e-pcie-link-down-irq", pcie); 558 if (ret < 0) { 559 dev_err_probe(dev, ret, "failed to request link state IRQ %d\n", irq); 560 goto err_get_sync; 561 } 562 563 j721e_pcie_config_link_irq(pcie); 564 565 switch (mode) { 566 case PCI_MODE_RC: 567 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 568 if (IS_ERR(gpiod)) { 569 ret = dev_err_probe(dev, PTR_ERR(gpiod), "Failed to get reset GPIO\n"); 570 goto err_get_sync; 571 } 572 pcie->reset_gpio = gpiod; 573 574 ret = cdns_pcie_init_phy(dev, cdns_pcie); 575 if (ret) { 576 dev_err_probe(dev, ret, "Failed to init phy\n"); 577 goto err_get_sync; 578 } 579 580 clk = devm_clk_get_optional(dev, "pcie_refclk"); 581 if (IS_ERR(clk)) { 582 ret = dev_err_probe(dev, PTR_ERR(clk), "failed to get pcie_refclk\n"); 583 goto err_pcie_setup; 584 } 585 586 ret = clk_prepare_enable(clk); 587 if (ret) { 588 dev_err_probe(dev, ret, "failed to enable pcie_refclk\n"); 589 goto err_pcie_setup; 590 } 591 pcie->refclk = clk; 592 593 /* 594 * Section 2.2 of the PCI Express Card Electromechanical 595 * Specification (Revision 5.1) mandates that the deassertion 596 * of the PERST# signal should be delayed by 100 ms (TPVPERL). 597 * This shall ensure that the power and the reference clock 598 * are stable. 599 */ 600 if (gpiod) { 601 msleep(PCIE_T_PVPERL_MS); 602 gpiod_set_value_cansleep(gpiod, 1); 603 } 604 605 ret = cdns_pcie_host_setup(rc); 606 if (ret < 0) { 607 clk_disable_unprepare(pcie->refclk); 608 goto err_pcie_setup; 609 } 610 611 break; 612 case PCI_MODE_EP: 613 ret = cdns_pcie_init_phy(dev, cdns_pcie); 614 if (ret) { 615 dev_err_probe(dev, ret, "Failed to init phy\n"); 616 goto err_get_sync; 617 } 618 619 ret = cdns_pcie_ep_setup(ep); 620 if (ret < 0) 621 goto err_pcie_setup; 622 623 break; 624 } 625 626 return 0; 627 628 err_pcie_setup: 629 cdns_pcie_disable_phy(cdns_pcie); 630 631 err_get_sync: 632 pm_runtime_put(dev); 633 pm_runtime_disable(dev); 634 635 return ret; 636 } 637 638 static void j721e_pcie_remove(struct platform_device *pdev) 639 { 640 struct j721e_pcie *pcie = platform_get_drvdata(pdev); 641 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; 642 struct device *dev = &pdev->dev; 643 struct cdns_pcie_ep *ep; 644 struct cdns_pcie_rc *rc; 645 646 if (pcie->mode == PCI_MODE_RC) { 647 rc = container_of(cdns_pcie, struct cdns_pcie_rc, pcie); 648 cdns_pcie_host_disable(rc); 649 } else { 650 ep = container_of(cdns_pcie, struct cdns_pcie_ep, pcie); 651 cdns_pcie_ep_disable(ep); 652 } 653 654 gpiod_set_value_cansleep(pcie->reset_gpio, 0); 655 656 clk_disable_unprepare(pcie->refclk); 657 cdns_pcie_disable_phy(cdns_pcie); 658 j721e_pcie_disable_link_irq(pcie); 659 pm_runtime_put(dev); 660 pm_runtime_disable(dev); 661 } 662 663 static int j721e_pcie_suspend_noirq(struct device *dev) 664 { 665 struct j721e_pcie *pcie = dev_get_drvdata(dev); 666 667 if (pcie->mode == PCI_MODE_RC) { 668 gpiod_set_value_cansleep(pcie->reset_gpio, 0); 669 clk_disable_unprepare(pcie->refclk); 670 } 671 672 cdns_pcie_disable_phy(pcie->cdns_pcie); 673 674 return 0; 675 } 676 677 static int j721e_pcie_resume_noirq(struct device *dev) 678 { 679 struct j721e_pcie *pcie = dev_get_drvdata(dev); 680 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; 681 int ret; 682 683 ret = j721e_pcie_ctrl_init(pcie); 684 if (ret < 0) 685 return ret; 686 687 j721e_pcie_config_link_irq(pcie); 688 689 /* 690 * This is not called explicitly in the probe, it is called by 691 * cdns_pcie_init_phy(). 692 */ 693 ret = cdns_pcie_enable_phy(pcie->cdns_pcie); 694 if (ret < 0) 695 return ret; 696 697 if (pcie->mode == PCI_MODE_RC) { 698 struct cdns_pcie_rc *rc = cdns_pcie_to_rc(cdns_pcie); 699 700 ret = clk_prepare_enable(pcie->refclk); 701 if (ret < 0) 702 return ret; 703 704 /* 705 * Section 2.2 of the PCI Express Card Electromechanical 706 * Specification (Revision 5.1) mandates that the deassertion 707 * of the PERST# signal should be delayed by 100 ms (TPVPERL). 708 * This shall ensure that the power and the reference clock 709 * are stable. 710 */ 711 if (pcie->reset_gpio) { 712 msleep(PCIE_T_PVPERL_MS); 713 gpiod_set_value_cansleep(pcie->reset_gpio, 1); 714 } 715 716 ret = cdns_pcie_host_link_setup(rc); 717 if (ret < 0) { 718 clk_disable_unprepare(pcie->refclk); 719 return ret; 720 } 721 722 /* 723 * Reset internal status of BARs to force reinitialization in 724 * cdns_pcie_host_init(). 725 */ 726 for (enum cdns_pcie_rp_bar bar = RP_BAR0; bar <= RP_NO_BAR; bar++) 727 rc->avail_ib_bar[bar] = true; 728 729 ret = cdns_pcie_host_init(rc); 730 if (ret) { 731 clk_disable_unprepare(pcie->refclk); 732 return ret; 733 } 734 } 735 736 return 0; 737 } 738 739 static DEFINE_NOIRQ_DEV_PM_OPS(j721e_pcie_pm_ops, 740 j721e_pcie_suspend_noirq, 741 j721e_pcie_resume_noirq); 742 743 static struct platform_driver j721e_pcie_driver = { 744 .probe = j721e_pcie_probe, 745 .remove = j721e_pcie_remove, 746 .driver = { 747 .name = "j721e-pcie", 748 .of_match_table = of_j721e_pcie_match, 749 .suppress_bind_attrs = true, 750 .pm = pm_sleep_ptr(&j721e_pcie_pm_ops), 751 }, 752 }; 753 module_platform_driver(j721e_pcie_driver); 754 755 MODULE_LICENSE("GPL"); 756 MODULE_DESCRIPTION("PCIe controller driver for TI's J721E and related SoCs"); 757 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>"); 758