113e920d9SHaijun Liu /* SPDX-License-Identifier: GPL-2.0-only 213e920d9SHaijun Liu * 313e920d9SHaijun Liu * Copyright (c) 2021, MediaTek Inc. 413e920d9SHaijun Liu * Copyright (c) 2021-2022, Intel Corporation. 513e920d9SHaijun Liu * 613e920d9SHaijun Liu * Authors: 713e920d9SHaijun Liu * Haijun Liu <haijun.liu@mediatek.com> 813e920d9SHaijun Liu * Ricardo Martinez <ricardo.martinez@linux.intel.com> 913e920d9SHaijun Liu * Sreehari Kancharla <sreehari.kancharla@intel.com> 1013e920d9SHaijun Liu * 1113e920d9SHaijun Liu * Contributors: 1213e920d9SHaijun Liu * Amir Hanania <amir.hanania@intel.com> 1313e920d9SHaijun Liu * Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> 1413e920d9SHaijun Liu * Moises Veleta <moises.veleta@intel.com> 1513e920d9SHaijun Liu */ 1613e920d9SHaijun Liu 1713e920d9SHaijun Liu #ifndef __T7XX_PCI_H__ 1813e920d9SHaijun Liu #define __T7XX_PCI_H__ 1913e920d9SHaijun Liu 2046e8f49eSHaijun Liu #include <linux/completion.h> 2113e920d9SHaijun Liu #include <linux/irqreturn.h> 2246e8f49eSHaijun Liu #include <linux/mutex.h> 2313e920d9SHaijun Liu #include <linux/pci.h> 24de49ea38SHaijun Liu #include <linux/spinlock.h> 2513e920d9SHaijun Liu #include <linux/types.h> 2613e920d9SHaijun Liu 2713e920d9SHaijun Liu #include "t7xx_reg.h" 2813e920d9SHaijun Liu 2913e920d9SHaijun Liu /* struct t7xx_addr_base - holds base addresses 3013e920d9SHaijun Liu * @pcie_mac_ireg_base: PCIe MAC register base 3113e920d9SHaijun Liu * @pcie_ext_reg_base: used to calculate base addresses for CLDMA, DPMA and MHCCIF registers 3213e920d9SHaijun Liu * @pcie_dev_reg_trsl_addr: used to calculate the register base address 3313e920d9SHaijun Liu * @infracfg_ao_base: base address used in CLDMA reset operations 3413e920d9SHaijun Liu * @mhccif_rc_base: host view of MHCCIF rc base addr 3513e920d9SHaijun Liu */ 3613e920d9SHaijun Liu struct t7xx_addr_base { 3713e920d9SHaijun Liu void __iomem *pcie_mac_ireg_base; 3813e920d9SHaijun Liu void __iomem *pcie_ext_reg_base; 3913e920d9SHaijun Liu u32 pcie_dev_reg_trsl_addr; 4013e920d9SHaijun Liu void __iomem *infracfg_ao_base; 4113e920d9SHaijun Liu void __iomem *mhccif_rc_base; 4213e920d9SHaijun Liu }; 4313e920d9SHaijun Liu 4413e920d9SHaijun Liu typedef irqreturn_t (*t7xx_intr_callback)(int irq, void *param); 4513e920d9SHaijun Liu 46409c38d4SJinjian Song enum t7xx_mode { 47409c38d4SJinjian Song T7XX_UNKNOWN, 48409c38d4SJinjian Song T7XX_READY, 49409c38d4SJinjian Song T7XX_RESET, 50409c38d4SJinjian Song T7XX_FASTBOOT_SWITCHING, 51409c38d4SJinjian Song T7XX_FASTBOOT_DOWNLOAD, 52409c38d4SJinjian Song T7XX_FASTBOOT_DUMP, 53409c38d4SJinjian Song T7XX_MODE_LAST, /* must always be last */ 54409c38d4SJinjian Song }; 55409c38d4SJinjian Song 5613e920d9SHaijun Liu /* struct t7xx_pci_dev - MTK device context structure 5713e920d9SHaijun Liu * @intr_handler: array of handler function for request_threaded_irq 5813e920d9SHaijun Liu * @intr_thread: array of thread_fn for request_threaded_irq 5913e920d9SHaijun Liu * @callback_param: array of cookie passed back to interrupt functions 6013e920d9SHaijun Liu * @pdev: PCI device 6113e920d9SHaijun Liu * @base_addr: memory base addresses of HW components 6213e920d9SHaijun Liu * @md: modem interface 6313e920d9SHaijun Liu * @ccmni_ctlb: context structure used to control the network data path 6413e920d9SHaijun Liu * @rgu_pci_irq_en: RGU callback ISR registered and active 6546e8f49eSHaijun Liu * @md_pm_entities: list of pm entities 6646e8f49eSHaijun Liu * @md_pm_entity_mtx: protects md_pm_entities list 6746e8f49eSHaijun Liu * @pm_sr_ack: ack from the device when went to sleep or woke up 6846e8f49eSHaijun Liu * @md_pm_state: state for resume/suspend 69de49ea38SHaijun Liu * @md_pm_lock: protects PCIe sleep lock 70de49ea38SHaijun Liu * @sleep_disable_count: PCIe L1.2 lock counter 71de49ea38SHaijun Liu * @sleep_lock_acquire: indicates that sleep has been disabled 72409c38d4SJinjian Song * @mode: indicates the device mode 7313e920d9SHaijun Liu */ 7413e920d9SHaijun Liu struct t7xx_pci_dev { 7513e920d9SHaijun Liu t7xx_intr_callback intr_handler[EXT_INT_NUM]; 7613e920d9SHaijun Liu t7xx_intr_callback intr_thread[EXT_INT_NUM]; 7713e920d9SHaijun Liu void *callback_param[EXT_INT_NUM]; 7813e920d9SHaijun Liu struct pci_dev *pdev; 7913e920d9SHaijun Liu struct t7xx_addr_base base_addr; 8013e920d9SHaijun Liu struct t7xx_modem *md; 8113e920d9SHaijun Liu struct t7xx_ccmni_ctrl *ccmni_ctlb; 8213e920d9SHaijun Liu bool rgu_pci_irq_en; 83ab87603bSKai-Heng Feng struct completion init_done; 8446e8f49eSHaijun Liu 8546e8f49eSHaijun Liu /* Low Power Items */ 8646e8f49eSHaijun Liu struct list_head md_pm_entities; 8746e8f49eSHaijun Liu struct mutex md_pm_entity_mtx; /* Protects MD PM entities list */ 8846e8f49eSHaijun Liu struct completion pm_sr_ack; 8946e8f49eSHaijun Liu atomic_t md_pm_state; 90de49ea38SHaijun Liu spinlock_t md_pm_lock; /* Protects PCI resource lock */ 91de49ea38SHaijun Liu unsigned int sleep_disable_count; 92de49ea38SHaijun Liu struct completion sleep_lock_acquire; 933349e4a4SM Chetan Kumar #ifdef CONFIG_WWAN_DEBUGFS 943349e4a4SM Chetan Kumar struct dentry *debugfs_dir; 953349e4a4SM Chetan Kumar #endif 96409c38d4SJinjian Song u32 mode; 97*61329a11SJinjian Song bool debug_ports_show; 9813e920d9SHaijun Liu }; 9913e920d9SHaijun Liu 10046e8f49eSHaijun Liu enum t7xx_pm_id { 10146e8f49eSHaijun Liu PM_ENTITY_ID_CTRL1, 10246e8f49eSHaijun Liu PM_ENTITY_ID_CTRL2, 10346e8f49eSHaijun Liu PM_ENTITY_ID_DATA, 10446e8f49eSHaijun Liu PM_ENTITY_ID_INVALID 10546e8f49eSHaijun Liu }; 10646e8f49eSHaijun Liu 10746e8f49eSHaijun Liu /* struct md_pm_entity - device power management entity 10846e8f49eSHaijun Liu * @entity: list of PM Entities 10946e8f49eSHaijun Liu * @suspend: callback invoked before sending D3 request to device 11046e8f49eSHaijun Liu * @suspend_late: callback invoked after getting D3 ACK from device 11146e8f49eSHaijun Liu * @resume_early: callback invoked before sending the resume request to device 11246e8f49eSHaijun Liu * @resume: callback invoked after getting resume ACK from device 11346e8f49eSHaijun Liu * @id: unique PM entity identifier 11446e8f49eSHaijun Liu * @entity_param: parameter passed to the registered callbacks 11546e8f49eSHaijun Liu * 11646e8f49eSHaijun Liu * This structure is used to indicate PM operations required by internal 11746e8f49eSHaijun Liu * HW modules such as CLDMA and DPMA. 11846e8f49eSHaijun Liu */ 11946e8f49eSHaijun Liu struct md_pm_entity { 12046e8f49eSHaijun Liu struct list_head entity; 12146e8f49eSHaijun Liu int (*suspend)(struct t7xx_pci_dev *t7xx_dev, void *entity_param); 12246e8f49eSHaijun Liu void (*suspend_late)(struct t7xx_pci_dev *t7xx_dev, void *entity_param); 12346e8f49eSHaijun Liu void (*resume_early)(struct t7xx_pci_dev *t7xx_dev, void *entity_param); 12446e8f49eSHaijun Liu int (*resume)(struct t7xx_pci_dev *t7xx_dev, void *entity_param); 12546e8f49eSHaijun Liu enum t7xx_pm_id id; 12646e8f49eSHaijun Liu void *entity_param; 12746e8f49eSHaijun Liu }; 12846e8f49eSHaijun Liu 129de49ea38SHaijun Liu void t7xx_pci_disable_sleep(struct t7xx_pci_dev *t7xx_dev); 130de49ea38SHaijun Liu void t7xx_pci_enable_sleep(struct t7xx_pci_dev *t7xx_dev); 131de49ea38SHaijun Liu int t7xx_pci_sleep_disable_complete(struct t7xx_pci_dev *t7xx_dev); 13246e8f49eSHaijun Liu int t7xx_pci_pm_entity_register(struct t7xx_pci_dev *t7xx_dev, struct md_pm_entity *pm_entity); 13346e8f49eSHaijun Liu int t7xx_pci_pm_entity_unregister(struct t7xx_pci_dev *t7xx_dev, struct md_pm_entity *pm_entity); 13446e8f49eSHaijun Liu void t7xx_pci_pm_init_late(struct t7xx_pci_dev *t7xx_dev); 13546e8f49eSHaijun Liu void t7xx_pci_pm_exp_detected(struct t7xx_pci_dev *t7xx_dev); 136409c38d4SJinjian Song void t7xx_mode_update(struct t7xx_pci_dev *t7xx_dev, enum t7xx_mode mode); 137d785ed94SJinjian Song int t7xx_pci_reprobe(struct t7xx_pci_dev *t7xx_dev, bool boot); 138d785ed94SJinjian Song int t7xx_pci_reprobe_early(struct t7xx_pci_dev *t7xx_dev); 139d785ed94SJinjian Song 14013e920d9SHaijun Liu #endif /* __T7XX_PCI_H__ */ 141