1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2023 Realtek Corporation 3 */ 4 5 #include "chan.h" 6 #include "debug.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8922a.h" 11 #include "rtw8922a_rfk.h" 12 13 static void rtw8922a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 14 enum rtw89_rf_path path) 15 { 16 static const u32 tssi_trk_man[2] = {R_TSSI_PWR_P0, R_TSSI_PWR_P1}; 17 18 if (en) 19 rtw89_phy_write32_mask(rtwdev, tssi_trk_man[path], B_TSSI_CONT_EN, 0); 20 else 21 rtw89_phy_write32_mask(rtwdev, tssi_trk_man[path], B_TSSI_CONT_EN, 1); 22 } 23 24 void rtw8922a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, u8 phy_idx) 25 { 26 if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) { 27 if (phy_idx == RTW89_PHY_0) 28 rtw8922a_tssi_cont_en(rtwdev, en, RF_PATH_A); 29 else 30 rtw8922a_tssi_cont_en(rtwdev, en, RF_PATH_B); 31 } else { 32 rtw8922a_tssi_cont_en(rtwdev, en, RF_PATH_A); 33 rtw8922a_tssi_cont_en(rtwdev, en, RF_PATH_B); 34 } 35 } 36 37 static 38 void rtw8922a_ctl_band_ch_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 39 u8 central_ch, enum rtw89_band band, 40 enum rtw89_bandwidth bw) 41 { 42 const u32 rf_addr[2] = {RR_CFGCH, RR_CFGCH_V1}; 43 struct rtw89_hal *hal = &rtwdev->hal; 44 u32 rf_reg[RF_PATH_NUM_8922A][2]; 45 u8 synpath; 46 u32 rf18; 47 u8 kpath; 48 u8 path; 49 u8 i; 50 51 rf_reg[RF_PATH_A][0] = rtw89_read_rf(rtwdev, RF_PATH_A, rf_addr[0], RFREG_MASK); 52 rf_reg[RF_PATH_A][1] = rtw89_read_rf(rtwdev, RF_PATH_A, rf_addr[1], RFREG_MASK); 53 rf_reg[RF_PATH_B][0] = rtw89_read_rf(rtwdev, RF_PATH_B, rf_addr[0], RFREG_MASK); 54 rf_reg[RF_PATH_B][1] = rtw89_read_rf(rtwdev, RF_PATH_B, rf_addr[1], RFREG_MASK); 55 56 kpath = rtw89_phy_get_kpath(rtwdev, phy); 57 synpath = rtw89_phy_get_syn_sel(rtwdev, phy); 58 59 rf18 = rtw89_read_rf(rtwdev, synpath, RR_CFGCH, RFREG_MASK); 60 if (rf18 == INV_RF_DATA) { 61 rtw89_warn(rtwdev, "[RFK] Invalid RF18 value\n"); 62 return; 63 } 64 65 for (path = 0; path < RF_PATH_NUM_8922A; path++) { 66 if (!(kpath & BIT(path))) 67 continue; 68 69 for (i = 0; i < 2; i++) { 70 if (rf_reg[path][i] == INV_RF_DATA) { 71 rtw89_warn(rtwdev, 72 "[RFK] Invalid RF_0x18 for Path-%d\n", path); 73 return; 74 } 75 76 rf_reg[path][i] &= ~(RR_CFGCH_BAND1 | RR_CFGCH_BW | 77 RR_CFGCH_BAND0 | RR_CFGCH_CH); 78 rf_reg[path][i] |= u32_encode_bits(central_ch, RR_CFGCH_CH); 79 80 switch (band) { 81 case RTW89_BAND_2G: 82 default: 83 break; 84 case RTW89_BAND_5G: 85 rf_reg[path][i] |= 86 u32_encode_bits(CFGCH_BAND1_5G, RR_CFGCH_BAND1) | 87 u32_encode_bits(CFGCH_BAND0_5G, RR_CFGCH_BAND0); 88 break; 89 case RTW89_BAND_6G: 90 rf_reg[path][i] |= 91 u32_encode_bits(CFGCH_BAND1_6G, RR_CFGCH_BAND1) | 92 u32_encode_bits(CFGCH_BAND0_6G, RR_CFGCH_BAND0); 93 break; 94 } 95 96 switch (bw) { 97 case RTW89_CHANNEL_WIDTH_5: 98 case RTW89_CHANNEL_WIDTH_10: 99 case RTW89_CHANNEL_WIDTH_20: 100 default: 101 break; 102 case RTW89_CHANNEL_WIDTH_40: 103 rf_reg[path][i] |= 104 u32_encode_bits(CFGCH_BW_V2_40M, RR_CFGCH_BW_V2); 105 break; 106 case RTW89_CHANNEL_WIDTH_80: 107 rf_reg[path][i] |= 108 u32_encode_bits(CFGCH_BW_V2_80M, RR_CFGCH_BW_V2); 109 break; 110 case RTW89_CHANNEL_WIDTH_160: 111 rf_reg[path][i] |= 112 u32_encode_bits(CFGCH_BW_V2_160M, RR_CFGCH_BW_V2); 113 break; 114 case RTW89_CHANNEL_WIDTH_320: 115 rf_reg[path][i] |= 116 u32_encode_bits(CFGCH_BW_V2_320M, RR_CFGCH_BW_V2); 117 break; 118 } 119 120 rtw89_write_rf(rtwdev, path, rf_addr[i], 121 RFREG_MASK, rf_reg[path][i]); 122 fsleep(100); 123 } 124 } 125 126 if (hal->cv != CHIP_CAV) 127 return; 128 129 if (band == RTW89_BAND_2G) { 130 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000); 131 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x00003); 132 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c990); 133 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0xebe38); 134 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000); 135 } else { 136 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000); 137 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x00003); 138 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c190); 139 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0xebe38); 140 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000); 141 } 142 } 143 144 void rtw8922a_set_channel_rf(struct rtw89_dev *rtwdev, 145 const struct rtw89_chan *chan, 146 enum rtw89_phy_idx phy_idx) 147 { 148 rtw8922a_ctl_band_ch_bw(rtwdev, phy_idx, chan->channel, chan->band_type, 149 chan->band_width); 150 } 151 152 enum _rf_syn_pow { 153 RF_SYN_ON_OFF, 154 RF_SYN_OFF_ON, 155 RF_SYN_ALLON, 156 RF_SYN_ALLOFF, 157 }; 158 159 static void rtw8922a_set_syn01_cav(struct rtw89_dev *rtwdev, enum _rf_syn_pow syn) 160 { 161 if (syn == RF_SYN_ALLON) { 162 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3); 163 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x2); 164 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3); 165 166 rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x3); 167 rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x2); 168 rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x3); 169 } else if (syn == RF_SYN_ON_OFF) { 170 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3); 171 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x2); 172 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3); 173 174 rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x0); 175 } else if (syn == RF_SYN_OFF_ON) { 176 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x0); 177 178 rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x3); 179 rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x2); 180 rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x3); 181 } else if (syn == RF_SYN_ALLOFF) { 182 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x0); 183 rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x0); 184 } 185 } 186 187 static void rtw8922a_set_syn01_cbv(struct rtw89_dev *rtwdev, enum _rf_syn_pow syn) 188 { 189 if (syn == RF_SYN_ALLON) { 190 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0xf); 191 rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0xf); 192 } else if (syn == RF_SYN_ON_OFF) { 193 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0xf); 194 rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0x0); 195 } else if (syn == RF_SYN_OFF_ON) { 196 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0x0); 197 rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0xf); 198 } else if (syn == RF_SYN_ALLOFF) { 199 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0x0); 200 rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0x0); 201 } 202 } 203 204 static void rtw8922a_set_syn01(struct rtw89_dev *rtwdev, enum _rf_syn_pow syn) 205 { 206 struct rtw89_hal *hal = &rtwdev->hal; 207 208 rtw89_debug(rtwdev, RTW89_DBG_RFK, "SYN config=%d\n", syn); 209 210 if (hal->cv == CHIP_CAV) 211 rtw8922a_set_syn01_cav(rtwdev, syn); 212 else 213 rtw8922a_set_syn01_cbv(rtwdev, syn); 214 } 215 216 static void rtw8922a_chlk_ktbl_sel(struct rtw89_dev *rtwdev, u8 kpath, u8 idx) 217 { 218 u32 tmp; 219 220 if (idx > 2) { 221 rtw89_warn(rtwdev, "[DBCC][ERROR]indx is out of limit!! index(%d)", idx); 222 return; 223 } 224 225 if (kpath & RF_A) { 226 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL, B_COEF_SEL_EN, 0x1); 227 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL, B_COEF_SEL_IQC_V1, idx); 228 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL, B_COEF_SEL_MDPD_V1, idx); 229 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RR_TXG_SEL, 0x4 | idx); 230 231 tmp = rtw89_phy_read32_mask(rtwdev, R_COEF_SEL, BIT(0)); 232 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, tmp); 233 tmp = rtw89_phy_read32_mask(rtwdev, R_COEF_SEL, BIT(1)); 234 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G5, tmp); 235 } 236 237 if (kpath & RF_B) { 238 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL_C1, B_COEF_SEL_EN, 0x1); 239 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL_C1, B_COEF_SEL_IQC_V1, idx); 240 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL_C1, B_COEF_SEL_MDPD_V1, idx); 241 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RR_TXG_SEL, 0x4 | idx); 242 243 tmp = rtw89_phy_read32_mask(rtwdev, R_COEF_SEL_C1, BIT(0)); 244 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT_C1, B_CFIR_LUT_G3, tmp); 245 tmp = rtw89_phy_read32_mask(rtwdev, R_COEF_SEL_C1, BIT(1)); 246 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT_C1, B_CFIR_LUT_G5, tmp); 247 } 248 } 249 250 static u8 rtw8922a_chlk_reload_sel_tbl(struct rtw89_dev *rtwdev, 251 const struct rtw89_chan *chan, u8 path) 252 { 253 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc; 254 struct rtw89_rfk_chan_desc desc[__RTW89_RFK_CHS_NR_V1] = {}; 255 u8 tbl_sel; 256 257 for (tbl_sel = 0; tbl_sel < ARRAY_SIZE(desc); tbl_sel++) { 258 struct rtw89_rfk_chan_desc *p = &desc[tbl_sel]; 259 260 p->ch = rfk_mcc->data[path].ch[tbl_sel]; 261 262 p->has_band = true; 263 p->band = rfk_mcc->data[path].band[tbl_sel]; 264 265 p->has_bw = true; 266 p->bw = rfk_mcc->data[path].bw[tbl_sel]; 267 } 268 269 tbl_sel = rtw89_rfk_chan_lookup(rtwdev, desc, ARRAY_SIZE(desc), chan); 270 271 rfk_mcc->data[path].ch[tbl_sel] = chan->channel; 272 rfk_mcc->data[path].band[tbl_sel] = chan->band_type; 273 rfk_mcc->data[path].bw[tbl_sel] = chan->band_width; 274 rfk_mcc->data[path].table_idx = tbl_sel; 275 276 return tbl_sel; 277 } 278 279 static void rtw8922a_chlk_reload(struct rtw89_dev *rtwdev) 280 { 281 const struct rtw89_chan *chan0, *chan1; 282 u8 s0_tbl, s1_tbl; 283 284 switch (rtwdev->mlo_dbcc_mode) { 285 default: 286 case MLO_2_PLUS_0_1RF: 287 chan0 = rtw89_mgnt_chan_get(rtwdev, 0); 288 chan1 = chan0; 289 break; 290 case MLO_0_PLUS_2_1RF: 291 chan1 = rtw89_mgnt_chan_get(rtwdev, 1); 292 chan0 = chan1; 293 break; 294 case MLO_1_PLUS_1_1RF: 295 chan0 = rtw89_mgnt_chan_get(rtwdev, 0); 296 chan1 = rtw89_mgnt_chan_get(rtwdev, 1); 297 break; 298 } 299 300 s0_tbl = rtw8922a_chlk_reload_sel_tbl(rtwdev, chan0, 0); 301 s1_tbl = rtw8922a_chlk_reload_sel_tbl(rtwdev, chan1, 1); 302 303 rtw8922a_chlk_ktbl_sel(rtwdev, RF_A, s0_tbl); 304 rtw8922a_chlk_ktbl_sel(rtwdev, RF_B, s1_tbl); 305 } 306 307 static void rtw8922a_rfk_mlo_ctrl(struct rtw89_dev *rtwdev) 308 { 309 enum _rf_syn_pow syn_pow; 310 311 if (!rtwdev->dbcc_en) 312 goto set_rfk_reload; 313 314 switch (rtwdev->mlo_dbcc_mode) { 315 case MLO_0_PLUS_2_1RF: 316 syn_pow = RF_SYN_OFF_ON; 317 break; 318 case MLO_0_PLUS_2_2RF: 319 case MLO_1_PLUS_1_2RF: 320 case MLO_2_PLUS_0_1RF: 321 case MLO_2_PLUS_0_2RF: 322 case MLO_2_PLUS_2_2RF: 323 case MLO_DBCC_NOT_SUPPORT: 324 default: 325 syn_pow = RF_SYN_ON_OFF; 326 break; 327 case MLO_1_PLUS_1_1RF: 328 case DBCC_LEGACY: 329 syn_pow = RF_SYN_ALLON; 330 break; 331 } 332 333 rtw8922a_set_syn01(rtwdev, syn_pow); 334 335 set_rfk_reload: 336 rtw8922a_chlk_reload(rtwdev); 337 } 338 339 static void rtw8922a_rfk_pll_init(struct rtw89_dev *rtwdev) 340 { 341 int ret; 342 u8 tmp; 343 344 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_PLL_1, &tmp); 345 if (ret) 346 return; 347 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL_1, tmp | 0xf8, 0xFF); 348 if (ret) 349 return; 350 351 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_APBT, &tmp); 352 if (ret) 353 return; 354 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_APBT, tmp & ~0x60, 0xFF); 355 if (ret) 356 return; 357 358 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_PLL, &tmp); 359 if (ret) 360 return; 361 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_PLL, tmp | 0x38, 0xFF); 362 if (ret) 363 return; 364 } 365 366 void rtw8922a_rfk_hw_init(struct rtw89_dev *rtwdev) 367 { 368 if (rtwdev->dbcc_en) 369 rtw8922a_rfk_mlo_ctrl(rtwdev); 370 371 rtw8922a_rfk_pll_init(rtwdev); 372 } 373 374 void rtw8922a_pre_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 375 { 376 bool mlo_1_1; 377 378 if (!rtwdev->dbcc_en) 379 return; 380 381 mlo_1_1 = rtw89_is_mlo_1_1(rtwdev); 382 if (mlo_1_1) 383 rtw8922a_set_syn01(rtwdev, RF_SYN_ALLON); 384 else if (phy_idx == RTW89_PHY_0) 385 rtw8922a_set_syn01(rtwdev, RF_SYN_ON_OFF); 386 else 387 rtw8922a_set_syn01(rtwdev, RF_SYN_OFF_ON); 388 389 fsleep(1000); 390 } 391 392 void rtw8922a_post_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 393 { 394 rtw8922a_rfk_mlo_ctrl(rtwdev); 395 } 396