1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_MAC_H__ 6 #define __RTW89_MAC_H__ 7 8 #include "core.h" 9 #include "reg.h" 10 11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000 12 #define ADDR_CAM_ENT_SIZE 0x40 13 #define ADDR_CAM_ENT_SHORT_SIZE 0x20 14 #define BSSID_CAM_ENT_SIZE 0x08 15 #define HFC_PAGE_UNIT 64 16 #define RPWM_TRY_CNT 3 17 18 enum rtw89_mac_hwmod_sel { 19 RTW89_DMAC_SEL = 0, 20 RTW89_CMAC_SEL = 1, 21 22 RTW89_MAC_INVALID, 23 }; 24 25 enum rtw89_mac_fwd_target { 26 RTW89_FWD_DONT_CARE = 0, 27 RTW89_FWD_TO_HOST = 1, 28 RTW89_FWD_TO_WLAN_CPU = 2 29 }; 30 31 enum rtw89_mac_wd_dma_intvl { 32 RTW89_MAC_WD_DMA_INTVL_0S, 33 RTW89_MAC_WD_DMA_INTVL_256NS, 34 RTW89_MAC_WD_DMA_INTVL_512NS, 35 RTW89_MAC_WD_DMA_INTVL_768NS, 36 RTW89_MAC_WD_DMA_INTVL_1US, 37 RTW89_MAC_WD_DMA_INTVL_1_5US, 38 RTW89_MAC_WD_DMA_INTVL_2US, 39 RTW89_MAC_WD_DMA_INTVL_4US, 40 RTW89_MAC_WD_DMA_INTVL_8US, 41 RTW89_MAC_WD_DMA_INTVL_16US, 42 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE 43 }; 44 45 enum rtw89_mac_multi_tag_num { 46 RTW89_MAC_TAG_NUM_1, 47 RTW89_MAC_TAG_NUM_2, 48 RTW89_MAC_TAG_NUM_3, 49 RTW89_MAC_TAG_NUM_4, 50 RTW89_MAC_TAG_NUM_5, 51 RTW89_MAC_TAG_NUM_6, 52 RTW89_MAC_TAG_NUM_7, 53 RTW89_MAC_TAG_NUM_8, 54 RTW89_MAC_TAG_NUM_DEF = 0xFE 55 }; 56 57 enum rtw89_mac_lbc_tmr { 58 RTW89_MAC_LBC_TMR_8US = 0, 59 RTW89_MAC_LBC_TMR_16US, 60 RTW89_MAC_LBC_TMR_32US, 61 RTW89_MAC_LBC_TMR_64US, 62 RTW89_MAC_LBC_TMR_128US, 63 RTW89_MAC_LBC_TMR_256US, 64 RTW89_MAC_LBC_TMR_512US, 65 RTW89_MAC_LBC_TMR_1MS, 66 RTW89_MAC_LBC_TMR_2MS, 67 RTW89_MAC_LBC_TMR_4MS, 68 RTW89_MAC_LBC_TMR_8MS, 69 RTW89_MAC_LBC_TMR_DEF = 0xFE 70 }; 71 72 enum rtw89_mac_cpuio_op_cmd_type { 73 CPUIO_OP_CMD_GET_1ST_PID = 0, 74 CPUIO_OP_CMD_GET_NEXT_PID = 1, 75 CPUIO_OP_CMD_ENQ_TO_TAIL = 4, 76 CPUIO_OP_CMD_ENQ_TO_HEAD = 5, 77 CPUIO_OP_CMD_DEQ = 8, 78 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9, 79 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12 80 }; 81 82 enum rtw89_mac_wde_dle_port_id { 83 WDE_DLE_PORT_ID_DISPATCH = 0, 84 WDE_DLE_PORT_ID_PKTIN = 1, 85 WDE_DLE_PORT_ID_CMAC0 = 3, 86 WDE_DLE_PORT_ID_CMAC1 = 4, 87 WDE_DLE_PORT_ID_CPU_IO = 6, 88 WDE_DLE_PORT_ID_WDRLS = 7, 89 WDE_DLE_PORT_ID_END = 8 90 }; 91 92 enum rtw89_mac_wde_dle_queid_wdrls { 93 WDE_DLE_QUEID_TXOK = 0, 94 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1, 95 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2, 96 WDE_DLE_QUEID_DROP_MACID_DROP = 3, 97 WDE_DLE_QUEID_NO_REPORT = 4 98 }; 99 100 enum rtw89_mac_ple_dle_port_id { 101 PLE_DLE_PORT_ID_DISPATCH = 0, 102 PLE_DLE_PORT_ID_MPDU = 1, 103 PLE_DLE_PORT_ID_SEC = 2, 104 PLE_DLE_PORT_ID_CMAC0 = 3, 105 PLE_DLE_PORT_ID_CMAC1 = 4, 106 PLE_DLE_PORT_ID_WDRLS = 5, 107 PLE_DLE_PORT_ID_CPU_IO = 6, 108 PLE_DLE_PORT_ID_PLRLS = 7, 109 PLE_DLE_PORT_ID_END = 8 110 }; 111 112 enum rtw89_mac_ple_dle_queid_plrls { 113 PLE_DLE_QUEID_NO_REPORT = 0x0 114 }; 115 116 enum rtw89_machdr_frame_type { 117 RTW89_MGNT = 0, 118 RTW89_CTRL = 1, 119 RTW89_DATA = 2, 120 }; 121 122 enum rtw89_mac_dle_dfi_type { 123 DLE_DFI_TYPE_FREEPG = 0, 124 DLE_DFI_TYPE_QUOTA = 1, 125 DLE_DFI_TYPE_PAGELLT = 2, 126 DLE_DFI_TYPE_PKTINFO = 3, 127 DLE_DFI_TYPE_PREPKTLLT = 4, 128 DLE_DFI_TYPE_NXTPKTLLT = 5, 129 DLE_DFI_TYPE_QLNKTBL = 6, 130 DLE_DFI_TYPE_QEMPTY = 7, 131 }; 132 133 enum rtw89_mac_dle_wde_quota_id { 134 WDE_QTAID_HOST_IF = 0, 135 WDE_QTAID_WLAN_CPU = 1, 136 WDE_QTAID_DATA_CPU = 2, 137 WDE_QTAID_PKTIN = 3, 138 WDE_QTAID_CPUIO = 4, 139 }; 140 141 enum rtw89_mac_dle_ple_quota_id { 142 PLE_QTAID_B0_TXPL = 0, 143 PLE_QTAID_B1_TXPL = 1, 144 PLE_QTAID_C2H = 2, 145 PLE_QTAID_H2C = 3, 146 PLE_QTAID_WLAN_CPU = 4, 147 PLE_QTAID_MPDU = 5, 148 PLE_QTAID_CMAC0_RX = 6, 149 PLE_QTAID_CMAC1_RX = 7, 150 PLE_QTAID_CMAC1_BBRPT = 8, 151 PLE_QTAID_WDRLS = 9, 152 PLE_QTAID_CPUIO = 10, 153 }; 154 155 enum rtw89_mac_dle_ctrl_type { 156 DLE_CTRL_TYPE_WDE = 0, 157 DLE_CTRL_TYPE_PLE = 1, 158 DLE_CTRL_TYPE_NUM = 2, 159 }; 160 161 enum rtw89_mac_ax_l0_to_l1_event { 162 MAC_AX_L0_TO_L1_CHIF_IDLE = 0, 163 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1, 164 MAC_AX_L0_TO_L1_RLS_PKID = 2, 165 MAC_AX_L0_TO_L1_PTCL_IDLE = 3, 166 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4, 167 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5, 168 MAC_AX_L0_TO_L1_PCIE_STUCK = 6, 169 MAC_AX_L0_TO_L1_EVENT_MAX = 15, 170 }; 171 172 enum rtw89_mac_phy_rpt_size { 173 MAC_AX_PHY_RPT_SIZE_0 = 0, 174 MAC_AX_PHY_RPT_SIZE_8 = 1, 175 MAC_AX_PHY_RPT_SIZE_16 = 2, 176 MAC_AX_PHY_RPT_SIZE_24 = 3, 177 }; 178 179 enum rtw89_mac_hdr_cnv_size { 180 MAC_AX_HDR_CNV_SIZE_0 = 0, 181 MAC_AX_HDR_CNV_SIZE_32 = 1, 182 MAC_AX_HDR_CNV_SIZE_64 = 2, 183 MAC_AX_HDR_CNV_SIZE_96 = 3, 184 }; 185 186 enum rtw89_mac_wow_fw_status { 187 WOWLAN_NOT_READY = 0x00, 188 WOWLAN_SLEEP_READY = 0x01, 189 WOWLAN_RESUME_READY = 0x02, 190 }; 191 192 #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32) 193 194 enum rtw89_mac_dbg_port_sel { 195 /* CMAC 0 related */ 196 RTW89_DBG_PORT_SEL_PTCL_C0 = 0, 197 RTW89_DBG_PORT_SEL_SCH_C0, 198 RTW89_DBG_PORT_SEL_TMAC_C0, 199 RTW89_DBG_PORT_SEL_RMAC_C0, 200 RTW89_DBG_PORT_SEL_RMACST_C0, 201 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0, 202 RTW89_DBG_PORT_SEL_TRXPTCL_C0, 203 RTW89_DBG_PORT_SEL_TX_INFOL_C0, 204 RTW89_DBG_PORT_SEL_TX_INFOH_C0, 205 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0, 206 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0, 207 /* CMAC 1 related */ 208 RTW89_DBG_PORT_SEL_PTCL_C1, 209 RTW89_DBG_PORT_SEL_SCH_C1, 210 RTW89_DBG_PORT_SEL_TMAC_C1, 211 RTW89_DBG_PORT_SEL_RMAC_C1, 212 RTW89_DBG_PORT_SEL_RMACST_C1, 213 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1, 214 RTW89_DBG_PORT_SEL_TRXPTCL_C1, 215 RTW89_DBG_PORT_SEL_TX_INFOL_C1, 216 RTW89_DBG_PORT_SEL_TX_INFOH_C1, 217 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1, 218 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1, 219 /* DLE related */ 220 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG, 221 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA, 222 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT, 223 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO, 224 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT, 225 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT, 226 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL, 227 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY, 228 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG, 229 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA, 230 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT, 231 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO, 232 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT, 233 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT, 234 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL, 235 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY, 236 RTW89_DBG_PORT_SEL_PKTINFO, 237 /* DISPATCHER related */ 238 RTW89_DBG_PORT_SEL_DSPT_HDT_TX0, 239 RTW89_DBG_PORT_SEL_DSPT_HDT_TX1, 240 RTW89_DBG_PORT_SEL_DSPT_HDT_TX2, 241 RTW89_DBG_PORT_SEL_DSPT_HDT_TX3, 242 RTW89_DBG_PORT_SEL_DSPT_HDT_TX4, 243 RTW89_DBG_PORT_SEL_DSPT_HDT_TX5, 244 RTW89_DBG_PORT_SEL_DSPT_HDT_TX6, 245 RTW89_DBG_PORT_SEL_DSPT_HDT_TX7, 246 RTW89_DBG_PORT_SEL_DSPT_HDT_TX8, 247 RTW89_DBG_PORT_SEL_DSPT_HDT_TX9, 248 RTW89_DBG_PORT_SEL_DSPT_HDT_TXA, 249 RTW89_DBG_PORT_SEL_DSPT_HDT_TXB, 250 RTW89_DBG_PORT_SEL_DSPT_HDT_TXC, 251 RTW89_DBG_PORT_SEL_DSPT_HDT_TXD, 252 RTW89_DBG_PORT_SEL_DSPT_HDT_TXE, 253 RTW89_DBG_PORT_SEL_DSPT_HDT_TXF, 254 RTW89_DBG_PORT_SEL_DSPT_CDT_TX0, 255 RTW89_DBG_PORT_SEL_DSPT_CDT_TX1, 256 RTW89_DBG_PORT_SEL_DSPT_CDT_TX3, 257 RTW89_DBG_PORT_SEL_DSPT_CDT_TX4, 258 RTW89_DBG_PORT_SEL_DSPT_CDT_TX5, 259 RTW89_DBG_PORT_SEL_DSPT_CDT_TX6, 260 RTW89_DBG_PORT_SEL_DSPT_CDT_TX7, 261 RTW89_DBG_PORT_SEL_DSPT_CDT_TX8, 262 RTW89_DBG_PORT_SEL_DSPT_CDT_TX9, 263 RTW89_DBG_PORT_SEL_DSPT_CDT_TXA, 264 RTW89_DBG_PORT_SEL_DSPT_CDT_TXB, 265 RTW89_DBG_PORT_SEL_DSPT_CDT_TXC, 266 RTW89_DBG_PORT_SEL_DSPT_HDT_RX0, 267 RTW89_DBG_PORT_SEL_DSPT_HDT_RX1, 268 RTW89_DBG_PORT_SEL_DSPT_HDT_RX2, 269 RTW89_DBG_PORT_SEL_DSPT_HDT_RX3, 270 RTW89_DBG_PORT_SEL_DSPT_HDT_RX4, 271 RTW89_DBG_PORT_SEL_DSPT_HDT_RX5, 272 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0, 273 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0, 274 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1, 275 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2, 276 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1, 277 RTW89_DBG_PORT_SEL_DSPT_STF_CTRL, 278 RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL, 279 RTW89_DBG_PORT_SEL_DSPT_WDE_INTF, 280 RTW89_DBG_PORT_SEL_DSPT_PLE_INTF, 281 RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL, 282 /* PCIE related */ 283 RTW89_DBG_PORT_SEL_PCIE_TXDMA, 284 RTW89_DBG_PORT_SEL_PCIE_RXDMA, 285 RTW89_DBG_PORT_SEL_PCIE_CVT, 286 RTW89_DBG_PORT_SEL_PCIE_CXPL, 287 RTW89_DBG_PORT_SEL_PCIE_IO, 288 RTW89_DBG_PORT_SEL_PCIE_MISC, 289 RTW89_DBG_PORT_SEL_PCIE_MISC2, 290 291 /* keep last */ 292 RTW89_DBG_PORT_SEL_LAST, 293 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST, 294 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST, 295 }; 296 297 /* SRAM mem dump */ 298 #define R_AX_INDIR_ACCESS_ENTRY 0x40000 299 #define R_BE_INDIR_ACCESS_ENTRY 0x80000 300 301 #define AXIDMA_BASE_ADDR 0x18006000 302 #define STA_SCHED_BASE_ADDR 0x18808000 303 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 304 #define SECURITY_CAM_BASE_ADDR 0x18814000 305 #define WOW_CAM_BASE_ADDR 0x18815000 306 #define CMAC_TBL_BASE_ADDR 0x18840000 307 #define ADDR_CAM_BASE_ADDR 0x18850000 308 #define BSSID_CAM_BASE_ADDR 0x18853000 309 #define BA_CAM_BASE_ADDR 0x18854000 310 #define BCN_IE_CAM0_BASE_ADDR 0x18855000 311 #define SHARED_BUF_BASE_ADDR 0x18700000 312 #define DMAC_TBL_BASE_ADDR 0x18800000 313 #define SHCUT_MACHDR_BASE_ADDR 0x18800800 314 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000 315 #define TXD_FIFO_0_BASE_ADDR 0x18856200 316 #define TXD_FIFO_1_BASE_ADDR 0x188A1080 317 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */ 318 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */ 319 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000 320 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 321 #define CPU_LOCAL_BASE_ADDR 0x18003000 322 323 #define WD_PAGE_BASE_ADDR_BE 0x0 324 #define CPU_LOCAL_BASE_ADDR_BE 0x18003000 325 #define AXIDMA_BASE_ADDR_BE 0x18006000 326 #define SHARED_BUF_BASE_ADDR_BE 0x18700000 327 #define DMAC_TBL_BASE_ADDR_BE 0x18800000 328 #define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800 329 #define STA_SCHED_BASE_ADDR_BE 0x18818000 330 #define NAT25_CAM_BASE_ADDR_BE 0x18820000 331 #define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000 332 #define SEC_CAM_BASE_ADDR_BE 0x18824000 333 #define WOW_CAM_BASE_ADDR_BE 0x18828000 334 #define MLD_TBL_BASE_ADDR_BE 0x18829000 335 #define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000 336 #define CMAC_TBL_BASE_ADDR_BE 0x18840000 337 #define ADDR_CAM_BASE_ADDR_BE 0x18850000 338 #define BSSID_CAM_BASE_ADDR_BE 0x18858000 339 #define BA_CAM_BASE_ADDR_BE 0x18859000 340 #define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000 341 #define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000 342 #define TXD_FIFO_0_BASE_ADDR_BE 0x18862000 343 #define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000 344 #define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000 345 #define TXD_FIFO_1_BASE_ADDR_BE 0x18881800 346 #define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000 347 348 #define CCTL_INFO_SIZE 32 349 350 enum rtw89_mac_mem_sel { 351 RTW89_MAC_MEM_AXIDMA, 352 RTW89_MAC_MEM_SHARED_BUF, 353 RTW89_MAC_MEM_DMAC_TBL, 354 RTW89_MAC_MEM_SHCUT_MACHDR, 355 RTW89_MAC_MEM_STA_SCHED, 356 RTW89_MAC_MEM_RXPLD_FLTR_CAM, 357 RTW89_MAC_MEM_SECURITY_CAM, 358 RTW89_MAC_MEM_WOW_CAM, 359 RTW89_MAC_MEM_CMAC_TBL, 360 RTW89_MAC_MEM_ADDR_CAM, 361 RTW89_MAC_MEM_BA_CAM, 362 RTW89_MAC_MEM_BCN_IE_CAM0, 363 RTW89_MAC_MEM_BCN_IE_CAM1, 364 RTW89_MAC_MEM_TXD_FIFO_0, 365 RTW89_MAC_MEM_TXD_FIFO_1, 366 RTW89_MAC_MEM_TXDATA_FIFO_0, 367 RTW89_MAC_MEM_TXDATA_FIFO_1, 368 RTW89_MAC_MEM_CPU_LOCAL, 369 RTW89_MAC_MEM_BSSID_CAM, 370 RTW89_MAC_MEM_TXD_FIFO_0_V1, 371 RTW89_MAC_MEM_TXD_FIFO_1_V1, 372 RTW89_MAC_MEM_WD_PAGE, 373 RTW89_MAC_MEM_MLD_TBL, 374 375 /* keep last */ 376 RTW89_MAC_MEM_NUM, 377 }; 378 379 enum rtw89_rpwm_req_pwr_state { 380 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0, 381 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, 382 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2, 383 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3, 384 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4, 385 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5, 386 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6, 387 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7, 388 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX, 389 }; 390 391 struct rtw89_pwr_cfg { 392 u16 addr; 393 u8 cv_msk; 394 u8 intf_msk; 395 u8 base:4; 396 u8 cmd:4; 397 u8 msk; 398 u8 val; 399 }; 400 401 enum rtw89_mac_c2h_ofld_func { 402 RTW89_MAC_C2H_FUNC_EFUSE_DUMP, 403 RTW89_MAC_C2H_FUNC_READ_RSP, 404 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP, 405 RTW89_MAC_C2H_FUNC_BCN_RESEND, 406 RTW89_MAC_C2H_FUNC_MACID_PAUSE, 407 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6, 408 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9, 409 RTW89_MAC_C2H_FUNC_TX_DUTY_RPT = 0xa, 410 RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd, 411 RTW89_MAC_C2H_FUNC_OFLD_MAX, 412 }; 413 414 enum rtw89_mac_c2h_info_func { 415 RTW89_MAC_C2H_FUNC_REC_ACK, 416 RTW89_MAC_C2H_FUNC_DONE_ACK, 417 RTW89_MAC_C2H_FUNC_C2H_LOG, 418 RTW89_MAC_C2H_FUNC_BCN_CNT, 419 RTW89_MAC_C2H_FUNC_INFO_MAX, 420 }; 421 422 enum rtw89_mac_c2h_mcc_func { 423 RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0, 424 RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1, 425 RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2, 426 RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3, 427 428 NUM_OF_RTW89_MAC_C2H_FUNC_MCC, 429 }; 430 431 enum rtw89_mac_c2h_mlo_func { 432 RTW89_MAC_C2H_FUNC_MLO_GET_TBL = 0x0, 433 RTW89_MAC_C2H_FUNC_MLO_EMLSR_TRANS_DONE = 0x1, 434 RTW89_MAC_C2H_FUNC_MLO_EMLSR_STA_CFG_DONE = 0x2, 435 RTW89_MAC_C2H_FUNC_MCMLO_RELINK_RPT = 0x3, 436 RTW89_MAC_C2H_FUNC_MCMLO_SN_SYNC_RPT = 0x4, 437 RTW89_MAC_C2H_FUNC_MLO_LINK_CFG_STAT = 0x5, 438 RTW89_MAC_C2H_FUNC_MLO_DM_DBG_DUMP = 0x6, 439 440 NUM_OF_RTW89_MAC_C2H_FUNC_MLO, 441 }; 442 443 enum rtw89_mac_c2h_mrc_func { 444 RTW89_MAC_C2H_FUNC_MRC_TSF_RPT = 0, 445 RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT = 1, 446 447 NUM_OF_RTW89_MAC_C2H_FUNC_MRC, 448 }; 449 450 enum rtw89_mac_c2h_wow_func { 451 RTW89_MAC_C2H_FUNC_AOAC_REPORT, 452 453 NUM_OF_RTW89_MAC_C2H_FUNC_WOW, 454 }; 455 456 enum rtw89_mac_c2h_ap_func { 457 RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY = 0, 458 459 NUM_OF_RTW89_MAC_C2H_FUNC_AP, 460 }; 461 462 enum rtw89_mac_c2h_class { 463 RTW89_MAC_C2H_CLASS_INFO = 0x0, 464 RTW89_MAC_C2H_CLASS_OFLD = 0x1, 465 RTW89_MAC_C2H_CLASS_TWT = 0x2, 466 RTW89_MAC_C2H_CLASS_WOW = 0x3, 467 RTW89_MAC_C2H_CLASS_MCC = 0x4, 468 RTW89_MAC_C2H_CLASS_FWDBG = 0x5, 469 RTW89_MAC_C2H_CLASS_MLO = 0xc, 470 RTW89_MAC_C2H_CLASS_MRC = 0xe, 471 RTW89_MAC_C2H_CLASS_AP = 0x18, 472 RTW89_MAC_C2H_CLASS_MAX, 473 }; 474 475 enum rtw89_mac_mcc_status { 476 RTW89_MAC_MCC_ADD_ROLE_OK = 0, 477 RTW89_MAC_MCC_START_GROUP_OK = 1, 478 RTW89_MAC_MCC_STOP_GROUP_OK = 2, 479 RTW89_MAC_MCC_DEL_GROUP_OK = 3, 480 RTW89_MAC_MCC_RESET_GROUP_OK = 4, 481 RTW89_MAC_MCC_SWITCH_CH_OK = 5, 482 RTW89_MAC_MCC_TXNULL0_OK = 6, 483 RTW89_MAC_MCC_TXNULL1_OK = 7, 484 485 RTW89_MAC_MCC_SWITCH_EARLY = 10, 486 RTW89_MAC_MCC_TBTT = 11, 487 RTW89_MAC_MCC_DURATION_START = 12, 488 RTW89_MAC_MCC_DURATION_END = 13, 489 490 RTW89_MAC_MCC_ADD_ROLE_FAIL = 20, 491 RTW89_MAC_MCC_START_GROUP_FAIL = 21, 492 RTW89_MAC_MCC_STOP_GROUP_FAIL = 22, 493 RTW89_MAC_MCC_DEL_GROUP_FAIL = 23, 494 RTW89_MAC_MCC_RESET_GROUP_FAIL = 24, 495 RTW89_MAC_MCC_SWITCH_CH_FAIL = 25, 496 RTW89_MAC_MCC_TXNULL0_FAIL = 26, 497 RTW89_MAC_MCC_TXNULL1_FAIL = 27, 498 }; 499 500 enum rtw89_mac_mrc_status { 501 RTW89_MAC_MRC_START_SCH_OK = 0, 502 RTW89_MAC_MRC_STOP_SCH_OK = 1, 503 RTW89_MAC_MRC_DEL_SCH_OK = 2, 504 RTW89_MAC_MRC_EMPTY_SCH_FAIL = 16, 505 RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL = 17, 506 RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL = 18, 507 RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL = 19, 508 RTW89_MAC_MRC_ALT_ROLE_FAIL = 20, 509 RTW89_MAC_MRC_ADD_PSTIMER_FAIL = 21, 510 RTW89_MAC_MRC_MALLOC_FAIL = 22, 511 RTW89_MAC_MRC_SWITCH_CH_FAIL = 23, 512 RTW89_MAC_MRC_TXNULL0_FAIL = 24, 513 RTW89_MAC_MRC_PORT_FUNC_EN_FAIL = 25, 514 }; 515 516 struct rtw89_mac_ax_coex { 517 #define RTW89_MAC_AX_COEX_RTK_MODE 0 518 #define RTW89_MAC_AX_COEX_CSR_MODE 1 519 u8 pta_mode; 520 #define RTW89_MAC_AX_COEX_INNER 0 521 #define RTW89_MAC_AX_COEX_OUTPUT 1 522 #define RTW89_MAC_AX_COEX_INPUT 2 523 u8 direction; 524 }; 525 526 struct rtw89_mac_ax_plt { 527 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0) 528 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1) 529 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2) 530 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3) 531 u8 band; 532 u8 tx; 533 u8 rx; 534 }; 535 536 enum rtw89_mac_bf_rrsc_rate { 537 RTW89_MAC_BF_RRSC_6M = 0, 538 RTW89_MAC_BF_RRSC_9M = 1, 539 RTW89_MAC_BF_RRSC_12M, 540 RTW89_MAC_BF_RRSC_18M, 541 RTW89_MAC_BF_RRSC_24M, 542 RTW89_MAC_BF_RRSC_36M, 543 RTW89_MAC_BF_RRSC_48M, 544 RTW89_MAC_BF_RRSC_54M, 545 RTW89_MAC_BF_RRSC_HT_MSC0, 546 RTW89_MAC_BF_RRSC_HT_MSC1, 547 RTW89_MAC_BF_RRSC_HT_MSC2, 548 RTW89_MAC_BF_RRSC_HT_MSC3, 549 RTW89_MAC_BF_RRSC_HT_MSC4, 550 RTW89_MAC_BF_RRSC_HT_MSC5, 551 RTW89_MAC_BF_RRSC_HT_MSC6, 552 RTW89_MAC_BF_RRSC_HT_MSC7, 553 RTW89_MAC_BF_RRSC_VHT_MSC0, 554 RTW89_MAC_BF_RRSC_VHT_MSC1, 555 RTW89_MAC_BF_RRSC_VHT_MSC2, 556 RTW89_MAC_BF_RRSC_VHT_MSC3, 557 RTW89_MAC_BF_RRSC_VHT_MSC4, 558 RTW89_MAC_BF_RRSC_VHT_MSC5, 559 RTW89_MAC_BF_RRSC_VHT_MSC6, 560 RTW89_MAC_BF_RRSC_VHT_MSC7, 561 RTW89_MAC_BF_RRSC_HE_MSC0, 562 RTW89_MAC_BF_RRSC_HE_MSC1, 563 RTW89_MAC_BF_RRSC_HE_MSC2, 564 RTW89_MAC_BF_RRSC_HE_MSC3, 565 RTW89_MAC_BF_RRSC_HE_MSC4, 566 RTW89_MAC_BF_RRSC_HE_MSC5, 567 RTW89_MAC_BF_RRSC_HE_MSC6, 568 RTW89_MAC_BF_RRSC_HE_MSC7 = 31, 569 RTW89_MAC_BF_RRSC_MAX = 32 570 }; 571 572 #define RTW89_R32_EA 0xEAEAEAEA 573 #define RTW89_R32_DEAD 0xDEADBEEF 574 #define MAC_REG_POOL_COUNT 10 575 #define ACCESS_CMAC(_addr) \ 576 ({typeof(_addr) __addr = (_addr); \ 577 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; }) 578 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000 579 #define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000 580 581 #define PTCL_IDLE_POLL_CNT 10000 582 #define SW_CVR_DUR_US 8 583 #define SW_CVR_CNT 8 584 585 #define DLE_BOUND_UNIT (8 * 1024) 586 #define DLE_WAIT_CNT 2000 587 #define TRXCFG_WAIT_CNT 2000 588 589 #define RTW89_WDE_PG_64 64 590 #define RTW89_WDE_PG_128 128 591 #define RTW89_WDE_PG_256 256 592 593 #define S_AX_WDE_PAGE_SEL_64 0 594 #define S_AX_WDE_PAGE_SEL_128 1 595 #define S_AX_WDE_PAGE_SEL_256 2 596 597 #define RTW89_PLE_PG_64 64 598 #define RTW89_PLE_PG_128 128 599 #define RTW89_PLE_PG_256 256 600 601 #define S_AX_PLE_PAGE_SEL_64 0 602 #define S_AX_PLE_PAGE_SEL_128 1 603 #define S_AX_PLE_PAGE_SEL_256 2 604 605 #define B_CMAC0_MGQ_NORMAL BIT(2) 606 #define B_CMAC0_MGQ_NO_PWRSAV BIT(3) 607 #define B_CMAC0_CPUMGQ BIT(4) 608 #define B_CMAC1_MGQ_NORMAL BIT(10) 609 #define B_CMAC1_MGQ_NO_PWRSAV BIT(11) 610 #define B_CMAC1_CPUMGQ BIT(12) 611 612 #define B_CMAC0_MGQ_NORMAL_BE BIT(2) 613 #define B_CMAC1_MGQ_NORMAL_BE BIT(30) 614 615 #define QEMP_ACQ_GRP_MACID_NUM 8 616 #define QEMP_ACQ_GRP_QSEL_SH 4 617 #define QEMP_ACQ_GRP_QSEL_MASK 0xF 618 619 #define SDIO_LOCAL_BASE_ADDR 0x80000000 620 621 #define PWR_CMD_WRITE 0 622 #define PWR_CMD_POLL 1 623 #define PWR_CMD_DELAY 2 624 #define PWR_CMD_END 3 625 626 #define PWR_INTF_MSK_SDIO BIT(0) 627 #define PWR_INTF_MSK_USB BIT(1) 628 #define PWR_INTF_MSK_PCIE BIT(2) 629 #define PWR_INTF_MSK_ALL 0x7 630 631 #define PWR_BASE_MAC 0 632 #define PWR_BASE_USB 1 633 #define PWR_BASE_PCIE 2 634 #define PWR_BASE_SDIO 3 635 636 #define PWR_CV_MSK_A BIT(0) 637 #define PWR_CV_MSK_B BIT(1) 638 #define PWR_CV_MSK_C BIT(2) 639 #define PWR_CV_MSK_D BIT(3) 640 #define PWR_CV_MSK_E BIT(4) 641 #define PWR_CV_MSK_F BIT(5) 642 #define PWR_CV_MSK_G BIT(6) 643 #define PWR_CV_MSK_TEST BIT(7) 644 #define PWR_CV_MSK_ALL 0xFF 645 646 #define PWR_DELAY_US 0 647 #define PWR_DELAY_MS 1 648 649 /* STA scheduler */ 650 #define SS_MACID_SH 8 651 #define SS_TX_LEN_MSK 0x1FFFFF 652 #define SS_CTRL1_R_TX_LEN 5 653 #define SS_CTRL1_R_NEXT_LINK 20 654 #define SS_LINK_SIZE 256 655 656 /* MAC debug port */ 657 #define TMAC_DBG_SEL_C0 0xA5 658 #define RMAC_DBG_SEL_C0 0xA6 659 #define TRXPTCL_DBG_SEL_C0 0xA7 660 #define TMAC_DBG_SEL_C1 0xB5 661 #define RMAC_DBG_SEL_C1 0xB6 662 #define TRXPTCL_DBG_SEL_C1 0xB7 663 #define FW_PROG_CNTR_DBG_SEL 0xF2 664 #define PCIE_TXDMA_DBG_SEL 0x30 665 #define PCIE_RXDMA_DBG_SEL 0x31 666 #define PCIE_CVT_DBG_SEL 0x32 667 #define PCIE_CXPL_DBG_SEL 0x33 668 #define PCIE_IO_DBG_SEL 0x37 669 #define PCIE_MISC_DBG_SEL 0x38 670 #define PCIE_MISC2_DBG_SEL 0x00 671 #define MAC_DBG_SEL 1 672 #define RMAC_CMAC_DBG_SEL 1 673 674 /* TRXPTCL dbg port sel */ 675 #define TRXPTRL_DBG_SEL_TMAC 0 676 #define TRXPTRL_DBG_SEL_RMAC 1 677 678 struct rtw89_cpuio_ctrl { 679 u16 pkt_num; 680 u16 start_pktid; 681 u16 end_pktid; 682 u8 cmd_type; 683 u8 macid; 684 u8 src_pid; 685 u8 src_qid; 686 u8 dst_pid; 687 u8 dst_qid; 688 u16 pktid; 689 }; 690 691 struct rtw89_mac_dbg_port_info { 692 u32 sel_addr; 693 u8 sel_byte; 694 u32 sel_msk; 695 u32 srt; 696 u32 end; 697 u32 rd_addr; 698 u8 rd_byte; 699 u32 rd_msk; 700 }; 701 702 #define QLNKTBL_ADDR_INFO_SEL BIT(0) 703 #define QLNKTBL_ADDR_INFO_SEL_0 0 704 #define QLNKTBL_ADDR_INFO_SEL_1 1 705 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1) 706 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0) 707 708 struct rtw89_mac_dle_dfi_ctrl { 709 enum rtw89_mac_dle_ctrl_type type; 710 u32 target; 711 u32 addr; 712 u32 out_data; 713 }; 714 715 struct rtw89_mac_dle_dfi_quota { 716 enum rtw89_mac_dle_ctrl_type dle_type; 717 u32 qtaid; 718 u16 rsv_pgnum; 719 u16 use_pgnum; 720 }; 721 722 struct rtw89_mac_dle_dfi_qempty { 723 enum rtw89_mac_dle_ctrl_type dle_type; 724 u32 grpsel; 725 u32 qempty; 726 }; 727 728 enum rtw89_mac_dle_rsvd_qt_type { 729 DLE_RSVD_QT_MPDU_INFO, 730 DLE_RSVD_QT_B0_CSI, 731 DLE_RSVD_QT_B1_CSI, 732 DLE_RSVD_QT_B0_LMR, 733 DLE_RSVD_QT_B1_LMR, 734 DLE_RSVD_QT_B0_FTM, 735 DLE_RSVD_QT_B1_FTM, 736 }; 737 738 struct rtw89_mac_dle_rsvd_qt_cfg { 739 u16 pktid; 740 u16 pg_num; 741 u32 size; 742 }; 743 744 enum rtw89_mac_error_scenario { 745 RTW89_RXI300_ERROR = 1, 746 RTW89_WCPU_CPU_EXCEPTION = 2, 747 RTW89_WCPU_ASSERTION = 3, 748 }; 749 750 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28) 751 752 /* Define DBG and recovery enum */ 753 enum mac_ax_err_info { 754 /* Get error info */ 755 756 /* L0 */ 757 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001, 758 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002, 759 MAC_AX_ERR_L0_RESET_DONE = 0x0003, 760 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010, 761 762 /* L1 */ 763 MAC_AX_ERR_L1_PREERR_DMAC = 0x999, 764 MAC_AX_ERR_L1_ERR_DMAC = 0x1000, 765 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001, 766 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002, 767 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010, 768 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011, 769 770 /* L2 */ 771 /* address hole (master) */ 772 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000, 773 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010, 774 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020, 775 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030, 776 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040, 777 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050, 778 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060, 779 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070, 780 781 /* AHB bridge timeout (master) */ 782 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100, 783 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110, 784 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120, 785 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130, 786 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140, 787 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150, 788 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160, 789 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170, 790 791 /* APB_SA bridge timeout (master + slave) */ 792 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200, 793 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201, 794 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202, 795 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203, 796 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204, 797 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205, 798 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206, 799 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207, 800 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208, 801 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209, 802 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A, 803 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210, 804 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211, 805 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212, 806 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213, 807 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214, 808 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215, 809 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216, 810 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218, 811 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219, 812 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A, 813 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220, 814 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221, 815 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222, 816 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223, 817 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224, 818 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225, 819 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226, 820 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227, 821 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228, 822 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229, 823 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A, 824 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230, 825 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231, 826 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232, 827 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233, 828 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234, 829 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235, 830 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236, 831 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237, 832 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238, 833 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239, 834 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A, 835 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240, 836 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241, 837 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242, 838 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243, 839 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244, 840 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245, 841 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246, 842 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247, 843 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248, 844 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249, 845 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A, 846 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250, 847 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251, 848 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252, 849 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253, 850 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254, 851 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255, 852 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256, 853 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257, 854 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258, 855 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259, 856 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A, 857 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260, 858 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261, 859 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262, 860 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263, 861 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264, 862 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265, 863 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266, 864 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267, 865 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268, 866 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269, 867 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A, 868 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270, 869 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271, 870 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272, 871 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273, 872 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274, 873 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275, 874 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276, 875 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277, 876 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278, 877 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279, 878 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A, 879 880 /* APB_BBRF bridge timeout (master) */ 881 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300, 882 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310, 883 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320, 884 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330, 885 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340, 886 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350, 887 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360, 888 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370, 889 MAC_AX_ERR_L2_RESET_DONE = 0x2400, 890 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599, 891 MAC_AX_ERR_CPU_EXCEPTION = 0x3000, 892 MAC_AX_ERR_ASSERTION = 0x4000, 893 MAC_AX_ERR_RXI300 = 0x5000, 894 MAC_AX_GET_ERR_MAX, 895 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000, 896 897 /* set error info */ 898 MAC_AX_ERR_L1_DISABLE_EN = 0x0001, 899 MAC_AX_ERR_L1_RCVY_EN = 0x0002, 900 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003, 901 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004, 902 MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A, 903 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010, 904 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011, 905 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012, 906 MAC_AX_ERR_L0_RCVY_EN = 0x0013, 907 MAC_AX_SET_ERR_MAX, 908 }; 909 910 struct rtw89_mac_size_set { 911 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie; 912 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0; 913 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2; 914 const struct rtw89_dle_size wde_size0; 915 const struct rtw89_dle_size wde_size0_v1; 916 const struct rtw89_dle_size wde_size4; 917 const struct rtw89_dle_size wde_size4_v1; 918 const struct rtw89_dle_size wde_size6; 919 const struct rtw89_dle_size wde_size7; 920 const struct rtw89_dle_size wde_size9; 921 const struct rtw89_dle_size wde_size18; 922 const struct rtw89_dle_size wde_size19; 923 const struct rtw89_dle_size wde_size23; 924 const struct rtw89_dle_size ple_size0; 925 const struct rtw89_dle_size ple_size0_v1; 926 const struct rtw89_dle_size ple_size3_v1; 927 const struct rtw89_dle_size ple_size4; 928 const struct rtw89_dle_size ple_size6; 929 const struct rtw89_dle_size ple_size8; 930 const struct rtw89_dle_size ple_size9; 931 const struct rtw89_dle_size ple_size18; 932 const struct rtw89_dle_size ple_size19; 933 const struct rtw89_wde_quota wde_qt0; 934 const struct rtw89_wde_quota wde_qt0_v1; 935 const struct rtw89_wde_quota wde_qt4; 936 const struct rtw89_wde_quota wde_qt6; 937 const struct rtw89_wde_quota wde_qt7; 938 const struct rtw89_wde_quota wde_qt17; 939 const struct rtw89_wde_quota wde_qt18; 940 const struct rtw89_wde_quota wde_qt23; 941 const struct rtw89_ple_quota ple_qt0; 942 const struct rtw89_ple_quota ple_qt1; 943 const struct rtw89_ple_quota ple_qt4; 944 const struct rtw89_ple_quota ple_qt5; 945 const struct rtw89_ple_quota ple_qt9; 946 const struct rtw89_ple_quota ple_qt13; 947 const struct rtw89_ple_quota ple_qt18; 948 const struct rtw89_ple_quota ple_qt44; 949 const struct rtw89_ple_quota ple_qt45; 950 const struct rtw89_ple_quota ple_qt46; 951 const struct rtw89_ple_quota ple_qt47; 952 const struct rtw89_ple_quota ple_qt57; 953 const struct rtw89_ple_quota ple_qt58; 954 const struct rtw89_ple_quota ple_qt59; 955 const struct rtw89_ple_quota ple_qt_52a_wow; 956 const struct rtw89_ple_quota ple_qt_52b_wow; 957 const struct rtw89_ple_quota ple_qt_52bt_wow; 958 const struct rtw89_ple_quota ple_qt_51b_wow; 959 const struct rtw89_rsvd_quota ple_rsvd_qt0; 960 const struct rtw89_rsvd_quota ple_rsvd_qt1; 961 const struct rtw89_dle_rsvd_size rsvd0_size0; 962 const struct rtw89_dle_rsvd_size rsvd1_size0; 963 }; 964 965 extern const struct rtw89_mac_size_set rtw89_mac_size; 966 967 struct rtw89_mac_gen_def { 968 u32 band1_offset; 969 u32 filter_model_addr; 970 u32 indir_access_addr; 971 const u32 *mem_base_addrs; 972 u32 rx_fltr; 973 const struct rtw89_port_reg *port_base; 974 u32 agg_len_ht; 975 u32 ps_status; 976 977 struct rtw89_reg_def muedca_ctrl; 978 struct rtw89_reg_def bfee_ctrl; 979 struct rtw89_reg_def narrow_bw_ru_dis; 980 struct rtw89_reg_def wow_ctrl; 981 struct rtw89_reg_def agg_limit; 982 struct rtw89_reg_def txcnt_limit; 983 984 int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band, 985 enum rtw89_mac_hwmod_sel sel); 986 int (*sys_init)(struct rtw89_dev *rtwdev); 987 int (*trx_init)(struct rtw89_dev *rtwdev); 988 void (*hci_func_en)(struct rtw89_dev *rtwdev); 989 void (*dmac_func_pre_en)(struct rtw89_dev *rtwdev); 990 void (*dle_func_en)(struct rtw89_dev *rtwdev, bool enable); 991 void (*dle_clk_en)(struct rtw89_dev *rtwdev, bool enable); 992 void (*bf_assoc)(struct rtw89_dev *rtwdev, 993 struct rtw89_vif_link *rtwvif_link, 994 struct rtw89_sta_link *rtwsta_link); 995 996 int (*typ_fltr_opt)(struct rtw89_dev *rtwdev, 997 enum rtw89_machdr_frame_type type, 998 enum rtw89_mac_fwd_target fwd_target, 999 u8 mac_idx); 1000 int (*cfg_ppdu_status)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable); 1001 void (*cfg_phy_rpt)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable); 1002 1003 int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg); 1004 int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple); 1005 int (*dle_buf_req)(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id); 1006 void (*hfc_func_en)(struct rtw89_dev *rtwdev, bool en, bool h2c_en); 1007 void (*hfc_h2c_cfg)(struct rtw89_dev *rtwdev); 1008 void (*hfc_mix_cfg)(struct rtw89_dev *rtwdev); 1009 void (*hfc_get_mix_info)(struct rtw89_dev *rtwdev); 1010 void (*wde_quota_cfg)(struct rtw89_dev *rtwdev, 1011 const struct rtw89_wde_quota *min_cfg, 1012 const struct rtw89_wde_quota *max_cfg, 1013 u16 ext_wde_min_qt_wcpu); 1014 void (*ple_quota_cfg)(struct rtw89_dev *rtwdev, 1015 const struct rtw89_ple_quota *min_cfg, 1016 const struct rtw89_ple_quota *max_cfg); 1017 int (*set_cpuio)(struct rtw89_dev *rtwdev, 1018 struct rtw89_cpuio_ctrl *ctrl_para, bool wd); 1019 int (*dle_quota_change)(struct rtw89_dev *rtwdev, bool band1_en); 1020 1021 void (*disable_cpu)(struct rtw89_dev *rtwdev); 1022 int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason, 1023 bool dlfw, bool include_bb); 1024 u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type); 1025 int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl); 1026 void (*fwdl_secure_idmem_share_mode)(struct rtw89_dev *rtwdev, u8 mode); 1027 int (*parse_efuse_map)(struct rtw89_dev *rtwdev); 1028 int (*parse_phycap_map)(struct rtw89_dev *rtwdev); 1029 int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle); 1030 int (*efuse_read_fw_secure)(struct rtw89_dev *rtwdev); 1031 1032 int (*cfg_plt)(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); 1033 u16 (*get_plt_cnt)(struct rtw89_dev *rtwdev, u8 band); 1034 1035 bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev, 1036 enum rtw89_phy_idx phy_idx, 1037 u32 reg_base, u32 *cr); 1038 1039 int (*write_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask); 1040 int (*read_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 *val); 1041 1042 void (*dump_qta_lost)(struct rtw89_dev *rtwdev); 1043 void (*dump_err_status)(struct rtw89_dev *rtwdev, 1044 enum mac_ax_err_info err); 1045 1046 bool (*is_txq_empty)(struct rtw89_dev *rtwdev); 1047 1048 int (*prep_chan_list)(struct rtw89_dev *rtwdev, 1049 struct rtw89_vif_link *rtwvif_link); 1050 void (*free_chan_list)(struct rtw89_dev *rtwdev); 1051 int (*add_chan_list)(struct rtw89_dev *rtwdev, 1052 struct rtw89_vif_link *rtwvif_link); 1053 int (*add_chan_list_pno)(struct rtw89_dev *rtwdev, 1054 struct rtw89_vif_link *rtwvif_link); 1055 int (*scan_offload)(struct rtw89_dev *rtwdev, 1056 struct rtw89_scan_option *option, 1057 struct rtw89_vif_link *rtwvif_link, 1058 bool wowlan); 1059 1060 int (*wow_config_mac)(struct rtw89_dev *rtwdev, bool enable_wow); 1061 }; 1062 1063 extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax; 1064 extern const struct rtw89_mac_gen_def rtw89_mac_gen_be; 1065 1066 static inline 1067 u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band) 1068 { 1069 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1070 1071 return band == 0 ? reg_base : (reg_base + mac->band1_offset); 1072 } 1073 1074 static inline 1075 u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx) 1076 { 1077 return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx); 1078 } 1079 1080 static inline u32 1081 rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, u32 base) 1082 { 1083 u32 reg; 1084 1085 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1086 rtwvif_link->mac_idx); 1087 return rtw89_read32(rtwdev, reg); 1088 } 1089 1090 static inline u32 1091 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1092 u32 base, u32 mask) 1093 { 1094 u32 reg; 1095 1096 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1097 rtwvif_link->mac_idx); 1098 return rtw89_read32_mask(rtwdev, reg, mask); 1099 } 1100 1101 static inline void 1102 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, u32 base, 1103 u32 data) 1104 { 1105 u32 reg; 1106 1107 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1108 rtwvif_link->mac_idx); 1109 rtw89_write32(rtwdev, reg, data); 1110 } 1111 1112 static inline void 1113 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1114 u32 base, u32 mask, u32 data) 1115 { 1116 u32 reg; 1117 1118 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1119 rtwvif_link->mac_idx); 1120 rtw89_write32_mask(rtwdev, reg, mask, data); 1121 } 1122 1123 static inline void 1124 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1125 u32 base, u32 mask, u16 data) 1126 { 1127 u32 reg; 1128 1129 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1130 rtwvif_link->mac_idx); 1131 rtw89_write16_mask(rtwdev, reg, mask, data); 1132 } 1133 1134 static inline void 1135 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1136 u32 base, u32 bit) 1137 { 1138 u32 reg; 1139 1140 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1141 rtwvif_link->mac_idx); 1142 rtw89_write32_clr(rtwdev, reg, bit); 1143 } 1144 1145 static inline void 1146 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1147 u32 base, u16 bit) 1148 { 1149 u32 reg; 1150 1151 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1152 rtwvif_link->mac_idx); 1153 rtw89_write16_clr(rtwdev, reg, bit); 1154 } 1155 1156 static inline void 1157 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1158 u32 base, u32 bit) 1159 { 1160 u32 reg; 1161 1162 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1163 rtwvif_link->mac_idx); 1164 rtw89_write32_set(rtwdev, reg, bit); 1165 } 1166 1167 int rtw89_mac_pwr_on(struct rtw89_dev *rtwdev); 1168 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); 1169 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb); 1170 int rtw89_mac_init(struct rtw89_dev *rtwdev); 1171 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1172 enum rtw89_qta_mode ext_mode); 1173 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en); 1174 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1175 enum rtw89_qta_mode mode); 1176 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode); 1177 static inline 1178 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, 1179 enum rtw89_mac_hwmod_sel sel) 1180 { 1181 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1182 1183 return mac->check_mac_en(rtwdev, band, sel); 1184 } 1185 1186 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); 1187 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); 1188 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl); 1189 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 1190 struct rtw89_mac_dle_dfi_quota *quota); 1191 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev); 1192 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 1193 struct rtw89_mac_dle_dfi_qempty *qempty); 1194 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 1195 enum mac_ax_err_info err); 1196 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif); 1197 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 1198 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 1199 struct rtw89_vif_link *rtwvif_link, 1200 struct rtw89_vif_link *rtwvif_src, 1201 u16 offset_tu); 1202 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1203 u64 *tsf); 1204 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 1205 struct rtw89_vif_link *rtwvif_link, bool en); 1206 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 1207 struct rtw89_vif_link *rtwvif_link); 1208 void rtw89_mac_set_he_tb(struct rtw89_dev *rtwdev, 1209 struct rtw89_vif_link *rtwvif_link); 1210 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 1211 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en); 1212 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif); 1213 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); 1214 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); 1215 1216 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev) 1217 { 1218 const struct rtw89_chip_info *chip = rtwdev->chip; 1219 1220 return chip->ops->enable_bb_rf(rtwdev); 1221 } 1222 1223 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev) 1224 { 1225 const struct rtw89_chip_info *chip = rtwdev->chip; 1226 1227 return chip->ops->disable_bb_rf(rtwdev); 1228 } 1229 1230 static inline int rtw89_chip_reset_bb_rf(struct rtw89_dev *rtwdev) 1231 { 1232 int ret; 1233 1234 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 1235 return 0; 1236 1237 ret = rtw89_chip_disable_bb_rf(rtwdev); 1238 if (ret) 1239 return ret; 1240 ret = rtw89_chip_enable_bb_rf(rtwdev); 1241 if (ret) 1242 return ret; 1243 1244 return 0; 1245 } 1246 1247 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); 1248 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); 1249 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 1250 u8 class, u8 func); 1251 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1252 u32 len, u8 class, u8 func); 1253 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); 1254 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 1255 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1256 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 1257 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1258 int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, 1259 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1260 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1261 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1262 int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1263 void rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable); 1264 1265 static inline 1266 void rtw89_mac_cfg_phy_rpt(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 1267 { 1268 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1269 1270 if (mac->cfg_phy_rpt) 1271 mac->cfg_phy_rpt(rtwdev, mac_idx, enable); 1272 } 1273 1274 static inline 1275 void rtw89_mac_cfg_phy_rpt_bands(struct rtw89_dev *rtwdev, bool enable) 1276 { 1277 rtw89_mac_cfg_phy_rpt(rtwdev, RTW89_MAC_0, enable); 1278 1279 if (!rtwdev->dbcc_en) 1280 return; 1281 1282 rtw89_mac_cfg_phy_rpt(rtwdev, RTW89_MAC_1, enable); 1283 } 1284 1285 static inline 1286 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 1287 { 1288 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1289 1290 return mac->cfg_ppdu_status(rtwdev, mac_idx, enable); 1291 } 1292 1293 static inline 1294 int rtw89_mac_cfg_ppdu_status_bands(struct rtw89_dev *rtwdev, bool enable) 1295 { 1296 int ret; 1297 1298 ret = rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, enable); 1299 if (ret) 1300 return ret; 1301 1302 if (!rtwdev->dbcc_en) 1303 return 0; 1304 1305 return rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_1, enable); 1306 } 1307 1308 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev); 1309 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); 1310 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); 1311 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 1312 const struct rtw89_mac_ax_coex *coex); 1313 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 1314 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1315 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 1316 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1317 int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev, 1318 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1319 1320 static inline 1321 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 1322 { 1323 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1324 1325 return mac->cfg_plt(rtwdev, plt); 1326 } 1327 1328 static inline 1329 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 1330 { 1331 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1332 1333 return mac->get_plt_cnt(rtwdev, band); 1334 } 1335 1336 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); 1337 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); 1338 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); 1339 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); 1340 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl); 1341 int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl); 1342 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); 1343 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev); 1344 1345 static inline 1346 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, 1347 struct rtw89_vif_link *rtwvif_link, 1348 struct rtw89_sta_link *rtwsta_link) 1349 { 1350 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1351 1352 if (mac->bf_assoc) 1353 mac->bf_assoc(rtwdev, rtwvif_link, rtwsta_link); 1354 } 1355 1356 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, 1357 struct rtw89_vif_link *rtwvif_link, 1358 struct rtw89_sta_link *rtwsta_link); 1359 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1360 struct ieee80211_bss_conf *conf); 1361 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 1362 struct rtw89_sta_link *rtwsta_link, 1363 bool disconnect); 1364 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev); 1365 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en); 1366 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 1367 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 1368 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 1369 struct rtw89_vif_link *rtwvif_link, bool en); 1370 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause); 1371 1372 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 1373 { 1374 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 1375 return; 1376 1377 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags)) 1378 return; 1379 1380 _rtw89_mac_bf_monitor_track(rtwdev); 1381 } 1382 1383 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, 1384 enum rtw89_phy_idx phy_idx, 1385 u32 reg_base, u32 *val) 1386 { 1387 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1388 u32 cr; 1389 1390 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1391 return -EINVAL; 1392 1393 *val = rtw89_read32(rtwdev, cr); 1394 return 0; 1395 } 1396 1397 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, 1398 enum rtw89_phy_idx phy_idx, 1399 u32 reg_base, u32 val) 1400 { 1401 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1402 u32 cr; 1403 1404 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1405 return -EINVAL; 1406 1407 rtw89_write32(rtwdev, cr, val); 1408 return 0; 1409 } 1410 1411 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, 1412 enum rtw89_phy_idx phy_idx, 1413 u32 reg_base, u32 mask, u32 val) 1414 { 1415 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1416 u32 cr; 1417 1418 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1419 return -EINVAL; 1420 1421 rtw89_write32_mask(rtwdev, cr, mask, val); 1422 return 0; 1423 } 1424 1425 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev, 1426 bool enable) 1427 { 1428 const struct rtw89_chip_info *chip = rtwdev->chip; 1429 1430 if (enable) 1431 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1432 B_AX_HCI_TXDMA_EN); 1433 else 1434 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1435 B_AX_HCI_TXDMA_EN); 1436 } 1437 1438 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev, 1439 bool enable) 1440 { 1441 const struct rtw89_chip_info *chip = rtwdev->chip; 1442 1443 if (enable) 1444 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1445 B_AX_HCI_RXDMA_EN); 1446 else 1447 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1448 B_AX_HCI_RXDMA_EN); 1449 } 1450 1451 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev, 1452 bool enable) 1453 { 1454 const struct rtw89_chip_info *chip = rtwdev->chip; 1455 1456 if (enable) 1457 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1458 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 1459 else 1460 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1461 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 1462 } 1463 1464 static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev) 1465 { 1466 u32 val; 1467 1468 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, 1469 B_AX_WLMAC_PWR_STE_MASK); 1470 1471 return !!val; 1472 } 1473 1474 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 1475 bool resume, u32 tx_time); 1476 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 1477 u32 *tx_time); 1478 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 1479 struct rtw89_sta_link *rtwsta_link, 1480 bool resume, u8 tx_retry); 1481 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 1482 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry); 1483 1484 enum rtw89_mac_xtal_si_offset { 1485 XTAL0 = 0x0, 1486 XTAL3 = 0x3, 1487 XTAL_SI_XTAL_SC_XI = 0x04, 1488 #define XTAL_SC_XI_MASK GENMASK(7, 0) 1489 XTAL_SI_XTAL_SC_XO = 0x05, 1490 #define XTAL_SC_XO_MASK GENMASK(7, 0) 1491 XTAL_SI_XREF_MODE = 0x0B, 1492 XTAL_SI_PWR_CUT = 0x10, 1493 #define XTAL_SI_SMALL_PWR_CUT BIT(0) 1494 #define XTAL_SI_BIG_PWR_CUT BIT(1) 1495 XTAL_SI_XTAL_DRV = 0x15, 1496 #define XTAL_SI_DRV_LATCH BIT(4) 1497 XTAL_SI_XTAL_PLL = 0x16, 1498 XTAL_SI_XTAL_XMD_2 = 0x24, 1499 #define XTAL_SI_LDO_LPS GENMASK(6, 4) 1500 XTAL_SI_XTAL_XMD_4 = 0x26, 1501 #define XTAL_SI_LPS_CAP GENMASK(3, 0) 1502 XTAL_SI_XREF_RF1 = 0x2D, 1503 XTAL_SI_XREF_RF2 = 0x2E, 1504 XTAL_SI_CV = 0x41, 1505 #define XTAL_SI_ACV_MASK GENMASK(3, 0) 1506 XTAL_SI_LOW_ADDR = 0x62, 1507 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0) 1508 XTAL_SI_CTRL = 0x63, 1509 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6) 1510 #define XTAL_SI_RDY BIT(5) 1511 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0) 1512 XTAL_SI_READ_VAL = 0x7A, 1513 XTAL_SI_WL_RFC_S0 = 0x80, 1514 #define XTAL_SI_RF00S_EN GENMASK(2, 0) 1515 #define XTAL_SI_RF00 BIT(0) 1516 XTAL_SI_WL_RFC_S1 = 0x81, 1517 #define XTAL_SI_RF10S_EN GENMASK(2, 0) 1518 #define XTAL_SI_RF10 BIT(0) 1519 XTAL_SI_ANAPAR_WL = 0x90, 1520 #define XTAL_SI_SRAM2RFC BIT(7) 1521 #define XTAL_SI_GND_SHDN_WL BIT(6) 1522 #define XTAL_SI_SHDN_WL BIT(5) 1523 #define XTAL_SI_RFC2RF BIT(4) 1524 #define XTAL_SI_OFF_EI BIT(3) 1525 #define XTAL_SI_OFF_WEI BIT(2) 1526 #define XTAL_SI_PON_EI BIT(1) 1527 #define XTAL_SI_PON_WEI BIT(0) 1528 XTAL_SI_SRAM_CTRL = 0xA1, 1529 #define XTAL_SI_SRAM_DIS BIT(1) 1530 #define FULL_BIT_MASK GENMASK(7, 0) 1531 XTAL_SI_APBT = 0xD1, 1532 XTAL_SI_PLL = 0xE0, 1533 XTAL_SI_PLL_1 = 0xE1, 1534 }; 1535 1536 static inline 1537 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 1538 { 1539 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1540 1541 return mac->write_xtal_si(rtwdev, offset, val, mask); 1542 } 1543 1544 static inline 1545 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 1546 { 1547 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1548 1549 return mac->read_xtal_si(rtwdev, offset, val); 1550 } 1551 1552 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1553 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow); 1554 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 1555 enum rtw89_mac_idx band); 1556 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow); 1557 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1558 bool band1_en); 1559 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1560 enum rtw89_mac_dle_rsvd_qt_type type, 1561 struct rtw89_mac_dle_rsvd_qt_cfg *cfg); 1562 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable); 1563 1564 static inline 1565 void rtw89_fwdl_secure_idmem_share_mode(struct rtw89_dev *rtwdev, u8 mode) 1566 { 1567 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1568 1569 if (!mac->fwdl_secure_idmem_share_mode) 1570 return; 1571 1572 return mac->fwdl_secure_idmem_share_mode(rtwdev, mode); 1573 } 1574 #endif 1575