11ccea77eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2e5553f08SGabor Juhos /* Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com> 3e5553f08SGabor Juhos * Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 4e5553f08SGabor Juhos * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 5e5553f08SGabor Juhos * Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 6e5553f08SGabor Juhos * Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 7e5553f08SGabor Juhos * Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 8e5553f08SGabor Juhos * Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 9e5553f08SGabor Juhos * Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com> 10e5553f08SGabor Juhos * <http://rt2x00.serialmonkey.com> 11e5553f08SGabor Juhos */ 12e5553f08SGabor Juhos 13e5553f08SGabor Juhos /* Module: rt2800mmio 14e5553f08SGabor Juhos * Abstract: forward declarations for the rt2800mmio module. 15e5553f08SGabor Juhos */ 16e5553f08SGabor Juhos 17e5553f08SGabor Juhos #ifndef RT2800MMIO_H 18e5553f08SGabor Juhos #define RT2800MMIO_H 19e5553f08SGabor Juhos 200bc202b3SGabor Juhos /* 21d5580adeSGabor Juhos * Queue register offset macros 22d5580adeSGabor Juhos */ 23d5580adeSGabor Juhos #define TX_QUEUE_REG_OFFSET 0x10 24d5580adeSGabor Juhos #define TX_BASE_PTR(__x) (TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)) 25d5580adeSGabor Juhos #define TX_MAX_CNT(__x) (TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)) 26d5580adeSGabor Juhos #define TX_CTX_IDX(__x) (TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)) 27d5580adeSGabor Juhos #define TX_DTX_IDX(__x) (TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)) 28d5580adeSGabor Juhos 29d5580adeSGabor Juhos /* 300bc202b3SGabor Juhos * DMA descriptor defines. 310bc202b3SGabor Juhos */ 320bc202b3SGabor Juhos #define TXD_DESC_SIZE (4 * sizeof(__le32)) 339732497dSGabor Juhos #define RXD_DESC_SIZE (4 * sizeof(__le32)) 340bc202b3SGabor Juhos 350bc202b3SGabor Juhos /* 360bc202b3SGabor Juhos * TX descriptor format for TX, PRIO and Beacon Ring. 370bc202b3SGabor Juhos */ 380bc202b3SGabor Juhos 390bc202b3SGabor Juhos /* 400bc202b3SGabor Juhos * Word0 410bc202b3SGabor Juhos */ 420bc202b3SGabor Juhos #define TXD_W0_SD_PTR0 FIELD32(0xffffffff) 430bc202b3SGabor Juhos 440bc202b3SGabor Juhos /* 450bc202b3SGabor Juhos * Word1 460bc202b3SGabor Juhos */ 470bc202b3SGabor Juhos #define TXD_W1_SD_LEN1 FIELD32(0x00003fff) 480bc202b3SGabor Juhos #define TXD_W1_LAST_SEC1 FIELD32(0x00004000) 490bc202b3SGabor Juhos #define TXD_W1_BURST FIELD32(0x00008000) 500bc202b3SGabor Juhos #define TXD_W1_SD_LEN0 FIELD32(0x3fff0000) 510bc202b3SGabor Juhos #define TXD_W1_LAST_SEC0 FIELD32(0x40000000) 520bc202b3SGabor Juhos #define TXD_W1_DMA_DONE FIELD32(0x80000000) 530bc202b3SGabor Juhos 540bc202b3SGabor Juhos /* 550bc202b3SGabor Juhos * Word2 560bc202b3SGabor Juhos */ 570bc202b3SGabor Juhos #define TXD_W2_SD_PTR1 FIELD32(0xffffffff) 580bc202b3SGabor Juhos 590bc202b3SGabor Juhos /* 600bc202b3SGabor Juhos * Word3 610bc202b3SGabor Juhos * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI 620bc202b3SGabor Juhos * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler. 630bc202b3SGabor Juhos * 0:MGMT, 1:HCCA 2:EDCA 640bc202b3SGabor Juhos */ 650bc202b3SGabor Juhos #define TXD_W3_WIV FIELD32(0x01000000) 660bc202b3SGabor Juhos #define TXD_W3_QSEL FIELD32(0x06000000) 670bc202b3SGabor Juhos #define TXD_W3_TCO FIELD32(0x20000000) 680bc202b3SGabor Juhos #define TXD_W3_UCO FIELD32(0x40000000) 690bc202b3SGabor Juhos #define TXD_W3_ICO FIELD32(0x80000000) 700bc202b3SGabor Juhos 719732497dSGabor Juhos /* 729732497dSGabor Juhos * RX descriptor format for RX Ring. 739732497dSGabor Juhos */ 749732497dSGabor Juhos 759732497dSGabor Juhos /* 769732497dSGabor Juhos * Word0 779732497dSGabor Juhos */ 789732497dSGabor Juhos #define RXD_W0_SDP0 FIELD32(0xffffffff) 799732497dSGabor Juhos 809732497dSGabor Juhos /* 819732497dSGabor Juhos * Word1 829732497dSGabor Juhos */ 839732497dSGabor Juhos #define RXD_W1_SDL1 FIELD32(0x00003fff) 849732497dSGabor Juhos #define RXD_W1_SDL0 FIELD32(0x3fff0000) 859732497dSGabor Juhos #define RXD_W1_LS0 FIELD32(0x40000000) 869732497dSGabor Juhos #define RXD_W1_DMA_DONE FIELD32(0x80000000) 879732497dSGabor Juhos 889732497dSGabor Juhos /* 899732497dSGabor Juhos * Word2 909732497dSGabor Juhos */ 919732497dSGabor Juhos #define RXD_W2_SDP1 FIELD32(0xffffffff) 929732497dSGabor Juhos 939732497dSGabor Juhos /* 949732497dSGabor Juhos * Word3 959732497dSGabor Juhos * AMSDU: RX with 802.3 header, not 802.11 header. 969732497dSGabor Juhos * DECRYPTED: This frame is being decrypted. 979732497dSGabor Juhos */ 989732497dSGabor Juhos #define RXD_W3_BA FIELD32(0x00000001) 999732497dSGabor Juhos #define RXD_W3_DATA FIELD32(0x00000002) 1009732497dSGabor Juhos #define RXD_W3_NULLDATA FIELD32(0x00000004) 1019732497dSGabor Juhos #define RXD_W3_FRAG FIELD32(0x00000008) 1029732497dSGabor Juhos #define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010) 1039732497dSGabor Juhos #define RXD_W3_MULTICAST FIELD32(0x00000020) 1049732497dSGabor Juhos #define RXD_W3_BROADCAST FIELD32(0x00000040) 1059732497dSGabor Juhos #define RXD_W3_MY_BSS FIELD32(0x00000080) 1069732497dSGabor Juhos #define RXD_W3_CRC_ERROR FIELD32(0x00000100) 1079732497dSGabor Juhos #define RXD_W3_CIPHER_ERROR FIELD32(0x00000600) 1089732497dSGabor Juhos #define RXD_W3_AMSDU FIELD32(0x00000800) 1099732497dSGabor Juhos #define RXD_W3_HTC FIELD32(0x00001000) 1109732497dSGabor Juhos #define RXD_W3_RSSI FIELD32(0x00002000) 1119732497dSGabor Juhos #define RXD_W3_L2PAD FIELD32(0x00004000) 1129732497dSGabor Juhos #define RXD_W3_AMPDU FIELD32(0x00008000) 1139732497dSGabor Juhos #define RXD_W3_DECRYPTED FIELD32(0x00010000) 1149732497dSGabor Juhos #define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000) 1159732497dSGabor Juhos #define RXD_W3_PLCP_RSSI FIELD32(0x00040000) 1160bc202b3SGabor Juhos 1172034afe4SStanislaw Gruszka unsigned int rt2800mmio_get_dma_done(struct data_queue *queue); 1182034afe4SStanislaw Gruszka 1190bc202b3SGabor Juhos /* TX descriptor initialization */ 1200bc202b3SGabor Juhos __le32 *rt2800mmio_get_txwi(struct queue_entry *entry); 1210bc202b3SGabor Juhos void rt2800mmio_write_tx_desc(struct queue_entry *entry, 1220bc202b3SGabor Juhos struct txentry_desc *txdesc); 1230bc202b3SGabor Juhos 1249732497dSGabor Juhos /* RX control handlers */ 1259732497dSGabor Juhos void rt2800mmio_fill_rxdone(struct queue_entry *entry, 1269732497dSGabor Juhos struct rxdone_entry_desc *rxdesc); 1279732497dSGabor Juhos 1288d03e772SGabor Juhos /* Interrupt functions */ 129*a0d6ea9bSAllen Pais void rt2800mmio_txstatus_tasklet(struct tasklet_struct *t); 130*a0d6ea9bSAllen Pais void rt2800mmio_pretbtt_tasklet(struct tasklet_struct *t); 131*a0d6ea9bSAllen Pais void rt2800mmio_tbtt_tasklet(struct tasklet_struct *t); 132*a0d6ea9bSAllen Pais void rt2800mmio_rxdone_tasklet(struct tasklet_struct *t); 133*a0d6ea9bSAllen Pais void rt2800mmio_autowake_tasklet(struct tasklet_struct *t); 1348d03e772SGabor Juhos irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance); 1358d03e772SGabor Juhos void rt2800mmio_toggle_irq(struct rt2x00_dev *rt2x00dev, 1368d03e772SGabor Juhos enum dev_state state); 1379732497dSGabor Juhos 138d5580adeSGabor Juhos /* Queue handlers */ 139d5580adeSGabor Juhos void rt2800mmio_start_queue(struct data_queue *queue); 140d5580adeSGabor Juhos void rt2800mmio_kick_queue(struct data_queue *queue); 14102405644SStanislaw Gruszka void rt2800mmio_flush_queue(struct data_queue *queue, bool drop); 142d5580adeSGabor Juhos void rt2800mmio_stop_queue(struct data_queue *queue); 143d5580adeSGabor Juhos void rt2800mmio_queue_init(struct data_queue *queue); 144d5580adeSGabor Juhos 1451052e3a6SGabor Juhos /* Initialization functions */ 146e5ceab9dSStanislaw Gruszka int rt2800mmio_probe_hw(struct rt2x00_dev *rt2x00dev); 1471052e3a6SGabor Juhos bool rt2800mmio_get_entry_state(struct queue_entry *entry); 1481052e3a6SGabor Juhos void rt2800mmio_clear_entry(struct queue_entry *entry); 1491052e3a6SGabor Juhos int rt2800mmio_init_queues(struct rt2x00_dev *rt2x00dev); 1501052e3a6SGabor Juhos int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev); 1511052e3a6SGabor Juhos 1523ccdcd51SGabor Juhos /* Device state switch handlers. */ 1533ccdcd51SGabor Juhos int rt2800mmio_enable_radio(struct rt2x00_dev *rt2x00dev); 1543ccdcd51SGabor Juhos 155e5553f08SGabor Juhos #endif /* RT2800MMIO_H */ 156