1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #ifndef __MT7996_REGS_H 7 #define __MT7996_REGS_H 8 9 struct __map { 10 u32 phys; 11 u32 mapped; 12 u32 size; 13 }; 14 15 struct __base { 16 u32 band_base[__MT_MAX_BAND]; 17 }; 18 19 /* used to differentiate between generations */ 20 struct mt7996_reg_desc { 21 const struct __base *base; 22 const struct __map *map; 23 u32 map_size; 24 }; 25 26 enum base_rev { 27 WF_AGG_BASE, 28 WF_ARB_BASE, 29 WF_TMAC_BASE, 30 WF_RMAC_BASE, 31 WF_DMA_BASE, 32 WF_WTBLOFF_BASE, 33 WF_ETBF_BASE, 34 WF_LPON_BASE, 35 WF_MIB_BASE, 36 WF_RATE_BASE, 37 __MT_REG_BASE_MAX, 38 }; 39 40 #define __BASE(_id, _band) (dev->reg.base[(_id)].band_base[(_band)]) 41 42 /* RRO TOP */ 43 #define MT_RRO_TOP_BASE 0xA000 44 #define MT_RRO_TOP(ofs) (MT_RRO_TOP_BASE + (ofs)) 45 46 #define MT_RRO_BA_BITMAP_BASE0 MT_RRO_TOP(0x8) 47 #define MT_RRO_BA_BITMAP_BASE1 MT_RRO_TOP(0xC) 48 #define WF_RRO_AXI_MST_CFG MT_RRO_TOP(0xB8) 49 #define WF_RRO_AXI_MST_CFG_DIDX_OK BIT(12) 50 #define MT_RRO_ADDR_ARRAY_BASE1 MT_RRO_TOP(0x34) 51 #define MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE BIT(31) 52 53 #define MT_RRO_IND_CMD_SIGNATURE_BASE0 MT_RRO_TOP(0x38) 54 #define MT_RRO_IND_CMD_SIGNATURE_BASE1 MT_RRO_TOP(0x3C) 55 #define MT_RRO_IND_CMD_0_CTRL0 MT_RRO_TOP(0x40) 56 #define MT_RRO_IND_CMD_SIGNATURE_BASE1_EN BIT(31) 57 58 #define MT_RRO_PARTICULAR_CFG0 MT_RRO_TOP(0x5C) 59 #define MT_RRO_PARTICULAR_CFG1 MT_RRO_TOP(0x60) 60 #define MT_RRO_PARTICULAR_CONFG_EN BIT(31) 61 #define MT_RRO_PARTICULAR_SID GENMASK(30, 16) 62 63 #define MT_RRO_BA_BITMAP_BASE_EXT0 MT_RRO_TOP(0x70) 64 #define MT_RRO_BA_BITMAP_BASE_EXT1 MT_RRO_TOP(0x74) 65 #define MT_RRO_HOST_INT_ENA MT_RRO_TOP(0x204) 66 #define MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA BIT(0) 67 68 #define MT_RRO_ADDR_ELEM_SEG_ADDR0 MT_RRO_TOP(0x400) 69 70 #define MT_RRO_ACK_SN_CTRL MT_RRO_TOP(0x50) 71 #define MT_RRO_ACK_SN_CTRL_SN_MASK GENMASK(27, 16) 72 #define MT_RRO_ACK_SN_CTRL_SESSION_MASK GENMASK(11, 0) 73 74 #define MT_RRO_DBG_RD_CTRL MT_RRO_TOP(0xe0) 75 #define MT_RRO_DBG_RD_ADDR GENMASK(15, 0) 76 #define MT_RRO_DBG_RD_EXEC BIT(31) 77 78 #define MT_RRO_DBG_RDAT_DW(_n) MT_RRO_TOP(0xf0 + (_n) * 0x4) 79 80 #define MT_MCU_INT_EVENT 0x2108 81 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0) 82 #define MT_MCU_INT_EVENT_DMA_INIT BIT(1) 83 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3) 84 85 /* PLE */ 86 #define MT_PLE_BASE 0x820c0000 87 #define MT_PLE(ofs) (MT_PLE_BASE + (ofs)) 88 89 #define MT_FL_Q_EMPTY MT_PLE(0x360) 90 #define MT_FL_Q0_CTRL MT_PLE(0x3e0) 91 #define MT_FL_Q2_CTRL MT_PLE(0x3e8) 92 #define MT_FL_Q3_CTRL MT_PLE(0x3ec) 93 94 #define MT_PLE_FREEPG_CNT MT_PLE(0x380) 95 #define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(0x384) 96 #define MT_PLE_PG_HIF_GROUP MT_PLE(0x00c) 97 #define MT_PLE_HIF_PG_INFO MT_PLE(0x388) 98 99 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x600 + 0x80 * (ac) + ((n) << 2)) 100 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2)) 101 102 /* WF MDP TOP */ 103 #define MT_MDP_BASE 0x820cc000 104 #define MT_MDP(ofs) (MT_MDP_BASE + (ofs)) 105 106 #define MT_MDP_DCR2 MT_MDP(0x8e8) 107 #define MT_MDP_DCR2_RX_TRANS_SHORT BIT(2) 108 109 /* TMAC: band 0(0x820e4000), band 1(0x820f4000), band 2(0x830e4000) */ 110 #define MT_WF_TMAC_BASE(_band) __BASE(WF_TMAC_BASE, (_band)) 111 #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs)) 112 113 #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0) 114 #define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6) 115 116 #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x0c8) 117 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x0cc) 118 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) 119 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) 120 121 #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x014) 122 #define MT_IFS_EIFS_OFDM GENMASK(8, 0) 123 #define MT_IFS_RIFS GENMASK(14, 10) 124 #define MT_IFS_SIFS GENMASK(22, 16) 125 #define MT_IFS_SLOT GENMASK(30, 24) 126 127 #define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, 0x018) 128 #define MT_IFS_EIFS_CCK GENMASK(8, 0) 129 130 /* WF DMA TOP: band 0(0x820e7000), band 1(0x820f7000), band 2(0x830e7000) */ 131 #define MT_WF_DMA_BASE(_band) __BASE(WF_DMA_BASE, (_band)) 132 #define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs)) 133 134 #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000) 135 #define MT_DMA_DCR0_RXD_G5_EN BIT(23) 136 137 #define MT_DMA_TCRF1(_band) MT_WF_DMA(_band, 0x054) 138 #define MT_DMA_TCRF1_QIDX GENMASK(15, 13) 139 140 /* WTBLOFF TOP: band 0(0x820e9000), band 1(0x820f9000), band 2(0x830e9000) */ 141 #define MT_WTBLOFF_BASE(_band) __BASE(WF_WTBLOFF_BASE, (_band)) 142 #define MT_WTBLOFF(_band, ofs) (MT_WTBLOFF_BASE(_band) + (ofs)) 143 144 #define MT_WTBLOFF_RSCR(_band) MT_WTBLOFF(_band, 0x008) 145 #define MT_WTBLOFF_RSCR_RCPI_MODE GENMASK(31, 30) 146 #define MT_WTBLOFF_RSCR_RCPI_PARAM GENMASK(25, 24) 147 148 /* ETBF: band 0(0x820ea000), band 1(0x820fa000), band 2(0x830ea000) */ 149 #define MT_WF_ETBF_BASE(_band) __BASE(WF_ETBF_BASE, (_band)) 150 #define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs)) 151 152 #define MT_ETBF_RX_FB_CONT(_band) MT_WF_ETBF(_band, 0x100) 153 #define MT_ETBF_RX_FB_BW GENMASK(10, 8) 154 #define MT_ETBF_RX_FB_NC GENMASK(7, 4) 155 #define MT_ETBF_RX_FB_NR GENMASK(3, 0) 156 157 /* LPON: band 0(0x820eb000), band 1(0x820fb000), band 2(0x830eb000) */ 158 #define MT_WF_LPON_BASE(_band) __BASE(WF_LPON_BASE, (_band)) 159 #define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs)) 160 161 #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x360) 162 #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x364) 163 #define MT_LPON_FRCR(_band) MT_WF_LPON(_band, 0x37c) 164 165 #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (((n) * 4) << 4)) 166 #define MT_LPON_TCR_SW_MODE GENMASK(1, 0) 167 #define MT_LPON_TCR_SW_WRITE BIT(0) 168 #define MT_LPON_TCR_SW_ADJUST BIT(1) 169 #define MT_LPON_TCR_SW_READ GENMASK(1, 0) 170 171 /* MIB: band 0(0x820ed000), band 1(0x820fd000), band 2(0x830ed000)*/ 172 /* These counters are (mostly?) clear-on-read. So, some should not 173 * be read at all in case firmware is already reading them. These 174 * are commented with 'DNR' below. The DNR stats will be read by querying 175 * the firmware API for the appropriate message. For counters the driver 176 * does read, the driver should accumulate the counters. 177 */ 178 #define MT_WF_MIB_BASE(_band) __BASE(WF_MIB_BASE, (_band)) 179 #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs)) 180 181 #define MT_MIB_BSCR0(_band) MT_WF_MIB(_band, 0x9cc) 182 #define MT_MIB_BSCR1(_band) MT_WF_MIB(_band, 0x9d0) 183 #define MT_MIB_BSCR2(_band) MT_WF_MIB(_band, 0x9d4) 184 #define MT_MIB_BSCR3(_band) MT_WF_MIB(_band, 0x9d8) 185 #define MT_MIB_BSCR4(_band) MT_WF_MIB(_band, 0x9dc) 186 #define MT_MIB_BSCR5(_band) MT_WF_MIB(_band, 0x9e0) 187 #define MT_MIB_BSCR6(_band) MT_WF_MIB(_band, 0x9e4) 188 #define MT_MIB_BSCR7(_band) MT_WF_MIB(_band, 0x9e8) 189 #define MT_MIB_BSCR17(_band) MT_WF_MIB(_band, 0xa10) 190 191 #define MT_MIB_TSCR5(_band) MT_WF_MIB(_band, 0x6c4) 192 #define MT_MIB_TSCR6(_band) MT_WF_MIB(_band, 0x6c8) 193 #define MT_MIB_TSCR7(_band) MT_WF_MIB(_band, 0x6d0) 194 195 #define MT_MIB_RSCR1(_band) MT_WF_MIB(_band, 0x7ac) 196 /* rx mpdu counter, full 32 bits */ 197 #define MT_MIB_RSCR31(_band) MT_WF_MIB(_band, 0x964) 198 #define MT_MIB_RSCR33(_band) MT_WF_MIB(_band, 0x96c) 199 200 #define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020) 201 #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0) 202 203 #define MT_MIB_RVSR0(_band) MT_WF_MIB(_band, 0x720) 204 205 #define MT_MIB_RSCR35(_band) MT_WF_MIB(_band, 0x974) 206 #define MT_MIB_RSCR36(_band) MT_WF_MIB(_band, 0x978) 207 208 /* tx ampdu cnt, full 32 bits */ 209 #define MT_MIB_TSCR0(_band) MT_WF_MIB(_band, 0x6b0) 210 #define MT_MIB_TSCR2(_band) MT_WF_MIB(_band, 0x6b8) 211 212 /* counts all mpdus in ampdu, regardless of success */ 213 #define MT_MIB_TSCR3(_band) MT_WF_MIB(_band, 0x6bc) 214 215 /* counts all successfully tx'd mpdus in ampdu */ 216 #define MT_MIB_TSCR4(_band) MT_WF_MIB(_band, 0x6c0) 217 218 /* rx ampdu count, 32-bit */ 219 #define MT_MIB_RSCR27(_band) MT_WF_MIB(_band, 0x954) 220 221 /* rx ampdu bytes count, 32-bit */ 222 #define MT_MIB_RSCR28(_band) MT_WF_MIB(_band, 0x958) 223 224 /* rx ampdu valid subframe count */ 225 #define MT_MIB_RSCR29(_band) MT_WF_MIB(_band, 0x95c) 226 227 /* rx ampdu valid subframe bytes count, 32bits */ 228 #define MT_MIB_RSCR30(_band) MT_WF_MIB(_band, 0x960) 229 230 /* remaining windows protected stats */ 231 #define MT_MIB_SDR27(_band) MT_WF_MIB(_band, 0x080) 232 #define MT_MIB_SDR27_TX_RWP_FAIL_CNT GENMASK(15, 0) 233 234 #define MT_MIB_SDR28(_band) MT_WF_MIB(_band, 0x084) 235 #define MT_MIB_SDR28_TX_RWP_NEED_CNT GENMASK(15, 0) 236 237 #define MT_MIB_RVSR1(_band) MT_WF_MIB(_band, 0x724) 238 239 /* rx blockack count, 32 bits */ 240 #define MT_MIB_TSCR1(_band) MT_WF_MIB(_band, 0x6b4) 241 242 #define MT_MIB_BTSCR0(_band) MT_WF_MIB(_band, 0x5e0) 243 #define MT_MIB_BTSCR5(_band) MT_WF_MIB(_band, 0x788) 244 #define MT_MIB_BTSCR6(_band) MT_WF_MIB(_band, 0x798) 245 246 #define MT_MIB_BFTFCR(_band) MT_WF_MIB(_band, 0x5d0) 247 248 #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0xa28 + ((n) << 2)) 249 #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x0b0 + ((n) << 2)) 250 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 4)) & GENMASK(9, 0)) 251 252 /* UMIB */ 253 #define MT_WF_UMIB_BASE 0x820cd000 254 #define MT_WF_UMIB(ofs) (MT_WF_UMIB_BASE + (ofs)) 255 256 #define MT_UMIB_RPDCR(_band) (MT_WF_UMIB(0x594) + (_band) * 0x164) 257 258 /* WTBLON TOP */ 259 #define MT_WTBLON_TOP_BASE 0x820d4000 260 #define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs)) 261 #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x370) 262 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0) 263 264 #define MT_WTBL_UPDATE MT_WTBLON_TOP(0x380) 265 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(11, 0) 266 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(14) 267 #define MT_WTBL_UPDATE_BUSY BIT(31) 268 269 #define MT_WTBL_ITCR MT_WTBLON_TOP(0x3b0) 270 #define MT_WTBL_ITCR_WR BIT(16) 271 #define MT_WTBL_ITCR_EXEC BIT(31) 272 #define MT_WTBL_ITDR0 MT_WTBLON_TOP(0x3b8) 273 #define MT_WTBL_ITDR1 MT_WTBLON_TOP(0x3bc) 274 #define MT_WTBL_SPE_IDX_SEL BIT(6) 275 276 /* WTBL */ 277 #define MT_WTBL_BASE 0x820d8000 278 #define MT_WTBL_LMAC_ID GENMASK(14, 8) 279 #define MT_WTBL_LMAC_DW GENMASK(7, 2) 280 #define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \ 281 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ 282 FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) 283 284 /* AGG: band 0(0x820e2000), band 1(0x820f2000), band 2(0x830e2000) */ 285 #define MT_WF_AGG_BASE(_band) __BASE(WF_AGG_BASE, (_band)) 286 #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs)) 287 288 #define MT_AGG_ACR4(_band) MT_WF_AGG(_band, 0x3c) 289 #define MT_AGG_ACR_PPDU_TXS2H BIT(1) 290 291 /* ARB: band 0(0x820e3000), band 1(0x820f3000), band 2(0x830e3000) */ 292 #define MT_WF_ARB_BASE(_band) __BASE(WF_ARB_BASE, (_band)) 293 #define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs)) 294 295 #define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x000) 296 #define MT_ARB_SCR_TX_DISABLE BIT(8) 297 #define MT_ARB_SCR_RX_DISABLE BIT(9) 298 299 /* RMAC: band 0(0x820e5000), band 1(0x820f5000), band 2(0x830e5000), */ 300 #define MT_WF_RMAC_BASE(_band) __BASE(WF_RMAC_BASE, (_band)) 301 #define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs)) 302 303 #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000) 304 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) 305 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) 306 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) 307 #define MT_WF_RFCR_DROP_MCAST BIT(5) 308 #define MT_WF_RFCR_DROP_BCAST BIT(6) 309 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) 310 #define MT_WF_RFCR_DROP_A3_MAC BIT(8) 311 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) 312 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) 313 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) 314 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) 315 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) 316 #define MT_WF_RFCR_DROP_CTS BIT(14) 317 #define MT_WF_RFCR_DROP_RTS BIT(15) 318 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) 319 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) 320 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) 321 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) 322 #define MT_WF_RFCR_DROP_NDPA BIT(20) 323 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) 324 325 #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004) 326 #define MT_WF_RFCR1_DROP_ACK BIT(4) 327 #define MT_WF_RFCR1_DROP_BF_POLL BIT(5) 328 #define MT_WF_RFCR1_DROP_BA BIT(6) 329 #define MT_WF_RFCR1_DROP_CFEND BIT(7) 330 #define MT_WF_RFCR1_DROP_CFACK BIT(8) 331 332 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380) 333 #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31) 334 #define MT_WF_RMAC_MIB_ED_OFFSET GENMASK(20, 16) 335 #define MT_WF_RMAC_MIB_OBSS_BACKOFF GENMASK(15, 0) 336 337 #define MT_WF_RMAC_MIB_AIRTIME1(_band) MT_WF_RMAC(_band, 0x0384) 338 #define MT_WF_RMAC_MIB_NONQOSD_BACKOFF GENMASK(31, 16) 339 340 #define MT_WF_RMAC_MIB_AIRTIME3(_band) MT_WF_RMAC(_band, 0x038c) 341 #define MT_WF_RMAC_MIB_QOS01_BACKOFF GENMASK(31, 0) 342 343 #define MT_WF_RMAC_MIB_AIRTIME4(_band) MT_WF_RMAC(_band, 0x0390) 344 #define MT_WF_RMAC_MIB_QOS23_BACKOFF GENMASK(31, 0) 345 346 #define MT_WF_RMAC_RSVD0(_band) MT_WF_RMAC(_band, 0x03e0) 347 #define MT_WF_RMAC_RSVD0_EIFS_CLR BIT(21) 348 349 /* RATE: band 0(0x820ee000), band 1(0x820fe000), band 2(0x830ee000) */ 350 #define MT_WF_RATE_BASE(_band) __BASE(WF_RATE_BASE, (_band)) 351 #define MT_WF_RATE(_band, ofs) (MT_WF_RATE_BASE(_band) + (ofs)) 352 353 #define MT_RATE_HRCR0(_band) MT_WF_RATE(_band, 0x050) 354 #define MT_RATE_HRCR0_CFEND_RATE GENMASK(14, 0) 355 356 /* WFDMA0 */ 357 #define MT_WFDMA0_BASE 0xd4000 358 #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) 359 360 #define MT_WFDMA0_RST MT_WFDMA0(0x100) 361 #define MT_WFDMA0_RST_LOGIC_RST BIT(4) 362 #define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5) 363 364 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c) 365 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0) 366 #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1) 367 #define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2) 368 369 #define MT_WFDMA0_RX_INT_PCIE_SEL MT_WFDMA0(0x154) 370 #define MT_WFDMA0_RX_INT_SEL_RING3 BIT(3) 371 #define MT_WFDMA0_RX_INT_SEL_RING6 BIT(6) 372 373 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4) 374 375 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) 376 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) 377 #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) 378 #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) 379 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) 380 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 381 382 #define MT_WFDMA0_PAUSE_RX_Q_45_TH MT_WFDMA0(0x268) 383 #define MT_WFDMA0_PAUSE_RX_Q_67_TH MT_WFDMA0(0x26c) 384 #define MT_WFDMA0_PAUSE_RX_Q_89_TH MT_WFDMA0(0x270) 385 #define MT_WFDMA0_PAUSE_RX_Q_RRO_TH MT_WFDMA0(0x27c) 386 387 #define WF_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0) 388 #define WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD BIT(18) 389 #define WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE BIT(14) 390 391 #define WF_WFDMA0_GLO_CFG_EXT1 MT_WFDMA0(0x2b4) 392 #define WF_WFDMA0_GLO_CFG_EXT1_CALC_MODE BIT(31) 393 #define WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE BIT(28) 394 395 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c) 396 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) 397 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4) 398 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8) 399 400 /* WFDMA1 */ 401 #define MT_WFDMA1_BASE 0xd5000 402 403 /* WFDMA CSR */ 404 #define MT_WFDMA_EXT_CSR_BASE 0xd7000 405 #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs)) 406 407 #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30) 408 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0) 409 #define MT_WFDMA_HOST_CONFIG_BAND2_PCIE1 BIT(22) 410 411 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) 412 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) 413 414 #define MT_WFDMA_AXI_R2A_CTRL MT_WFDMA_EXT_CSR(0x500) 415 #define MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK GENMASK(4, 0) 416 417 #define MT_PCIE_RECOG_ID 0xd7090 418 #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) 419 #define MT_PCIE_RECOG_ID_SEM BIT(31) 420 421 /* WFDMA0 PCIE1 */ 422 #define MT_WFDMA0_PCIE1_BASE 0xd8000 423 #define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs)) 424 425 #define MT_INT_PCIE1_SOURCE_CSR_EXT MT_WFDMA0_PCIE1(0x118) 426 #define MT_INT_PCIE1_MASK_CSR MT_WFDMA0_PCIE1(0x11c) 427 428 #define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c) 429 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) 430 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) 431 #define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2) 432 433 /* WFDMA COMMON */ 434 #define __RXQ(q) ((q) + __MT_MCUQ_MAX) 435 #define __TXQ(q) (__RXQ(q) + __MT_RXQ_MAX) 436 437 #define MT_Q_ID(q) (dev->q_id[(q)]) 438 #define MT_Q_BASE(q) ((dev->q_wfdma_mask >> (q)) & 0x1 ? \ 439 MT_WFDMA1_BASE : MT_WFDMA0_BASE) 440 441 #define MT_MCUQ_ID(q) MT_Q_ID(q) 442 #define MT_TXQ_ID(q) MT_Q_ID(__TXQ(q)) 443 #define MT_RXQ_ID(q) MT_Q_ID(__RXQ(q)) 444 445 #define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300) 446 #define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300) 447 #define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500) 448 #define MT_RXQ_RRO_IND_RING_BASE MT_RRO_TOP(0x40) 449 450 #define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \ 451 MT_MCUQ_ID(q) * 0x4) 452 #define MT_RXQ_BAND1_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \ 453 MT_RXQ_ID(q) * 0x4) 454 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \ 455 MT_TXQ_ID(q) * 0x4) 456 457 #define MT_INT_SOURCE_CSR MT_WFDMA0(0x200) 458 #define MT_INT_MASK_CSR MT_WFDMA0(0x204) 459 460 #define MT_INT1_SOURCE_CSR MT_WFDMA0_PCIE1(0x200) 461 #define MT_INT1_MASK_CSR MT_WFDMA0_PCIE1(0x204) 462 463 #define MT_INT_RX_DONE_BAND0 BIT(12) 464 #define MT_INT_RX_DONE_BAND1 BIT(12) 465 #define MT_INT_RX_DONE_BAND2 BIT(13) 466 #define MT_INT_RX_DONE_WM BIT(0) 467 #define MT_INT_RX_DONE_WA BIT(1) 468 #define MT_INT_RX_DONE_WA_MAIN BIT(2) 469 #define MT_INT_RX_DONE_WA_EXT BIT(2) 470 #define MT_INT_RX_DONE_WA_TRI BIT(3) 471 #define MT_INT_RX_TXFREE_MAIN BIT(17) 472 #define MT_INT_RX_TXFREE_TRI BIT(15) 473 #define MT_INT_RX_DONE_BAND2_EXT BIT(23) 474 #define MT_INT_RX_TXFREE_EXT BIT(26) 475 #define MT_INT_MCU_CMD BIT(29) 476 477 #define MT_INT_RX_DONE_RRO_BAND0 BIT(16) 478 #define MT_INT_RX_DONE_RRO_BAND1 BIT(16) 479 #define MT_INT_RX_DONE_RRO_BAND2 BIT(14) 480 #define MT_INT_RX_DONE_RRO_IND BIT(11) 481 #define MT_INT_RX_DONE_MSDU_PG_BAND0 BIT(18) 482 #define MT_INT_RX_DONE_MSDU_PG_BAND1 BIT(19) 483 #define MT_INT_RX_DONE_MSDU_PG_BAND2 BIT(23) 484 485 #define MT_INT_RX(q) (dev->q_int_mask[__RXQ(q)]) 486 #define MT_INT_TX_MCU(q) (dev->q_int_mask[(q)]) 487 488 #define MT_INT_RX_DONE_MCU (MT_INT_RX(MT_RXQ_MCU) | \ 489 MT_INT_RX(MT_RXQ_MCU_WA)) 490 491 #define MT_INT_BAND0_RX_DONE (MT_INT_RX(MT_RXQ_MAIN) | \ 492 MT_INT_RX(MT_RXQ_MAIN_WA) | \ 493 MT_INT_RX(MT_RXQ_TXFREE_BAND0)) 494 495 #define MT_INT_BAND1_RX_DONE (MT_INT_RX(MT_RXQ_BAND1) | \ 496 MT_INT_RX(MT_RXQ_BAND1_WA) | \ 497 MT_INT_RX(MT_RXQ_MAIN_WA) | \ 498 MT_INT_RX(MT_RXQ_TXFREE_BAND0)) 499 500 #define MT_INT_BAND2_RX_DONE (MT_INT_RX(MT_RXQ_BAND2) | \ 501 MT_INT_RX(MT_RXQ_BAND2_WA) | \ 502 MT_INT_RX(MT_RXQ_MAIN_WA) | \ 503 MT_INT_RX(MT_RXQ_TXFREE_BAND0)) 504 505 #define MT_INT_RRO_RX_DONE (MT_INT_RX(MT_RXQ_RRO_BAND0) | \ 506 MT_INT_RX(MT_RXQ_RRO_BAND1) | \ 507 MT_INT_RX(MT_RXQ_RRO_BAND2) | \ 508 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND0) | \ 509 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND1) | \ 510 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND2)) 511 512 #define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_MCU | \ 513 MT_INT_BAND0_RX_DONE | \ 514 MT_INT_BAND1_RX_DONE | \ 515 MT_INT_BAND2_RX_DONE | \ 516 MT_INT_RRO_RX_DONE) 517 518 #define MT_INT_TX_DONE_FWDL BIT(26) 519 #define MT_INT_TX_DONE_MCU_WM BIT(27) 520 #define MT_INT_TX_DONE_MCU_WA BIT(22) 521 #define MT_INT_TX_DONE_BAND0 BIT(30) 522 #define MT_INT_TX_DONE_BAND1 BIT(31) 523 #define MT_INT_TX_DONE_BAND2 BIT(15) 524 525 #define MT_INT_TX_RX_DONE_EXT (MT_INT_TX_DONE_BAND2 | \ 526 MT_INT_RX_DONE_BAND2_EXT | \ 527 MT_INT_RX_TXFREE_EXT) 528 529 #define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \ 530 MT_INT_TX_MCU(MT_MCUQ_WM) | \ 531 MT_INT_TX_MCU(MT_MCUQ_FWDL)) 532 533 #define MT_MCU_CMD MT_WFDMA0(0x1f0) 534 #define MT_MCU_CMD_STOP_DMA BIT(2) 535 #define MT_MCU_CMD_RESET_DONE BIT(3) 536 #define MT_MCU_CMD_RECOVERY_DONE BIT(4) 537 #define MT_MCU_CMD_NORMAL_STATE BIT(5) 538 #define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1) 539 540 #define MT_MCU_CMD_WA_WDT BIT(31) 541 #define MT_MCU_CMD_WM_WDT BIT(30) 542 #define MT_MCU_CMD_WDT_MASK GENMASK(31, 30) 543 544 /* l1/l2 remap */ 545 #define MT_HIF_REMAP_L1 0x155024 546 #define MT_HIF_REMAP_L1_MASK GENMASK(31, 16) 547 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0) 548 #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16) 549 #define MT_HIF_REMAP_BASE_L1 0x130000 550 551 #define MT_HIF_REMAP_L2 0x1b4 552 #define MT_HIF_REMAP_L2_MASK GENMASK(19, 0) 553 #define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0) 554 #define MT_HIF_REMAP_L2_BASE GENMASK(31, 12) 555 #define MT_HIF_REMAP_BASE_L2 0x1000 556 557 #define MT_INFRA_BASE 0x18000000 558 #define MT_WFSYS0_PHY_START 0x18400000 559 #define MT_WFSYS1_PHY_START 0x18800000 560 #define MT_WFSYS1_PHY_END 0x18bfffff 561 #define MT_CBTOP1_PHY_START 0x70000000 562 #define MT_CBTOP1_PHY_END 0x77ffffff 563 #define MT_CBTOP2_PHY_START 0xf0000000 564 #define MT_INFRA_MCU_START 0x7c000000 565 #define MT_INFRA_MCU_END 0x7c3fffff 566 567 /* FW MODE SYNC */ 568 #define MT_FW_ASSERT_CNT 0x02208274 569 #define MT_FW_DUMP_STATE 0x02209e90 570 571 #define MT_SWDEF_BASE 0x00401400 572 573 #define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs)) 574 #define MT_SWDEF_MODE MT_SWDEF(0x3c) 575 #define MT_SWDEF_NORMAL_MODE 0 576 577 #define MT_SWDEF_SER_STATS MT_SWDEF(0x040) 578 #define MT_SWDEF_PLE_STATS MT_SWDEF(0x044) 579 #define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048) 580 #define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04c) 581 #define MT_SWDEF_PSE_STATS MT_SWDEF(0x050) 582 #define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054) 583 #define MT_SWDEF_LAMC_WISR6_BN0_STATS MT_SWDEF(0x058) 584 #define MT_SWDEF_LAMC_WISR6_BN1_STATS MT_SWDEF(0x05c) 585 #define MT_SWDEF_LAMC_WISR6_BN2_STATS MT_SWDEF(0x060) 586 #define MT_SWDEF_LAMC_WISR7_BN0_STATS MT_SWDEF(0x064) 587 #define MT_SWDEF_LAMC_WISR7_BN1_STATS MT_SWDEF(0x068) 588 #define MT_SWDEF_LAMC_WISR7_BN2_STATS MT_SWDEF(0x06c) 589 590 /* LED */ 591 #define MT_LED_TOP_BASE 0x18013000 592 #define MT_LED_PHYS(_n) (MT_LED_TOP_BASE + (_n)) 593 594 #define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4)) 595 #define MT_LED_CTRL_KICK BIT(7) 596 #define MT_LED_CTRL_BLINK_BAND_SEL BIT(4) 597 #define MT_LED_CTRL_BLINK_MODE BIT(2) 598 #define MT_LED_CTRL_POLARITY BIT(1) 599 600 #define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4)) 601 #define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0) 602 #define MT_LED_TX_BLINK_OFF_MASK GENMASK(15, 8) 603 604 #define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4)) 605 606 /* CONN DBG */ 607 #define MT_CONN_DBG_CTL_BASE 0x18023000 608 #define MT_CONN_DBG_CTL(ofs) (MT_CONN_DBG_CTL_BASE + (ofs)) 609 #define MT_CONN_DBG_CTL_OUT_SEL MT_CONN_DBG_CTL(0x604) 610 #define MT_CONN_DBG_CTL_PC_LOG_SEL MT_CONN_DBG_CTL(0x60c) 611 #define MT_CONN_DBG_CTL_PC_LOG MT_CONN_DBG_CTL(0x610) 612 613 #define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */ 614 #define MT_LED_GPIO_MUX3 0x7000505C /* GPIO 26 */ 615 #define MT_LED_GPIO_SEL_MASK GENMASK(11, 8) 616 617 /* MT TOP */ 618 #define MT_TOP_BASE 0xe0000 619 #define MT_TOP(ofs) (MT_TOP_BASE + (ofs)) 620 621 #define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10)) 622 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0) 623 #define MT_TOP_LPCR_HOST_DRV_OWN BIT(1) 624 #define MT_TOP_LPCR_HOST_FW_OWN_STAT BIT(2) 625 626 #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10)) 627 #define MT_TOP_LPCR_HOST_BAND_STAT BIT(0) 628 629 #define MT_TOP_MISC MT_TOP(0xf0) 630 #define MT_TOP_MISC_FW_STATE GENMASK(2, 0) 631 632 #define MT_PAD_GPIO 0x700056f0 633 #define MT_PAD_GPIO_ADIE_COMB GENMASK(16, 15) 634 635 #define MT_HW_REV 0x70010204 636 #define MT_HW_REV1 0x8a00 637 638 #define MT_WF_SUBSYS_RST 0x70028600 639 640 /* PCIE MAC */ 641 #define MT_PCIE_MAC_BASE 0x74030000 642 #define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs)) 643 #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188) 644 645 #define MT_PCIE1_MAC_BASE 0x74090000 646 #define MT_PCIE1_MAC(ofs) (MT_PCIE1_MAC_BASE + (ofs)) 647 648 #define MT_PCIE1_MAC_INT_ENABLE MT_PCIE1_MAC(0x188) 649 650 /* PHYRX CSD */ 651 #define MT_WF_PHYRX_CSD_BASE 0x83000000 652 #define MT_WF_PHYRX_CSD(_band, _wf, ofs) (MT_WF_PHYRX_CSD_BASE + \ 653 ((_band) << 20) + \ 654 ((_wf) << 16) + (ofs)) 655 #define MT_WF_PHYRX_CSD_IRPI(_band, _wf) MT_WF_PHYRX_CSD(_band, _wf, 0x1000) 656 657 /* PHYRX CTRL */ 658 #define MT_WF_PHYRX_BAND_BASE 0x83080000 659 #define MT_WF_PHYRX_BAND(_band, ofs) (MT_WF_PHYRX_BAND_BASE + \ 660 ((_band) << 20) + (ofs)) 661 662 #define MT_WF_PHYRX_BAND_GID_TAB_VLD0(_band) MT_WF_PHYRX_BAND(_band, 0x1054) 663 #define MT_WF_PHYRX_BAND_GID_TAB_VLD1(_band) MT_WF_PHYRX_BAND(_band, 0x1058) 664 #define MT_WF_PHYRX_BAND_GID_TAB_POS0(_band) MT_WF_PHYRX_BAND(_band, 0x105c) 665 #define MT_WF_PHYRX_BAND_GID_TAB_POS1(_band) MT_WF_PHYRX_BAND(_band, 0x1060) 666 #define MT_WF_PHYRX_BAND_GID_TAB_POS2(_band) MT_WF_PHYRX_BAND(_band, 0x1064) 667 #define MT_WF_PHYRX_BAND_GID_TAB_POS3(_band) MT_WF_PHYRX_BAND(_band, 0x1068) 668 669 #define MT_WF_PHYRX_BAND_RX_CTRL1(_band) MT_WF_PHYRX_BAND(_band, 0x2004) 670 #define MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN GENMASK(2, 0) 671 #define MT_WF_PHYRX_BAND_RX_CTRL1_STSCNT_EN GENMASK(11, 9) 672 673 /* PHYRX CSD BAND */ 674 #define MT_WF_PHYRX_CSD_BAND_RXTD12(_band) MT_WF_PHYRX_BAND(_band, 0x8230) 675 #define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR_ONLY BIT(18) 676 #define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR BIT(29) 677 678 /* CONN MCU EXCP CON */ 679 #define MT_MCU_WM_EXCP_BASE 0x89050000 680 #define MT_MCU_WM_EXCP(ofs) (MT_MCU_WM_EXCP_BASE + (ofs)) 681 #define MT_MCU_WM_EXCP_PC_CTRL MT_MCU_WM_EXCP(0x100) 682 #define MT_MCU_WM_EXCP_PC_LOG MT_MCU_WM_EXCP(0x104) 683 #define MT_MCU_WM_EXCP_LR_CTRL MT_MCU_WM_EXCP(0x200) 684 #define MT_MCU_WM_EXCP_LR_LOG MT_MCU_WM_EXCP(0x204) 685 686 #endif 687