17f17b86aSRyder Lee // SPDX-License-Identifier: ISC
2c8846e10SFelix Fietkau
3c8846e10SFelix Fietkau #include "mt7603.h"
4a3f657ecSLorenzo Bianconi #include "../trace.h"
5c8846e10SFelix Fietkau
mt7603_rx_poll_complete(struct mt76_dev * mdev,enum mt76_rxq_id q)6c8846e10SFelix Fietkau void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
7c8846e10SFelix Fietkau {
8c8846e10SFelix Fietkau struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
9c8846e10SFelix Fietkau
10c8846e10SFelix Fietkau mt7603_irq_enable(dev, MT_INT_RX_DONE(q));
11c8846e10SFelix Fietkau }
12c8846e10SFelix Fietkau
mt7603_irq_handler(int irq,void * dev_instance)13c8846e10SFelix Fietkau irqreturn_t mt7603_irq_handler(int irq, void *dev_instance)
14c8846e10SFelix Fietkau {
15c8846e10SFelix Fietkau struct mt7603_dev *dev = dev_instance;
16c8846e10SFelix Fietkau u32 intr;
17c8846e10SFelix Fietkau
18c8846e10SFelix Fietkau intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
19c8846e10SFelix Fietkau mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
20c8846e10SFelix Fietkau
21011849e0SFelix Fietkau if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
22c8846e10SFelix Fietkau return IRQ_NONE;
23c8846e10SFelix Fietkau
24a3f657ecSLorenzo Bianconi trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
25a3f657ecSLorenzo Bianconi
26c8846e10SFelix Fietkau intr &= dev->mt76.mmio.irqmask;
27c8846e10SFelix Fietkau
28c8846e10SFelix Fietkau if (intr & MT_INT_MAC_IRQ3) {
29c8846e10SFelix Fietkau u32 hwintr = mt76_rr(dev, MT_HW_INT_STATUS(3));
30c8846e10SFelix Fietkau
31c8846e10SFelix Fietkau mt76_wr(dev, MT_HW_INT_STATUS(3), hwintr);
32c8846e10SFelix Fietkau if (hwintr & MT_HW_INT3_PRE_TBTT0)
33dc6057f4SLorenzo Bianconi tasklet_schedule(&dev->mt76.pre_tbtt_tasklet);
34c8846e10SFelix Fietkau
35c8846e10SFelix Fietkau if ((hwintr & MT_HW_INT3_TBTT0) && dev->mt76.csa_complete)
36c8846e10SFelix Fietkau mt76_csa_finish(&dev->mt76);
37c8846e10SFelix Fietkau }
38c8846e10SFelix Fietkau
39c8846e10SFelix Fietkau if (intr & MT_INT_TX_DONE_ALL) {
40c8846e10SFelix Fietkau mt7603_irq_disable(dev, MT_INT_TX_DONE_ALL);
419e63f5e7SLorenzo Bianconi napi_schedule(&dev->mt76.tx_napi);
42c8846e10SFelix Fietkau }
43c8846e10SFelix Fietkau
44c8846e10SFelix Fietkau if (intr & MT_INT_RX_DONE(0)) {
45baa19b2eSFelix Fietkau dev->rx_pse_check = 0;
46c8846e10SFelix Fietkau mt7603_irq_disable(dev, MT_INT_RX_DONE(0));
47c8846e10SFelix Fietkau napi_schedule(&dev->mt76.napi[0]);
48c8846e10SFelix Fietkau }
49c8846e10SFelix Fietkau
50c8846e10SFelix Fietkau if (intr & MT_INT_RX_DONE(1)) {
51baa19b2eSFelix Fietkau dev->rx_pse_check = 0;
52c8846e10SFelix Fietkau mt7603_irq_disable(dev, MT_INT_RX_DONE(1));
53c8846e10SFelix Fietkau napi_schedule(&dev->mt76.napi[1]);
54c8846e10SFelix Fietkau }
55c8846e10SFelix Fietkau
56c8846e10SFelix Fietkau return IRQ_HANDLED;
57c8846e10SFelix Fietkau }
58c8846e10SFelix Fietkau
mt7603_reg_map(struct mt7603_dev * dev,u32 addr)59c8846e10SFelix Fietkau u32 mt7603_reg_map(struct mt7603_dev *dev, u32 addr)
60c8846e10SFelix Fietkau {
614e04ba6aSLorenzo Bianconi u32 base = addr & MT_MCU_PCIE_REMAP_2_BASE;
624e04ba6aSLorenzo Bianconi u32 offset = addr & MT_MCU_PCIE_REMAP_2_OFFSET;
63c8846e10SFelix Fietkau
64c8846e10SFelix Fietkau dev->bus_ops->wr(&dev->mt76, MT_MCU_PCIE_REMAP_2, base);
65c8846e10SFelix Fietkau
66c8846e10SFelix Fietkau return MT_PCIE_REMAP_BASE_2 + offset;
67c8846e10SFelix Fietkau }
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