1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 232ddf071SChristian Lamparter #ifndef P54PCI_H 332ddf071SChristian Lamparter #define P54PCI_H 4a6b7a407SAlexey Dobriyan #include <linux/interrupt.h> 5eff1a59cSMichael Wu 6eff1a59cSMichael Wu /* 7eff1a59cSMichael Wu * Defines for PCI based mac80211 Prism54 driver 8eff1a59cSMichael Wu * 9eff1a59cSMichael Wu * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net> 10eff1a59cSMichael Wu * 11eff1a59cSMichael Wu * Based on the islsm (softmac prism54) driver, which is: 12eff1a59cSMichael Wu * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al. 13eff1a59cSMichael Wu */ 14eff1a59cSMichael Wu 15eff1a59cSMichael Wu /* Device Interrupt register bits */ 16eff1a59cSMichael Wu #define ISL38XX_DEV_INT_RESET 0x0001 17eff1a59cSMichael Wu #define ISL38XX_DEV_INT_UPDATE 0x0002 18eff1a59cSMichael Wu #define ISL38XX_DEV_INT_WAKEUP 0x0008 19eff1a59cSMichael Wu #define ISL38XX_DEV_INT_SLEEP 0x0010 20eff1a59cSMichael Wu #define ISL38XX_DEV_INT_ABORT 0x0020 21eff1a59cSMichael Wu /* these two only used in USB */ 22eff1a59cSMichael Wu #define ISL38XX_DEV_INT_DATA 0x0040 23eff1a59cSMichael Wu #define ISL38XX_DEV_INT_MGMT 0x0080 24eff1a59cSMichael Wu 25eff1a59cSMichael Wu #define ISL38XX_DEV_INT_PCIUART_CTS 0x4000 26eff1a59cSMichael Wu #define ISL38XX_DEV_INT_PCIUART_DR 0x8000 27eff1a59cSMichael Wu 28eff1a59cSMichael Wu /* Interrupt Identification/Acknowledge/Enable register bits */ 29eff1a59cSMichael Wu #define ISL38XX_INT_IDENT_UPDATE 0x0002 30eff1a59cSMichael Wu #define ISL38XX_INT_IDENT_INIT 0x0004 31eff1a59cSMichael Wu #define ISL38XX_INT_IDENT_WAKEUP 0x0008 32eff1a59cSMichael Wu #define ISL38XX_INT_IDENT_SLEEP 0x0010 33eff1a59cSMichael Wu #define ISL38XX_INT_IDENT_PCIUART_CTS 0x4000 34eff1a59cSMichael Wu #define ISL38XX_INT_IDENT_PCIUART_DR 0x8000 35eff1a59cSMichael Wu 36eff1a59cSMichael Wu /* Control/Status register bits */ 37eff1a59cSMichael Wu #define ISL38XX_CTRL_STAT_SLEEPMODE 0x00000200 38eff1a59cSMichael Wu #define ISL38XX_CTRL_STAT_CLKRUN 0x00800000 39eff1a59cSMichael Wu #define ISL38XX_CTRL_STAT_RESET 0x10000000 40eff1a59cSMichael Wu #define ISL38XX_CTRL_STAT_RAMBOOT 0x20000000 41eff1a59cSMichael Wu #define ISL38XX_CTRL_STAT_STARTHALTED 0x40000000 42eff1a59cSMichael Wu #define ISL38XX_CTRL_STAT_HOST_OVERRIDE 0x80000000 43eff1a59cSMichael Wu 44eff1a59cSMichael Wu struct p54p_csr { 45eff1a59cSMichael Wu __le32 dev_int; 46eff1a59cSMichael Wu u8 unused_1[12]; 47eff1a59cSMichael Wu __le32 int_ident; 48eff1a59cSMichael Wu __le32 int_ack; 49eff1a59cSMichael Wu __le32 int_enable; 50eff1a59cSMichael Wu u8 unused_2[4]; 51eff1a59cSMichael Wu union { 52eff1a59cSMichael Wu __le32 ring_control_base; 53eff1a59cSMichael Wu __le32 gen_purp_com[2]; 54eff1a59cSMichael Wu }; 55eff1a59cSMichael Wu u8 unused_3[8]; 56eff1a59cSMichael Wu __le32 direct_mem_base; 57eff1a59cSMichael Wu u8 unused_4[44]; 58eff1a59cSMichael Wu __le32 dma_addr; 59eff1a59cSMichael Wu __le32 dma_len; 60eff1a59cSMichael Wu __le32 dma_ctrl; 61eff1a59cSMichael Wu u8 unused_5[12]; 62eff1a59cSMichael Wu __le32 ctrl_stat; 63eff1a59cSMichael Wu u8 unused_6[1924]; 64eff1a59cSMichael Wu u8 cardbus_cis[0x800]; 65eff1a59cSMichael Wu u8 direct_mem_win[0x1000]; 66ba2d3587SEric Dumazet } __packed; 67eff1a59cSMichael Wu 68eff1a59cSMichael Wu /* usb backend only needs the register defines above */ 6932ddf071SChristian Lamparter #ifndef P54USB_H 70eff1a59cSMichael Wu struct p54p_desc { 71eff1a59cSMichael Wu __le32 host_addr; 72eff1a59cSMichael Wu __le32 device_addr; 73eff1a59cSMichael Wu __le16 len; 74eff1a59cSMichael Wu __le16 flags; 75ba2d3587SEric Dumazet } __packed; 76eff1a59cSMichael Wu 77eff1a59cSMichael Wu struct p54p_ring_control { 78eff1a59cSMichael Wu __le32 host_idx[4]; 79eff1a59cSMichael Wu __le32 device_idx[4]; 80eff1a59cSMichael Wu struct p54p_desc rx_data[8]; 81eff1a59cSMichael Wu struct p54p_desc tx_data[32]; 82eff1a59cSMichael Wu struct p54p_desc rx_mgmt[4]; 83eff1a59cSMichael Wu struct p54p_desc tx_mgmt[4]; 84ba2d3587SEric Dumazet } __packed; 85eff1a59cSMichael Wu 868160c031SAl Viro #define P54P_READ(r) (__force __le32)__raw_readl(&priv->map->r) 878160c031SAl Viro #define P54P_WRITE(r, val) __raw_writel((__force u32)(__le32)(val), &priv->map->r) 88eff1a59cSMichael Wu 89eff1a59cSMichael Wu struct p54p_priv { 90eff1a59cSMichael Wu struct p54_common common; 91eff1a59cSMichael Wu struct pci_dev *pdev; 92eff1a59cSMichael Wu struct p54p_csr __iomem *map; 93d713804cSChristian Lamparter struct tasklet_struct tasklet; 9440db0b22SChristian Lamparter const struct firmware *firmware; 95eff1a59cSMichael Wu spinlock_t lock; 96eff1a59cSMichael Wu struct p54p_ring_control *ring_control; 97eff1a59cSMichael Wu dma_addr_t ring_control_dma; 987262d593SChristian Lamparter u32 rx_idx_data, tx_idx_data; 997262d593SChristian Lamparter u32 rx_idx_mgmt, tx_idx_mgmt; 1007262d593SChristian Lamparter struct sk_buff *rx_buf_data[8]; 1017262d593SChristian Lamparter struct sk_buff *rx_buf_mgmt[4]; 102d713804cSChristian Lamparter struct sk_buff *tx_buf_data[32]; 103d713804cSChristian Lamparter struct sk_buff *tx_buf_mgmt[4]; 104eff1a59cSMichael Wu struct completion boot_comp; 10595a96e08SLarry Finger struct completion fw_loaded; 106eff1a59cSMichael Wu }; 107eff1a59cSMichael Wu 10832ddf071SChristian Lamparter #endif /* P54USB_H */ 10932ddf071SChristian Lamparter #endif /* P54PCI_H */ 110