1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_fw_api_rx_h__ 8 #define __iwl_fw_api_rx_h__ 9 10 /* API for pre-9000 hardware */ 11 12 #define IWL_RX_INFO_PHY_CNT 8 13 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1 14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 16 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0 17 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8 18 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16 19 20 enum iwl_mac_context_info { 21 MAC_CONTEXT_INFO_NONE, 22 MAC_CONTEXT_INFO_GSCAN, 23 }; 24 25 /** 26 * struct iwl_rx_phy_info - phy info 27 * (REPLY_RX_PHY_CMD = 0xc0) 28 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 29 * @cfg_phy_cnt: configurable DSP phy data byte count 30 * @stat_id: configurable DSP phy data set ID 31 * @reserved1: reserved 32 * @system_timestamp: GP2 at on air rise 33 * @timestamp: TSF at on air rise 34 * @beacon_time_stamp: beacon at on-air rise 35 * @phy_flags: general phy flags: band, modulation, ... 36 * @channel: channel number 37 * @non_cfg_phy: for various implementations of non_cfg_phy 38 * @rate_n_flags: RATE_MCS_* 39 * @byte_count: frame's byte-count 40 * @frame_time: frame's time on the air, based on byte count and frame rate 41 * calculation 42 * @mac_active_msk: what MACs were active when the frame was received 43 * @mac_context_info: additional info on the context in which the frame was 44 * received as defined in &enum iwl_mac_context_info 45 * 46 * Before each Rx, the device sends this data. It contains PHY information 47 * about the reception of the packet. 48 */ 49 struct iwl_rx_phy_info { 50 u8 non_cfg_phy_cnt; 51 u8 cfg_phy_cnt; 52 u8 stat_id; 53 u8 reserved1; 54 __le32 system_timestamp; 55 __le64 timestamp; 56 __le32 beacon_time_stamp; 57 __le16 phy_flags; 58 __le16 channel; 59 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT]; 60 __le32 rate_n_flags; 61 __le32 byte_count; 62 u8 mac_active_msk; 63 u8 mac_context_info; 64 __le16 frame_time; 65 } __packed; 66 67 /* 68 * TCP offload Rx assist info 69 * 70 * bits 0:3 - reserved 71 * bits 4:7 - MIC CRC length 72 * bits 8:12 - MAC header length 73 * bit 13 - Padding indication 74 * bit 14 - A-AMSDU indication 75 * bit 15 - Offload enabled 76 */ 77 enum iwl_csum_rx_assist_info { 78 CSUM_RXA_RESERVED_MASK = 0x000f, 79 CSUM_RXA_MICSIZE_MASK = 0x00f0, 80 CSUM_RXA_HEADERLEN_MASK = 0x1f00, 81 CSUM_RXA_PADD = BIT(13), 82 CSUM_RXA_AMSDU = BIT(14), 83 CSUM_RXA_ENA = BIT(15) 84 }; 85 86 /** 87 * struct iwl_rx_mpdu_res_start - phy info 88 * @byte_count: byte count of the frame 89 * @assist: see &enum iwl_csum_rx_assist_info 90 */ 91 struct iwl_rx_mpdu_res_start { 92 __le16 byte_count; 93 __le16 assist; 94 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */ 95 96 /** 97 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags 98 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 99 * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK 100 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 101 * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive 102 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 103 * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position 104 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 105 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 106 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 107 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 108 */ 109 enum iwl_rx_phy_flags { 110 RX_RES_PHY_FLAGS_BAND_24 = BIT(0), 111 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), 112 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), 113 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), 114 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 115 RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 116 RX_RES_PHY_FLAGS_AGG = BIT(7), 117 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), 118 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), 119 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), 120 }; 121 122 /** 123 * enum iwl_mvm_rx_status - written by fw for each Rx packet 124 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 125 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 126 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found 127 * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid 128 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 129 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 130 * in the driver. 131 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 132 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 133 * alg = CCM only. Checks replay attack for 11w frames. 134 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 135 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 136 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 137 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 138 * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension 139 * algorithm 140 * @RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC: this frame is protected using 141 * CMAC or GMAC 142 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 143 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 144 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 145 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw 146 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors 147 * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask 148 * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift 149 */ 150 enum iwl_mvm_rx_status { 151 RX_MPDU_RES_STATUS_CRC_OK = BIT(0), 152 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), 153 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), 154 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), 155 RX_MPDU_RES_STATUS_ICV_OK = BIT(5), 156 RX_MPDU_RES_STATUS_MIC_OK = BIT(6), 157 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 158 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), 159 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 160 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 161 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 162 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 163 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 164 RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC = (6 << 8), 165 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 166 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 167 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), 168 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16), 169 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17), 170 RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24, 171 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT, 172 }; 173 174 /* 9000 series API */ 175 enum iwl_rx_mpdu_mac_flags1 { 176 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03, 177 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0, 178 /* shift should be 4, but the length is measured in 2-byte 179 * words, so shifting only by 3 gives a byte result 180 */ 181 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3, 182 }; 183 184 enum iwl_rx_mpdu_mac_flags2 { 185 /* in 2-byte words */ 186 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f, 187 IWL_RX_MPDU_MFLG2_PAD = 0x20, 188 IWL_RX_MPDU_MFLG2_AMSDU = 0x40, 189 }; 190 191 enum iwl_rx_mpdu_amsdu_info { 192 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f, 193 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80, 194 }; 195 196 enum iwl_rx_mpdu_mac_phy_band { 197 IWL_RX_MPDU_MAC_PHY_BAND_MAC_MASK = 0x0f, 198 IWL_RX_MPDU_MAC_PHY_BAND_PHY_MASK = 0x30, 199 IWL_RX_MPDU_MAC_PHY_BAND_BAND_MASK = 0xc0, 200 }; 201 202 enum iwl_rx_l3_proto_values { 203 IWL_RX_L3_TYPE_NONE, 204 IWL_RX_L3_TYPE_IPV4, 205 IWL_RX_L3_TYPE_IPV4_FRAG, 206 IWL_RX_L3_TYPE_IPV6_FRAG, 207 IWL_RX_L3_TYPE_IPV6, 208 IWL_RX_L3_TYPE_IPV6_IN_IPV4, 209 IWL_RX_L3_TYPE_ARP, 210 IWL_RX_L3_TYPE_EAPOL, 211 }; 212 213 #define IWL_RX_L3_PROTO_POS 4 214 215 enum iwl_rx_l3l4_flags { 216 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0), 217 IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1), 218 IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2), 219 IWL_RX_L3L4_TCP_ACK = BIT(3), 220 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS, 221 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8, 222 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12, 223 }; 224 225 enum iwl_rx_mpdu_status { 226 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0), 227 IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1), 228 IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2), 229 IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3), 230 IWL_RX_MPDU_STATUS_ICV_OK = BIT(5), 231 IWL_RX_MPDU_STATUS_MIC_OK = BIT(6), 232 IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 233 /* overlayed since IWL_UCODE_TLV_API_DEPRECATE_TTAK */ 234 IWL_RX_MPDU_STATUS_REPLAY_ERROR = BIT(7), 235 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8, 236 IWL_RX_MPDU_STATUS_SEC_UNKNOWN = IWL_RX_MPDU_STATUS_SEC_MASK, 237 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8, 238 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8, 239 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8, 240 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8, 241 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8, 242 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8, 243 IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11), 244 IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15), 245 246 IWL_RX_MPDU_STATUS_DUPLICATE = BIT(22), 247 248 IWL_RX_MPDU_STATUS_STA_ID = 0x1f000000, 249 }; 250 251 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f 252 253 enum iwl_rx_mpdu_reorder_data { 254 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff, 255 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000, 256 IWL_RX_MPDU_REORDER_SN_SHIFT = 12, 257 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000, 258 IWL_RX_MPDU_REORDER_BAID_SHIFT = 24, 259 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000, 260 }; 261 262 enum iwl_rx_mpdu_phy_info { 263 IWL_RX_MPDU_PHY_AMPDU = BIT(5), 264 IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6), 265 IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7), 266 /* short preamble is only for CCK, for non-CCK overridden by this */ 267 IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY = BIT(7), 268 IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8), 269 }; 270 271 enum iwl_rx_mpdu_mac_info { 272 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f, 273 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0, 274 }; 275 276 /* TSF overload low dword */ 277 enum iwl_rx_phy_he_data0 { 278 /* info type: HE any */ 279 IWL_RX_PHY_DATA0_HE_BEAM_CHNG = 0x00000001, 280 IWL_RX_PHY_DATA0_HE_UPLINK = 0x00000002, 281 IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK = 0x000000fc, 282 IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK = 0x00000f00, 283 /* 1 bit reserved */ 284 IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK = 0x000fe000, 285 IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM = 0x00100000, 286 IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK = 0x00600000, 287 IWL_RX_PHY_DATA0_HE_PE_DISAMBIG = 0x00800000, 288 IWL_RX_PHY_DATA0_HE_DOPPLER = 0x01000000, 289 /* 6 bits reserved */ 290 IWL_RX_PHY_DATA0_HE_DELIM_EOF = 0x80000000, 291 }; 292 293 /* TSF overload low dword */ 294 enum iwl_rx_phy_eht_data0 { 295 /* info type: EHT any */ 296 IWL_RX_PHY_DATA0_EHT_VALIDATE = BIT(0), 297 IWL_RX_PHY_DATA0_EHT_UPLINK = BIT(1), 298 IWL_RX_PHY_DATA0_EHT_BSS_COLOR_MASK = 0x000000fc, 299 IWL_RX_PHY_DATA0_ETH_SPATIAL_REUSE_MASK = 0x00000f00, 300 IWL_RX_PHY_DATA0_EHT_PS160 = BIT(12), 301 IWL_RX_PHY_DATA0_EHT_TXOP_DUR_MASK = 0x000fe000, 302 IWL_RX_PHY_DATA0_EHT_LDPC_EXT_SYM = BIT(20), 303 IWL_RX_PHY_DATA0_EHT_PRE_FEC_PAD_MASK = 0x00600000, 304 IWL_RX_PHY_DATA0_EHT_PE_DISAMBIG = BIT(23), 305 IWL_RX_PHY_DATA0_EHT_BW320_SLOT = BIT(24), 306 IWL_RX_PHY_DATA0_EHT_SIGA_CRC_OK = BIT(25), 307 IWL_RX_PHY_DATA0_EHT_PHY_VER = 0x1c000000, 308 /* 2 bits reserved */ 309 IWL_RX_PHY_DATA0_EHT_DELIM_EOF = BIT(31), 310 }; 311 312 enum iwl_rx_phy_info_type { 313 IWL_RX_PHY_INFO_TYPE_NONE = 0, 314 IWL_RX_PHY_INFO_TYPE_CCK = 1, 315 IWL_RX_PHY_INFO_TYPE_OFDM_LGCY = 2, 316 IWL_RX_PHY_INFO_TYPE_HT = 3, 317 IWL_RX_PHY_INFO_TYPE_VHT_SU = 4, 318 IWL_RX_PHY_INFO_TYPE_VHT_MU = 5, 319 IWL_RX_PHY_INFO_TYPE_HE_SU = 6, 320 IWL_RX_PHY_INFO_TYPE_HE_MU = 7, 321 IWL_RX_PHY_INFO_TYPE_HE_TB = 8, 322 IWL_RX_PHY_INFO_TYPE_HE_MU_EXT = 9, 323 IWL_RX_PHY_INFO_TYPE_HE_TB_EXT = 10, 324 IWL_RX_PHY_INFO_TYPE_EHT_MU = 11, 325 IWL_RX_PHY_INFO_TYPE_EHT_TB = 12, 326 IWL_RX_PHY_INFO_TYPE_EHT_MU_EXT = 13, 327 IWL_RX_PHY_INFO_TYPE_EHT_TB_EXT = 14, 328 }; 329 330 /* TSF overload high dword */ 331 enum iwl_rx_phy_common_data1 { 332 /* 333 * check this first - if TSF overload is set, 334 * see &enum iwl_rx_phy_info_type 335 */ 336 IWL_RX_PHY_DATA1_INFO_TYPE_MASK = 0xf0000000, 337 338 /* info type: HT/VHT/HE/EHT any */ 339 IWL_RX_PHY_DATA1_LSIG_LEN_MASK = 0x0fff0000, 340 }; 341 342 /* TSF overload high dword For HE rates*/ 343 enum iwl_rx_phy_he_data1 { 344 /* info type: HE MU/MU-EXT */ 345 IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION = 0x00000001, 346 IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK = 0x0000001e, 347 348 /* info type: HE any */ 349 IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK = 0x000000e0, 350 IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80 = 0x00000100, 351 /* trigger encoded */ 352 IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK = 0x0000fe00, 353 354 /* info type: HE TB/TX-EXT */ 355 IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE = 0x00000001, 356 IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK = 0x0000000e, 357 }; 358 359 /* TSF overload high dword For EHT-MU/TB rates*/ 360 enum iwl_rx_phy_eht_data1 { 361 /* info type: EHT-MU */ 362 IWL_RX_PHY_DATA1_EHT_MU_NUM_SIG_SYM_USIGA2 = 0x0000001f, 363 /* info type: EHT-TB */ 364 IWL_RX_PHY_DATA1_EHT_TB_PILOT_TYPE = BIT(0), 365 IWL_RX_PHY_DATA1_EHT_TB_LOW_SS = 0x0000001e, 366 367 /* info type: EHT any */ 368 /* number of EHT-LTF symbols 0 - 1 EHT-LTF, 1 - 2 EHT-LTFs, 2 - 4 EHT-LTFs, 369 * 3 - 6 EHT-LTFs, 4 - 8 EHT-LTFs */ 370 IWL_RX_PHY_DATA1_EHT_SIG_LTF_NUM = 0x000000e0, 371 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B0 = 0x00000100, 372 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B1_B7 = 0x0000fe00, 373 }; 374 375 /* goes into Metadata DW 7 (Qu) or 8 (So or higher) */ 376 enum iwl_rx_phy_he_data2 { 377 /* info type: HE MU-EXT */ 378 /* the a1/a2/... is what the PHY/firmware calls the values */ 379 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0 = 0x000000ff, /* a1 */ 380 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2 = 0x0000ff00, /* a2 */ 381 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0 = 0x00ff0000, /* b1 */ 382 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2 = 0xff000000, /* b2 */ 383 384 /* info type: HE TB-EXT */ 385 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1 = 0x0000000f, 386 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2 = 0x000000f0, 387 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3 = 0x00000f00, 388 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4 = 0x0000f000, 389 }; 390 391 /* goes into Metadata DW 8 (Qu) or 7 (So or higher) */ 392 enum iwl_rx_phy_he_data3 { 393 /* info type: HE MU-EXT */ 394 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1 = 0x000000ff, /* c1 */ 395 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3 = 0x0000ff00, /* c2 */ 396 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1 = 0x00ff0000, /* d1 */ 397 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3 = 0xff000000, /* d2 */ 398 }; 399 400 /* goes into Metadata DW 4 high 16 bits */ 401 enum iwl_rx_phy_he_he_data4 { 402 /* info type: HE MU-EXT */ 403 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU = 0x0001, 404 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU = 0x0002, 405 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK = 0x0004, 406 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK = 0x0008, 407 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK = 0x00f0, 408 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM = 0x0100, 409 IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK = 0x0600, 410 }; 411 412 /* goes into Metadata DW 8 (Qu has no EHT) */ 413 enum iwl_rx_phy_eht_data2 { 414 /* info type: EHT-MU-EXT */ 415 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A1 = 0x000001ff, 416 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A2 = 0x0003fe00, 417 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_B1 = 0x07fc0000, 418 419 /* info type: EHT-TB-EXT */ 420 IWL_RX_PHY_DATA2_EHT_TB_EXT_TRIG_SIGA1 = 0xffffffff, 421 }; 422 423 /* goes into Metadata DW 7 (Qu has no EHT) */ 424 enum iwl_rx_phy_eht_data3 { 425 /* note: low 8 bits cannot be used */ 426 /* info type: EHT-MU-EXT */ 427 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C1 = 0x0003fe00, 428 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C2 = 0x07fc0000, 429 }; 430 431 /* goes into Metadata DW 4 */ 432 enum iwl_rx_phy_eht_data4 { 433 /* info type: EHT-MU-EXT */ 434 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D1 = 0x000001ff, 435 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D2 = 0x0003fe00, 436 IWL_RX_PHY_DATA4_EHT_MU_EXT_SIGB_MCS = 0x000c0000, 437 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_B2 = 0x1ff00000, 438 }; 439 440 /* goes into Metadata DW 16 */ 441 enum iwl_rx_phy_data5 { 442 /* info type: EHT any */ 443 IWL_RX_PHY_DATA5_EHT_TYPE_AND_COMP = 0x00000003, 444 /* info type: EHT-TB */ 445 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE1 = 0x0000003c, 446 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE2 = 0x000003c0, 447 /* info type: EHT-MU */ 448 IWL_RX_PHY_DATA5_EHT_MU_PUNC_CH_CODE = 0x0000007c, 449 IWL_RX_PHY_DATA5_EHT_MU_STA_ID_USR = 0x0003ff80, 450 IWL_RX_PHY_DATA5_EHT_MU_NUM_USR_NON_OFDMA = 0x001c0000, 451 IWL_RX_PHY_DATA5_EHT_MU_SPATIAL_CONF_USR_FIELD = 0x0fe00000, 452 }; 453 454 /** 455 * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor 456 */ 457 struct iwl_rx_mpdu_desc_v1 { 458 /* DW7 - carries rss_hash only when rpa_en == 1 */ 459 union { 460 /** 461 * @rss_hash: RSS hash value 462 */ 463 __le32 rss_hash; 464 465 /** 466 * @phy_data2: depends on info type (see @phy_data1) 467 */ 468 __le32 phy_data2; 469 }; 470 471 /* DW8 - carries filter_match only when rpa_en == 1 */ 472 union { 473 /** 474 * @filter_match: filter match value 475 */ 476 __le32 filter_match; 477 478 /** 479 * @phy_data3: depends on info type (see @phy_data1) 480 */ 481 __le32 phy_data3; 482 }; 483 484 /* DW9 */ 485 /** 486 * @rate_n_flags: RX rate/flags encoding 487 */ 488 __le32 rate_n_flags; 489 /* DW10 */ 490 /** 491 * @energy_a: energy chain A 492 */ 493 u8 energy_a; 494 /** 495 * @energy_b: energy chain B 496 */ 497 u8 energy_b; 498 /** 499 * @channel: channel number 500 */ 501 u8 channel; 502 /** 503 * @mac_context: MAC context mask 504 */ 505 u8 mac_context; 506 /* DW11 */ 507 /** 508 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 509 */ 510 __le32 gp2_on_air_rise; 511 /* DW12 & DW13 */ 512 union { 513 /** 514 * @tsf_on_air_rise: 515 * TSF value on air rise (INA), only valid if 516 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 517 */ 518 __le64 tsf_on_air_rise; 519 520 struct { 521 /** 522 * @phy_data0: depends on info_type, see @phy_data1 523 */ 524 __le32 phy_data0; 525 /** 526 * @phy_data1: valid only if 527 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 528 * see &enum iwl_rx_phy_common_data1 or 529 * &enum iwl_rx_phy_he_data1 or 530 * &enum iwl_rx_phy_eht_data1. 531 */ 532 __le32 phy_data1; 533 }; 534 }; 535 } __packed; /* RX_MPDU_RES_START_API_S_VER_4 */ 536 537 /** 538 * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor 539 */ 540 struct iwl_rx_mpdu_desc_v3 { 541 /* DW7 - carries filter_match only when rpa_en == 1 */ 542 union { 543 /** 544 * @filter_match: filter match value 545 */ 546 __le32 filter_match; 547 548 /** 549 * @phy_data3: depends on info type (see @phy_data1) 550 */ 551 __le32 phy_data3; 552 }; 553 554 /* DW8 - carries rss_hash only when rpa_en == 1 */ 555 union { 556 /** 557 * @rss_hash: RSS hash value 558 */ 559 __le32 rss_hash; 560 561 /** 562 * @phy_data2: depends on info type (see @phy_data1) 563 */ 564 __le32 phy_data2; 565 }; 566 /* DW9 */ 567 /** 568 * @partial_hash: 31:0 ip/tcp header hash 569 * w/o some fields (such as IP SRC addr) 570 */ 571 __le32 partial_hash; 572 /* DW10 */ 573 /** 574 * @raw_xsum: raw xsum value 575 */ 576 __be16 raw_xsum; 577 /** 578 * @reserved_xsum: reserved high bits in the raw checksum 579 */ 580 __le16 reserved_xsum; 581 /* DW11 */ 582 /** 583 * @rate_n_flags: RX rate/flags encoding 584 */ 585 __le32 rate_n_flags; 586 /* DW12 */ 587 /** 588 * @energy_a: energy chain A 589 */ 590 u8 energy_a; 591 /** 592 * @energy_b: energy chain B 593 */ 594 u8 energy_b; 595 /** 596 * @channel: channel number 597 */ 598 u8 channel; 599 /** 600 * @mac_context: MAC context mask 601 */ 602 u8 mac_context; 603 /* DW13 */ 604 /** 605 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 606 */ 607 __le32 gp2_on_air_rise; 608 /* DW14 & DW15 */ 609 union { 610 /** 611 * @tsf_on_air_rise: 612 * TSF value on air rise (INA), only valid if 613 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 614 */ 615 __le64 tsf_on_air_rise; 616 617 struct { 618 /** 619 * @phy_data0: depends on info_type, see @phy_data1 620 */ 621 __le32 phy_data0; 622 /** 623 * @phy_data1: valid only if 624 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 625 * see &enum iwl_rx_phy_data1. 626 */ 627 __le32 phy_data1; 628 }; 629 }; 630 /* DW16 */ 631 /** 632 * @phy_data5: valid only if 633 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 634 * see &enum iwl_rx_phy_data5. 635 */ 636 __le32 phy_data5; 637 /* DW17 */ 638 /** 639 * @reserved: reserved 640 */ 641 __le32 reserved[1]; 642 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 643 RX_MPDU_RES_START_API_S_VER_5 */ 644 645 /** 646 * struct iwl_rx_mpdu_desc - RX MPDU descriptor 647 */ 648 struct iwl_rx_mpdu_desc { 649 /* DW2 */ 650 /** 651 * @mpdu_len: MPDU length 652 */ 653 __le16 mpdu_len; 654 /** 655 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1 656 */ 657 u8 mac_flags1; 658 /** 659 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2 660 */ 661 u8 mac_flags2; 662 /* DW3 */ 663 /** 664 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info 665 */ 666 u8 amsdu_info; 667 /** 668 * @phy_info: &enum iwl_rx_mpdu_phy_info 669 */ 670 __le16 phy_info; 671 /** 672 * @mac_phy_band: MAC ID, PHY ID, band; 673 * see &enum iwl_rx_mpdu_mac_phy_band 674 */ 675 u8 mac_phy_band; 676 /* DW4 */ 677 union { 678 struct { 679 /* carries csum data only when rpa_en == 1 */ 680 /** 681 * @raw_csum: raw checksum (alledgedly unreliable) 682 */ 683 __le16 raw_csum; 684 685 union { 686 /** 687 * @l3l4_flags: &enum iwl_rx_l3l4_flags 688 */ 689 __le16 l3l4_flags; 690 691 /** 692 * @phy_data4: depends on info type, see phy_data1 693 */ 694 __le16 phy_data4; 695 }; 696 }; 697 /** 698 * @phy_eht_data4: depends on info type, see phy_data1 699 */ 700 __le32 phy_eht_data4; 701 }; 702 /* DW5 */ 703 /** 704 * @status: &enum iwl_rx_mpdu_status 705 */ 706 __le32 status; 707 708 /* DW6 */ 709 /** 710 * @reorder_data: &enum iwl_rx_mpdu_reorder_data 711 */ 712 __le32 reorder_data; 713 714 union { 715 /** 716 * @v1: version 1 of the remaining RX descriptor, 717 * see &struct iwl_rx_mpdu_desc_v1 718 */ 719 struct iwl_rx_mpdu_desc_v1 v1; 720 /** 721 * @v3: version 3 of the remaining RX descriptor, 722 * see &struct iwl_rx_mpdu_desc_v3 723 */ 724 struct iwl_rx_mpdu_desc_v3 v3; 725 }; 726 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 727 RX_MPDU_RES_START_API_S_VER_4, 728 RX_MPDU_RES_START_API_S_VER_5 */ 729 730 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1) 731 732 #define RX_NO_DATA_CHAIN_A_POS 0 733 #define RX_NO_DATA_CHAIN_A_MSK (0xff << RX_NO_DATA_CHAIN_A_POS) 734 #define RX_NO_DATA_CHAIN_B_POS 8 735 #define RX_NO_DATA_CHAIN_B_MSK (0xff << RX_NO_DATA_CHAIN_B_POS) 736 #define RX_NO_DATA_CHANNEL_POS 16 737 #define RX_NO_DATA_CHANNEL_MSK (0xff << RX_NO_DATA_CHANNEL_POS) 738 739 #define RX_NO_DATA_INFO_TYPE_POS 0 740 #define RX_NO_DATA_INFO_TYPE_MSK (0xff << RX_NO_DATA_INFO_TYPE_POS) 741 #define RX_NO_DATA_INFO_TYPE_NONE 0 742 #define RX_NO_DATA_INFO_TYPE_RX_ERR 1 743 #define RX_NO_DATA_INFO_TYPE_NDP 2 744 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED 3 745 #define RX_NO_DATA_INFO_TYPE_TB_UNMATCHED 4 746 747 #define RX_NO_DATA_INFO_ERR_POS 8 748 #define RX_NO_DATA_INFO_ERR_MSK (0xff << RX_NO_DATA_INFO_ERR_POS) 749 #define RX_NO_DATA_INFO_ERR_NONE 0 750 #define RX_NO_DATA_INFO_ERR_BAD_PLCP 1 751 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE 2 752 #define RX_NO_DATA_INFO_ERR_NO_DELIM 3 753 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR 4 754 #define RX_NO_DATA_INFO_LOW_ENERGY 5 755 756 #define RX_NO_DATA_FRAME_TIME_POS 0 757 #define RX_NO_DATA_FRAME_TIME_MSK (0xfffff << RX_NO_DATA_FRAME_TIME_POS) 758 759 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK 0x03800000 760 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK 0x38000000 761 #define RX_NO_DATA_RX_VEC2_EHT_NSTS_MSK 0x00f00000 762 763 /* content of OFDM_RX_VECTOR_USIG_A1_OUT */ 764 enum iwl_rx_usig_a1 { 765 IWL_RX_USIG_A1_ENHANCED_WIFI_VER_ID = 0x00000007, 766 IWL_RX_USIG_A1_BANDWIDTH = 0x00000038, 767 IWL_RX_USIG_A1_UL_FLAG = 0x00000040, 768 IWL_RX_USIG_A1_BSS_COLOR = 0x00001f80, 769 IWL_RX_USIG_A1_TXOP_DURATION = 0x000fe000, 770 IWL_RX_USIG_A1_DISREGARD = 0x01f00000, 771 IWL_RX_USIG_A1_VALIDATE = 0x02000000, 772 IWL_RX_USIG_A1_EHT_BW320_SLOT = 0x04000000, 773 IWL_RX_USIG_A1_EHT_TYPE = 0x18000000, 774 IWL_RX_USIG_A1_RDY = 0x80000000, 775 }; 776 777 /* content of OFDM_RX_VECTOR_USIG_A2_EHT_OUT */ 778 enum iwl_rx_usig_a2_eht { 779 IWL_RX_USIG_A2_EHT_PPDU_TYPE = 0x00000003, 780 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B2 = 0x00000004, 781 IWL_RX_USIG_A2_EHT_PUNC_CHANNEL = 0x000000f8, 782 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B8 = 0x00000100, 783 IWL_RX_USIG_A2_EHT_SIG_MCS = 0x00000600, 784 IWL_RX_USIG_A2_EHT_SIG_SYM_NUM = 0x0000f800, 785 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_1 = 0x000f0000, 786 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_2 = 0x00f00000, 787 IWL_RX_USIG_A2_EHT_TRIG_USIG2_DISREGARD = 0x1f000000, 788 IWL_RX_USIG_A2_EHT_CRC_OK = 0x40000000, 789 IWL_RX_USIG_A2_EHT_RDY = 0x80000000, 790 }; 791 792 /** 793 * struct iwl_rx_no_data - RX no data descriptor 794 * @info: 7:0 frame type, 15:8 RX error type 795 * @rssi: 7:0 energy chain-A, 796 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 797 * @on_air_rise_time: GP2 during on air rise 798 * @fr_time: frame time 799 * @rate: rate/mcs of frame 800 * @phy_info: &enum iwl_rx_phy_he_data0 or &enum iwl_rx_phy_eht_data0 801 * based on &enum iwl_rx_phy_info_type 802 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 803 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 804 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 805 */ 806 struct iwl_rx_no_data { 807 __le32 info; 808 __le32 rssi; 809 __le32 on_air_rise_time; 810 __le32 fr_time; 811 __le32 rate; 812 __le32 phy_info[2]; 813 __le32 rx_vec[2]; 814 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1, 815 RX_NO_DATA_NTFY_API_S_VER_2 */ 816 817 /** 818 * struct iwl_rx_no_data_ver_3 - RX no data descriptor 819 * @info: 7:0 frame type, 15:8 RX error type 820 * @rssi: 7:0 energy chain-A, 821 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 822 * @on_air_rise_time: GP2 during on air rise 823 * @fr_time: frame time 824 * @rate: rate/mcs of frame 825 * @phy_info: &enum iwl_rx_phy_eht_data0 and &enum iwl_rx_phy_info_type 826 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 827 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 828 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 829 * for EHT: OFDM_RX_VECTOR_USIG_A1_OUT, OFDM_RX_VECTOR_USIG_A2_EHT_OUT, 830 * OFDM_RX_VECTOR_EHT_OUT, OFDM_RX_VECTOR_EHT_USER_FIELD_OUT 831 */ 832 struct iwl_rx_no_data_ver_3 { 833 __le32 info; 834 __le32 rssi; 835 __le32 on_air_rise_time; 836 __le32 fr_time; 837 __le32 rate; 838 __le32 phy_info[2]; 839 __le32 rx_vec[4]; 840 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1, 841 RX_NO_DATA_NTFY_API_S_VER_2 842 RX_NO_DATA_NTFY_API_S_VER_3 */ 843 844 struct iwl_frame_release { 845 u8 baid; 846 u8 reserved; 847 __le16 nssn; 848 }; 849 850 /** 851 * enum iwl_bar_frame_release_sta_tid - STA/TID information for BAR release 852 * @IWL_BAR_FRAME_RELEASE_TID_MASK: TID mask 853 * @IWL_BAR_FRAME_RELEASE_STA_MASK: STA mask 854 */ 855 enum iwl_bar_frame_release_sta_tid { 856 IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f, 857 IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0, 858 }; 859 860 /** 861 * enum iwl_bar_frame_release_ba_info - BA information for BAR release 862 * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask 863 * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver) 864 * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask 865 */ 866 enum iwl_bar_frame_release_ba_info { 867 IWL_BAR_FRAME_RELEASE_NSSN_MASK = 0x00000fff, 868 IWL_BAR_FRAME_RELEASE_SN_MASK = 0x00fff000, 869 IWL_BAR_FRAME_RELEASE_BAID_MASK = 0x3f000000, 870 }; 871 872 /** 873 * struct iwl_bar_frame_release - frame release from BAR info 874 * @sta_tid: STA & TID information, see &enum iwl_bar_frame_release_sta_tid. 875 * @ba_info: BA information, see &enum iwl_bar_frame_release_ba_info. 876 */ 877 struct iwl_bar_frame_release { 878 __le32 sta_tid; 879 __le32 ba_info; 880 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */ 881 882 enum iwl_rss_hash_func_en { 883 IWL_RSS_HASH_TYPE_IPV4_TCP, 884 IWL_RSS_HASH_TYPE_IPV4_UDP, 885 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD, 886 IWL_RSS_HASH_TYPE_IPV6_TCP, 887 IWL_RSS_HASH_TYPE_IPV6_UDP, 888 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 889 }; 890 891 #define IWL_RSS_HASH_KEY_CNT 10 892 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128 893 #define IWL_RSS_ENABLE 1 894 895 /** 896 * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration 897 * 898 * @flags: 1 - enable, 0 - disable 899 * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en 900 * @reserved: reserved 901 * @secret_key: 320 bit input of random key configuration from driver 902 * @indirection_table: indirection table 903 */ 904 struct iwl_rss_config_cmd { 905 __le32 flags; 906 u8 hash_mask; 907 u8 reserved[3]; 908 __le32 secret_key[IWL_RSS_HASH_KEY_CNT]; 909 u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE]; 910 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */ 911 912 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0 913 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf 914 915 /** 916 * struct iwl_rxq_sync_cmd - RXQ notification trigger 917 * 918 * @flags: flags of the notification. bit 0:3 are the sender queue 919 * @rxq_mask: rx queues to send the notification on 920 * @count: number of bytes in payload, should be DWORD aligned 921 * @payload: data to send to rx queues 922 */ 923 struct iwl_rxq_sync_cmd { 924 __le32 flags; 925 __le32 rxq_mask; 926 __le32 count; 927 u8 payload[]; 928 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 929 930 /** 931 * struct iwl_rxq_sync_notification - Notification triggered by RXQ 932 * sync command 933 * 934 * @count: number of bytes in payload 935 * @payload: data to send to rx queues 936 */ 937 struct iwl_rxq_sync_notification { 938 __le32 count; 939 u8 payload[]; 940 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 941 942 /** 943 * enum iwl_mvm_pm_event - type of station PM event 944 * @IWL_MVM_PM_EVENT_AWAKE: station woke up 945 * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep 946 * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger 947 * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll 948 */ 949 enum iwl_mvm_pm_event { 950 IWL_MVM_PM_EVENT_AWAKE, 951 IWL_MVM_PM_EVENT_ASLEEP, 952 IWL_MVM_PM_EVENT_UAPSD, 953 IWL_MVM_PM_EVENT_PS_POLL, 954 }; /* PEER_PM_NTFY_API_E_VER_1 */ 955 956 /** 957 * struct iwl_mvm_pm_state_notification - station PM state notification 958 * @sta_id: station ID of the station changing state 959 * @type: the new powersave state, see &enum iwl_mvm_pm_event 960 */ 961 struct iwl_mvm_pm_state_notification { 962 u8 sta_id; 963 u8 type; 964 /* private: */ 965 __le16 reserved; 966 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */ 967 968 #define BA_WINDOW_STREAMS_MAX 16 969 #define BA_WINDOW_STATUS_TID_MSK 0x000F 970 #define BA_WINDOW_STATUS_STA_ID_POS 4 971 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0 972 #define BA_WINDOW_STATUS_VALID_MSK BIT(9) 973 974 /** 975 * struct iwl_ba_window_status_notif - reordering window's status notification 976 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63] 977 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid 978 * @start_seq_num: the start sequence number of the bitmap 979 * @mpdu_rx_count: the number of received MPDUs since entering D0i3 980 */ 981 struct iwl_ba_window_status_notif { 982 __le64 bitmap[BA_WINDOW_STREAMS_MAX]; 983 __le16 ra_tid[BA_WINDOW_STREAMS_MAX]; 984 __le32 start_seq_num[BA_WINDOW_STREAMS_MAX]; 985 __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX]; 986 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */ 987 988 /** 989 * struct iwl_rfh_queue_data - RX queue configuration 990 * @q_num: Q num 991 * @enable: enable queue 992 * @reserved: alignment 993 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 994 * @fr_bd_cb: DMA address of freeRB table 995 * @ur_bd_cb: DMA address of used RB table 996 * @fr_bd_wid: Initial index of the free table 997 */ 998 struct iwl_rfh_queue_data { 999 u8 q_num; 1000 u8 enable; 1001 __le16 reserved; 1002 __le64 urbd_stts_wrptr; 1003 __le64 fr_bd_cb; 1004 __le64 ur_bd_cb; 1005 __le32 fr_bd_wid; 1006 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */ 1007 1008 /** 1009 * struct iwl_rfh_queue_config - RX queue configuration 1010 * @num_queues: number of queues configured 1011 * @reserved: alignment 1012 * @data: DMA addresses per-queue 1013 */ 1014 struct iwl_rfh_queue_config { 1015 u8 num_queues; 1016 u8 reserved[3]; 1017 struct iwl_rfh_queue_data data[]; 1018 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */ 1019 1020 #endif /* __iwl_fw_api_rx_h__ */ 1021