1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2025 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_BZ_UCODE_API_MAX 99 14 15 /* Lowest firmware API version supported */ 16 #define IWL_BZ_UCODE_API_MIN 93 17 18 /* Memory offsets and lengths */ 19 #define IWL_BZ_SMEM_OFFSET 0x400000 20 #define IWL_BZ_SMEM_LEN 0xD0000 21 22 #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0" 23 #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0" 24 #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0" 25 #define IWL_BZ_A_FM_B_FW_PRE "iwlwifi-bz-a0-fm-b0" 26 #define IWL_BZ_A_FM_C_FW_PRE "iwlwifi-bz-a0-fm-c0" 27 #define IWL_BZ_A_FM4_B_FW_PRE "iwlwifi-bz-a0-fm4-b0" 28 #define IWL_GL_B_FM_B_FW_PRE "iwlwifi-gl-b0-fm-b0" 29 #define IWL_GL_C_FM_C_FW_PRE "iwlwifi-gl-c0-fm-c0" 30 31 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \ 32 IWL_BZ_A_HR_B_FW_PRE "-" __stringify(api) ".ucode" 33 34 static const struct iwl_family_base_params iwl_bz_base = { 35 .num_of_queues = 512, 36 .max_tfd_queue_size = 65536, 37 .shadow_ram_support = true, 38 .led_compensation = 57, 39 .wd_timeout = IWL_LONG_WD_TIMEOUT, 40 .max_event_log_size = 512, 41 .shadow_reg_enable = true, 42 .pcie_l1_allowed = true, 43 .smem_offset = IWL_BZ_SMEM_OFFSET, 44 .smem_len = IWL_BZ_SMEM_LEN, 45 .apmg_not_supported = true, 46 .mac_addr_from_csr = 0x30, 47 .min_umac_error_event_table = 0xD0000, 48 .d3_debug_data_base_addr = 0x401000, 49 .d3_debug_data_length = 60 * 1024, 50 .mon_smem_regs = { 51 .write_ptr = { 52 .addr = LDBG_M2S_BUF_WPTR, 53 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, 54 }, 55 .cycle_cnt = { 56 .addr = LDBG_M2S_BUF_WRAP_CNT, 57 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, 58 }, 59 }, 60 .min_txq_size = 128, 61 .gp2_reg_addr = 0xd02c68, 62 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, 63 .mon_dram_regs = { 64 .write_ptr = { 65 .addr = DBGC_CUR_DBGBUF_STATUS, 66 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, 67 }, 68 .cycle_cnt = { 69 .addr = DBGC_DBGBUF_WRAP_AROUND, 70 .mask = 0xffffffff, 71 }, 72 .cur_frag = { 73 .addr = DBGC_CUR_DBGBUF_STATUS, 74 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, 75 }, 76 }, 77 .mon_dbgi_regs = { 78 .write_ptr = { 79 .addr = DBGI_SRAM_FIFO_POINTERS, 80 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, 81 }, 82 }, 83 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 84 .ucode_api_max = IWL_BZ_UCODE_API_MAX, 85 .ucode_api_min = IWL_BZ_UCODE_API_MIN, 86 }; 87 88 const struct iwl_mac_cfg iwl_bz_mac_cfg = { 89 .device_family = IWL_DEVICE_FAMILY_BZ, 90 .base = &iwl_bz_base, 91 .mq_rx_supported = true, 92 .gen2 = true, 93 .integrated = true, 94 .umac_prph_offset = 0x300000, 95 .xtal_latency = 12000, 96 .low_latency_xtal = true, 97 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 98 }; 99 100 const struct iwl_mac_cfg iwl_gl_mac_cfg = { 101 .device_family = IWL_DEVICE_FAMILY_BZ, 102 .base = &iwl_bz_base, 103 .mq_rx_supported = true, 104 .gen2 = true, 105 .umac_prph_offset = 0x300000, 106 .xtal_latency = 12000, 107 .low_latency_xtal = true, 108 }; 109 110 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 111 IWL_FW_AND_PNVM(IWL_BZ_A_GF_A_FW_PRE, IWL_BZ_UCODE_API_MAX); 112 IWL_FW_AND_PNVM(IWL_BZ_A_GF4_A_FW_PRE, IWL_BZ_UCODE_API_MAX); 113 IWL_FW_AND_PNVM(IWL_BZ_A_FM_B_FW_PRE, IWL_BZ_UCODE_API_MAX); 114 IWL_FW_AND_PNVM(IWL_BZ_A_FM_C_FW_PRE, IWL_BZ_UCODE_API_MAX); 115 IWL_FW_AND_PNVM(IWL_BZ_A_FM4_B_FW_PRE, IWL_BZ_UCODE_API_MAX); 116 IWL_FW_AND_PNVM(IWL_GL_B_FM_B_FW_PRE, IWL_BZ_UCODE_API_MAX); 117 IWL_FW_AND_PNVM(IWL_GL_C_FM_C_FW_PRE, IWL_BZ_UCODE_API_MAX); 118