1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include "core.h" 8 #include "dp_tx.h" 9 #include "debug.h" 10 #include "debugfs.h" 11 #include "hw.h" 12 #include "peer.h" 13 #include "mac.h" 14 15 static enum hal_tcl_encap_type 16 ath12k_dp_tx_get_encap_type(struct ath12k_link_vif *arvif, struct sk_buff *skb) 17 { 18 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 19 struct ath12k_base *ab = arvif->ar->ab; 20 21 if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) 22 return HAL_TCL_ENCAP_TYPE_RAW; 23 24 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 25 return HAL_TCL_ENCAP_TYPE_ETHERNET; 26 27 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 28 } 29 30 static void ath12k_dp_tx_encap_nwifi(struct sk_buff *skb) 31 { 32 struct ieee80211_hdr *hdr = (void *)skb->data; 33 u8 *qos_ctl; 34 35 if (!ieee80211_is_data_qos(hdr->frame_control)) 36 return; 37 38 qos_ctl = ieee80211_get_qos_ctl(hdr); 39 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 40 skb->data, (void *)qos_ctl - (void *)skb->data); 41 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 42 43 hdr = (void *)skb->data; 44 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 45 } 46 47 static u8 ath12k_dp_tx_get_tid(struct sk_buff *skb) 48 { 49 struct ieee80211_hdr *hdr = (void *)skb->data; 50 struct ath12k_skb_cb *cb = ATH12K_SKB_CB(skb); 51 52 if (cb->flags & ATH12K_SKB_HW_80211_ENCAP) 53 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 54 else if (!ieee80211_is_data_qos(hdr->frame_control)) 55 return HAL_DESC_REO_NON_QOS_TID; 56 else 57 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 58 } 59 60 enum hal_encrypt_type ath12k_dp_tx_get_encrypt_type(u32 cipher) 61 { 62 switch (cipher) { 63 case WLAN_CIPHER_SUITE_WEP40: 64 return HAL_ENCRYPT_TYPE_WEP_40; 65 case WLAN_CIPHER_SUITE_WEP104: 66 return HAL_ENCRYPT_TYPE_WEP_104; 67 case WLAN_CIPHER_SUITE_TKIP: 68 return HAL_ENCRYPT_TYPE_TKIP_MIC; 69 case WLAN_CIPHER_SUITE_CCMP: 70 return HAL_ENCRYPT_TYPE_CCMP_128; 71 case WLAN_CIPHER_SUITE_CCMP_256: 72 return HAL_ENCRYPT_TYPE_CCMP_256; 73 case WLAN_CIPHER_SUITE_GCMP: 74 return HAL_ENCRYPT_TYPE_GCMP_128; 75 case WLAN_CIPHER_SUITE_GCMP_256: 76 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 77 default: 78 return HAL_ENCRYPT_TYPE_OPEN; 79 } 80 } 81 82 static void ath12k_dp_tx_release_txbuf(struct ath12k_dp *dp, 83 struct ath12k_tx_desc_info *tx_desc, 84 u8 pool_id) 85 { 86 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 87 tx_desc->skb_ext_desc = NULL; 88 list_move_tail(&tx_desc->list, &dp->tx_desc_free_list[pool_id]); 89 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 90 } 91 92 static struct ath12k_tx_desc_info *ath12k_dp_tx_assign_buffer(struct ath12k_dp *dp, 93 u8 pool_id) 94 { 95 struct ath12k_tx_desc_info *desc; 96 97 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 98 desc = list_first_entry_or_null(&dp->tx_desc_free_list[pool_id], 99 struct ath12k_tx_desc_info, 100 list); 101 if (!desc) { 102 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 103 ath12k_warn(dp->ab, "failed to allocate data Tx buffer\n"); 104 return NULL; 105 } 106 107 list_move_tail(&desc->list, &dp->tx_desc_used_list[pool_id]); 108 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 109 110 return desc; 111 } 112 113 static void ath12k_hal_tx_cmd_ext_desc_setup(struct ath12k_base *ab, 114 struct hal_tx_msdu_ext_desc *tcl_ext_cmd, 115 struct hal_tx_info *ti) 116 { 117 tcl_ext_cmd->info0 = le32_encode_bits(ti->paddr, 118 HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO); 119 tcl_ext_cmd->info1 = le32_encode_bits(0x0, 120 HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI) | 121 le32_encode_bits(ti->data_len, 122 HAL_TX_MSDU_EXT_INFO1_BUF_LEN); 123 124 tcl_ext_cmd->info1 |= le32_encode_bits(1, HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE) | 125 le32_encode_bits(ti->encap_type, 126 HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE) | 127 le32_encode_bits(ti->encrypt_type, 128 HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE); 129 } 130 131 #define HTT_META_DATA_ALIGNMENT 0x8 132 133 static void *ath12k_dp_metadata_align_skb(struct sk_buff *skb, u8 tail_len) 134 { 135 struct sk_buff *tail; 136 void *metadata; 137 138 if (unlikely(skb_cow_data(skb, tail_len, &tail) < 0)) 139 return NULL; 140 141 metadata = pskb_put(skb, tail, tail_len); 142 memset(metadata, 0, tail_len); 143 return metadata; 144 } 145 146 /* Preparing HTT Metadata when utilized with ext MSDU */ 147 static int ath12k_dp_prepare_htt_metadata(struct sk_buff *skb) 148 { 149 struct hal_tx_msdu_metadata *desc_ext; 150 u8 htt_desc_size; 151 /* Size rounded of multiple of 8 bytes */ 152 u8 htt_desc_size_aligned; 153 154 htt_desc_size = sizeof(struct hal_tx_msdu_metadata); 155 htt_desc_size_aligned = ALIGN(htt_desc_size, HTT_META_DATA_ALIGNMENT); 156 157 desc_ext = ath12k_dp_metadata_align_skb(skb, htt_desc_size_aligned); 158 if (!desc_ext) 159 return -ENOMEM; 160 161 desc_ext->info0 = le32_encode_bits(1, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_FLAG) | 162 le32_encode_bits(0, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_TYPE) | 163 le32_encode_bits(1, 164 HAL_TX_MSDU_METADATA_INFO0_HOST_TX_DESC_POOL); 165 166 return 0; 167 } 168 169 static void ath12k_dp_tx_move_payload(struct sk_buff *skb, 170 unsigned long delta, 171 bool head) 172 { 173 unsigned long len = skb->len; 174 175 if (head) { 176 skb_push(skb, delta); 177 memmove(skb->data, skb->data + delta, len); 178 skb_trim(skb, len); 179 } else { 180 skb_put(skb, delta); 181 memmove(skb->data + delta, skb->data, len); 182 skb_pull(skb, delta); 183 } 184 } 185 186 static int ath12k_dp_tx_align_payload(struct ath12k_base *ab, 187 struct sk_buff **pskb) 188 { 189 u32 iova_mask = ab->hw_params->iova_mask; 190 unsigned long offset, delta1, delta2; 191 struct sk_buff *skb2, *skb = *pskb; 192 unsigned int headroom = skb_headroom(skb); 193 int tailroom = skb_tailroom(skb); 194 int ret = 0; 195 196 offset = (unsigned long)skb->data & iova_mask; 197 delta1 = offset; 198 delta2 = iova_mask - offset + 1; 199 200 if (headroom >= delta1) { 201 ath12k_dp_tx_move_payload(skb, delta1, true); 202 } else if (tailroom >= delta2) { 203 ath12k_dp_tx_move_payload(skb, delta2, false); 204 } else { 205 skb2 = skb_realloc_headroom(skb, iova_mask); 206 if (!skb2) { 207 ret = -ENOMEM; 208 goto out; 209 } 210 211 dev_kfree_skb_any(skb); 212 213 offset = (unsigned long)skb2->data & iova_mask; 214 if (offset) 215 ath12k_dp_tx_move_payload(skb2, offset, true); 216 *pskb = skb2; 217 } 218 219 out: 220 return ret; 221 } 222 223 int ath12k_dp_tx(struct ath12k *ar, struct ath12k_link_vif *arvif, 224 struct sk_buff *skb, bool gsn_valid, int mcbc_gsn, 225 bool is_mcast) 226 { 227 struct ath12k_base *ab = ar->ab; 228 struct ath12k_dp *dp = &ab->dp; 229 struct hal_tx_info ti = {0}; 230 struct ath12k_tx_desc_info *tx_desc; 231 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 232 struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb); 233 struct hal_tcl_data_cmd *hal_tcl_desc; 234 struct hal_tx_msdu_ext_desc *msg; 235 struct sk_buff *skb_ext_desc = NULL; 236 struct hal_srng *tcl_ring; 237 struct ieee80211_hdr *hdr = (void *)skb->data; 238 struct ath12k_vif *ahvif = arvif->ahvif; 239 struct dp_tx_ring *tx_ring; 240 u8 pool_id; 241 u8 hal_ring_id; 242 int ret; 243 u8 ring_selector, ring_map = 0; 244 bool tcl_ring_retry; 245 bool msdu_ext_desc = false; 246 bool add_htt_metadata = false; 247 u32 iova_mask = ab->hw_params->iova_mask; 248 249 if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) 250 return -ESHUTDOWN; 251 252 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 253 !ieee80211_is_data(hdr->frame_control)) 254 return -EOPNOTSUPP; 255 256 pool_id = skb_get_queue_mapping(skb) & (ATH12K_HW_MAX_QUEUES - 1); 257 258 /* Let the default ring selection be based on current processor 259 * number, where one of the 3 tcl rings are selected based on 260 * the smp_processor_id(). In case that ring 261 * is full/busy, we resort to other available rings. 262 * If all rings are full, we drop the packet. 263 * TODO: Add throttling logic when all rings are full 264 */ 265 ring_selector = ab->hw_params->hw_ops->get_ring_selector(skb); 266 267 tcl_ring_sel: 268 tcl_ring_retry = false; 269 ti.ring_id = ring_selector % ab->hw_params->max_tx_ring; 270 271 ring_map |= BIT(ti.ring_id); 272 ti.rbm_id = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[ti.ring_id].rbm_id; 273 274 tx_ring = &dp->tx_ring[ti.ring_id]; 275 276 tx_desc = ath12k_dp_tx_assign_buffer(dp, pool_id); 277 if (!tx_desc) 278 return -ENOMEM; 279 280 ti.bank_id = arvif->bank_id; 281 ti.meta_data_flags = arvif->tcl_metadata; 282 283 if (ahvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW && 284 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags)) { 285 if (skb_cb->flags & ATH12K_SKB_CIPHER_SET) { 286 ti.encrypt_type = 287 ath12k_dp_tx_get_encrypt_type(skb_cb->cipher); 288 289 if (ieee80211_has_protected(hdr->frame_control)) 290 skb_put(skb, IEEE80211_CCMP_MIC_LEN); 291 } else { 292 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 293 } 294 295 msdu_ext_desc = true; 296 } 297 298 if (gsn_valid) { 299 /* Reset and Initialize meta_data_flags with Global Sequence 300 * Number (GSN) info. 301 */ 302 ti.meta_data_flags = 303 u32_encode_bits(HTT_TCL_META_DATA_TYPE_GLOBAL_SEQ_NUM, 304 HTT_TCL_META_DATA_TYPE) | 305 u32_encode_bits(mcbc_gsn, HTT_TCL_META_DATA_GLOBAL_SEQ_NUM); 306 } 307 308 ti.encap_type = ath12k_dp_tx_get_encap_type(arvif, skb); 309 ti.addr_search_flags = arvif->hal_addr_search_flags; 310 ti.search_type = arvif->search_type; 311 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 312 ti.pkt_offset = 0; 313 ti.lmac_id = ar->lmac_id; 314 315 ti.vdev_id = arvif->vdev_id; 316 if (gsn_valid) 317 ti.vdev_id += HTT_TX_MLO_MCAST_HOST_REINJECT_BASE_VDEV_ID; 318 319 ti.bss_ast_hash = arvif->ast_hash; 320 ti.bss_ast_idx = arvif->ast_idx; 321 ti.dscp_tid_tbl_idx = 0; 322 323 if (skb->ip_summed == CHECKSUM_PARTIAL && 324 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) { 325 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN) | 326 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN) | 327 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN) | 328 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN) | 329 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN); 330 } 331 332 ti.flags1 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE); 333 334 ti.tid = ath12k_dp_tx_get_tid(skb); 335 336 switch (ti.encap_type) { 337 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 338 ath12k_dp_tx_encap_nwifi(skb); 339 break; 340 case HAL_TCL_ENCAP_TYPE_RAW: 341 if (!test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) { 342 ret = -EINVAL; 343 goto fail_remove_tx_buf; 344 } 345 break; 346 case HAL_TCL_ENCAP_TYPE_ETHERNET: 347 /* no need to encap */ 348 break; 349 case HAL_TCL_ENCAP_TYPE_802_3: 350 default: 351 /* TODO: Take care of other encap modes as well */ 352 ret = -EINVAL; 353 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 354 goto fail_remove_tx_buf; 355 } 356 357 if (iova_mask && 358 (unsigned long)skb->data & iova_mask) { 359 ret = ath12k_dp_tx_align_payload(ab, &skb); 360 if (ret) { 361 ath12k_warn(ab, "failed to align TX buffer %d\n", ret); 362 /* don't bail out, give original buffer 363 * a chance even unaligned. 364 */ 365 goto map; 366 } 367 368 /* hdr is pointing to a wrong place after alignment, 369 * so refresh it for later use. 370 */ 371 hdr = (void *)skb->data; 372 } 373 map: 374 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 375 if (dma_mapping_error(ab->dev, ti.paddr)) { 376 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 377 ath12k_warn(ab, "failed to DMA map data Tx buffer\n"); 378 ret = -ENOMEM; 379 goto fail_remove_tx_buf; 380 } 381 382 if (!test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags) && 383 !(skb_cb->flags & ATH12K_SKB_HW_80211_ENCAP) && 384 !(skb_cb->flags & ATH12K_SKB_CIPHER_SET) && 385 ieee80211_has_protected(hdr->frame_control)) { 386 /* Add metadata for sw encrypted vlan group traffic */ 387 add_htt_metadata = true; 388 msdu_ext_desc = true; 389 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TO_FW); 390 ti.meta_data_flags |= HTT_TCL_META_DATA_VALID_HTT; 391 ti.encap_type = HAL_TCL_ENCAP_TYPE_RAW; 392 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 393 } 394 395 tx_desc->skb = skb; 396 tx_desc->mac_id = ar->pdev_idx; 397 ti.desc_id = tx_desc->desc_id; 398 ti.data_len = skb->len; 399 skb_cb->paddr = ti.paddr; 400 skb_cb->vif = ahvif->vif; 401 skb_cb->ar = ar; 402 403 if (msdu_ext_desc) { 404 skb_ext_desc = dev_alloc_skb(sizeof(struct hal_tx_msdu_ext_desc)); 405 if (!skb_ext_desc) { 406 ret = -ENOMEM; 407 goto fail_unmap_dma; 408 } 409 410 skb_put(skb_ext_desc, sizeof(struct hal_tx_msdu_ext_desc)); 411 memset(skb_ext_desc->data, 0, skb_ext_desc->len); 412 413 msg = (struct hal_tx_msdu_ext_desc *)skb_ext_desc->data; 414 ath12k_hal_tx_cmd_ext_desc_setup(ab, msg, &ti); 415 416 if (add_htt_metadata) { 417 ret = ath12k_dp_prepare_htt_metadata(skb_ext_desc); 418 if (ret < 0) { 419 ath12k_dbg(ab, ATH12K_DBG_DP_TX, 420 "Failed to add HTT meta data, dropping packet\n"); 421 goto fail_free_ext_skb; 422 } 423 } 424 425 ti.paddr = dma_map_single(ab->dev, skb_ext_desc->data, 426 skb_ext_desc->len, DMA_TO_DEVICE); 427 ret = dma_mapping_error(ab->dev, ti.paddr); 428 if (ret) 429 goto fail_free_ext_skb; 430 431 ti.data_len = skb_ext_desc->len; 432 ti.type = HAL_TCL_DESC_TYPE_EXT_DESC; 433 434 skb_cb->paddr_ext_desc = ti.paddr; 435 tx_desc->skb_ext_desc = skb_ext_desc; 436 } 437 438 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 439 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 440 441 spin_lock_bh(&tcl_ring->lock); 442 443 ath12k_hal_srng_access_begin(ab, tcl_ring); 444 445 hal_tcl_desc = ath12k_hal_srng_src_get_next_entry(ab, tcl_ring); 446 if (!hal_tcl_desc) { 447 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 448 * desc because the desc is directly enqueued onto hw queue. 449 */ 450 ath12k_hal_srng_access_end(ab, tcl_ring); 451 ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 452 spin_unlock_bh(&tcl_ring->lock); 453 ret = -ENOMEM; 454 455 /* Checking for available tcl descriptors in another ring in 456 * case of failure due to full tcl ring now, is better than 457 * checking this ring earlier for each pkt tx. 458 * Restart ring selection if some rings are not checked yet. 459 */ 460 if (ring_map != (BIT(ab->hw_params->max_tx_ring) - 1) && 461 ab->hw_params->tcl_ring_retry) { 462 tcl_ring_retry = true; 463 ring_selector++; 464 } 465 466 goto fail_unmap_dma_ext; 467 } 468 469 spin_lock_bh(&arvif->link_stats_lock); 470 arvif->link_stats.tx_encap_type[ti.encap_type]++; 471 arvif->link_stats.tx_encrypt_type[ti.encrypt_type]++; 472 arvif->link_stats.tx_desc_type[ti.type]++; 473 474 if (is_mcast) 475 arvif->link_stats.tx_bcast_mcast++; 476 else 477 arvif->link_stats.tx_enqueued++; 478 spin_unlock_bh(&arvif->link_stats_lock); 479 480 ath12k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc, &ti); 481 482 ath12k_hal_srng_access_end(ab, tcl_ring); 483 484 spin_unlock_bh(&tcl_ring->lock); 485 486 ath12k_dbg_dump(ab, ATH12K_DBG_DP_TX, NULL, "dp tx msdu: ", 487 skb->data, skb->len); 488 489 atomic_inc(&ar->dp.num_tx_pending); 490 491 return 0; 492 493 fail_unmap_dma_ext: 494 if (skb_cb->paddr_ext_desc) 495 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 496 skb_ext_desc->len, 497 DMA_TO_DEVICE); 498 fail_free_ext_skb: 499 kfree_skb(skb_ext_desc); 500 501 fail_unmap_dma: 502 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 503 504 fail_remove_tx_buf: 505 ath12k_dp_tx_release_txbuf(dp, tx_desc, pool_id); 506 507 spin_lock_bh(&arvif->link_stats_lock); 508 arvif->link_stats.tx_dropped++; 509 spin_unlock_bh(&arvif->link_stats_lock); 510 511 if (tcl_ring_retry) 512 goto tcl_ring_sel; 513 514 return ret; 515 } 516 517 static void ath12k_dp_tx_free_txbuf(struct ath12k_base *ab, 518 struct dp_tx_ring *tx_ring, 519 struct ath12k_tx_desc_params *desc_params) 520 { 521 struct ath12k *ar; 522 struct sk_buff *msdu = desc_params->skb; 523 struct ath12k_skb_cb *skb_cb; 524 u8 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, desc_params->mac_id); 525 526 skb_cb = ATH12K_SKB_CB(msdu); 527 ar = ab->pdevs[pdev_id].ar; 528 529 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 530 if (skb_cb->paddr_ext_desc) { 531 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 532 desc_params->skb_ext_desc->len, DMA_TO_DEVICE); 533 dev_kfree_skb_any(desc_params->skb_ext_desc); 534 } 535 536 ieee80211_free_txskb(ar->ah->hw, msdu); 537 538 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 539 wake_up(&ar->dp.tx_empty_waitq); 540 } 541 542 static void 543 ath12k_dp_tx_htt_tx_complete_buf(struct ath12k_base *ab, 544 struct ath12k_tx_desc_params *desc_params, 545 struct dp_tx_ring *tx_ring, 546 struct ath12k_dp_htt_wbm_tx_status *ts) 547 { 548 struct ieee80211_tx_info *info; 549 struct ath12k_link_vif *arvif; 550 struct ath12k_skb_cb *skb_cb; 551 struct ieee80211_vif *vif; 552 struct ath12k_vif *ahvif; 553 struct ath12k *ar; 554 struct sk_buff *msdu = desc_params->skb; 555 556 skb_cb = ATH12K_SKB_CB(msdu); 557 info = IEEE80211_SKB_CB(msdu); 558 559 ar = skb_cb->ar; 560 561 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 562 wake_up(&ar->dp.tx_empty_waitq); 563 564 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 565 if (skb_cb->paddr_ext_desc) { 566 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 567 desc_params->skb_ext_desc->len, DMA_TO_DEVICE); 568 dev_kfree_skb_any(desc_params->skb_ext_desc); 569 } 570 571 vif = skb_cb->vif; 572 if (vif) { 573 ahvif = ath12k_vif_to_ahvif(vif); 574 rcu_read_lock(); 575 arvif = rcu_dereference(ahvif->link[skb_cb->link_id]); 576 if (arvif) { 577 spin_lock_bh(&arvif->link_stats_lock); 578 arvif->link_stats.tx_completed++; 579 spin_unlock_bh(&arvif->link_stats_lock); 580 } 581 rcu_read_unlock(); 582 } 583 584 memset(&info->status, 0, sizeof(info->status)); 585 586 if (ts->acked) { 587 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 588 info->flags |= IEEE80211_TX_STAT_ACK; 589 info->status.ack_signal = ts->ack_rssi; 590 591 if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT, 592 ab->wmi_ab.svc_map)) 593 info->status.ack_signal += ATH12K_DEFAULT_NOISE_FLOOR; 594 595 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 596 } else { 597 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 598 } 599 } 600 601 ieee80211_tx_status_skb(ath12k_ar_to_hw(ar), msdu); 602 } 603 604 static void 605 ath12k_dp_tx_process_htt_tx_complete(struct ath12k_base *ab, void *desc, 606 struct dp_tx_ring *tx_ring, 607 struct ath12k_tx_desc_params *desc_params) 608 { 609 struct htt_tx_wbm_completion *status_desc; 610 struct ath12k_dp_htt_wbm_tx_status ts = {0}; 611 enum hal_wbm_htt_tx_comp_status wbm_status; 612 613 status_desc = desc; 614 615 wbm_status = le32_get_bits(status_desc->info0, 616 HTT_TX_WBM_COMP_INFO0_STATUS); 617 618 switch (wbm_status) { 619 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 620 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 621 ts.ack_rssi = le32_get_bits(status_desc->info2, 622 HTT_TX_WBM_COMP_INFO2_ACK_RSSI); 623 ath12k_dp_tx_htt_tx_complete_buf(ab, desc_params, tx_ring, &ts); 624 break; 625 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 626 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 627 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 628 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 629 case HAL_WBM_REL_HTT_TX_COMP_STATUS_VDEVID_MISMATCH: 630 ath12k_dp_tx_free_txbuf(ab, tx_ring, desc_params); 631 break; 632 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 633 /* This event is to be handled only when the driver decides to 634 * use WDS offload functionality. 635 */ 636 break; 637 default: 638 ath12k_warn(ab, "Unknown htt wbm tx status %d\n", wbm_status); 639 break; 640 } 641 } 642 643 static void ath12k_dp_tx_update_txcompl(struct ath12k *ar, struct hal_tx_status *ts) 644 { 645 struct ath12k_base *ab = ar->ab; 646 struct ath12k_peer *peer; 647 struct ieee80211_sta *sta; 648 struct ath12k_sta *ahsta; 649 struct ath12k_link_sta *arsta; 650 struct rate_info txrate = {0}; 651 u16 rate, ru_tones; 652 u8 rate_idx = 0; 653 int ret; 654 655 spin_lock_bh(&ab->base_lock); 656 peer = ath12k_peer_find_by_id(ab, ts->peer_id); 657 if (!peer || !peer->sta) { 658 ath12k_dbg(ab, ATH12K_DBG_DP_TX, 659 "failed to find the peer by id %u\n", ts->peer_id); 660 spin_unlock_bh(&ab->base_lock); 661 return; 662 } 663 sta = peer->sta; 664 ahsta = ath12k_sta_to_ahsta(sta); 665 arsta = &ahsta->deflink; 666 667 /* This is to prefer choose the real NSS value arsta->last_txrate.nss, 668 * if it is invalid, then choose the NSS value while assoc. 669 */ 670 if (arsta->last_txrate.nss) 671 txrate.nss = arsta->last_txrate.nss; 672 else 673 txrate.nss = arsta->peer_nss; 674 spin_unlock_bh(&ab->base_lock); 675 676 switch (ts->pkt_type) { 677 case HAL_TX_RATE_STATS_PKT_TYPE_11A: 678 case HAL_TX_RATE_STATS_PKT_TYPE_11B: 679 ret = ath12k_mac_hw_ratecode_to_legacy_rate(ts->mcs, 680 ts->pkt_type, 681 &rate_idx, 682 &rate); 683 if (ret < 0) { 684 ath12k_warn(ab, "Invalid tx legacy rate %d\n", ret); 685 return; 686 } 687 688 txrate.legacy = rate; 689 break; 690 case HAL_TX_RATE_STATS_PKT_TYPE_11N: 691 if (ts->mcs > ATH12K_HT_MCS_MAX) { 692 ath12k_warn(ab, "Invalid HT mcs index %d\n", ts->mcs); 693 return; 694 } 695 696 if (txrate.nss != 0) 697 txrate.mcs = ts->mcs + 8 * (txrate.nss - 1); 698 699 txrate.flags = RATE_INFO_FLAGS_MCS; 700 701 if (ts->sgi) 702 txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 703 break; 704 case HAL_TX_RATE_STATS_PKT_TYPE_11AC: 705 if (ts->mcs > ATH12K_VHT_MCS_MAX) { 706 ath12k_warn(ab, "Invalid VHT mcs index %d\n", ts->mcs); 707 return; 708 } 709 710 txrate.mcs = ts->mcs; 711 txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 712 713 if (ts->sgi) 714 txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 715 break; 716 case HAL_TX_RATE_STATS_PKT_TYPE_11AX: 717 if (ts->mcs > ATH12K_HE_MCS_MAX) { 718 ath12k_warn(ab, "Invalid HE mcs index %d\n", ts->mcs); 719 return; 720 } 721 722 txrate.mcs = ts->mcs; 723 txrate.flags = RATE_INFO_FLAGS_HE_MCS; 724 txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(ts->sgi); 725 break; 726 case HAL_TX_RATE_STATS_PKT_TYPE_11BE: 727 if (ts->mcs > ATH12K_EHT_MCS_MAX) { 728 ath12k_warn(ab, "Invalid EHT mcs index %d\n", ts->mcs); 729 return; 730 } 731 732 txrate.mcs = ts->mcs; 733 txrate.flags = RATE_INFO_FLAGS_EHT_MCS; 734 txrate.eht_gi = ath12k_mac_eht_gi_to_nl80211_eht_gi(ts->sgi); 735 break; 736 default: 737 ath12k_warn(ab, "Invalid tx pkt type: %d\n", ts->pkt_type); 738 return; 739 } 740 741 txrate.bw = ath12k_mac_bw_to_mac80211_bw(ts->bw); 742 743 if (ts->ofdma && ts->pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) { 744 txrate.bw = RATE_INFO_BW_HE_RU; 745 ru_tones = ath12k_mac_he_convert_tones_to_ru_tones(ts->tones); 746 txrate.he_ru_alloc = 747 ath12k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones); 748 } 749 750 if (ts->ofdma && ts->pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11BE) { 751 txrate.bw = RATE_INFO_BW_EHT_RU; 752 txrate.eht_ru_alloc = 753 ath12k_mac_eht_ru_tones_to_nl80211_eht_ru_alloc(ts->tones); 754 } 755 756 spin_lock_bh(&ab->base_lock); 757 arsta->txrate = txrate; 758 spin_unlock_bh(&ab->base_lock); 759 } 760 761 static void ath12k_dp_tx_complete_msdu(struct ath12k *ar, 762 struct ath12k_tx_desc_params *desc_params, 763 struct hal_tx_status *ts) 764 { 765 struct ath12k_base *ab = ar->ab; 766 struct ath12k_hw *ah = ar->ah; 767 struct ieee80211_tx_info *info; 768 struct ath12k_link_vif *arvif; 769 struct ath12k_skb_cb *skb_cb; 770 struct ieee80211_vif *vif; 771 struct ath12k_vif *ahvif; 772 struct sk_buff *msdu = desc_params->skb; 773 774 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 775 /* Must not happen */ 776 return; 777 } 778 779 skb_cb = ATH12K_SKB_CB(msdu); 780 781 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 782 if (skb_cb->paddr_ext_desc) { 783 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 784 desc_params->skb_ext_desc->len, DMA_TO_DEVICE); 785 dev_kfree_skb_any(desc_params->skb_ext_desc); 786 } 787 788 rcu_read_lock(); 789 790 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) { 791 ieee80211_free_txskb(ah->hw, msdu); 792 goto exit; 793 } 794 795 if (!skb_cb->vif) { 796 ieee80211_free_txskb(ah->hw, msdu); 797 goto exit; 798 } 799 800 vif = skb_cb->vif; 801 if (vif) { 802 ahvif = ath12k_vif_to_ahvif(vif); 803 arvif = rcu_dereference(ahvif->link[skb_cb->link_id]); 804 if (arvif) { 805 spin_lock_bh(&arvif->link_stats_lock); 806 arvif->link_stats.tx_completed++; 807 spin_unlock_bh(&arvif->link_stats_lock); 808 } 809 } 810 811 info = IEEE80211_SKB_CB(msdu); 812 memset(&info->status, 0, sizeof(info->status)); 813 814 /* skip tx rate update from ieee80211_status*/ 815 info->status.rates[0].idx = -1; 816 817 switch (ts->status) { 818 case HAL_WBM_TQM_REL_REASON_FRAME_ACKED: 819 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 820 info->flags |= IEEE80211_TX_STAT_ACK; 821 info->status.ack_signal = ts->ack_rssi; 822 823 if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT, 824 ab->wmi_ab.svc_map)) 825 info->status.ack_signal += ATH12K_DEFAULT_NOISE_FLOOR; 826 827 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 828 } 829 break; 830 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: 831 if (info->flags & IEEE80211_TX_CTL_NO_ACK) { 832 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 833 break; 834 } 835 fallthrough; 836 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: 837 case HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD: 838 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: 839 /* The failure status is due to internal firmware tx failure 840 * hence drop the frame; do not update the status of frame to 841 * the upper layer 842 */ 843 ieee80211_free_txskb(ah->hw, msdu); 844 goto exit; 845 default: 846 ath12k_dbg(ab, ATH12K_DBG_DP_TX, "tx frame is not acked status %d\n", 847 ts->status); 848 break; 849 } 850 851 /* NOTE: Tx rate status reporting. Tx completion status does not have 852 * necessary information (for example nss) to build the tx rate. 853 * Might end up reporting it out-of-band from HTT stats. 854 */ 855 856 ath12k_dp_tx_update_txcompl(ar, ts); 857 858 ieee80211_tx_status_skb(ath12k_ar_to_hw(ar), msdu); 859 860 exit: 861 rcu_read_unlock(); 862 } 863 864 static void ath12k_dp_tx_status_parse(struct ath12k_base *ab, 865 struct hal_wbm_completion_ring_tx *desc, 866 struct hal_tx_status *ts) 867 { 868 u32 info0 = le32_to_cpu(desc->rate_stats.info0); 869 870 ts->buf_rel_source = 871 le32_get_bits(desc->info0, HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE); 872 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 873 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) 874 return; 875 876 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) 877 return; 878 879 ts->status = le32_get_bits(desc->info0, 880 HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON); 881 882 ts->ppdu_id = le32_get_bits(desc->info1, 883 HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER); 884 885 ts->peer_id = le32_get_bits(desc->info3, HAL_WBM_COMPL_TX_INFO3_PEER_ID); 886 887 if (info0 & HAL_TX_RATE_STATS_INFO0_VALID) { 888 ts->pkt_type = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_PKT_TYPE); 889 ts->mcs = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_MCS); 890 ts->sgi = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_SGI); 891 ts->bw = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_BW); 892 ts->tones = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_TONES_IN_RU); 893 ts->ofdma = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_OFDMA_TX); 894 } 895 } 896 897 void ath12k_dp_tx_completion_handler(struct ath12k_base *ab, int ring_id) 898 { 899 struct ath12k *ar; 900 struct ath12k_dp *dp = &ab->dp; 901 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 902 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 903 struct ath12k_tx_desc_info *tx_desc = NULL; 904 struct hal_tx_status ts = { 0 }; 905 struct ath12k_tx_desc_params desc_params; 906 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 907 struct hal_wbm_release_ring *desc; 908 u8 pdev_id; 909 u64 desc_va; 910 911 spin_lock_bh(&status_ring->lock); 912 913 ath12k_hal_srng_access_begin(ab, status_ring); 914 915 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) != tx_ring->tx_status_tail) { 916 desc = ath12k_hal_srng_dst_get_next_entry(ab, status_ring); 917 if (!desc) 918 break; 919 920 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 921 desc, sizeof(*desc)); 922 tx_ring->tx_status_head = 923 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head); 924 } 925 926 if (ath12k_hal_srng_dst_peek(ab, status_ring) && 927 (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) { 928 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 929 ath12k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 930 } 931 932 ath12k_hal_srng_access_end(ab, status_ring); 933 934 spin_unlock_bh(&status_ring->lock); 935 936 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 937 struct hal_wbm_completion_ring_tx *tx_status; 938 u32 desc_id; 939 940 tx_ring->tx_status_tail = 941 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 942 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 943 ath12k_dp_tx_status_parse(ab, tx_status, &ts); 944 945 if (le32_get_bits(tx_status->info0, HAL_WBM_COMPL_TX_INFO0_CC_DONE)) { 946 /* HW done cookie conversion */ 947 desc_va = ((u64)le32_to_cpu(tx_status->buf_va_hi) << 32 | 948 le32_to_cpu(tx_status->buf_va_lo)); 949 tx_desc = (struct ath12k_tx_desc_info *)((unsigned long)desc_va); 950 } else { 951 /* SW does cookie conversion to VA */ 952 desc_id = le32_get_bits(tx_status->buf_va_hi, 953 BUFFER_ADDR_INFO1_SW_COOKIE); 954 955 tx_desc = ath12k_dp_get_tx_desc(ab, desc_id); 956 } 957 if (!tx_desc) { 958 ath12k_warn(ab, "unable to retrieve tx_desc!"); 959 continue; 960 } 961 962 desc_params.mac_id = tx_desc->mac_id; 963 desc_params.skb = tx_desc->skb; 964 desc_params.skb_ext_desc = tx_desc->skb_ext_desc; 965 966 /* Release descriptor as soon as extracting necessary info 967 * to reduce contention 968 */ 969 ath12k_dp_tx_release_txbuf(dp, tx_desc, tx_desc->pool_id); 970 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { 971 ath12k_dp_tx_process_htt_tx_complete(ab, (void *)tx_status, 972 tx_ring, &desc_params); 973 continue; 974 } 975 976 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, desc_params.mac_id); 977 ar = ab->pdevs[pdev_id].ar; 978 979 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 980 wake_up(&ar->dp.tx_empty_waitq); 981 982 ath12k_dp_tx_complete_msdu(ar, &desc_params, &ts); 983 } 984 } 985 986 static int 987 ath12k_dp_tx_get_ring_id_type(struct ath12k_base *ab, 988 int mac_id, u32 ring_id, 989 enum hal_ring_type ring_type, 990 enum htt_srng_ring_type *htt_ring_type, 991 enum htt_srng_ring_id *htt_ring_id) 992 { 993 int ret = 0; 994 995 switch (ring_type) { 996 case HAL_RXDMA_BUF: 997 /* for some targets, host fills rx buffer to fw and fw fills to 998 * rxbuf ring for each rxdma 999 */ 1000 if (!ab->hw_params->rx_mac_buf_ring) { 1001 if (!(ring_id == HAL_SRNG_SW2RXDMA_BUF0 || 1002 ring_id == HAL_SRNG_SW2RXDMA_BUF1)) { 1003 ret = -EINVAL; 1004 } 1005 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 1006 *htt_ring_type = HTT_SW_TO_HW_RING; 1007 } else { 1008 if (ring_id == HAL_SRNG_SW2RXDMA_BUF0) { 1009 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 1010 *htt_ring_type = HTT_SW_TO_SW_RING; 1011 } else { 1012 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 1013 *htt_ring_type = HTT_SW_TO_HW_RING; 1014 } 1015 } 1016 break; 1017 case HAL_RXDMA_DST: 1018 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 1019 *htt_ring_type = HTT_HW_TO_SW_RING; 1020 break; 1021 case HAL_RXDMA_MONITOR_BUF: 1022 *htt_ring_id = HTT_RX_MON_HOST2MON_BUF_RING; 1023 *htt_ring_type = HTT_SW_TO_HW_RING; 1024 break; 1025 case HAL_RXDMA_MONITOR_STATUS: 1026 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 1027 *htt_ring_type = HTT_SW_TO_HW_RING; 1028 break; 1029 case HAL_RXDMA_MONITOR_DST: 1030 *htt_ring_id = HTT_RX_MON_MON2HOST_DEST_RING; 1031 *htt_ring_type = HTT_HW_TO_SW_RING; 1032 break; 1033 case HAL_RXDMA_MONITOR_DESC: 1034 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 1035 *htt_ring_type = HTT_SW_TO_HW_RING; 1036 break; 1037 default: 1038 ath12k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 1039 ret = -EINVAL; 1040 } 1041 return ret; 1042 } 1043 1044 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 1045 int mac_id, enum hal_ring_type ring_type) 1046 { 1047 struct htt_srng_setup_cmd *cmd; 1048 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 1049 struct hal_srng_params params; 1050 struct sk_buff *skb; 1051 u32 ring_entry_sz; 1052 int len = sizeof(*cmd); 1053 dma_addr_t hp_addr, tp_addr; 1054 enum htt_srng_ring_type htt_ring_type; 1055 enum htt_srng_ring_id htt_ring_id; 1056 int ret; 1057 1058 skb = ath12k_htc_alloc_skb(ab, len); 1059 if (!skb) 1060 return -ENOMEM; 1061 1062 memset(¶ms, 0, sizeof(params)); 1063 ath12k_hal_srng_get_params(ab, srng, ¶ms); 1064 1065 hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng); 1066 tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng); 1067 1068 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 1069 ring_type, &htt_ring_type, 1070 &htt_ring_id); 1071 if (ret) 1072 goto err_free; 1073 1074 skb_put(skb, len); 1075 cmd = (struct htt_srng_setup_cmd *)skb->data; 1076 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_SRING_SETUP, 1077 HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE); 1078 if (htt_ring_type == HTT_SW_TO_HW_RING || 1079 htt_ring_type == HTT_HW_TO_SW_RING) 1080 cmd->info0 |= le32_encode_bits(DP_SW2HW_MACID(mac_id), 1081 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID); 1082 else 1083 cmd->info0 |= le32_encode_bits(mac_id, 1084 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID); 1085 cmd->info0 |= le32_encode_bits(htt_ring_type, 1086 HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE); 1087 cmd->info0 |= le32_encode_bits(htt_ring_id, 1088 HTT_SRNG_SETUP_CMD_INFO0_RING_ID); 1089 1090 cmd->ring_base_addr_lo = cpu_to_le32(params.ring_base_paddr & 1091 HAL_ADDR_LSB_REG_MASK); 1092 1093 cmd->ring_base_addr_hi = cpu_to_le32((u64)params.ring_base_paddr >> 1094 HAL_ADDR_MSB_REG_SHIFT); 1095 1096 ret = ath12k_hal_srng_get_entrysize(ab, ring_type); 1097 if (ret < 0) 1098 goto err_free; 1099 1100 ring_entry_sz = ret; 1101 1102 ring_entry_sz >>= 2; 1103 cmd->info1 = le32_encode_bits(ring_entry_sz, 1104 HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE); 1105 cmd->info1 |= le32_encode_bits(params.num_entries * ring_entry_sz, 1106 HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE); 1107 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 1108 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP); 1109 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 1110 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP); 1111 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP), 1112 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP); 1113 if (htt_ring_type == HTT_SW_TO_HW_RING) 1114 cmd->info1 |= cpu_to_le32(HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS); 1115 1116 cmd->ring_head_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(hp_addr)); 1117 cmd->ring_head_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(hp_addr)); 1118 1119 cmd->ring_tail_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(tp_addr)); 1120 cmd->ring_tail_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(tp_addr)); 1121 1122 cmd->ring_msi_addr_lo = cpu_to_le32(lower_32_bits(params.msi_addr)); 1123 cmd->ring_msi_addr_hi = cpu_to_le32(upper_32_bits(params.msi_addr)); 1124 cmd->msi_data = cpu_to_le32(params.msi_data); 1125 1126 cmd->intr_info = 1127 le32_encode_bits(params.intr_batch_cntr_thres_entries * ring_entry_sz, 1128 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH); 1129 cmd->intr_info |= 1130 le32_encode_bits(params.intr_timer_thres_us >> 3, 1131 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH); 1132 1133 cmd->info2 = 0; 1134 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 1135 cmd->info2 = le32_encode_bits(params.low_threshold, 1136 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH); 1137 } 1138 1139 ath12k_dbg(ab, ATH12K_DBG_HAL, 1140 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n", 1141 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi, 1142 cmd->msi_data); 1143 1144 ath12k_dbg(ab, ATH12K_DBG_HAL, 1145 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n", 1146 ring_id, ring_type, cmd->intr_info, cmd->info2); 1147 1148 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 1149 if (ret) 1150 goto err_free; 1151 1152 return 0; 1153 1154 err_free: 1155 dev_kfree_skb_any(skb); 1156 1157 return ret; 1158 } 1159 1160 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 1161 1162 int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab) 1163 { 1164 struct ath12k_dp *dp = &ab->dp; 1165 struct sk_buff *skb; 1166 struct htt_ver_req_cmd *cmd; 1167 int len = sizeof(*cmd); 1168 int ret; 1169 1170 init_completion(&dp->htt_tgt_version_received); 1171 1172 skb = ath12k_htc_alloc_skb(ab, len); 1173 if (!skb) 1174 return -ENOMEM; 1175 1176 skb_put(skb, len); 1177 cmd = (struct htt_ver_req_cmd *)skb->data; 1178 cmd->ver_reg_info = le32_encode_bits(HTT_H2T_MSG_TYPE_VERSION_REQ, 1179 HTT_OPTION_TAG); 1180 1181 cmd->tcl_metadata_version = le32_encode_bits(HTT_TAG_TCL_METADATA_VERSION, 1182 HTT_OPTION_TAG) | 1183 le32_encode_bits(HTT_TCL_METADATA_VER_SZ, 1184 HTT_OPTION_LEN) | 1185 le32_encode_bits(HTT_OPTION_TCL_METADATA_VER_V2, 1186 HTT_OPTION_VALUE); 1187 1188 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 1189 if (ret) { 1190 dev_kfree_skb_any(skb); 1191 return ret; 1192 } 1193 1194 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 1195 HTT_TARGET_VERSION_TIMEOUT_HZ); 1196 if (ret == 0) { 1197 ath12k_warn(ab, "htt target version request timed out\n"); 1198 return -ETIMEDOUT; 1199 } 1200 1201 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 1202 ath12k_err(ab, "unsupported htt major version %d supported version is %d\n", 1203 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 1204 return -EOPNOTSUPP; 1205 } 1206 1207 return 0; 1208 } 1209 1210 int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask) 1211 { 1212 struct ath12k_base *ab = ar->ab; 1213 struct ath12k_dp *dp = &ab->dp; 1214 struct sk_buff *skb; 1215 struct htt_ppdu_stats_cfg_cmd *cmd; 1216 int len = sizeof(*cmd); 1217 u8 pdev_mask; 1218 int ret; 1219 int i; 1220 1221 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1222 skb = ath12k_htc_alloc_skb(ab, len); 1223 if (!skb) 1224 return -ENOMEM; 1225 1226 skb_put(skb, len); 1227 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 1228 cmd->msg = le32_encode_bits(HTT_H2T_MSG_TYPE_PPDU_STATS_CFG, 1229 HTT_PPDU_STATS_CFG_MSG_TYPE); 1230 1231 pdev_mask = 1 << (i + 1); 1232 cmd->msg |= le32_encode_bits(pdev_mask, HTT_PPDU_STATS_CFG_PDEV_ID); 1233 cmd->msg |= le32_encode_bits(mask, HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK); 1234 1235 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 1236 if (ret) { 1237 dev_kfree_skb_any(skb); 1238 return ret; 1239 } 1240 } 1241 1242 return 0; 1243 } 1244 1245 int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id, 1246 int mac_id, enum hal_ring_type ring_type, 1247 int rx_buf_size, 1248 struct htt_rx_ring_tlv_filter *tlv_filter) 1249 { 1250 struct htt_rx_ring_selection_cfg_cmd *cmd; 1251 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 1252 struct hal_srng_params params; 1253 struct sk_buff *skb; 1254 int len = sizeof(*cmd); 1255 enum htt_srng_ring_type htt_ring_type; 1256 enum htt_srng_ring_id htt_ring_id; 1257 int ret; 1258 1259 skb = ath12k_htc_alloc_skb(ab, len); 1260 if (!skb) 1261 return -ENOMEM; 1262 1263 memset(¶ms, 0, sizeof(params)); 1264 ath12k_hal_srng_get_params(ab, srng, ¶ms); 1265 1266 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 1267 ring_type, &htt_ring_type, 1268 &htt_ring_id); 1269 if (ret) 1270 goto err_free; 1271 1272 skb_put(skb, len); 1273 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 1274 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG, 1275 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE); 1276 if (htt_ring_type == HTT_SW_TO_HW_RING || 1277 htt_ring_type == HTT_HW_TO_SW_RING) 1278 cmd->info0 |= 1279 le32_encode_bits(DP_SW2HW_MACID(mac_id), 1280 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1281 else 1282 cmd->info0 |= 1283 le32_encode_bits(mac_id, 1284 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1285 cmd->info0 |= le32_encode_bits(htt_ring_id, 1286 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID); 1287 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 1288 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS); 1289 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 1290 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS); 1291 cmd->info0 |= le32_encode_bits(tlv_filter->offset_valid, 1292 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_OFFSET_VALID); 1293 cmd->info0 |= 1294 le32_encode_bits(tlv_filter->drop_threshold_valid, 1295 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_DROP_THRES_VAL); 1296 cmd->info0 |= le32_encode_bits(!tlv_filter->rxmon_disable, 1297 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_EN_RXMON); 1298 1299 cmd->info1 = le32_encode_bits(rx_buf_size, 1300 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE); 1301 cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_mgmt, 1302 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT); 1303 cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_ctrl, 1304 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL); 1305 cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_data, 1306 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA); 1307 cmd->pkt_type_en_flags0 = cpu_to_le32(tlv_filter->pkt_filter_flags0); 1308 cmd->pkt_type_en_flags1 = cpu_to_le32(tlv_filter->pkt_filter_flags1); 1309 cmd->pkt_type_en_flags2 = cpu_to_le32(tlv_filter->pkt_filter_flags2); 1310 cmd->pkt_type_en_flags3 = cpu_to_le32(tlv_filter->pkt_filter_flags3); 1311 cmd->rx_filter_tlv = cpu_to_le32(tlv_filter->rx_filter); 1312 1313 cmd->info2 = le32_encode_bits(tlv_filter->rx_drop_threshold, 1314 HTT_RX_RING_SELECTION_CFG_CMD_INFO2_DROP_THRESHOLD); 1315 cmd->info2 |= 1316 le32_encode_bits(tlv_filter->enable_log_mgmt_type, 1317 HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_MGMT_TYPE); 1318 cmd->info2 |= 1319 le32_encode_bits(tlv_filter->enable_log_ctrl_type, 1320 HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_CTRL_TYPE); 1321 cmd->info2 |= 1322 le32_encode_bits(tlv_filter->enable_log_data_type, 1323 HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_DATA_TYPE); 1324 1325 cmd->info3 = 1326 le32_encode_bits(tlv_filter->enable_rx_tlv_offset, 1327 HTT_RX_RING_SELECTION_CFG_CMD_INFO3_EN_TLV_PKT_OFFSET); 1328 cmd->info3 |= 1329 le32_encode_bits(tlv_filter->rx_tlv_offset, 1330 HTT_RX_RING_SELECTION_CFG_CMD_INFO3_PKT_TLV_OFFSET); 1331 1332 if (tlv_filter->offset_valid) { 1333 cmd->rx_packet_offset = 1334 le32_encode_bits(tlv_filter->rx_packet_offset, 1335 HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET); 1336 1337 cmd->rx_packet_offset |= 1338 le32_encode_bits(tlv_filter->rx_header_offset, 1339 HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET); 1340 1341 cmd->rx_mpdu_offset = 1342 le32_encode_bits(tlv_filter->rx_mpdu_end_offset, 1343 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET); 1344 1345 cmd->rx_mpdu_offset |= 1346 le32_encode_bits(tlv_filter->rx_mpdu_start_offset, 1347 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET); 1348 1349 cmd->rx_msdu_offset = 1350 le32_encode_bits(tlv_filter->rx_msdu_end_offset, 1351 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET); 1352 1353 cmd->rx_msdu_offset |= 1354 le32_encode_bits(tlv_filter->rx_msdu_start_offset, 1355 HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET); 1356 1357 cmd->rx_attn_offset = 1358 le32_encode_bits(tlv_filter->rx_attn_offset, 1359 HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET); 1360 } 1361 1362 if (tlv_filter->rx_mpdu_start_wmask > 0 && 1363 tlv_filter->rx_msdu_end_wmask > 0) { 1364 cmd->info2 |= 1365 le32_encode_bits(true, 1366 HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET); 1367 cmd->rx_mpdu_start_end_mask = 1368 le32_encode_bits(tlv_filter->rx_mpdu_start_wmask, 1369 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK); 1370 /* mpdu_end is not used for any hardwares so far 1371 * please assign it in future if any chip is 1372 * using through hal ops 1373 */ 1374 cmd->rx_mpdu_start_end_mask |= 1375 le32_encode_bits(tlv_filter->rx_mpdu_end_wmask, 1376 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK); 1377 cmd->rx_msdu_end_word_mask = 1378 le32_encode_bits(tlv_filter->rx_msdu_end_wmask, 1379 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK); 1380 } 1381 1382 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 1383 if (ret) 1384 goto err_free; 1385 1386 return 0; 1387 1388 err_free: 1389 dev_kfree_skb_any(skb); 1390 1391 return ret; 1392 } 1393 1394 int 1395 ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type, 1396 struct htt_ext_stats_cfg_params *cfg_params, 1397 u64 cookie) 1398 { 1399 struct ath12k_base *ab = ar->ab; 1400 struct ath12k_dp *dp = &ab->dp; 1401 struct sk_buff *skb; 1402 struct htt_ext_stats_cfg_cmd *cmd; 1403 int len = sizeof(*cmd); 1404 int ret; 1405 u32 pdev_id; 1406 1407 skb = ath12k_htc_alloc_skb(ab, len); 1408 if (!skb) 1409 return -ENOMEM; 1410 1411 skb_put(skb, len); 1412 1413 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 1414 memset(cmd, 0, sizeof(*cmd)); 1415 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 1416 1417 pdev_id = ath12k_mac_get_target_pdev_id(ar); 1418 cmd->hdr.pdev_mask = 1 << pdev_id; 1419 1420 cmd->hdr.stats_type = type; 1421 cmd->cfg_param0 = cpu_to_le32(cfg_params->cfg0); 1422 cmd->cfg_param1 = cpu_to_le32(cfg_params->cfg1); 1423 cmd->cfg_param2 = cpu_to_le32(cfg_params->cfg2); 1424 cmd->cfg_param3 = cpu_to_le32(cfg_params->cfg3); 1425 cmd->cookie_lsb = cpu_to_le32(lower_32_bits(cookie)); 1426 cmd->cookie_msb = cpu_to_le32(upper_32_bits(cookie)); 1427 1428 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 1429 if (ret) { 1430 ath12k_warn(ab, "failed to send htt type stats request: %d", 1431 ret); 1432 dev_kfree_skb_any(skb); 1433 return ret; 1434 } 1435 1436 return 0; 1437 } 1438 1439 int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1440 { 1441 struct ath12k_base *ab = ar->ab; 1442 int ret; 1443 1444 ret = ath12k_dp_tx_htt_rx_monitor_mode_ring_config(ar, reset); 1445 if (ret) { 1446 ath12k_err(ab, "failed to setup rx monitor filter %d\n", ret); 1447 return ret; 1448 } 1449 1450 return 0; 1451 } 1452 1453 int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1454 { 1455 struct ath12k_base *ab = ar->ab; 1456 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 1457 int ret, ring_id, i; 1458 1459 tlv_filter.offset_valid = false; 1460 1461 if (!reset) { 1462 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_DEST_RING; 1463 1464 tlv_filter.drop_threshold_valid = true; 1465 tlv_filter.rx_drop_threshold = HTT_RX_RING_TLV_DROP_THRESHOLD_VALUE; 1466 1467 tlv_filter.enable_log_mgmt_type = true; 1468 tlv_filter.enable_log_ctrl_type = true; 1469 tlv_filter.enable_log_data_type = true; 1470 1471 tlv_filter.conf_len_ctrl = HTT_RX_RING_DEFAULT_DMA_LENGTH; 1472 tlv_filter.conf_len_mgmt = HTT_RX_RING_DEFAULT_DMA_LENGTH; 1473 tlv_filter.conf_len_data = HTT_RX_RING_DEFAULT_DMA_LENGTH; 1474 1475 tlv_filter.enable_rx_tlv_offset = true; 1476 tlv_filter.rx_tlv_offset = HTT_RX_RING_PKT_TLV_OFFSET; 1477 1478 tlv_filter.pkt_filter_flags0 = 1479 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1480 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1481 tlv_filter.pkt_filter_flags1 = 1482 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1483 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1484 tlv_filter.pkt_filter_flags2 = 1485 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1486 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1487 tlv_filter.pkt_filter_flags3 = 1488 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1489 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1490 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1491 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1492 } else { 1493 tlv_filter = ath12k_mac_mon_status_filter_default; 1494 1495 if (ath12k_debugfs_is_extd_rx_stats_enabled(ar)) 1496 tlv_filter.rx_filter = ath12k_debugfs_rx_filter(ar); 1497 } 1498 1499 if (ab->hw_params->rxdma1_enable) { 1500 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1501 ring_id = ar->dp.rxdma_mon_dst_ring[i].ring_id; 1502 ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 1503 ar->dp.mac_id + i, 1504 HAL_RXDMA_MONITOR_DST, 1505 DP_RXDMA_REFILL_RING_SIZE, 1506 &tlv_filter); 1507 if (ret) { 1508 ath12k_err(ab, 1509 "failed to setup filter for monitor buf %d\n", 1510 ret); 1511 return ret; 1512 } 1513 } 1514 } 1515 1516 return 0; 1517 } 1518 1519 int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id, 1520 int mac_id, enum hal_ring_type ring_type, 1521 int tx_buf_size, 1522 struct htt_tx_ring_tlv_filter *htt_tlv_filter) 1523 { 1524 struct htt_tx_ring_selection_cfg_cmd *cmd; 1525 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 1526 struct hal_srng_params params; 1527 struct sk_buff *skb; 1528 int len = sizeof(*cmd); 1529 enum htt_srng_ring_type htt_ring_type; 1530 enum htt_srng_ring_id htt_ring_id; 1531 int ret; 1532 1533 skb = ath12k_htc_alloc_skb(ab, len); 1534 if (!skb) 1535 return -ENOMEM; 1536 1537 memset(¶ms, 0, sizeof(params)); 1538 ath12k_hal_srng_get_params(ab, srng, ¶ms); 1539 1540 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 1541 ring_type, &htt_ring_type, 1542 &htt_ring_id); 1543 1544 if (ret) 1545 goto err_free; 1546 1547 skb_put(skb, len); 1548 cmd = (struct htt_tx_ring_selection_cfg_cmd *)skb->data; 1549 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_TX_MONITOR_CFG, 1550 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE); 1551 if (htt_ring_type == HTT_SW_TO_HW_RING || 1552 htt_ring_type == HTT_HW_TO_SW_RING) 1553 cmd->info0 |= 1554 le32_encode_bits(DP_SW2HW_MACID(mac_id), 1555 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1556 else 1557 cmd->info0 |= 1558 le32_encode_bits(mac_id, 1559 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1560 cmd->info0 |= le32_encode_bits(htt_ring_id, 1561 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID); 1562 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 1563 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS); 1564 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 1565 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS); 1566 1567 cmd->info1 |= 1568 le32_encode_bits(tx_buf_size, 1569 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE); 1570 1571 if (htt_tlv_filter->tx_mon_mgmt_filter) { 1572 cmd->info1 |= 1573 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT, 1574 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1575 cmd->info1 |= 1576 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1577 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT); 1578 cmd->info2 |= 1579 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT, 1580 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1581 } 1582 1583 if (htt_tlv_filter->tx_mon_data_filter) { 1584 cmd->info1 |= 1585 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL, 1586 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1587 cmd->info1 |= 1588 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1589 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL); 1590 cmd->info2 |= 1591 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL, 1592 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1593 } 1594 1595 if (htt_tlv_filter->tx_mon_ctrl_filter) { 1596 cmd->info1 |= 1597 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA, 1598 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1599 cmd->info1 |= 1600 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1601 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA); 1602 cmd->info2 |= 1603 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA, 1604 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1605 } 1606 1607 cmd->tlv_filter_mask_in0 = 1608 cpu_to_le32(htt_tlv_filter->tx_mon_downstream_tlv_flags); 1609 cmd->tlv_filter_mask_in1 = 1610 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags0); 1611 cmd->tlv_filter_mask_in2 = 1612 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags1); 1613 cmd->tlv_filter_mask_in3 = 1614 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags2); 1615 1616 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 1617 if (ret) 1618 goto err_free; 1619 1620 return 0; 1621 1622 err_free: 1623 dev_kfree_skb_any(skb); 1624 return ret; 1625 } 1626