1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef DEBUG_HTT_STATS_H 8 #define DEBUG_HTT_STATS_H 9 10 #define ATH12K_HTT_STATS_BUF_SIZE (1024 * 512) 11 #define ATH12K_HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0) 12 #define ATH12K_HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32) 13 #define ATH12K_HTT_STATS_MAGIC_VALUE 0xF0F0F0F0 14 #define ATH12K_HTT_STATS_SUBTYPE_MAX 16 15 #define ATH12K_HTT_MAX_STRING_LEN 256 16 17 #define ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx) ((_idx) & 0x1f) 18 #define ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx) ((_idx) & 0x3f) 19 #define ATH12K_HTT_STATS_RESET_BITMAP32_BIT(_idx) (1 << \ 20 ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx)) 21 #define ATH12K_HTT_STATS_RESET_BITMAP64_BIT(_idx) (1 << \ 22 ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx)) 23 24 void ath12k_debugfs_htt_stats_register(struct ath12k *ar); 25 26 #ifdef CONFIG_ATH12K_DEBUGFS 27 void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab, 28 struct sk_buff *skb); 29 #else /* CONFIG_ATH12K_DEBUGFS */ 30 static inline void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab, 31 struct sk_buff *skb) 32 { 33 } 34 #endif 35 36 /** 37 * DOC: target -> host extended statistics upload 38 * 39 * The following field definitions describe the format of the HTT 40 * target to host stats upload confirmation message. 41 * The message contains a cookie echoed from the HTT host->target stats 42 * upload request, which identifies which request the confirmation is 43 * for, and a single stats can span over multiple HTT stats indication 44 * due to the HTT message size limitation so every HTT ext stats 45 * indication will have tag-length-value stats information elements. 46 * The tag-length header for each HTT stats IND message also includes a 47 * status field, to indicate whether the request for the stat type in 48 * question was fully met, partially met, unable to be met, or invalid 49 * (if the stat type in question is disabled in the target). 50 * A Done bit 1's indicate the end of the of stats info elements. 51 * 52 * 53 * |31 16|15 12|11|10 8|7 5|4 0| 54 * |--------------------------------------------------------------| 55 * | reserved | msg type | 56 * |--------------------------------------------------------------| 57 * | cookie LSBs | 58 * |--------------------------------------------------------------| 59 * | cookie MSBs | 60 * |--------------------------------------------------------------| 61 * | stats entry length | rsvd | D| S | stat type | 62 * |--------------------------------------------------------------| 63 * | type-specific stats info | 64 * | (see debugfs_htt_stats.h) | 65 * |--------------------------------------------------------------| 66 * Header fields: 67 * - MSG_TYPE 68 * Bits 7:0 69 * Purpose: Identifies this is a extended statistics upload confirmation 70 * message. 71 * Value: 0x1c 72 * - COOKIE_LSBS 73 * Bits 31:0 74 * Purpose: Provide a mechanism to match a target->host stats confirmation 75 * message with its preceding host->target stats request message. 76 * Value: MSBs of the opaque cookie specified by the host-side requestor 77 * - COOKIE_MSBS 78 * Bits 31:0 79 * Purpose: Provide a mechanism to match a target->host stats confirmation 80 * message with its preceding host->target stats request message. 81 * Value: MSBs of the opaque cookie specified by the host-side requestor 82 * 83 * Stats Information Element tag-length header fields: 84 * - STAT_TYPE 85 * Bits 7:0 86 * Purpose: identifies the type of statistics info held in the 87 * following information element 88 * Value: ath12k_dbg_htt_ext_stats_type 89 * - STATUS 90 * Bits 10:8 91 * Purpose: indicate whether the requested stats are present 92 * Value: 93 * 0 -> The requested stats have been delivered in full 94 * 1 -> The requested stats have been delivered in part 95 * 2 -> The requested stats could not be delivered (error case) 96 * 3 -> The requested stat type is either not recognized (invalid) 97 * - DONE 98 * Bits 11 99 * Purpose: 100 * Indicates the completion of the stats entry, this will be the last 101 * stats conf HTT segment for the requested stats type. 102 * Value: 103 * 0 -> the stats retrieval is ongoing 104 * 1 -> the stats retrieval is complete 105 * - LENGTH 106 * Bits 31:16 107 * Purpose: indicate the stats information size 108 * Value: This field specifies the number of bytes of stats information 109 * that follows the element tag-length header. 110 * It is expected but not required that this length is a multiple of 111 * 4 bytes. 112 */ 113 114 #define ATH12K_HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) 115 #define ATH12K_HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 116 117 struct ath12k_htt_extd_stats_msg { 118 __le32 info0; 119 __le64 cookie; 120 __le32 info1; 121 u8 data[]; 122 } __packed; 123 124 /* htt_dbg_ext_stats_type */ 125 enum ath12k_dbg_htt_ext_stats_type { 126 ATH12K_DBG_HTT_EXT_STATS_RESET = 0, 127 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX = 1, 128 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_SCHED = 4, 129 ATH12K_DBG_HTT_EXT_STATS_PDEV_ERROR = 5, 130 ATH12K_DBG_HTT_EXT_STATS_PDEV_TQM = 6, 131 ATH12K_DBG_HTT_EXT_STATS_TX_DE_INFO = 8, 132 ATH12K_DBG_HTT_EXT_STATS_TX_SELFGEN_INFO = 12, 133 ATH12K_DBG_HTT_EXT_STATS_SRNG_INFO = 15, 134 ATH12K_DBG_HTT_EXT_STATS_SFM_INFO = 16, 135 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_MU = 17, 136 ATH12K_DBG_HTT_EXT_STATS_PDEV_CCA_STATS = 19, 137 ATH12K_DBG_HTT_EXT_STATS_PDEV_OBSS_PD_STATS = 23, 138 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_RATE_TXBF = 31, 139 ATH12K_DBG_HTT_EXT_STATS_TXBF_OFDMA = 32, 140 ATH12K_DBG_HTT_EXT_STATS_DLPAGER_STATS = 36, 141 ATH12K_DBG_HTT_EXT_PHY_COUNTERS_AND_PHY_STATS = 37, 142 ATH12K_DBG_HTT_EXT_VDEVS_TXRX_STATS = 38, 143 ATH12K_DBG_HTT_EXT_PDEV_PER_STATS = 40, 144 ATH12K_DBG_HTT_EXT_AST_ENTRIES = 41, 145 ATH12K_DBG_HTT_EXT_STATS_SOC_ERROR = 45, 146 ATH12K_DBG_HTT_DBG_PDEV_PUNCTURE_STATS = 46, 147 ATH12K_DBG_HTT_EXT_STATS_PDEV_SCHED_ALGO = 49, 148 ATH12K_DBG_HTT_EXT_STATS_MANDATORY_MUOFDMA = 51, 149 ATH12K_DGB_HTT_EXT_STATS_PDEV_MBSSID_CTRL_FRAME = 54, 150 151 /* keep this last */ 152 ATH12K_DBG_HTT_NUM_EXT_STATS, 153 }; 154 155 enum ath12k_dbg_htt_tlv_tag { 156 HTT_STATS_TX_PDEV_CMN_TAG = 0, 157 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, 158 HTT_STATS_TX_PDEV_SIFS_TAG = 2, 159 HTT_STATS_TX_PDEV_FLUSH_TAG = 3, 160 HTT_STATS_STRING_TAG = 5, 161 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, 162 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, 163 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, 164 HTT_STATS_TX_TQM_CMN_TAG = 14, 165 HTT_STATS_TX_TQM_PDEV_TAG = 15, 166 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, 167 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, 168 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, 169 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, 170 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, 171 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, 172 HTT_STATS_TX_DE_CMN_TAG = 23, 173 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, 174 HTT_STATS_SFM_CMN_TAG = 26, 175 HTT_STATS_SRING_STATS_TAG = 27, 176 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, 177 HTT_STATS_TX_SCHED_CMN_TAG = 37, 178 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, 179 HTT_STATS_SFM_CLIENT_USER_TAG = 41, 180 HTT_STATS_SFM_CLIENT_TAG = 42, 181 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, 182 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, 183 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, 184 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, 185 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, 186 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, 187 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, 188 HTT_STATS_HW_INTR_MISC_TAG = 54, 189 HTT_STATS_HW_PDEV_ERRS_TAG = 56, 190 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, 191 HTT_STATS_WHAL_TX_TAG = 66, 192 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, 193 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, 194 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, 195 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, 196 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, 197 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, 198 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, 199 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, 200 HTT_STATS_PDEV_OBSS_PD_TAG = 88, 201 HTT_STATS_HW_WAR_TAG = 89, 202 HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG = 100, 203 HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG = 102, 204 HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108, 205 HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG = 111, 206 HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG = 112, 207 HTT_STATS_DLPAGER_STATS_TAG = 120, 208 HTT_STATS_PHY_COUNTERS_TAG = 121, 209 HTT_STATS_PHY_STATS_TAG = 122, 210 HTT_STATS_PHY_RESET_COUNTERS_TAG = 123, 211 HTT_STATS_PHY_RESET_STATS_TAG = 124, 212 HTT_STATS_SOC_TXRX_STATS_COMMON_TAG = 125, 213 HTT_STATS_PER_RATE_STATS_TAG = 128, 214 HTT_STATS_MU_PPDU_DIST_TAG = 129, 215 HTT_STATS_TX_PDEV_MUMIMO_GRP_STATS_TAG = 130, 216 HTT_STATS_AST_ENTRY_TAG = 132, 217 HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = 135, 218 HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137, 219 HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138, 220 HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG = 139, 221 HTT_STATS_TXBF_OFDMA_AX_NDPA_STATS_TAG = 147, 222 HTT_STATS_TXBF_OFDMA_AX_NDP_STATS_TAG = 148, 223 HTT_STATS_TXBF_OFDMA_AX_BRP_STATS_TAG = 149, 224 HTT_STATS_TXBF_OFDMA_AX_STEER_STATS_TAG = 150, 225 HTT_STATS_DMAC_RESET_STATS_TAG = 155, 226 HTT_STATS_PHY_TPC_STATS_TAG = 157, 227 HTT_STATS_PDEV_PUNCTURE_STATS_TAG = 158, 228 HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_TAG = 165, 229 HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG = 172, 230 HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, 231 232 HTT_STATS_MAX_TAG, 233 }; 234 235 #define ATH12K_HTT_STATS_MAC_ID GENMASK(7, 0) 236 237 #define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9 238 #define ATH12K_HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 150 239 240 /* MU MIMO distribution stats is a 2-dimensional array 241 * with dimension one denoting stats for nr4[0] or nr8[1] 242 */ 243 #define ATH12K_HTT_STATS_NUM_NR_BINS 2 244 #define ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST 10 245 #define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10 246 #define ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS 9 247 #define ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS \ 248 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS) 249 #define ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS \ 250 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST) 251 252 enum ath12k_htt_tx_pdev_underrun_enum { 253 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0, 254 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1, 255 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2, 256 HTT_TX_PDEV_MAX_URRN_STATS = 3, 257 }; 258 259 enum ath12k_htt_stats_reset_cfg_param_alloc_pos { 260 ATH12K_HTT_STATS_RESET_PARAM_CFG_32_BYTES = 1, 261 ATH12K_HTT_STATS_RESET_PARAM_CFG_64_BYTES, 262 ATH12K_HTT_STATS_RESET_PARAM_CFG_128_BYTES, 263 }; 264 265 struct debug_htt_stats_req { 266 bool done; 267 bool override_cfg_param; 268 u8 pdev_id; 269 enum ath12k_dbg_htt_ext_stats_type type; 270 u32 cfg_param[4]; 271 u8 peer_addr[ETH_ALEN]; 272 struct completion htt_stats_rcvd; 273 u32 buf_len; 274 u8 buf[]; 275 }; 276 277 struct ath12k_htt_tx_pdev_stats_cmn_tlv { 278 __le32 mac_id__word; 279 __le32 hw_queued; 280 __le32 hw_reaped; 281 __le32 underrun; 282 __le32 hw_paused; 283 __le32 hw_flush; 284 __le32 hw_filt; 285 __le32 tx_abort; 286 __le32 mpdu_requed; 287 __le32 tx_xretry; 288 __le32 data_rc; 289 __le32 mpdu_dropped_xretry; 290 __le32 illgl_rate_phy_err; 291 __le32 cont_xretry; 292 __le32 tx_timeout; 293 __le32 pdev_resets; 294 __le32 phy_underrun; 295 __le32 txop_ovf; 296 __le32 seq_posted; 297 __le32 seq_failed_queueing; 298 __le32 seq_completed; 299 __le32 seq_restarted; 300 __le32 mu_seq_posted; 301 __le32 seq_switch_hw_paused; 302 __le32 next_seq_posted_dsr; 303 __le32 seq_posted_isr; 304 __le32 seq_ctrl_cached; 305 __le32 mpdu_count_tqm; 306 __le32 msdu_count_tqm; 307 __le32 mpdu_removed_tqm; 308 __le32 msdu_removed_tqm; 309 __le32 mpdus_sw_flush; 310 __le32 mpdus_hw_filter; 311 __le32 mpdus_truncated; 312 __le32 mpdus_ack_failed; 313 __le32 mpdus_expired; 314 __le32 mpdus_seq_hw_retry; 315 __le32 ack_tlv_proc; 316 __le32 coex_abort_mpdu_cnt_valid; 317 __le32 coex_abort_mpdu_cnt; 318 __le32 num_total_ppdus_tried_ota; 319 __le32 num_data_ppdus_tried_ota; 320 __le32 local_ctrl_mgmt_enqued; 321 __le32 local_ctrl_mgmt_freed; 322 __le32 local_data_enqued; 323 __le32 local_data_freed; 324 __le32 mpdu_tried; 325 __le32 isr_wait_seq_posted; 326 327 __le32 tx_active_dur_us_low; 328 __le32 tx_active_dur_us_high; 329 __le32 remove_mpdus_max_retries; 330 __le32 comp_delivered; 331 __le32 ppdu_ok; 332 __le32 self_triggers; 333 __le32 tx_time_dur_data; 334 __le32 seq_qdepth_repost_stop; 335 __le32 mu_seq_min_msdu_repost_stop; 336 __le32 seq_min_msdu_repost_stop; 337 __le32 seq_txop_repost_stop; 338 __le32 next_seq_cancel; 339 __le32 fes_offsets_err_cnt; 340 __le32 num_mu_peer_blacklisted; 341 __le32 mu_ofdma_seq_posted; 342 __le32 ul_mumimo_seq_posted; 343 __le32 ul_ofdma_seq_posted; 344 345 __le32 thermal_suspend_cnt; 346 __le32 dfs_suspend_cnt; 347 __le32 tx_abort_suspend_cnt; 348 __le32 tgt_specific_opaque_txq_suspend_info; 349 __le32 last_suspend_reason; 350 } __packed; 351 352 struct ath12k_htt_tx_pdev_stats_urrn_tlv { 353 DECLARE_FLEX_ARRAY(__le32, urrn_stats); 354 } __packed; 355 356 struct ath12k_htt_tx_pdev_stats_flush_tlv { 357 DECLARE_FLEX_ARRAY(__le32, flush_errs); 358 } __packed; 359 360 struct ath12k_htt_tx_pdev_stats_phy_err_tlv { 361 DECLARE_FLEX_ARRAY(__le32, phy_errs); 362 } __packed; 363 364 struct ath12k_htt_tx_pdev_stats_sifs_tlv { 365 DECLARE_FLEX_ARRAY(__le32, sifs_status); 366 } __packed; 367 368 struct ath12k_htt_pdev_ctrl_path_tx_stats_tlv { 369 __le32 fw_tx_mgmt_subtype[ATH12K_HTT_STATS_SUBTYPE_MAX]; 370 } __packed; 371 372 struct ath12k_htt_tx_pdev_stats_sifs_hist_tlv { 373 DECLARE_FLEX_ARRAY(__le32, sifs_hist_status); 374 } __packed; 375 376 enum ath12k_htt_stats_hw_mode { 377 ATH12K_HTT_STATS_HWMODE_AC = 0, 378 ATH12K_HTT_STATS_HWMODE_AX = 1, 379 ATH12K_HTT_STATS_HWMODE_BE = 2, 380 }; 381 382 struct ath12k_htt_tx_pdev_mu_ppdu_dist_stats_tlv { 383 __le32 hw_mode; 384 __le32 num_seq_term_status[ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS]; 385 __le32 num_ppdu_cmpl_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS]; 386 __le32 num_seq_posted[ATH12K_HTT_STATS_NUM_NR_BINS]; 387 __le32 num_ppdu_posted_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS]; 388 } __packed; 389 390 #define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0) 391 #define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8) 392 393 #define ATH12K_HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20 394 395 struct ath12k_htt_stats_tx_sched_cmn_tlv { 396 __le32 mac_id__word; 397 __le32 current_timestamp; 398 } __packed; 399 400 struct ath12k_htt_tx_pdev_stats_sched_per_txq_tlv { 401 __le32 mac_id__word; 402 __le32 sched_policy; 403 __le32 last_sched_cmd_posted_timestamp; 404 __le32 last_sched_cmd_compl_timestamp; 405 __le32 sched_2_tac_lwm_count; 406 __le32 sched_2_tac_ring_full; 407 __le32 sched_cmd_post_failure; 408 __le32 num_active_tids; 409 __le32 num_ps_schedules; 410 __le32 sched_cmds_pending; 411 __le32 num_tid_register; 412 __le32 num_tid_unregister; 413 __le32 num_qstats_queried; 414 __le32 qstats_update_pending; 415 __le32 last_qstats_query_timestamp; 416 __le32 num_tqm_cmdq_full; 417 __le32 num_de_sched_algo_trigger; 418 __le32 num_rt_sched_algo_trigger; 419 __le32 num_tqm_sched_algo_trigger; 420 __le32 notify_sched; 421 __le32 dur_based_sendn_term; 422 __le32 su_notify2_sched; 423 __le32 su_optimal_queued_msdus_sched; 424 __le32 su_delay_timeout_sched; 425 __le32 su_min_txtime_sched_delay; 426 __le32 su_no_delay; 427 __le32 num_supercycles; 428 __le32 num_subcycles_with_sort; 429 __le32 num_subcycles_no_sort; 430 } __packed; 431 432 struct ath12k_htt_sched_txq_cmd_posted_tlv { 433 DECLARE_FLEX_ARRAY(__le32, sched_cmd_posted); 434 } __packed; 435 436 struct ath12k_htt_sched_txq_cmd_reaped_tlv { 437 DECLARE_FLEX_ARRAY(__le32, sched_cmd_reaped); 438 } __packed; 439 440 struct ath12k_htt_sched_txq_sched_order_su_tlv { 441 DECLARE_FLEX_ARRAY(__le32, sched_order_su); 442 } __packed; 443 444 struct ath12k_htt_sched_txq_sched_ineligibility_tlv { 445 DECLARE_FLEX_ARRAY(__le32, sched_ineligibility); 446 } __packed; 447 448 enum ath12k_htt_sched_txq_supercycle_triggers_tlv_enum { 449 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0, 450 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_FORCED, 451 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_TIDQ_ENTRIES, 452 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_ACTIVE_TIDS, 453 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX_ITR_REACHED, 454 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_DUR_THRESHOLD_REACHED, 455 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_TWT_TRIGGER, 456 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX, 457 }; 458 459 struct ath12k_htt_sched_txq_supercycle_triggers_tlv { 460 DECLARE_FLEX_ARRAY(__le32, supercycle_triggers); 461 } __packed; 462 463 struct ath12k_htt_hw_stats_pdev_errs_tlv { 464 __le32 mac_id__word; 465 __le32 tx_abort; 466 __le32 tx_abort_fail_count; 467 __le32 rx_abort; 468 __le32 rx_abort_fail_count; 469 __le32 warm_reset; 470 __le32 cold_reset; 471 __le32 tx_flush; 472 __le32 tx_glb_reset; 473 __le32 tx_txq_reset; 474 __le32 rx_timeout_reset; 475 __le32 mac_cold_reset_restore_cal; 476 __le32 mac_cold_reset; 477 __le32 mac_warm_reset; 478 __le32 mac_only_reset; 479 __le32 phy_warm_reset; 480 __le32 phy_warm_reset_ucode_trig; 481 __le32 mac_warm_reset_restore_cal; 482 __le32 mac_sfm_reset; 483 __le32 phy_warm_reset_m3_ssr; 484 __le32 phy_warm_reset_reason_phy_m3; 485 __le32 phy_warm_reset_reason_tx_hw_stuck; 486 __le32 phy_warm_reset_reason_num_rx_frame_stuck; 487 __le32 phy_warm_reset_reason_wal_rx_rec_rx_busy; 488 __le32 phy_warm_reset_reason_wal_rx_rec_mac_hng; 489 __le32 phy_warm_reset_reason_mac_conv_phy_reset; 490 __le32 wal_rx_recovery_rst_mac_hang_cnt; 491 __le32 wal_rx_recovery_rst_known_sig_cnt; 492 __le32 wal_rx_recovery_rst_no_rx_cnt; 493 __le32 wal_rx_recovery_rst_no_rx_consec_cnt; 494 __le32 wal_rx_recovery_rst_rx_busy_cnt; 495 __le32 wal_rx_recovery_rst_phy_mac_hang_cnt; 496 __le32 rx_flush_cnt; 497 __le32 phy_warm_reset_reason_tx_exp_cca_stuck; 498 __le32 phy_warm_reset_reason_tx_consec_flsh_war; 499 __le32 phy_warm_reset_reason_tx_hwsch_reset_war; 500 __le32 phy_warm_reset_reason_hwsch_cca_wdog_war; 501 __le32 fw_rx_rings_reset; 502 __le32 rx_dest_drain_rx_descs_leak_prevented; 503 __le32 rx_dest_drain_rx_descs_saved_cnt; 504 __le32 rx_dest_drain_rxdma2reo_leak_detected; 505 __le32 rx_dest_drain_rxdma2fw_leak_detected; 506 __le32 rx_dest_drain_rxdma2wbm_leak_detected; 507 __le32 rx_dest_drain_rxdma1_2sw_leak_detected; 508 __le32 rx_dest_drain_rx_drain_ok_mac_idle; 509 __le32 rx_dest_drain_ok_mac_not_idle; 510 __le32 rx_dest_drain_prerequisite_invld; 511 __le32 rx_dest_drain_skip_non_lmac_reset; 512 __le32 rx_dest_drain_hw_fifo_notempty_post_wait; 513 } __packed; 514 515 #define ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN 8 516 struct ath12k_htt_hw_stats_intr_misc_tlv { 517 u8 hw_intr_name[ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN]; 518 __le32 mask; 519 __le32 count; 520 } __packed; 521 522 struct ath12k_htt_hw_stats_whal_tx_tlv { 523 __le32 mac_id__word; 524 __le32 last_unpause_ppdu_id; 525 __le32 hwsch_unpause_wait_tqm_write; 526 __le32 hwsch_dummy_tlv_skipped; 527 __le32 hwsch_misaligned_offset_received; 528 __le32 hwsch_reset_count; 529 __le32 hwsch_dev_reset_war; 530 __le32 hwsch_delayed_pause; 531 __le32 hwsch_long_delayed_pause; 532 __le32 sch_rx_ppdu_no_response; 533 __le32 sch_selfgen_response; 534 __le32 sch_rx_sifs_resp_trigger; 535 } __packed; 536 537 struct ath12k_htt_hw_war_stats_tlv { 538 __le32 mac_id__word; 539 DECLARE_FLEX_ARRAY(__le32, hw_wars); 540 } __packed; 541 542 struct ath12k_htt_tx_tqm_cmn_stats_tlv { 543 __le32 mac_id__word; 544 __le32 max_cmdq_id; 545 __le32 list_mpdu_cnt_hist_intvl; 546 __le32 add_msdu; 547 __le32 q_empty; 548 __le32 q_not_empty; 549 __le32 drop_notification; 550 __le32 desc_threshold; 551 __le32 hwsch_tqm_invalid_status; 552 __le32 missed_tqm_gen_mpdus; 553 __le32 tqm_active_tids; 554 __le32 tqm_inactive_tids; 555 __le32 tqm_active_msduq_flows; 556 __le32 msduq_timestamp_updates; 557 __le32 msduq_updates_mpdu_head_info_cmd; 558 __le32 msduq_updates_emp_to_nonemp_status; 559 __le32 get_mpdu_head_info_cmds_by_query; 560 __le32 get_mpdu_head_info_cmds_by_tac; 561 __le32 gen_mpdu_cmds_by_query; 562 __le32 high_prio_q_not_empty; 563 } __packed; 564 565 struct ath12k_htt_tx_tqm_error_stats_tlv { 566 __le32 q_empty_failure; 567 __le32 q_not_empty_failure; 568 __le32 add_msdu_failure; 569 __le32 tqm_cache_ctl_err; 570 __le32 tqm_soft_reset; 571 __le32 tqm_reset_num_in_use_link_descs; 572 __le32 tqm_reset_num_lost_link_descs; 573 __le32 tqm_reset_num_lost_host_tx_buf_cnt; 574 __le32 tqm_reset_num_in_use_internal_tqm; 575 __le32 tqm_reset_num_in_use_idle_link_rng; 576 __le32 tqm_reset_time_to_tqm_hang_delta_ms; 577 __le32 tqm_reset_recovery_time_ms; 578 __le32 tqm_reset_num_peers_hdl; 579 __le32 tqm_reset_cumm_dirty_hw_mpduq_cnt; 580 __le32 tqm_reset_cumm_dirty_hw_msduq_proc; 581 __le32 tqm_reset_flush_cache_cmd_su_cnt; 582 __le32 tqm_reset_flush_cache_cmd_other_cnt; 583 __le32 tqm_reset_flush_cache_cmd_trig_type; 584 __le32 tqm_reset_flush_cache_cmd_trig_cfg; 585 __le32 tqm_reset_flush_cmd_skp_status_null; 586 } __packed; 587 588 struct ath12k_htt_tx_tqm_gen_mpdu_stats_tlv { 589 DECLARE_FLEX_ARRAY(__le32, gen_mpdu_end_reason); 590 } __packed; 591 592 #define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16 593 #define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16 594 595 struct ath12k_htt_tx_tqm_list_mpdu_stats_tlv { 596 DECLARE_FLEX_ARRAY(__le32, list_mpdu_end_reason); 597 } __packed; 598 599 struct ath12k_htt_tx_tqm_list_mpdu_cnt_tlv { 600 DECLARE_FLEX_ARRAY(__le32, list_mpdu_cnt_hist); 601 } __packed; 602 603 struct ath12k_htt_tx_tqm_pdev_stats_tlv { 604 __le32 msdu_count; 605 __le32 mpdu_count; 606 __le32 remove_msdu; 607 __le32 remove_mpdu; 608 __le32 remove_msdu_ttl; 609 __le32 send_bar; 610 __le32 bar_sync; 611 __le32 notify_mpdu; 612 __le32 sync_cmd; 613 __le32 write_cmd; 614 __le32 hwsch_trigger; 615 __le32 ack_tlv_proc; 616 __le32 gen_mpdu_cmd; 617 __le32 gen_list_cmd; 618 __le32 remove_mpdu_cmd; 619 __le32 remove_mpdu_tried_cmd; 620 __le32 mpdu_queue_stats_cmd; 621 __le32 mpdu_head_info_cmd; 622 __le32 msdu_flow_stats_cmd; 623 __le32 remove_msdu_cmd; 624 __le32 remove_msdu_ttl_cmd; 625 __le32 flush_cache_cmd; 626 __le32 update_mpduq_cmd; 627 __le32 enqueue; 628 __le32 enqueue_notify; 629 __le32 notify_mpdu_at_head; 630 __le32 notify_mpdu_state_valid; 631 __le32 sched_udp_notify1; 632 __le32 sched_udp_notify2; 633 __le32 sched_nonudp_notify1; 634 __le32 sched_nonudp_notify2; 635 } __packed; 636 637 struct ath12k_htt_tx_de_cmn_stats_tlv { 638 __le32 mac_id__word; 639 __le32 tcl2fw_entry_count; 640 __le32 not_to_fw; 641 __le32 invalid_pdev_vdev_peer; 642 __le32 tcl_res_invalid_addrx; 643 __le32 wbm2fw_entry_count; 644 __le32 invalid_pdev; 645 __le32 tcl_res_addrx_timeout; 646 __le32 invalid_vdev; 647 __le32 invalid_tcl_exp_frame_desc; 648 __le32 vdev_id_mismatch_cnt; 649 } __packed; 650 651 struct ath12k_htt_tx_de_eapol_packets_stats_tlv { 652 __le32 m1_packets; 653 __le32 m2_packets; 654 __le32 m3_packets; 655 __le32 m4_packets; 656 __le32 g1_packets; 657 __le32 g2_packets; 658 __le32 rc4_packets; 659 __le32 eap_packets; 660 __le32 eapol_start_packets; 661 __le32 eapol_logoff_packets; 662 __le32 eapol_encap_asf_packets; 663 } __packed; 664 665 struct ath12k_htt_tx_de_classify_stats_tlv { 666 __le32 arp_packets; 667 __le32 igmp_packets; 668 __le32 dhcp_packets; 669 __le32 host_inspected; 670 __le32 htt_included; 671 __le32 htt_valid_mcs; 672 __le32 htt_valid_nss; 673 __le32 htt_valid_preamble_type; 674 __le32 htt_valid_chainmask; 675 __le32 htt_valid_guard_interval; 676 __le32 htt_valid_retries; 677 __le32 htt_valid_bw_info; 678 __le32 htt_valid_power; 679 __le32 htt_valid_key_flags; 680 __le32 htt_valid_no_encryption; 681 __le32 fse_entry_count; 682 __le32 fse_priority_be; 683 __le32 fse_priority_high; 684 __le32 fse_priority_low; 685 __le32 fse_traffic_ptrn_be; 686 __le32 fse_traffic_ptrn_over_sub; 687 __le32 fse_traffic_ptrn_bursty; 688 __le32 fse_traffic_ptrn_interactive; 689 __le32 fse_traffic_ptrn_periodic; 690 __le32 fse_hwqueue_alloc; 691 __le32 fse_hwqueue_created; 692 __le32 fse_hwqueue_send_to_host; 693 __le32 mcast_entry; 694 __le32 bcast_entry; 695 __le32 htt_update_peer_cache; 696 __le32 htt_learning_frame; 697 __le32 fse_invalid_peer; 698 __le32 mec_notify; 699 } __packed; 700 701 struct ath12k_htt_tx_de_classify_failed_stats_tlv { 702 __le32 ap_bss_peer_not_found; 703 __le32 ap_bcast_mcast_no_peer; 704 __le32 sta_delete_in_progress; 705 __le32 ibss_no_bss_peer; 706 __le32 invalid_vdev_type; 707 __le32 invalid_ast_peer_entry; 708 __le32 peer_entry_invalid; 709 __le32 ethertype_not_ip; 710 __le32 eapol_lookup_failed; 711 __le32 qpeer_not_allow_data; 712 __le32 fse_tid_override; 713 __le32 ipv6_jumbogram_zero_length; 714 __le32 qos_to_non_qos_in_prog; 715 __le32 ap_bcast_mcast_eapol; 716 __le32 unicast_on_ap_bss_peer; 717 __le32 ap_vdev_invalid; 718 __le32 incomplete_llc; 719 __le32 eapol_duplicate_m3; 720 __le32 eapol_duplicate_m4; 721 } __packed; 722 723 struct ath12k_htt_tx_de_classify_status_stats_tlv { 724 __le32 eok; 725 __le32 classify_done; 726 __le32 lookup_failed; 727 __le32 send_host_dhcp; 728 __le32 send_host_mcast; 729 __le32 send_host_unknown_dest; 730 __le32 send_host; 731 __le32 status_invalid; 732 } __packed; 733 734 struct ath12k_htt_tx_de_enqueue_packets_stats_tlv { 735 __le32 enqueued_pkts; 736 __le32 to_tqm; 737 __le32 to_tqm_bypass; 738 } __packed; 739 740 struct ath12k_htt_tx_de_enqueue_discard_stats_tlv { 741 __le32 discarded_pkts; 742 __le32 local_frames; 743 __le32 is_ext_msdu; 744 } __packed; 745 746 struct ath12k_htt_tx_de_compl_stats_tlv { 747 __le32 tcl_dummy_frame; 748 __le32 tqm_dummy_frame; 749 __le32 tqm_notify_frame; 750 __le32 fw2wbm_enq; 751 __le32 tqm_bypass_frame; 752 } __packed; 753 754 enum ath12k_htt_tx_mumimo_grp_invalid_reason_code_stats { 755 ATH12K_HTT_TX_MUMIMO_GRP_VALID, 756 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_NUM_MU_USERS_EXCEEDED_MU_MAX_USERS, 757 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_SCHED_ALGO_NOT_MU_COMPATIBLE_GID, 758 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_NON_PRIMARY_GRP, 759 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_ZERO_CANDIDATES, 760 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MORE_CANDIDATES, 761 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_SIZE_EXCEED_NSS, 762 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_INELIGIBLE, 763 ATH12K_HTT_TX_MUMIMO_GRP_INVALID, 764 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_EFF_MU_TPUT_OMBPS, 765 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE, 766 }; 767 768 #define ATH12K_HTT_NUM_AC_WMM 0x4 769 #define ATH12K_HTT_MAX_NUM_SBT_INTR 4 770 #define ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS 4 771 #define ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS 8 772 #define ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS 8 773 #define ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS 7 774 #define ATH12K_HTT_TX_NUM_OFDMA_USER_STATS 74 775 #define ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS 8 776 #define ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ 8 777 #define ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS 10 778 779 #define ATH12K_HTT_STATS_MAX_INVALID_REASON_CODE \ 780 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE 781 #define ATH12K_HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS \ 782 (ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ * ATH12K_HTT_STATS_MAX_INVALID_REASON_CODE) 783 784 struct ath12k_htt_tx_selfgen_cmn_stats_tlv { 785 __le32 mac_id__word; 786 __le32 su_bar; 787 __le32 rts; 788 __le32 cts2self; 789 __le32 qos_null; 790 __le32 delayed_bar_1; 791 __le32 delayed_bar_2; 792 __le32 delayed_bar_3; 793 __le32 delayed_bar_4; 794 __le32 delayed_bar_5; 795 __le32 delayed_bar_6; 796 __le32 delayed_bar_7; 797 } __packed; 798 799 struct ath12k_htt_tx_selfgen_ac_stats_tlv { 800 __le32 ac_su_ndpa; 801 __le32 ac_su_ndp; 802 __le32 ac_mu_mimo_ndpa; 803 __le32 ac_mu_mimo_ndp; 804 __le32 ac_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS - 1]; 805 } __packed; 806 807 struct ath12k_htt_tx_selfgen_ax_stats_tlv { 808 __le32 ax_su_ndpa; 809 __le32 ax_su_ndp; 810 __le32 ax_mu_mimo_ndpa; 811 __le32 ax_mu_mimo_ndp; 812 __le32 ax_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS - 1]; 813 __le32 ax_basic_trigger; 814 __le32 ax_bsr_trigger; 815 __le32 ax_mu_bar_trigger; 816 __le32 ax_mu_rts_trigger; 817 __le32 ax_ulmumimo_trigger; 818 } __packed; 819 820 struct ath12k_htt_tx_selfgen_be_stats_tlv { 821 __le32 be_su_ndpa; 822 __le32 be_su_ndp; 823 __le32 be_mu_mimo_ndpa; 824 __le32 be_mu_mimo_ndp; 825 __le32 be_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 826 __le32 be_basic_trigger; 827 __le32 be_bsr_trigger; 828 __le32 be_mu_bar_trigger; 829 __le32 be_mu_rts_trigger; 830 __le32 be_ulmumimo_trigger; 831 __le32 be_su_ndpa_queued; 832 __le32 be_su_ndp_queued; 833 __le32 be_mu_mimo_ndpa_queued; 834 __le32 be_mu_mimo_ndp_queued; 835 __le32 be_mu_mimo_brpoll_queued[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 836 __le32 be_ul_mumimo_trigger[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 837 } __packed; 838 839 struct ath12k_htt_tx_selfgen_ac_err_stats_tlv { 840 __le32 ac_su_ndp_err; 841 __le32 ac_su_ndpa_err; 842 __le32 ac_mu_mimo_ndpa_err; 843 __le32 ac_mu_mimo_ndp_err; 844 __le32 ac_mu_mimo_brp1_err; 845 __le32 ac_mu_mimo_brp2_err; 846 __le32 ac_mu_mimo_brp3_err; 847 } __packed; 848 849 struct ath12k_htt_tx_selfgen_ax_err_stats_tlv { 850 __le32 ax_su_ndp_err; 851 __le32 ax_su_ndpa_err; 852 __le32 ax_mu_mimo_ndpa_err; 853 __le32 ax_mu_mimo_ndp_err; 854 __le32 ax_mu_mimo_brp_err[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS - 1]; 855 __le32 ax_basic_trigger_err; 856 __le32 ax_bsr_trigger_err; 857 __le32 ax_mu_bar_trigger_err; 858 __le32 ax_mu_rts_trigger_err; 859 __le32 ax_ulmumimo_trigger_err; 860 } __packed; 861 862 struct ath12k_htt_tx_selfgen_be_err_stats_tlv { 863 __le32 be_su_ndp_err; 864 __le32 be_su_ndpa_err; 865 __le32 be_mu_mimo_ndpa_err; 866 __le32 be_mu_mimo_ndp_err; 867 __le32 be_mu_mimo_brp_err[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 868 __le32 be_basic_trigger_err; 869 __le32 be_bsr_trigger_err; 870 __le32 be_mu_bar_trigger_err; 871 __le32 be_mu_rts_trigger_err; 872 __le32 be_ulmumimo_trigger_err; 873 __le32 be_mu_mimo_brp_err_num_cbf_rxd[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 874 __le32 be_su_ndpa_flushed; 875 __le32 be_su_ndp_flushed; 876 __le32 be_mu_mimo_ndpa_flushed; 877 __le32 be_mu_mimo_ndp_flushed; 878 __le32 be_mu_mimo_brpoll_flushed[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 879 __le32 be_ul_mumimo_trigger_err[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 880 } __packed; 881 882 enum ath12k_htt_tx_selfgen_sch_tsflag_error_stats { 883 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_FLUSH_RCVD_ERR, 884 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_FILT_SCHED_CMD_ERR, 885 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_MISMATCH_ERR, 886 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_MIMO_CTRL_MISMATCH_ERR, 887 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_BW_MISMATCH_ERR, 888 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RETRY_COUNT_FAIL_ERR, 889 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_TOO_LATE_RECEIVED_ERR, 890 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_SIFS_STALL_NO_NEXT_CMD_ERR, 891 892 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS 893 }; 894 895 struct ath12k_htt_tx_selfgen_ac_sched_status_stats_tlv { 896 __le32 ac_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 897 __le32 ac_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 898 __le32 ac_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 899 __le32 ac_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 900 __le32 ac_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 901 __le32 ac_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 902 __le32 ac_mu_mimo_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 903 __le32 ac_mu_mimo_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 904 } __packed; 905 906 struct ath12k_htt_tx_selfgen_ax_sched_status_stats_tlv { 907 __le32 ax_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 908 __le32 ax_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 909 __le32 ax_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 910 __le32 ax_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 911 __le32 ax_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 912 __le32 ax_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 913 __le32 ax_mu_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 914 __le32 ax_mu_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 915 __le32 ax_mu_bar_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 916 __le32 ax_mu_bar_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 917 __le32 ax_basic_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 918 __le32 ax_basic_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 919 __le32 ax_ulmumimo_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 920 __le32 ax_ulmumimo_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 921 } __packed; 922 923 struct ath12k_htt_tx_selfgen_be_sched_status_stats_tlv { 924 __le32 be_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 925 __le32 be_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 926 __le32 be_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 927 __le32 be_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 928 __le32 be_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 929 __le32 be_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 930 __le32 be_mu_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 931 __le32 be_mu_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 932 __le32 be_mu_bar_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 933 __le32 be_mu_bar_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 934 __le32 be_basic_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 935 __le32 be_basic_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 936 __le32 be_ulmumimo_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 937 __le32 be_ulmumimo_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 938 } __packed; 939 940 struct ath12k_htt_stats_string_tlv { 941 DECLARE_FLEX_ARRAY(__le32, data); 942 } __packed; 943 944 #define ATH12K_HTT_SRING_STATS_MAC_ID GENMASK(7, 0) 945 #define ATH12K_HTT_SRING_STATS_RING_ID GENMASK(15, 8) 946 #define ATH12K_HTT_SRING_STATS_ARENA GENMASK(23, 16) 947 #define ATH12K_HTT_SRING_STATS_EP BIT(24) 948 #define ATH12K_HTT_SRING_STATS_NUM_AVAIL_WORDS GENMASK(15, 0) 949 #define ATH12K_HTT_SRING_STATS_NUM_VALID_WORDS GENMASK(31, 16) 950 #define ATH12K_HTT_SRING_STATS_HEAD_PTR GENMASK(15, 0) 951 #define ATH12K_HTT_SRING_STATS_TAIL_PTR GENMASK(31, 16) 952 #define ATH12K_HTT_SRING_STATS_CONSUMER_EMPTY GENMASK(15, 0) 953 #define ATH12K_HTT_SRING_STATS_PRODUCER_FULL GENMASK(31, 16) 954 #define ATH12K_HTT_SRING_STATS_PREFETCH_COUNT GENMASK(15, 0) 955 #define ATH12K_HTT_SRING_STATS_INTERNAL_TAIL_PTR GENMASK(31, 16) 956 957 struct ath12k_htt_sring_stats_tlv { 958 __le32 mac_id__ring_id__arena__ep; 959 __le32 base_addr_lsb; 960 __le32 base_addr_msb; 961 __le32 ring_size; 962 __le32 elem_size; 963 __le32 num_avail_words__num_valid_words; 964 __le32 head_ptr__tail_ptr; 965 __le32 consumer_empty__producer_full; 966 __le32 prefetch_count__internal_tail_ptr; 967 } __packed; 968 969 struct ath12k_htt_sfm_cmn_tlv { 970 __le32 mac_id__word; 971 __le32 buf_total; 972 __le32 mem_empty; 973 __le32 deallocate_bufs; 974 __le32 num_records; 975 } __packed; 976 977 struct ath12k_htt_sfm_client_tlv { 978 __le32 client_id; 979 __le32 buf_min; 980 __le32 buf_max; 981 __le32 buf_busy; 982 __le32 buf_alloc; 983 __le32 buf_avail; 984 __le32 num_users; 985 } __packed; 986 987 struct ath12k_htt_sfm_client_user_tlv { 988 DECLARE_FLEX_ARRAY(__le32, dwords_used_by_user_n); 989 } __packed; 990 991 struct ath12k_htt_tx_pdev_mu_mimo_sch_stats_tlv { 992 __le32 mu_mimo_sch_posted; 993 __le32 mu_mimo_sch_failed; 994 __le32 mu_mimo_ppdu_posted; 995 __le32 ac_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS]; 996 __le32 ax_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 997 __le32 ax_ofdma_sch_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 998 __le32 ax_ul_ofdma_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 999 __le32 ax_ul_ofdma_bsr_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1000 __le32 ax_ul_ofdma_bar_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1001 __le32 ax_ul_ofdma_brp_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1002 __le32 ax_ul_mumimo_nusers[ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS]; 1003 __le32 ax_ul_mumimo_brp_nusers[ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS]; 1004 __le32 ac_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS]; 1005 __le32 ax_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1006 __le32 be_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1007 __le32 be_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1008 __le32 ac_mu_mimo_grp_sz_ext[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS]; 1009 } __packed; 1010 1011 struct ath12k_htt_tx_pdev_mumimo_grp_stats_tlv { 1012 __le32 dl_mumimo_grp_best_grp_size[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1013 __le32 dl_mumimo_grp_best_num_usrs[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1014 __le32 dl_mumimo_grp_eligible[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1015 __le32 dl_mumimo_grp_ineligible[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1016 __le32 dl_mumimo_grp_invalid[ATH12K_HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS]; 1017 __le32 dl_mumimo_grp_tputs[ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS]; 1018 __le32 ul_mumimo_grp_best_grp_size[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1019 __le32 ul_mumimo_grp_best_usrs[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1020 __le32 ul_mumimo_grp_tputs[ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS]; 1021 } __packed; 1022 1023 enum ath12k_htt_stats_tx_sched_modes { 1024 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC = 0, 1025 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX, 1026 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX, 1027 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_OFDMA_BE, 1028 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_BE 1029 }; 1030 1031 struct ath12k_htt_tx_pdev_mpdu_stats_tlv { 1032 __le32 mpdus_queued_usr; 1033 __le32 mpdus_tried_usr; 1034 __le32 mpdus_failed_usr; 1035 __le32 mpdus_requeued_usr; 1036 __le32 err_no_ba_usr; 1037 __le32 mpdu_underrun_usr; 1038 __le32 ampdu_underrun_usr; 1039 __le32 user_index; 1040 __le32 tx_sched_mode; 1041 } __packed; 1042 1043 struct ath12k_htt_pdev_stats_cca_counters_tlv { 1044 __le32 tx_frame_usec; 1045 __le32 rx_frame_usec; 1046 __le32 rx_clear_usec; 1047 __le32 my_rx_frame_usec; 1048 __le32 usec_cnt; 1049 __le32 med_rx_idle_usec; 1050 __le32 med_tx_idle_global_usec; 1051 __le32 cca_obss_usec; 1052 } __packed; 1053 1054 struct ath12k_htt_pdev_cca_stats_hist_v1_tlv { 1055 __le32 chan_num; 1056 __le32 num_records; 1057 __le32 valid_cca_counters_bitmap; 1058 __le32 collection_interval; 1059 } __packed; 1060 1061 struct ath12k_htt_pdev_obss_pd_stats_tlv { 1062 __le32 num_obss_tx_ppdu_success; 1063 __le32 num_obss_tx_ppdu_failure; 1064 __le32 num_sr_tx_transmissions; 1065 __le32 num_spatial_reuse_opportunities; 1066 __le32 num_non_srg_opportunities; 1067 __le32 num_non_srg_ppdu_tried; 1068 __le32 num_non_srg_ppdu_success; 1069 __le32 num_srg_opportunities; 1070 __le32 num_srg_ppdu_tried; 1071 __le32 num_srg_ppdu_success; 1072 __le32 num_psr_opportunities; 1073 __le32 num_psr_ppdu_tried; 1074 __le32 num_psr_ppdu_success; 1075 __le32 num_non_srg_tried_per_ac[ATH12K_HTT_NUM_AC_WMM]; 1076 __le32 num_non_srg_success_ac[ATH12K_HTT_NUM_AC_WMM]; 1077 __le32 num_srg_tried_per_ac[ATH12K_HTT_NUM_AC_WMM]; 1078 __le32 num_srg_success_per_ac[ATH12K_HTT_NUM_AC_WMM]; 1079 __le32 num_obss_min_dur_check_flush_cnt; 1080 __le32 num_sr_ppdu_abort_flush_cnt; 1081 } __packed; 1082 1083 #define ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS 14 1084 #define ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 1085 #define ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 1086 #define ATH12K_HTT_TXBF_NUM_BW_CNTRS 5 1087 #define ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES 2 1088 1089 struct ath12k_htt_pdev_txrate_txbf_stats_tlv { 1090 __le32 tx_su_txbf_mcs[ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS]; 1091 __le32 tx_su_ibf_mcs[ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS]; 1092 __le32 tx_su_ol_mcs[ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS]; 1093 __le32 tx_su_txbf_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1094 __le32 tx_su_ibf_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1095 __le32 tx_su_ol_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1096 __le32 tx_su_txbf_bw[ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1097 __le32 tx_su_ibf_bw[ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1098 __le32 tx_su_ol_bw[ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1099 __le32 tx_legacy_ofdm_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 1100 __le32 txbf[ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1101 __le32 ibf[ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1102 __le32 ol[ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1103 __le32 txbf_flag_set_mu_mode; 1104 __le32 txbf_flag_set_final_status; 1105 __le32 txbf_flag_not_set_verified_txbf_mode; 1106 __le32 txbf_flag_not_set_disable_p2p_access; 1107 __le32 txbf_flag_not_set_max_nss_in_he160; 1108 __le32 txbf_flag_not_set_disable_uldlofdma; 1109 __le32 txbf_flag_not_set_mcs_threshold_val; 1110 __le32 txbf_flag_not_set_final_status; 1111 } __packed; 1112 1113 struct ath12k_htt_txbf_ofdma_ax_ndpa_stats_elem_t { 1114 __le32 ax_ofdma_ndpa_queued; 1115 __le32 ax_ofdma_ndpa_tried; 1116 __le32 ax_ofdma_ndpa_flush; 1117 __le32 ax_ofdma_ndpa_err; 1118 } __packed; 1119 1120 struct ath12k_htt_txbf_ofdma_ax_ndpa_stats_tlv { 1121 __le32 num_elems_ax_ndpa_arr; 1122 __le32 arr_elem_size_ax_ndpa; 1123 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_ndpa_stats_elem_t, ax_ndpa); 1124 } __packed; 1125 1126 struct ath12k_htt_txbf_ofdma_ax_ndp_stats_elem_t { 1127 __le32 ax_ofdma_ndp_queued; 1128 __le32 ax_ofdma_ndp_tried; 1129 __le32 ax_ofdma_ndp_flush; 1130 __le32 ax_ofdma_ndp_err; 1131 } __packed; 1132 1133 struct ath12k_htt_txbf_ofdma_ax_ndp_stats_tlv { 1134 __le32 num_elems_ax_ndp_arr; 1135 __le32 arr_elem_size_ax_ndp; 1136 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_ndp_stats_elem_t, ax_ndp); 1137 } __packed; 1138 1139 struct ath12k_htt_txbf_ofdma_ax_brp_stats_elem_t { 1140 __le32 ax_ofdma_brp_queued; 1141 __le32 ax_ofdma_brp_tried; 1142 __le32 ax_ofdma_brp_flushed; 1143 __le32 ax_ofdma_brp_err; 1144 __le32 ax_ofdma_num_cbf_rcvd; 1145 } __packed; 1146 1147 struct ath12k_htt_txbf_ofdma_ax_brp_stats_tlv { 1148 __le32 num_elems_ax_brp_arr; 1149 __le32 arr_elem_size_ax_brp; 1150 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_brp_stats_elem_t, ax_brp); 1151 } __packed; 1152 1153 struct ath12k_htt_txbf_ofdma_ax_steer_stats_elem_t { 1154 __le32 num_ppdu_steer; 1155 __le32 num_ppdu_ol; 1156 __le32 num_usr_prefetch; 1157 __le32 num_usr_sound; 1158 __le32 num_usr_force_sound; 1159 } __packed; 1160 1161 struct ath12k_htt_txbf_ofdma_ax_steer_stats_tlv { 1162 __le32 num_elems_ax_steer_arr; 1163 __le32 arr_elem_size_ax_steer; 1164 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_steer_stats_elem_t, ax_steer); 1165 } __packed; 1166 1167 struct ath12k_htt_txbf_ofdma_ax_steer_mpdu_stats_tlv { 1168 __le32 ax_ofdma_rbo_steer_mpdus_tried; 1169 __le32 ax_ofdma_rbo_steer_mpdus_failed; 1170 __le32 ax_ofdma_sifs_steer_mpdus_tried; 1171 __le32 ax_ofdma_sifs_steer_mpdus_failed; 1172 } __packed; 1173 1174 enum ath12k_htt_stats_page_lock_state { 1175 ATH12K_HTT_STATS_PAGE_LOCKED = 0, 1176 ATH12K_HTT_STATS_PAGE_UNLOCKED = 1, 1177 ATH12K_NUM_PG_LOCK_STATE 1178 }; 1179 1180 #define ATH12K_PAGER_MAX 10 1181 1182 #define ATH12K_HTT_DLPAGER_ASYNC_LOCK_PG_CNT_INFO0 GENMASK(7, 0) 1183 #define ATH12K_HTT_DLPAGER_SYNC_LOCK_PG_CNT_INFO0 GENMASK(15, 8) 1184 #define ATH12K_HTT_DLPAGER_TOTAL_LOCK_PAGES_INFO1 GENMASK(15, 0) 1185 #define ATH12K_HTT_DLPAGER_TOTAL_FREE_PAGES_INFO1 GENMASK(31, 16) 1186 #define ATH12K_HTT_DLPAGER_TOTAL_LOCK_PAGES_INFO2 GENMASK(15, 0) 1187 #define ATH12K_HTT_DLPAGER_TOTAL_FREE_PAGES_INFO2 GENMASK(31, 16) 1188 1189 struct ath12k_htt_pgs_info { 1190 __le32 page_num; 1191 __le32 num_pgs; 1192 __le32 ts_lsb; 1193 __le32 ts_msb; 1194 } __packed; 1195 1196 struct ath12k_htt_dl_pager_stats_tlv { 1197 __le32 info0; 1198 __le32 info1; 1199 __le32 info2; 1200 struct ath12k_htt_pgs_info pgs_info[ATH12K_NUM_PG_LOCK_STATE][ATH12K_PAGER_MAX]; 1201 } __packed; 1202 1203 #define ATH12K_HTT_STATS_MAX_CHAINS 8 1204 #define ATH12K_HTT_MAX_RX_PKT_CNT 8 1205 #define ATH12K_HTT_MAX_RX_PKT_CRC_PASS_CNT 8 1206 #define ATH12K_HTT_MAX_PER_BLK_ERR_CNT 20 1207 #define ATH12K_HTT_MAX_RX_OTA_ERR_CNT 14 1208 #define ATH12K_HTT_MAX_CH_PWR_INFO_SIZE 16 1209 1210 struct ath12k_htt_phy_stats_tlv { 1211 a_sle32 nf_chain[ATH12K_HTT_STATS_MAX_CHAINS]; 1212 __le32 false_radar_cnt; 1213 __le32 radar_cs_cnt; 1214 a_sle32 ani_level; 1215 __le32 fw_run_time; 1216 a_sle32 runtime_nf_chain[ATH12K_HTT_STATS_MAX_CHAINS]; 1217 } __packed; 1218 1219 struct ath12k_htt_phy_counters_tlv { 1220 __le32 rx_ofdma_timing_err_cnt; 1221 __le32 rx_cck_fail_cnt; 1222 __le32 mactx_abort_cnt; 1223 __le32 macrx_abort_cnt; 1224 __le32 phytx_abort_cnt; 1225 __le32 phyrx_abort_cnt; 1226 __le32 phyrx_defer_abort_cnt; 1227 __le32 rx_gain_adj_lstf_event_cnt; 1228 __le32 rx_gain_adj_non_legacy_cnt; 1229 __le32 rx_pkt_cnt[ATH12K_HTT_MAX_RX_PKT_CNT]; 1230 __le32 rx_pkt_crc_pass_cnt[ATH12K_HTT_MAX_RX_PKT_CRC_PASS_CNT]; 1231 __le32 per_blk_err_cnt[ATH12K_HTT_MAX_PER_BLK_ERR_CNT]; 1232 __le32 rx_ota_err_cnt[ATH12K_HTT_MAX_RX_OTA_ERR_CNT]; 1233 } __packed; 1234 1235 struct ath12k_htt_phy_reset_stats_tlv { 1236 __le32 pdev_id; 1237 __le32 chan_mhz; 1238 __le32 chan_band_center_freq1; 1239 __le32 chan_band_center_freq2; 1240 __le32 chan_phy_mode; 1241 __le32 chan_flags; 1242 __le32 chan_num; 1243 __le32 reset_cause; 1244 __le32 prev_reset_cause; 1245 __le32 phy_warm_reset_src; 1246 __le32 rx_gain_tbl_mode; 1247 __le32 xbar_val; 1248 __le32 force_calibration; 1249 __le32 phyrf_mode; 1250 __le32 phy_homechan; 1251 __le32 phy_tx_ch_mask; 1252 __le32 phy_rx_ch_mask; 1253 __le32 phybb_ini_mask; 1254 __le32 phyrf_ini_mask; 1255 __le32 phy_dfs_en_mask; 1256 __le32 phy_sscan_en_mask; 1257 __le32 phy_synth_sel_mask; 1258 __le32 phy_adfs_freq; 1259 __le32 cck_fir_settings; 1260 __le32 phy_dyn_pri_chan; 1261 __le32 cca_thresh; 1262 __le32 dyn_cca_status; 1263 __le32 rxdesense_thresh_hw; 1264 __le32 rxdesense_thresh_sw; 1265 } __packed; 1266 1267 struct ath12k_htt_phy_reset_counters_tlv { 1268 __le32 pdev_id; 1269 __le32 cf_active_low_fail_cnt; 1270 __le32 cf_active_low_pass_cnt; 1271 __le32 phy_off_through_vreg_cnt; 1272 __le32 force_calibration_cnt; 1273 __le32 rf_mode_switch_phy_off_cnt; 1274 __le32 temperature_recal_cnt; 1275 } __packed; 1276 1277 struct ath12k_htt_phy_tpc_stats_tlv { 1278 __le32 pdev_id; 1279 __le32 tx_power_scale; 1280 __le32 tx_power_scale_db; 1281 __le32 min_negative_tx_power; 1282 __le32 reg_ctl_domain; 1283 __le32 max_reg_allowed_power[ATH12K_HTT_STATS_MAX_CHAINS]; 1284 __le32 max_reg_allowed_power_6ghz[ATH12K_HTT_STATS_MAX_CHAINS]; 1285 __le32 twice_max_rd_power; 1286 __le32 max_tx_power; 1287 __le32 home_max_tx_power; 1288 __le32 psd_power; 1289 __le32 eirp_power; 1290 __le32 power_type_6ghz; 1291 __le32 sub_band_cfreq[ATH12K_HTT_MAX_CH_PWR_INFO_SIZE]; 1292 __le32 sub_band_txpower[ATH12K_HTT_MAX_CH_PWR_INFO_SIZE]; 1293 } __packed; 1294 1295 struct ath12k_htt_t2h_soc_txrx_stats_common_tlv { 1296 __le32 inv_peers_msdu_drop_count_hi; 1297 __le32 inv_peers_msdu_drop_count_lo; 1298 } __packed; 1299 1300 #define ATH12K_HTT_AST_PDEV_ID_INFO GENMASK(1, 0) 1301 #define ATH12K_HTT_AST_VDEV_ID_INFO GENMASK(9, 2) 1302 #define ATH12K_HTT_AST_NEXT_HOP_INFO BIT(10) 1303 #define ATH12K_HTT_AST_MCAST_INFO BIT(11) 1304 #define ATH12K_HTT_AST_MONITOR_DIRECT_INFO BIT(12) 1305 #define ATH12K_HTT_AST_MESH_STA_INFO BIT(13) 1306 #define ATH12K_HTT_AST_MEC_INFO BIT(14) 1307 #define ATH12K_HTT_AST_INTRA_BSS_INFO BIT(15) 1308 1309 struct ath12k_htt_ast_entry_tlv { 1310 __le32 sw_peer_id; 1311 __le32 ast_index; 1312 struct htt_mac_addr mac_addr; 1313 __le32 info; 1314 } __packed; 1315 1316 enum ath12k_htt_stats_direction { 1317 ATH12K_HTT_STATS_DIRECTION_TX, 1318 ATH12K_HTT_STATS_DIRECTION_RX 1319 }; 1320 1321 enum ath12k_htt_stats_ppdu_type { 1322 ATH12K_HTT_STATS_PPDU_TYPE_MODE_SU, 1323 ATH12K_HTT_STATS_PPDU_TYPE_DL_MU_MIMO, 1324 ATH12K_HTT_STATS_PPDU_TYPE_UL_MU_MIMO, 1325 ATH12K_HTT_STATS_PPDU_TYPE_DL_MU_OFDMA, 1326 ATH12K_HTT_STATS_PPDU_TYPE_UL_MU_OFDMA 1327 }; 1328 1329 enum ath12k_htt_stats_param_type { 1330 ATH12K_HTT_STATS_PREAM_OFDM, 1331 ATH12K_HTT_STATS_PREAM_CCK, 1332 ATH12K_HTT_STATS_PREAM_HT, 1333 ATH12K_HTT_STATS_PREAM_VHT, 1334 ATH12K_HTT_STATS_PREAM_HE, 1335 ATH12K_HTT_STATS_PREAM_EHT, 1336 ATH12K_HTT_STATS_PREAM_RSVD1, 1337 ATH12K_HTT_STATS_PREAM_COUNT, 1338 }; 1339 1340 #define ATH12K_HTT_PUNCT_STATS_MAX_SUBBAND_CNT 32 1341 1342 struct ath12k_htt_pdev_puncture_stats_tlv { 1343 __le32 mac_id__word; 1344 __le32 direction; 1345 __le32 preamble; 1346 __le32 ppdu_type; 1347 __le32 subband_cnt; 1348 __le32 last_used_pattern_mask; 1349 __le32 num_subbands_used_cnt[ATH12K_HTT_PUNCT_STATS_MAX_SUBBAND_CNT]; 1350 } __packed; 1351 1352 struct ath12k_htt_dmac_reset_stats_tlv { 1353 __le32 reset_count; 1354 __le32 reset_time_lo_ms; 1355 __le32 reset_time_hi_ms; 1356 __le32 disengage_time_lo_ms; 1357 __le32 disengage_time_hi_ms; 1358 __le32 engage_time_lo_ms; 1359 __le32 engage_time_hi_ms; 1360 __le32 disengage_count; 1361 __le32 engage_count; 1362 __le32 drain_dest_ring_mask; 1363 } __packed; 1364 1365 struct ath12k_htt_pdev_sched_algo_ofdma_stats_tlv { 1366 __le32 mac_id__word; 1367 __le32 rate_based_dlofdma_enabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1368 __le32 rate_based_dlofdma_disabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1369 __le32 rate_based_dlofdma_probing_cnt[ATH12K_HTT_NUM_AC_WMM]; 1370 __le32 rate_based_dlofdma_monitor_cnt[ATH12K_HTT_NUM_AC_WMM]; 1371 __le32 chan_acc_lat_based_dlofdma_enabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1372 __le32 chan_acc_lat_based_dlofdma_disabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1373 __le32 chan_acc_lat_based_dlofdma_monitor_cnt[ATH12K_HTT_NUM_AC_WMM]; 1374 __le32 downgrade_to_dl_su_ru_alloc_fail[ATH12K_HTT_NUM_AC_WMM]; 1375 __le32 candidate_list_single_user_disable_ofdma[ATH12K_HTT_NUM_AC_WMM]; 1376 __le32 dl_cand_list_dropped_high_ul_qos_weight[ATH12K_HTT_NUM_AC_WMM]; 1377 __le32 ax_dlofdma_disabled_due_to_pipelining[ATH12K_HTT_NUM_AC_WMM]; 1378 __le32 dlofdma_disabled_su_only_eligible[ATH12K_HTT_NUM_AC_WMM]; 1379 __le32 dlofdma_disabled_consec_no_mpdus_tried[ATH12K_HTT_NUM_AC_WMM]; 1380 __le32 dlofdma_disabled_consec_no_mpdus_success[ATH12K_HTT_NUM_AC_WMM]; 1381 } __packed; 1382 1383 #define ATH12K_HTT_TX_PDEV_STATS_NUM_BW_CNTRS 4 1384 #define ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS 8 1385 #define ATH12K_HTT_TXBF_RATE_STAT_NUM_MCS_CNTRS 14 1386 1387 enum ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE { 1388 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_26, 1389 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_52, 1390 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_52_26, 1391 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_106, 1392 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_106_26, 1393 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_242, 1394 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_484, 1395 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_484_242, 1396 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996, 1397 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996_484, 1398 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996_484_242, 1399 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x2, 1400 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x2_484, 1401 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x3, 1402 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x3_484, 1403 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x4, 1404 ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS, 1405 }; 1406 1407 enum ATH12K_HTT_RC_MODE { 1408 ATH12K_HTT_RC_MODE_SU_OL, 1409 ATH12K_HTT_RC_MODE_SU_BF, 1410 ATH12K_HTT_RC_MODE_MU1_INTF, 1411 ATH12K_HTT_RC_MODE_MU2_INTF, 1412 ATH12K_HTT_RC_MODE_MU3_INTF, 1413 ATH12K_HTT_RC_MODE_MU4_INTF, 1414 ATH12K_HTT_RC_MODE_MU5_INTF, 1415 ATH12K_HTT_RC_MODE_MU6_INTF, 1416 ATH12K_HTT_RC_MODE_MU7_INTF, 1417 ATH12K_HTT_RC_MODE_2D_COUNT 1418 }; 1419 1420 enum ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE { 1421 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_26, 1422 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_52, 1423 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_106, 1424 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_242, 1425 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_484, 1426 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_996, 1427 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_996x2, 1428 ATH12K_HTT_TX_RX_PDEV_STATS_NUM_AX_RU_SIZE_CNTRS 1429 }; 1430 1431 enum ath12k_htt_stats_rc_mode { 1432 ATH12K_HTT_STATS_RC_MODE_DLSU = 0, 1433 ATH12K_HTT_STATS_RC_MODE_DLMUMIMO = 1, 1434 ATH12K_HTT_STATS_RC_MODE_DLOFDMA = 2, 1435 ATH12K_HTT_STATS_RC_MODE_ULMUMIMO = 3, 1436 ATH12K_HTT_STATS_RC_MODE_ULOFDMA = 4, 1437 }; 1438 1439 enum ath12k_htt_stats_ru_type { 1440 ATH12K_HTT_STATS_RU_TYPE_INVALID, 1441 ATH12K_HTT_STATS_RU_TYPE_SINGLE_RU_ONLY, 1442 ATH12K_HTT_STATS_RU_TYPE_SINGLE_AND_MULTI_RU, 1443 }; 1444 1445 struct ath12k_htt_tx_rate_stats { 1446 __le32 ppdus_tried; 1447 __le32 ppdus_ack_failed; 1448 __le32 mpdus_tried; 1449 __le32 mpdus_failed; 1450 } __packed; 1451 1452 struct ath12k_htt_tx_per_rate_stats_tlv { 1453 __le32 rc_mode; 1454 __le32 last_probed_mcs; 1455 __le32 last_probed_nss; 1456 __le32 last_probed_bw; 1457 struct ath12k_htt_tx_rate_stats per_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_CNTRS]; 1458 struct ath12k_htt_tx_rate_stats per_nss[ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS]; 1459 struct ath12k_htt_tx_rate_stats per_mcs[ATH12K_HTT_TXBF_RATE_STAT_NUM_MCS_CNTRS]; 1460 struct ath12k_htt_tx_rate_stats per_bw320; 1461 __le32 probe_cnt[ATH12K_HTT_RC_MODE_2D_COUNT]; 1462 __le32 ru_type; 1463 struct ath12k_htt_tx_rate_stats ru[ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS]; 1464 } __packed; 1465 1466 #define ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS 16 1467 #define ATH12K_HTT_TX_PDEV_NUM_BE_BW_CNTRS 5 1468 #define ATH12K_HTT_TX_PDEV_NUM_EHT_SIG_MCS_CNTRS 4 1469 #define ATH12K_HTT_TX_PDEV_NUM_GI_CNTRS 4 1470 1471 struct ath12k_htt_tx_pdev_rate_stats_be_ofdma_tlv { 1472 __le32 mac_id__word; 1473 __le32 be_ofdma_tx_ldpc; 1474 __le32 be_ofdma_tx_mcs[ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS]; 1475 __le32 be_ofdma_tx_nss[ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS]; 1476 __le32 be_ofdma_tx_bw[ATH12K_HTT_TX_PDEV_NUM_BE_BW_CNTRS]; 1477 __le32 gi[ATH12K_HTT_TX_PDEV_NUM_GI_CNTRS][ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS]; 1478 __le32 be_ofdma_tx_ru_size[ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS]; 1479 __le32 be_ofdma_eht_sig_mcs[ATH12K_HTT_TX_PDEV_NUM_EHT_SIG_MCS_CNTRS]; 1480 } __packed; 1481 1482 struct ath12k_htt_pdev_mbssid_ctrl_frame_tlv { 1483 __le32 mac_id__word; 1484 __le32 basic_trigger_across_bss; 1485 __le32 basic_trigger_within_bss; 1486 __le32 bsr_trigger_across_bss; 1487 __le32 bsr_trigger_within_bss; 1488 __le32 mu_rts_across_bss; 1489 __le32 mu_rts_within_bss; 1490 __le32 ul_mumimo_trigger_across_bss; 1491 __le32 ul_mumimo_trigger_within_bss; 1492 } __packed; 1493 1494 #endif 1495