xref: /linux/drivers/net/wireless/ath/ath11k/core.h (revision 74c12ee02af109adcde36ec184fa59c0afb0edaa)
1d5c65159SKalle Valo /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2d5c65159SKalle Valo /*
3d5c65159SKalle Valo  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4d5c65159SKalle Valo  */
5d5c65159SKalle Valo 
6d5c65159SKalle Valo #ifndef ATH11K_CORE_H
7d5c65159SKalle Valo #define ATH11K_CORE_H
8d5c65159SKalle Valo 
9d5c65159SKalle Valo #include <linux/types.h>
10d5c65159SKalle Valo #include <linux/interrupt.h>
11d5c65159SKalle Valo #include <linux/irq.h>
12d5c65159SKalle Valo #include <linux/bitfield.h>
13d5c65159SKalle Valo #include "qmi.h"
14d5c65159SKalle Valo #include "htc.h"
15d5c65159SKalle Valo #include "wmi.h"
16d5c65159SKalle Valo #include "hal.h"
17d5c65159SKalle Valo #include "dp.h"
18d5c65159SKalle Valo #include "ce.h"
19d5c65159SKalle Valo #include "mac.h"
20d5c65159SKalle Valo #include "hw.h"
21d5c65159SKalle Valo #include "hal_rx.h"
22d5c65159SKalle Valo #include "reg.h"
23d5c65159SKalle Valo 
24d5c65159SKalle Valo #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
25d5c65159SKalle Valo 
26d5c65159SKalle Valo #define ATH11K_TX_MGMT_NUM_PENDING_MAX	512
27d5c65159SKalle Valo 
28d5c65159SKalle Valo #define ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64
29d5c65159SKalle Valo 
30d5c65159SKalle Valo /* Pending management packets threshold for dropping probe responses */
31d5c65159SKalle Valo #define ATH11K_PRB_RSP_DROP_THRESHOLD ((ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)
32d5c65159SKalle Valo 
33d5c65159SKalle Valo #define ATH11K_INVALID_HW_MAC_ID	0xFF
34d5c65159SKalle Valo 
35d5c65159SKalle Valo enum ath11k_supported_bw {
36d5c65159SKalle Valo 	ATH11K_BW_20	= 0,
37d5c65159SKalle Valo 	ATH11K_BW_40	= 1,
38d5c65159SKalle Valo 	ATH11K_BW_80	= 2,
39d5c65159SKalle Valo 	ATH11K_BW_160	= 3,
40d5c65159SKalle Valo };
41d5c65159SKalle Valo 
42d5c65159SKalle Valo enum wme_ac {
43d5c65159SKalle Valo 	WME_AC_BE,
44d5c65159SKalle Valo 	WME_AC_BK,
45d5c65159SKalle Valo 	WME_AC_VI,
46d5c65159SKalle Valo 	WME_AC_VO,
47d5c65159SKalle Valo 	WME_NUM_AC
48d5c65159SKalle Valo };
49d5c65159SKalle Valo 
50d5c65159SKalle Valo #define ATH11K_HT_MCS_MAX	7
51d5c65159SKalle Valo #define ATH11K_VHT_MCS_MAX	9
52d5c65159SKalle Valo #define ATH11K_HE_MCS_MAX	11
53d5c65159SKalle Valo 
54d5c65159SKalle Valo static inline enum wme_ac ath11k_tid_to_ac(u32 tid)
55d5c65159SKalle Valo {
56d5c65159SKalle Valo 	return (((tid == 0) || (tid == 3)) ? WME_AC_BE :
57d5c65159SKalle Valo 		((tid == 1) || (tid == 2)) ? WME_AC_BK :
58d5c65159SKalle Valo 		((tid == 4) || (tid == 5)) ? WME_AC_VI :
59d5c65159SKalle Valo 		WME_AC_VO);
60d5c65159SKalle Valo }
61d5c65159SKalle Valo 
62d5c65159SKalle Valo struct ath11k_skb_cb {
63d5c65159SKalle Valo 	dma_addr_t paddr;
64d5c65159SKalle Valo 	u8 eid;
65d5c65159SKalle Valo 	struct ath11k *ar;
66d5c65159SKalle Valo 	struct ieee80211_vif *vif;
67d5c65159SKalle Valo } __packed;
68d5c65159SKalle Valo 
69d5c65159SKalle Valo struct ath11k_skb_rxcb {
70d5c65159SKalle Valo 	dma_addr_t paddr;
71d5c65159SKalle Valo 	bool is_first_msdu;
72d5c65159SKalle Valo 	bool is_last_msdu;
73d5c65159SKalle Valo 	bool is_continuation;
74d5c65159SKalle Valo 	struct hal_rx_desc *rx_desc;
75d5c65159SKalle Valo 	u8 err_rel_src;
76d5c65159SKalle Valo 	u8 err_code;
77d5c65159SKalle Valo 	u8 mac_id;
78d5c65159SKalle Valo 	u8 unmapped;
79d5c65159SKalle Valo };
80d5c65159SKalle Valo 
81d5c65159SKalle Valo enum ath11k_hw_rev {
82d5c65159SKalle Valo 	ATH11K_HW_IPQ8074,
83d5c65159SKalle Valo };
84d5c65159SKalle Valo 
85d5c65159SKalle Valo enum ath11k_firmware_mode {
86d5c65159SKalle Valo 	/* the default mode, standard 802.11 functionality */
87d5c65159SKalle Valo 	ATH11K_FIRMWARE_MODE_NORMAL,
88d5c65159SKalle Valo 
89d5c65159SKalle Valo 	/* factory tests etc */
90d5c65159SKalle Valo 	ATH11K_FIRMWARE_MODE_FTM,
91d5c65159SKalle Valo };
92d5c65159SKalle Valo 
93d5c65159SKalle Valo #define ATH11K_IRQ_NUM_MAX 52
94d5c65159SKalle Valo #define ATH11K_EXT_IRQ_GRP_NUM_MAX 11
95d5c65159SKalle Valo #define ATH11K_EXT_IRQ_NUM_MAX	16
96d5c65159SKalle Valo 
97d5c65159SKalle Valo extern const u8 ath11k_reo_status_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX];
98d5c65159SKalle Valo extern const u8 ath11k_tx_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX];
99d5c65159SKalle Valo extern const u8 ath11k_rx_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX];
100d5c65159SKalle Valo extern const u8 ath11k_rx_err_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX];
101d5c65159SKalle Valo extern const u8 ath11k_rx_wbm_rel_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX];
102d5c65159SKalle Valo extern const u8 ath11k_rxdma2host_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX];
103d5c65159SKalle Valo extern const u8 ath11k_host2rxdma_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX];
104d5c65159SKalle Valo extern const u8 rx_mon_status_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX];
105d5c65159SKalle Valo 
106d5c65159SKalle Valo struct ath11k_ext_irq_grp {
107d5c65159SKalle Valo 	struct ath11k_base *ab;
108d5c65159SKalle Valo 	u32 irqs[ATH11K_EXT_IRQ_NUM_MAX];
109d5c65159SKalle Valo 	u32 num_irq;
110d5c65159SKalle Valo 	u32 grp_id;
111d5c65159SKalle Valo 	struct napi_struct napi;
112d5c65159SKalle Valo 	struct net_device napi_ndev;
113d5c65159SKalle Valo 	/* Queue of pending packets, not expected to be accessed concurrently
114d5c65159SKalle Valo 	 * to avoid locking overhead.
115d5c65159SKalle Valo 	 */
116d5c65159SKalle Valo 	struct sk_buff_head pending_q;
117d5c65159SKalle Valo };
118d5c65159SKalle Valo 
119d5c65159SKalle Valo #define HEHANDLE_CAP_PHYINFO_SIZE       3
120d5c65159SKalle Valo #define HECAP_PHYINFO_SIZE              9
121d5c65159SKalle Valo #define HECAP_MACINFO_SIZE              5
122d5c65159SKalle Valo #define HECAP_TXRX_MCS_NSS_SIZE         2
123d5c65159SKalle Valo #define HECAP_PPET16_PPET8_MAX_SIZE     25
124d5c65159SKalle Valo 
125d5c65159SKalle Valo #define HE_PPET16_PPET8_SIZE            8
126d5c65159SKalle Valo 
127d5c65159SKalle Valo /* 802.11ax PPE (PPDU packet Extension) threshold */
128d5c65159SKalle Valo struct he_ppe_threshold {
129d5c65159SKalle Valo 	u32 numss_m1;
130d5c65159SKalle Valo 	u32 ru_mask;
131d5c65159SKalle Valo 	u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE];
132d5c65159SKalle Valo };
133d5c65159SKalle Valo 
134d5c65159SKalle Valo struct ath11k_he {
135d5c65159SKalle Valo 	u8 hecap_macinfo[HECAP_MACINFO_SIZE];
136d5c65159SKalle Valo 	u32 hecap_rxmcsnssmap;
137d5c65159SKalle Valo 	u32 hecap_txmcsnssmap;
138d5c65159SKalle Valo 	u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE];
139d5c65159SKalle Valo 	struct he_ppe_threshold   hecap_ppet;
140d5c65159SKalle Valo 	u32 heop_param;
141d5c65159SKalle Valo };
142d5c65159SKalle Valo 
143d5c65159SKalle Valo #define MAX_RADIOS 3
144d5c65159SKalle Valo 
145d5c65159SKalle Valo enum {
146d5c65159SKalle Valo 	WMI_HOST_TP_SCALE_MAX   = 0,
147d5c65159SKalle Valo 	WMI_HOST_TP_SCALE_50    = 1,
148d5c65159SKalle Valo 	WMI_HOST_TP_SCALE_25    = 2,
149d5c65159SKalle Valo 	WMI_HOST_TP_SCALE_12    = 3,
150d5c65159SKalle Valo 	WMI_HOST_TP_SCALE_MIN   = 4,
151d5c65159SKalle Valo 	WMI_HOST_TP_SCALE_SIZE   = 5,
152d5c65159SKalle Valo };
153d5c65159SKalle Valo 
154d5c65159SKalle Valo enum ath11k_scan_state {
155d5c65159SKalle Valo 	ATH11K_SCAN_IDLE,
156d5c65159SKalle Valo 	ATH11K_SCAN_STARTING,
157d5c65159SKalle Valo 	ATH11K_SCAN_RUNNING,
158d5c65159SKalle Valo 	ATH11K_SCAN_ABORTING,
159d5c65159SKalle Valo };
160d5c65159SKalle Valo 
161d5c65159SKalle Valo enum ath11k_dev_flags {
162d5c65159SKalle Valo 	ATH11K_CAC_RUNNING,
163d5c65159SKalle Valo 	ATH11K_FLAG_CORE_REGISTERED,
164d5c65159SKalle Valo 	ATH11K_FLAG_CRASH_FLUSH,
165d5c65159SKalle Valo 	ATH11K_FLAG_RAW_MODE,
166d5c65159SKalle Valo 	ATH11K_FLAG_HW_CRYPTO_DISABLED,
167d5c65159SKalle Valo 	ATH11K_FLAG_BTCOEX,
168d5c65159SKalle Valo 	ATH11K_FLAG_RECOVERY,
169d5c65159SKalle Valo 	ATH11K_FLAG_UNREGISTERING,
170d5c65159SKalle Valo 	ATH11K_FLAG_REGISTERED,
171d5c65159SKalle Valo };
172d5c65159SKalle Valo 
173d5c65159SKalle Valo enum ath11k_monitor_flags {
174d5c65159SKalle Valo 	ATH11K_FLAG_MONITOR_ENABLED,
175d5c65159SKalle Valo };
176d5c65159SKalle Valo 
177d5c65159SKalle Valo struct ath11k_vif {
178d5c65159SKalle Valo 	u32 vdev_id;
179d5c65159SKalle Valo 	enum wmi_vdev_type vdev_type;
180d5c65159SKalle Valo 	enum wmi_vdev_subtype vdev_subtype;
181d5c65159SKalle Valo 	u32 beacon_interval;
182d5c65159SKalle Valo 	u32 dtim_period;
183d5c65159SKalle Valo 	u16 ast_hash;
184d5c65159SKalle Valo 	u16 tcl_metadata;
185d5c65159SKalle Valo 	u8 hal_addr_search_flags;
186d5c65159SKalle Valo 	u8 search_type;
187d5c65159SKalle Valo 
188d5c65159SKalle Valo 	struct ath11k *ar;
189d5c65159SKalle Valo 	struct ieee80211_vif *vif;
190d5c65159SKalle Valo 
191d5c65159SKalle Valo 	u16 tx_seq_no;
192d5c65159SKalle Valo 	struct wmi_wmm_params_all_arg wmm_params;
193d5c65159SKalle Valo 	struct list_head list;
194d5c65159SKalle Valo 	union {
195d5c65159SKalle Valo 		struct {
196d5c65159SKalle Valo 			u32 uapsd;
197d5c65159SKalle Valo 		} sta;
198d5c65159SKalle Valo 		struct {
199d5c65159SKalle Valo 			/* 127 stations; wmi limit */
200d5c65159SKalle Valo 			u8 tim_bitmap[16];
201d5c65159SKalle Valo 			u8 tim_len;
202d5c65159SKalle Valo 			u32 ssid_len;
203d5c65159SKalle Valo 			u8 ssid[IEEE80211_MAX_SSID_LEN];
204d5c65159SKalle Valo 			bool hidden_ssid;
205d5c65159SKalle Valo 			/* P2P_IE with NoA attribute for P2P_GO case */
206d5c65159SKalle Valo 			u32 noa_len;
207d5c65159SKalle Valo 			u8 *noa_data;
208d5c65159SKalle Valo 		} ap;
209d5c65159SKalle Valo 	} u;
210d5c65159SKalle Valo 
211d5c65159SKalle Valo 	bool is_started;
212d5c65159SKalle Valo 	bool is_up;
213d5c65159SKalle Valo 	u32 aid;
214d5c65159SKalle Valo 	u8 bssid[ETH_ALEN];
215d5c65159SKalle Valo 	struct cfg80211_bitrate_mask bitrate_mask;
216d5c65159SKalle Valo 	int num_legacy_stations;
217d5c65159SKalle Valo 	int rtscts_prot_mode;
218d5c65159SKalle Valo 	int txpower;
219d5c65159SKalle Valo };
220d5c65159SKalle Valo 
221d5c65159SKalle Valo struct ath11k_vif_iter {
222d5c65159SKalle Valo 	u32 vdev_id;
223d5c65159SKalle Valo 	struct ath11k_vif *arvif;
224d5c65159SKalle Valo };
225d5c65159SKalle Valo 
226d5c65159SKalle Valo struct ath11k_rx_peer_stats {
227d5c65159SKalle Valo 	u64 num_msdu;
228d5c65159SKalle Valo 	u64 num_mpdu_fcs_ok;
229d5c65159SKalle Valo 	u64 num_mpdu_fcs_err;
230d5c65159SKalle Valo 	u64 tcp_msdu_count;
231d5c65159SKalle Valo 	u64 udp_msdu_count;
232d5c65159SKalle Valo 	u64 other_msdu_count;
233d5c65159SKalle Valo 	u64 ampdu_msdu_count;
234d5c65159SKalle Valo 	u64 non_ampdu_msdu_count;
235d5c65159SKalle Valo 	u64 stbc_count;
236d5c65159SKalle Valo 	u64 beamformed_count;
237d5c65159SKalle Valo 	u64 mcs_count[HAL_RX_MAX_MCS + 1];
238d5c65159SKalle Valo 	u64 nss_count[HAL_RX_MAX_NSS];
239d5c65159SKalle Valo 	u64 bw_count[HAL_RX_BW_MAX];
240d5c65159SKalle Valo 	u64 gi_count[HAL_RX_GI_MAX];
241d5c65159SKalle Valo 	u64 coding_count[HAL_RX_SU_MU_CODING_MAX];
242d5c65159SKalle Valo 	u64 tid_count[IEEE80211_NUM_TIDS + 1];
243d5c65159SKalle Valo 	u64 pream_cnt[HAL_RX_PREAMBLE_MAX];
244d5c65159SKalle Valo 	u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX];
245d5c65159SKalle Valo 	u64 rx_duration;
246d5c65159SKalle Valo };
247d5c65159SKalle Valo 
248d5c65159SKalle Valo #define ATH11K_HE_MCS_NUM       12
249d5c65159SKalle Valo #define ATH11K_VHT_MCS_NUM      10
250d5c65159SKalle Valo #define ATH11K_BW_NUM           4
251d5c65159SKalle Valo #define ATH11K_NSS_NUM          4
252d5c65159SKalle Valo #define ATH11K_LEGACY_NUM       12
253d5c65159SKalle Valo #define ATH11K_GI_NUM           4
254d5c65159SKalle Valo #define ATH11K_HT_MCS_NUM       32
255d5c65159SKalle Valo 
256d5c65159SKalle Valo enum ath11k_pkt_rx_err {
257d5c65159SKalle Valo 	ATH11K_PKT_RX_ERR_FCS,
258d5c65159SKalle Valo 	ATH11K_PKT_RX_ERR_TKIP,
259d5c65159SKalle Valo 	ATH11K_PKT_RX_ERR_CRYPT,
260d5c65159SKalle Valo 	ATH11K_PKT_RX_ERR_PEER_IDX_INVAL,
261d5c65159SKalle Valo 	ATH11K_PKT_RX_ERR_MAX,
262d5c65159SKalle Valo };
263d5c65159SKalle Valo 
264d5c65159SKalle Valo enum ath11k_ampdu_subfrm_num {
265d5c65159SKalle Valo 	ATH11K_AMPDU_SUBFRM_NUM_10,
266d5c65159SKalle Valo 	ATH11K_AMPDU_SUBFRM_NUM_20,
267d5c65159SKalle Valo 	ATH11K_AMPDU_SUBFRM_NUM_30,
268d5c65159SKalle Valo 	ATH11K_AMPDU_SUBFRM_NUM_40,
269d5c65159SKalle Valo 	ATH11K_AMPDU_SUBFRM_NUM_50,
270d5c65159SKalle Valo 	ATH11K_AMPDU_SUBFRM_NUM_60,
271d5c65159SKalle Valo 	ATH11K_AMPDU_SUBFRM_NUM_MORE,
272d5c65159SKalle Valo 	ATH11K_AMPDU_SUBFRM_NUM_MAX,
273d5c65159SKalle Valo };
274d5c65159SKalle Valo 
275d5c65159SKalle Valo enum ath11k_amsdu_subfrm_num {
276d5c65159SKalle Valo 	ATH11K_AMSDU_SUBFRM_NUM_1,
277d5c65159SKalle Valo 	ATH11K_AMSDU_SUBFRM_NUM_2,
278d5c65159SKalle Valo 	ATH11K_AMSDU_SUBFRM_NUM_3,
279d5c65159SKalle Valo 	ATH11K_AMSDU_SUBFRM_NUM_4,
280d5c65159SKalle Valo 	ATH11K_AMSDU_SUBFRM_NUM_MORE,
281d5c65159SKalle Valo 	ATH11K_AMSDU_SUBFRM_NUM_MAX,
282d5c65159SKalle Valo };
283d5c65159SKalle Valo 
284d5c65159SKalle Valo enum ath11k_counter_type {
285d5c65159SKalle Valo 	ATH11K_COUNTER_TYPE_BYTES,
286d5c65159SKalle Valo 	ATH11K_COUNTER_TYPE_PKTS,
287d5c65159SKalle Valo 	ATH11K_COUNTER_TYPE_MAX,
288d5c65159SKalle Valo };
289d5c65159SKalle Valo 
290d5c65159SKalle Valo enum ath11k_stats_type {
291d5c65159SKalle Valo 	ATH11K_STATS_TYPE_SUCC,
292d5c65159SKalle Valo 	ATH11K_STATS_TYPE_FAIL,
293d5c65159SKalle Valo 	ATH11K_STATS_TYPE_RETRY,
294d5c65159SKalle Valo 	ATH11K_STATS_TYPE_AMPDU,
295d5c65159SKalle Valo 	ATH11K_STATS_TYPE_MAX,
296d5c65159SKalle Valo };
297d5c65159SKalle Valo 
298d5c65159SKalle Valo struct ath11k_htt_data_stats {
299d5c65159SKalle Valo 	u64 legacy[ATH11K_COUNTER_TYPE_MAX][ATH11K_LEGACY_NUM];
300d5c65159SKalle Valo 	u64 ht[ATH11K_COUNTER_TYPE_MAX][ATH11K_HT_MCS_NUM];
301d5c65159SKalle Valo 	u64 vht[ATH11K_COUNTER_TYPE_MAX][ATH11K_VHT_MCS_NUM];
302d5c65159SKalle Valo 	u64 he[ATH11K_COUNTER_TYPE_MAX][ATH11K_HE_MCS_NUM];
303d5c65159SKalle Valo 	u64 bw[ATH11K_COUNTER_TYPE_MAX][ATH11K_BW_NUM];
304d5c65159SKalle Valo 	u64 nss[ATH11K_COUNTER_TYPE_MAX][ATH11K_NSS_NUM];
305d5c65159SKalle Valo 	u64 gi[ATH11K_COUNTER_TYPE_MAX][ATH11K_GI_NUM];
306d5c65159SKalle Valo };
307d5c65159SKalle Valo 
308d5c65159SKalle Valo struct ath11k_htt_tx_stats {
309d5c65159SKalle Valo 	struct ath11k_htt_data_stats stats[ATH11K_STATS_TYPE_MAX];
310d5c65159SKalle Valo 	u64 tx_duration;
311d5c65159SKalle Valo 	u64 ba_fails;
312d5c65159SKalle Valo 	u64 ack_fails;
313d5c65159SKalle Valo };
314d5c65159SKalle Valo 
315d5c65159SKalle Valo struct ath11k_per_ppdu_tx_stats {
316d5c65159SKalle Valo 	u16 succ_pkts;
317d5c65159SKalle Valo 	u16 failed_pkts;
318d5c65159SKalle Valo 	u16 retry_pkts;
319d5c65159SKalle Valo 	u32 succ_bytes;
320d5c65159SKalle Valo 	u32 failed_bytes;
321d5c65159SKalle Valo 	u32 retry_bytes;
322d5c65159SKalle Valo };
323d5c65159SKalle Valo 
324d5c65159SKalle Valo struct ath11k_sta {
325d5c65159SKalle Valo 	struct ath11k_vif *arvif;
326d5c65159SKalle Valo 
327d5c65159SKalle Valo 	/* the following are protected by ar->data_lock */
328d5c65159SKalle Valo 	u32 changed; /* IEEE80211_RC_* */
329d5c65159SKalle Valo 	u32 bw;
330d5c65159SKalle Valo 	u32 nss;
331d5c65159SKalle Valo 	u32 smps;
332d5c65159SKalle Valo 
333d5c65159SKalle Valo 	struct work_struct update_wk;
334d5c65159SKalle Valo 	struct ieee80211_tx_info tx_info;
335d5c65159SKalle Valo 	struct rate_info txrate;
336d5c65159SKalle Valo 	struct rate_info last_txrate;
337d5c65159SKalle Valo 	u64 rx_duration;
338a9e945eaSVenkateswara Naralasetty 	u64 tx_duration;
339d5c65159SKalle Valo 	u8 rssi_comb;
340d5c65159SKalle Valo 	struct ath11k_htt_tx_stats *tx_stats;
341d5c65159SKalle Valo 	struct ath11k_rx_peer_stats *rx_stats;
342d5c65159SKalle Valo };
343d5c65159SKalle Valo 
344d5c65159SKalle Valo #define ATH11K_NUM_CHANS 41
345d5c65159SKalle Valo #define ATH11K_MAX_5G_CHAN 173
346d5c65159SKalle Valo 
347d5c65159SKalle Valo enum ath11k_state {
348d5c65159SKalle Valo 	ATH11K_STATE_OFF,
349d5c65159SKalle Valo 	ATH11K_STATE_ON,
350d5c65159SKalle Valo 	ATH11K_STATE_RESTARTING,
351d5c65159SKalle Valo 	ATH11K_STATE_RESTARTED,
352d5c65159SKalle Valo 	ATH11K_STATE_WEDGED,
353d5c65159SKalle Valo 	/* Add other states as required */
354d5c65159SKalle Valo };
355d5c65159SKalle Valo 
356d5c65159SKalle Valo /* Antenna noise floor */
357d5c65159SKalle Valo #define ATH11K_DEFAULT_NOISE_FLOOR -95
358d5c65159SKalle Valo 
359d5c65159SKalle Valo struct ath11k_fw_stats {
360d5c65159SKalle Valo 	struct dentry *debugfs_fwstats;
361d5c65159SKalle Valo 	u32 pdev_id;
362d5c65159SKalle Valo 	u32 stats_id;
363d5c65159SKalle Valo 	struct list_head pdevs;
364d5c65159SKalle Valo 	struct list_head vdevs;
365d5c65159SKalle Valo 	struct list_head bcn;
366d5c65159SKalle Valo };
367d5c65159SKalle Valo 
368d5c65159SKalle Valo struct ath11k_dbg_htt_stats {
369d5c65159SKalle Valo 	u8 type;
370d5c65159SKalle Valo 	u8 reset;
371d5c65159SKalle Valo 	struct debug_htt_stats_req *stats_req;
372d5c65159SKalle Valo 	/* protects shared stats req buffer */
373d5c65159SKalle Valo 	spinlock_t lock;
374d5c65159SKalle Valo };
375d5c65159SKalle Valo 
376d5c65159SKalle Valo struct ath11k_debug {
377d5c65159SKalle Valo 	struct dentry *debugfs_pdev;
378d5c65159SKalle Valo 	struct ath11k_dbg_htt_stats htt_stats;
379d5c65159SKalle Valo 	u32 extd_tx_stats;
380d5c65159SKalle Valo 	struct ath11k_fw_stats fw_stats;
381d5c65159SKalle Valo 	struct completion fw_stats_complete;
382d5c65159SKalle Valo 	bool fw_stats_done;
383d5c65159SKalle Valo 	u32 extd_rx_stats;
384d5c65159SKalle Valo 	u32 pktlog_filter;
385d5c65159SKalle Valo 	u32 pktlog_mode;
386d5c65159SKalle Valo 	u32 pktlog_peer_valid;
387d5c65159SKalle Valo 	u8 pktlog_peer_addr[ETH_ALEN];
388d5c65159SKalle Valo };
389d5c65159SKalle Valo 
390d5c65159SKalle Valo struct ath11k_per_peer_tx_stats {
391d5c65159SKalle Valo 	u32 succ_bytes;
392d5c65159SKalle Valo 	u32 retry_bytes;
393d5c65159SKalle Valo 	u32 failed_bytes;
394d5c65159SKalle Valo 	u16 succ_pkts;
395d5c65159SKalle Valo 	u16 retry_pkts;
396d5c65159SKalle Valo 	u16 failed_pkts;
397d5c65159SKalle Valo 	u32 duration;
398d5c65159SKalle Valo 	u8 ba_fails;
399d5c65159SKalle Valo 	bool is_ampdu;
400d5c65159SKalle Valo };
401d5c65159SKalle Valo 
402d5c65159SKalle Valo #define ATH11K_FLUSH_TIMEOUT (5 * HZ)
403d5c65159SKalle Valo 
404d5c65159SKalle Valo struct ath11k_vdev_stop_status {
405d5c65159SKalle Valo 	bool stop_in_progress;
406d5c65159SKalle Valo 	u32  vdev_id;
407d5c65159SKalle Valo };
408d5c65159SKalle Valo 
409d5c65159SKalle Valo struct ath11k {
410d5c65159SKalle Valo 	struct ath11k_base *ab;
411d5c65159SKalle Valo 	struct ath11k_pdev *pdev;
412d5c65159SKalle Valo 	struct ieee80211_hw *hw;
413d5c65159SKalle Valo 	struct ieee80211_ops *ops;
414d5c65159SKalle Valo 	struct ath11k_pdev_wmi *wmi;
415d5c65159SKalle Valo 	struct ath11k_pdev_dp dp;
416d5c65159SKalle Valo 	u8 mac_addr[ETH_ALEN];
417d5c65159SKalle Valo 	u32 ht_cap_info;
418d5c65159SKalle Valo 	u32 vht_cap_info;
419d5c65159SKalle Valo 	struct ath11k_he ar_he;
420d5c65159SKalle Valo 	enum ath11k_state state;
421d5c65159SKalle Valo 	struct {
422d5c65159SKalle Valo 		struct completion started;
423d5c65159SKalle Valo 		struct completion completed;
424d5c65159SKalle Valo 		struct completion on_channel;
425d5c65159SKalle Valo 		struct delayed_work timeout;
426d5c65159SKalle Valo 		enum ath11k_scan_state state;
427d5c65159SKalle Valo 		bool is_roc;
428d5c65159SKalle Valo 		int vdev_id;
429d5c65159SKalle Valo 		int roc_freq;
430d5c65159SKalle Valo 		bool roc_notify;
431d5c65159SKalle Valo 	} scan;
432d5c65159SKalle Valo 
433d5c65159SKalle Valo 	struct {
434d5c65159SKalle Valo 		struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
4359f056ed8SJohn Crispin 		struct ieee80211_sband_iftype_data
4369f056ed8SJohn Crispin 			iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
437d5c65159SKalle Valo 	} mac;
438d5c65159SKalle Valo 	unsigned long dev_flags;
439d5c65159SKalle Valo 	unsigned int filter_flags;
440d5c65159SKalle Valo 	unsigned long monitor_flags;
441d5c65159SKalle Valo 	u32 min_tx_power;
442d5c65159SKalle Valo 	u32 max_tx_power;
443d5c65159SKalle Valo 	u32 txpower_limit_2g;
444d5c65159SKalle Valo 	u32 txpower_limit_5g;
445d5c65159SKalle Valo 	u32 txpower_scale;
446d5c65159SKalle Valo 	u32 power_scale;
447d5c65159SKalle Valo 	u32 chan_tx_pwr;
448d5c65159SKalle Valo 	u32 num_stations;
449d5c65159SKalle Valo 	u32 max_num_stations;
450d5c65159SKalle Valo 	bool monitor_present;
451d5c65159SKalle Valo 	/* To synchronize concurrent synchronous mac80211 callback operations,
452d5c65159SKalle Valo 	 * concurrent debugfs configuration and concurrent FW statistics events.
453d5c65159SKalle Valo 	 */
454d5c65159SKalle Valo 	struct mutex conf_mutex;
455d5c65159SKalle Valo 	/* protects the radio specific data like debug stats, ppdu_stats_info stats,
456d5c65159SKalle Valo 	 * vdev_stop_status info, scan data, ath11k_sta info, ath11k_vif info,
457d5c65159SKalle Valo 	 * channel context data, survey info, test mode data.
458d5c65159SKalle Valo 	 */
459d5c65159SKalle Valo 	spinlock_t data_lock;
460d5c65159SKalle Valo 
461d5c65159SKalle Valo 	struct list_head arvifs;
462d5c65159SKalle Valo 	/* should never be NULL; needed for regular htt rx */
463d5c65159SKalle Valo 	struct ieee80211_channel *rx_channel;
464d5c65159SKalle Valo 
465d5c65159SKalle Valo 	/* valid during scan; needed for mgmt rx during scan */
466d5c65159SKalle Valo 	struct ieee80211_channel *scan_channel;
467d5c65159SKalle Valo 
468d5c65159SKalle Valo 	u8 cfg_tx_chainmask;
469d5c65159SKalle Valo 	u8 cfg_rx_chainmask;
470d5c65159SKalle Valo 	u8 num_rx_chains;
471d5c65159SKalle Valo 	u8 num_tx_chains;
472d5c65159SKalle Valo 	/* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */
473d5c65159SKalle Valo 	u8 pdev_idx;
474d5c65159SKalle Valo 	u8 lmac_id;
475d5c65159SKalle Valo 
476d5c65159SKalle Valo 	struct completion peer_assoc_done;
477d5c65159SKalle Valo 
478d5c65159SKalle Valo 	int install_key_status;
479d5c65159SKalle Valo 	struct completion install_key_done;
480d5c65159SKalle Valo 
481d5c65159SKalle Valo 	int last_wmi_vdev_start_status;
482d5c65159SKalle Valo 	struct ath11k_vdev_stop_status vdev_stop_status;
483d5c65159SKalle Valo 	struct completion vdev_setup_done;
484d5c65159SKalle Valo 
485d5c65159SKalle Valo 	int num_peers;
486d5c65159SKalle Valo 	int max_num_peers;
487d5c65159SKalle Valo 	u32 num_started_vdevs;
488d5c65159SKalle Valo 	u32 num_created_vdevs;
489d5c65159SKalle Valo 
490d5c65159SKalle Valo 	struct idr txmgmt_idr;
491d5c65159SKalle Valo 	/* protects txmgmt_idr data */
492d5c65159SKalle Valo 	spinlock_t txmgmt_idr_lock;
493d5c65159SKalle Valo 	atomic_t num_pending_mgmt_tx;
494d5c65159SKalle Valo 
495d5c65159SKalle Valo 	/* cycle count is reported twice for each visited channel during scan.
496d5c65159SKalle Valo 	 * access protected by data_lock
497d5c65159SKalle Valo 	 */
498d5c65159SKalle Valo 	u32 survey_last_rx_clear_count;
499d5c65159SKalle Valo 	u32 survey_last_cycle_count;
500d5c65159SKalle Valo 
501d5c65159SKalle Valo 	/* Channel info events are expected to come in pairs without and with
502d5c65159SKalle Valo 	 * COMPLETE flag set respectively for each channel visit during scan.
503d5c65159SKalle Valo 	 *
504d5c65159SKalle Valo 	 * However there are deviations from this rule. This flag is used to
505d5c65159SKalle Valo 	 * avoid reporting garbage data.
506d5c65159SKalle Valo 	 */
507d5c65159SKalle Valo 	bool ch_info_can_report_survey;
508d5c65159SKalle Valo 	struct survey_info survey[ATH11K_NUM_CHANS];
509d5c65159SKalle Valo 	struct completion bss_survey_done;
510d5c65159SKalle Valo 
511d5c65159SKalle Valo 	struct work_struct regd_update_work;
512d5c65159SKalle Valo 
513d5c65159SKalle Valo 	struct work_struct wmi_mgmt_tx_work;
514d5c65159SKalle Valo 	struct sk_buff_head wmi_mgmt_tx_queue;
515d5c65159SKalle Valo 
516d5c65159SKalle Valo 	struct ath11k_per_peer_tx_stats peer_tx_stats;
517d5c65159SKalle Valo 	struct list_head ppdu_stats_info;
518d5c65159SKalle Valo 	u32 ppdu_stat_list_depth;
519d5c65159SKalle Valo 
520d5c65159SKalle Valo 	struct ath11k_per_peer_tx_stats cached_stats;
521d5c65159SKalle Valo 	u32 last_ppdu_id;
522d5c65159SKalle Valo 	u32 cached_ppdu_id;
523d5c65159SKalle Valo #ifdef CONFIG_ATH11K_DEBUGFS
524d5c65159SKalle Valo 	struct ath11k_debug debug;
525d5c65159SKalle Valo #endif
526d5c65159SKalle Valo 	bool dfs_block_radar_events;
527d5c65159SKalle Valo };
528d5c65159SKalle Valo 
529d5c65159SKalle Valo struct ath11k_band_cap {
530d5c65159SKalle Valo 	u32 max_bw_supported;
531d5c65159SKalle Valo 	u32 ht_cap_info;
532d5c65159SKalle Valo 	u32 he_cap_info[2];
533d5c65159SKalle Valo 	u32 he_mcs;
534d5c65159SKalle Valo 	u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
535d5c65159SKalle Valo 	struct ath11k_ppe_threshold he_ppet;
536d5c65159SKalle Valo };
537d5c65159SKalle Valo 
538d5c65159SKalle Valo struct ath11k_pdev_cap {
539d5c65159SKalle Valo 	u32 supported_bands;
540d5c65159SKalle Valo 	u32 ampdu_density;
541d5c65159SKalle Valo 	u32 vht_cap;
542d5c65159SKalle Valo 	u32 vht_mcs;
543d5c65159SKalle Valo 	u32 he_mcs;
544d5c65159SKalle Valo 	u32 tx_chain_mask;
545d5c65159SKalle Valo 	u32 rx_chain_mask;
546d5c65159SKalle Valo 	u32 tx_chain_mask_shift;
547d5c65159SKalle Valo 	u32 rx_chain_mask_shift;
548d5c65159SKalle Valo 	struct ath11k_band_cap band[NUM_NL80211_BANDS];
549d5c65159SKalle Valo };
550d5c65159SKalle Valo 
551d5c65159SKalle Valo struct ath11k_pdev {
552d5c65159SKalle Valo 	struct ath11k *ar;
553d5c65159SKalle Valo 	u32 pdev_id;
554d5c65159SKalle Valo 	struct ath11k_pdev_cap cap;
555d5c65159SKalle Valo 	u8 mac_addr[ETH_ALEN];
556d5c65159SKalle Valo };
557d5c65159SKalle Valo 
558d5c65159SKalle Valo struct ath11k_board_data {
559d5c65159SKalle Valo 	const struct firmware *fw;
560d5c65159SKalle Valo 	const void *data;
561d5c65159SKalle Valo 	size_t len;
562d5c65159SKalle Valo };
563d5c65159SKalle Valo 
564d5c65159SKalle Valo /* IPQ8074 HW channel counters frequency value in hertz */
565d5c65159SKalle Valo #define IPQ8074_CC_FREQ_HERTZ 320000
566d5c65159SKalle Valo 
567d5c65159SKalle Valo struct ath11k_soc_dp_rx_stats {
568d5c65159SKalle Valo 	u32 err_ring_pkts;
569d5c65159SKalle Valo 	u32 invalid_rbm;
570d5c65159SKalle Valo 	u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX];
571d5c65159SKalle Valo 	u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX];
572d5c65159SKalle Valo 	u32 hal_reo_error[DP_REO_DST_RING_MAX];
573d5c65159SKalle Valo };
574d5c65159SKalle Valo 
575d5c65159SKalle Valo /* Master structure to hold the hw data which may be used in core module */
576d5c65159SKalle Valo struct ath11k_base {
577d5c65159SKalle Valo 	enum ath11k_hw_rev hw_rev;
578d5c65159SKalle Valo 	struct platform_device *pdev;
579d5c65159SKalle Valo 	struct device *dev;
580d5c65159SKalle Valo 	struct ath11k_qmi qmi;
581*6bc9d6f7SJohn Crispin 	struct ath11k_wmi_base wmi_ab;
582d5c65159SKalle Valo 	struct completion fw_ready;
583d5c65159SKalle Valo 	struct rproc *tgt_rproc;
584d5c65159SKalle Valo 	int num_radios;
585d5c65159SKalle Valo 	/* HW channel counters frequency value in hertz common to all MACs */
586d5c65159SKalle Valo 	u32 cc_freq_hz;
587d5c65159SKalle Valo 
588d5c65159SKalle Valo 	struct ath11k_htc htc;
589d5c65159SKalle Valo 
590d5c65159SKalle Valo 	struct ath11k_dp dp;
591d5c65159SKalle Valo 
592d5c65159SKalle Valo 	void __iomem *mem;
593d5c65159SKalle Valo 	unsigned long mem_len;
594d5c65159SKalle Valo 
595d5c65159SKalle Valo 	const struct ath11k_hif_ops *hif_ops;
596d5c65159SKalle Valo 
597d5c65159SKalle Valo 	struct ath11k_ce ce;
598d5c65159SKalle Valo 	struct timer_list rx_replenish_retry;
599d5c65159SKalle Valo 	struct ath11k_hal hal;
600d5c65159SKalle Valo 	/* To synchronize core_start/core_stop */
601d5c65159SKalle Valo 	struct mutex core_lock;
602d5c65159SKalle Valo 	/* Protects data like peers */
603d5c65159SKalle Valo 	spinlock_t base_lock;
604d5c65159SKalle Valo 	struct ath11k_pdev pdevs[MAX_RADIOS];
605d5c65159SKalle Valo 	struct ath11k_pdev __rcu *pdevs_active[MAX_RADIOS];
606d5c65159SKalle Valo 	struct ath11k_hal_reg_capabilities_ext hal_reg_cap[MAX_RADIOS];
607d5c65159SKalle Valo 	unsigned long long free_vdev_map;
608d5c65159SKalle Valo 	struct list_head peers;
609d5c65159SKalle Valo 	wait_queue_head_t peer_mapping_wq;
610d5c65159SKalle Valo 	u8 mac_addr[ETH_ALEN];
611d5c65159SKalle Valo 	bool wmi_ready;
612d5c65159SKalle Valo 	u32 wlan_init_status;
613d5c65159SKalle Valo 	int irq_num[ATH11K_IRQ_NUM_MAX];
614d5c65159SKalle Valo 	struct ath11k_ext_irq_grp ext_irq_grp[ATH11K_EXT_IRQ_GRP_NUM_MAX];
615d5c65159SKalle Valo 	struct napi_struct *napi;
616d5c65159SKalle Valo 	struct ath11k_targ_cap target_caps;
617d5c65159SKalle Valo 	u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE];
618d5c65159SKalle Valo 	bool pdevs_macaddr_valid;
619d5c65159SKalle Valo 	int bd_api;
620d5c65159SKalle Valo 	struct ath11k_hw_params hw_params;
621d5c65159SKalle Valo 	const struct firmware *cal_file;
622d5c65159SKalle Valo 
623d5c65159SKalle Valo 	/* Below regd's are protected by ab->data_lock */
624d5c65159SKalle Valo 	/* This is the regd set for every radio
625d5c65159SKalle Valo 	 * by the firmware during initializatin
626d5c65159SKalle Valo 	 */
627d5c65159SKalle Valo 	struct ieee80211_regdomain *default_regd[MAX_RADIOS];
628d5c65159SKalle Valo 	/* This regd is set during dynamic country setting
629d5c65159SKalle Valo 	 * This may or may not be used during the runtime
630d5c65159SKalle Valo 	 */
631d5c65159SKalle Valo 	struct ieee80211_regdomain *new_regd[MAX_RADIOS];
632d5c65159SKalle Valo 
633d5c65159SKalle Valo 	/* Current DFS Regulatory */
634d5c65159SKalle Valo 	enum ath11k_dfs_region dfs_region;
635d5c65159SKalle Valo #ifdef CONFIG_ATH11K_DEBUGFS
636d5c65159SKalle Valo 	struct dentry *debugfs_soc;
637d5c65159SKalle Valo 	struct dentry *debugfs_ath11k;
638d5c65159SKalle Valo #endif
639d5c65159SKalle Valo 	struct ath11k_soc_dp_rx_stats soc_stats;
640d5c65159SKalle Valo 
641d5c65159SKalle Valo 	unsigned long dev_flags;
642d5c65159SKalle Valo 	struct completion driver_recovery;
643d5c65159SKalle Valo 	struct workqueue_struct *workqueue;
644d5c65159SKalle Valo 	struct work_struct restart_work;
645d5c65159SKalle Valo 	struct {
646d5c65159SKalle Valo 		/* protected by data_lock */
647d5c65159SKalle Valo 		u32 fw_crash_counter;
648d5c65159SKalle Valo 	} stats;
649d5c65159SKalle Valo };
650d5c65159SKalle Valo 
651d5c65159SKalle Valo struct ath11k_fw_stats_pdev {
652d5c65159SKalle Valo 	struct list_head list;
653d5c65159SKalle Valo 
654d5c65159SKalle Valo 	/* PDEV stats */
655d5c65159SKalle Valo 	s32 ch_noise_floor;
656d5c65159SKalle Valo 	/* Cycles spent transmitting frames */
657d5c65159SKalle Valo 	u32 tx_frame_count;
658d5c65159SKalle Valo 	/* Cycles spent receiving frames */
659d5c65159SKalle Valo 	u32 rx_frame_count;
660d5c65159SKalle Valo 	/* Total channel busy time, evidently */
661d5c65159SKalle Valo 	u32 rx_clear_count;
662d5c65159SKalle Valo 	/* Total on-channel time */
663d5c65159SKalle Valo 	u32 cycle_count;
664d5c65159SKalle Valo 	u32 phy_err_count;
665d5c65159SKalle Valo 	u32 chan_tx_power;
666d5c65159SKalle Valo 	u32 ack_rx_bad;
667d5c65159SKalle Valo 	u32 rts_bad;
668d5c65159SKalle Valo 	u32 rts_good;
669d5c65159SKalle Valo 	u32 fcs_bad;
670d5c65159SKalle Valo 	u32 no_beacons;
671d5c65159SKalle Valo 	u32 mib_int_count;
672d5c65159SKalle Valo 
673d5c65159SKalle Valo 	/* PDEV TX stats */
674d5c65159SKalle Valo 	/* Num HTT cookies queued to dispatch list */
675d5c65159SKalle Valo 	s32 comp_queued;
676d5c65159SKalle Valo 	/* Num HTT cookies dispatched */
677d5c65159SKalle Valo 	s32 comp_delivered;
678d5c65159SKalle Valo 	/* Num MSDU queued to WAL */
679d5c65159SKalle Valo 	s32 msdu_enqued;
680d5c65159SKalle Valo 	/* Num MPDU queue to WAL */
681d5c65159SKalle Valo 	s32 mpdu_enqued;
682d5c65159SKalle Valo 	/* Num MSDUs dropped by WMM limit */
683d5c65159SKalle Valo 	s32 wmm_drop;
684d5c65159SKalle Valo 	/* Num Local frames queued */
685d5c65159SKalle Valo 	s32 local_enqued;
686d5c65159SKalle Valo 	/* Num Local frames done */
687d5c65159SKalle Valo 	s32 local_freed;
688d5c65159SKalle Valo 	/* Num queued to HW */
689d5c65159SKalle Valo 	s32 hw_queued;
690d5c65159SKalle Valo 	/* Num PPDU reaped from HW */
691d5c65159SKalle Valo 	s32 hw_reaped;
692d5c65159SKalle Valo 	/* Num underruns */
693d5c65159SKalle Valo 	s32 underrun;
694d5c65159SKalle Valo 	/* Num PPDUs cleaned up in TX abort */
695d5c65159SKalle Valo 	s32 tx_abort;
696d5c65159SKalle Valo 	/* Num MPDUs requed by SW */
697d5c65159SKalle Valo 	s32 mpdus_requed;
698d5c65159SKalle Valo 	/* excessive retries */
699d5c65159SKalle Valo 	u32 tx_ko;
700d5c65159SKalle Valo 	/* data hw rate code */
701d5c65159SKalle Valo 	u32 data_rc;
702d5c65159SKalle Valo 	/* Scheduler self triggers */
703d5c65159SKalle Valo 	u32 self_triggers;
704d5c65159SKalle Valo 	/* frames dropped due to excessive sw retries */
705d5c65159SKalle Valo 	u32 sw_retry_failure;
706d5c65159SKalle Valo 	/* illegal rate phy errors	*/
707d5c65159SKalle Valo 	u32 illgl_rate_phy_err;
708d5c65159SKalle Valo 	/* wal pdev continuous xretry */
709d5c65159SKalle Valo 	u32 pdev_cont_xretry;
710d5c65159SKalle Valo 	/* wal pdev tx timeouts */
711d5c65159SKalle Valo 	u32 pdev_tx_timeout;
712d5c65159SKalle Valo 	/* wal pdev resets */
713d5c65159SKalle Valo 	u32 pdev_resets;
714d5c65159SKalle Valo 	/* frames dropped due to non-availability of stateless TIDs */
715d5c65159SKalle Valo 	u32 stateless_tid_alloc_failure;
716d5c65159SKalle Valo 	/* PhY/BB underrun */
717d5c65159SKalle Valo 	u32 phy_underrun;
718d5c65159SKalle Valo 	/* MPDU is more than txop limit */
719d5c65159SKalle Valo 	u32 txop_ovf;
720d5c65159SKalle Valo 
721d5c65159SKalle Valo 	/* PDEV RX stats */
722d5c65159SKalle Valo 	/* Cnts any change in ring routing mid-ppdu */
723d5c65159SKalle Valo 	s32 mid_ppdu_route_change;
724d5c65159SKalle Valo 	/* Total number of statuses processed */
725d5c65159SKalle Valo 	s32 status_rcvd;
726d5c65159SKalle Valo 	/* Extra frags on rings 0-3 */
727d5c65159SKalle Valo 	s32 r0_frags;
728d5c65159SKalle Valo 	s32 r1_frags;
729d5c65159SKalle Valo 	s32 r2_frags;
730d5c65159SKalle Valo 	s32 r3_frags;
731d5c65159SKalle Valo 	/* MSDUs / MPDUs delivered to HTT */
732d5c65159SKalle Valo 	s32 htt_msdus;
733d5c65159SKalle Valo 	s32 htt_mpdus;
734d5c65159SKalle Valo 	/* MSDUs / MPDUs delivered to local stack */
735d5c65159SKalle Valo 	s32 loc_msdus;
736d5c65159SKalle Valo 	s32 loc_mpdus;
737d5c65159SKalle Valo 	/* AMSDUs that have more MSDUs than the status ring size */
738d5c65159SKalle Valo 	s32 oversize_amsdu;
739d5c65159SKalle Valo 	/* Number of PHY errors */
740d5c65159SKalle Valo 	s32 phy_errs;
741d5c65159SKalle Valo 	/* Number of PHY errors drops */
742d5c65159SKalle Valo 	s32 phy_err_drop;
743d5c65159SKalle Valo 	/* Number of mpdu errors - FCS, MIC, ENC etc. */
744d5c65159SKalle Valo 	s32 mpdu_errs;
745d5c65159SKalle Valo };
746d5c65159SKalle Valo 
747d5c65159SKalle Valo struct ath11k_fw_stats_vdev {
748d5c65159SKalle Valo 	struct list_head list;
749d5c65159SKalle Valo 
750d5c65159SKalle Valo 	u32 vdev_id;
751d5c65159SKalle Valo 	u32 beacon_snr;
752d5c65159SKalle Valo 	u32 data_snr;
753d5c65159SKalle Valo 	u32 num_tx_frames[WLAN_MAX_AC];
754d5c65159SKalle Valo 	u32 num_rx_frames;
755d5c65159SKalle Valo 	u32 num_tx_frames_retries[WLAN_MAX_AC];
756d5c65159SKalle Valo 	u32 num_tx_frames_failures[WLAN_MAX_AC];
757d5c65159SKalle Valo 	u32 num_rts_fail;
758d5c65159SKalle Valo 	u32 num_rts_success;
759d5c65159SKalle Valo 	u32 num_rx_err;
760d5c65159SKalle Valo 	u32 num_rx_discard;
761d5c65159SKalle Valo 	u32 num_tx_not_acked;
762d5c65159SKalle Valo 	u32 tx_rate_history[MAX_TX_RATE_VALUES];
763d5c65159SKalle Valo 	u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
764d5c65159SKalle Valo };
765d5c65159SKalle Valo 
766d5c65159SKalle Valo struct ath11k_fw_stats_bcn {
767d5c65159SKalle Valo 	struct list_head list;
768d5c65159SKalle Valo 
769d5c65159SKalle Valo 	u32 vdev_id;
770d5c65159SKalle Valo 	u32 tx_bcn_succ_cnt;
771d5c65159SKalle Valo 	u32 tx_bcn_outage_cnt;
772d5c65159SKalle Valo };
773d5c65159SKalle Valo 
774d5c65159SKalle Valo void ath11k_peer_unmap_event(struct ath11k_base *ab, u16 peer_id);
775d5c65159SKalle Valo void ath11k_peer_map_event(struct ath11k_base *ab, u8 vdev_id, u16 peer_id,
776d5c65159SKalle Valo 			   u8 *mac_addr, u16 ast_hash);
777d5c65159SKalle Valo struct ath11k_peer *ath11k_peer_find(struct ath11k_base *ab, int vdev_id,
778d5c65159SKalle Valo 				     const u8 *addr);
779d5c65159SKalle Valo struct ath11k_peer *ath11k_peer_find_by_addr(struct ath11k_base *ab,
780d5c65159SKalle Valo 					     const u8 *addr);
781d5c65159SKalle Valo struct ath11k_peer *ath11k_peer_find_by_id(struct ath11k_base *ab, int peer_id);
782d5c65159SKalle Valo int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab);
783d5c65159SKalle Valo int ath11k_core_init(struct ath11k_base *ath11k);
784d5c65159SKalle Valo void ath11k_core_deinit(struct ath11k_base *ath11k);
785d5c65159SKalle Valo struct ath11k_base *ath11k_core_alloc(struct device *dev);
786d5c65159SKalle Valo void ath11k_core_free(struct ath11k_base *ath11k);
787d5c65159SKalle Valo int ath11k_core_fetch_bdf(struct ath11k_base *ath11k,
788d5c65159SKalle Valo 			  struct ath11k_board_data *bd);
789d5c65159SKalle Valo void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd);
790d5c65159SKalle Valo 
791d5c65159SKalle Valo void ath11k_core_halt(struct ath11k *ar);
792d5c65159SKalle Valo u8 ath11k_core_get_hw_mac_id(struct ath11k_base *ab, int pdev_idx);
793d5c65159SKalle Valo 
794d5c65159SKalle Valo static inline const char *ath11k_scan_state_str(enum ath11k_scan_state state)
795d5c65159SKalle Valo {
796d5c65159SKalle Valo 	switch (state) {
797d5c65159SKalle Valo 	case ATH11K_SCAN_IDLE:
798d5c65159SKalle Valo 		return "idle";
799d5c65159SKalle Valo 	case ATH11K_SCAN_STARTING:
800d5c65159SKalle Valo 		return "starting";
801d5c65159SKalle Valo 	case ATH11K_SCAN_RUNNING:
802d5c65159SKalle Valo 		return "running";
803d5c65159SKalle Valo 	case ATH11K_SCAN_ABORTING:
804d5c65159SKalle Valo 		return "aborting";
805d5c65159SKalle Valo 	}
806d5c65159SKalle Valo 
807d5c65159SKalle Valo 	return "unknown";
808d5c65159SKalle Valo }
809d5c65159SKalle Valo 
810d5c65159SKalle Valo static inline struct ath11k_skb_cb *ATH11K_SKB_CB(struct sk_buff *skb)
811d5c65159SKalle Valo {
812d5c65159SKalle Valo 	return (struct ath11k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
813d5c65159SKalle Valo }
814d5c65159SKalle Valo 
815d5c65159SKalle Valo static inline struct ath11k_skb_rxcb *ATH11K_SKB_RXCB(struct sk_buff *skb)
816d5c65159SKalle Valo {
817d5c65159SKalle Valo 	BUILD_BUG_ON(sizeof(struct ath11k_skb_rxcb) > sizeof(skb->cb));
818d5c65159SKalle Valo 	return (struct ath11k_skb_rxcb *)skb->cb;
819d5c65159SKalle Valo }
820d5c65159SKalle Valo 
821d5c65159SKalle Valo static inline struct ath11k_vif *ath11k_vif_to_arvif(struct ieee80211_vif *vif)
822d5c65159SKalle Valo {
823d5c65159SKalle Valo 	return (struct ath11k_vif *)vif->drv_priv;
824d5c65159SKalle Valo }
825d5c65159SKalle Valo 
826d5c65159SKalle Valo #endif /* _CORE_H_ */
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