1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/netdevice.h> 14 #include <linux/module.h> 15 #include <linux/delay.h> 16 #include <linux/clk.h> 17 #include <linux/string_choices.h> 18 19 #include "realtek.h" 20 21 #define RTL8201F_IER 0x13 22 23 #define RTL8201F_ISR 0x1e 24 #define RTL8201F_ISR_ANERR BIT(15) 25 #define RTL8201F_ISR_DUPLEX BIT(13) 26 #define RTL8201F_ISR_LINK BIT(11) 27 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 28 RTL8201F_ISR_DUPLEX | \ 29 RTL8201F_ISR_LINK) 30 31 #define RTL821x_INER 0x12 32 #define RTL8211B_INER_INIT 0x6400 33 #define RTL8211E_INER_LINK_STATUS BIT(10) 34 #define RTL8211F_INER_LINK_STATUS BIT(4) 35 36 #define RTL821x_INSR 0x13 37 38 #define RTL821x_EXT_PAGE_SELECT 0x1e 39 40 #define RTL821x_PAGE_SELECT 0x1f 41 #define RTL821x_SET_EXT_PAGE 0x07 42 43 /* RTL8211E extension page 44/0x2c */ 44 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 45 #define RTL8211E_LEDCR1 0x1a 46 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 47 #define RTL8211E_LEDCR1_MASK BIT(4) 48 #define RTL8211E_LEDCR1_SHIFT 1 49 50 #define RTL8211E_LEDCR2 0x1c 51 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 52 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 53 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 54 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 55 #define RTL8211E_LEDCR2_SHIFT 4 56 57 /* RTL8211E extension page 164/0xa4 */ 58 #define RTL8211E_RGMII_EXT_PAGE 0xa4 59 #define RTL8211E_RGMII_DELAY 0x1c 60 #define RTL8211E_CTRL_DELAY BIT(13) 61 #define RTL8211E_TX_DELAY BIT(12) 62 #define RTL8211E_RX_DELAY BIT(11) 63 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 64 65 /* RTL8211F PHY configuration */ 66 #define RTL8211F_PHYCR_PAGE 0xa43 67 #define RTL8211F_PHYCR1 0x18 68 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 69 #define RTL8211F_ALDPS_ENABLE BIT(2) 70 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 71 72 #define RTL8211F_PHYCR2 0x19 73 #define RTL8211F_CLKOUT_EN BIT(0) 74 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 75 76 #define RTL8211F_INSR_PAGE 0xa43 77 #define RTL8211F_INSR 0x1d 78 79 /* RTL8211F LED configuration */ 80 #define RTL8211F_LEDCR_PAGE 0xd04 81 #define RTL8211F_LEDCR 0x10 82 #define RTL8211F_LEDCR_MODE BIT(15) 83 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 84 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 85 #define RTL8211F_LEDCR_LINK_100 BIT(1) 86 #define RTL8211F_LEDCR_LINK_10 BIT(0) 87 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 88 #define RTL8211F_LEDCR_SHIFT 5 89 90 /* RTL8211F RGMII configuration */ 91 #define RTL8211F_RGMII_PAGE 0xd08 92 93 #define RTL8211F_TXCR 0x11 94 #define RTL8211F_TX_DELAY BIT(8) 95 96 #define RTL8211F_RXCR 0x15 97 #define RTL8211F_RX_DELAY BIT(3) 98 99 /* RTL8211F WOL interrupt configuration */ 100 #define RTL8211F_INTBCR_PAGE 0xd40 101 #define RTL8211F_INTBCR 0x16 102 #define RTL8211F_INTBCR_INTB_PMEB BIT(5) 103 104 /* RTL8211F WOL settings */ 105 #define RTL8211F_WOL_SETTINGS_PAGE 0xd8a 106 #define RTL8211F_WOL_SETTINGS_EVENTS 16 107 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 108 #define RTL8211F_WOL_SETTINGS_STATUS 17 109 #define RTL8211F_WOL_STATUS_RESET (BIT(15) | 0x1fff) 110 111 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 112 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 113 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 114 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 115 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 116 117 #define RTL822X_VND1_SERDES_OPTION 0x697a 118 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 119 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 120 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 121 122 #define RTL822X_VND1_SERDES_CTRL3 0x7580 123 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 124 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 125 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 126 127 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45 128 * is set, they cannot be accessed by C45-over-C22. 129 */ 130 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 131 132 #define RTL8366RB_POWER_SAVE 0x15 133 #define RTL8366RB_POWER_SAVE_ON BIT(12) 134 135 #define RTL9000A_GINMR 0x14 136 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 137 138 #define RTL_VND2_PHYSR 0xa434 139 #define RTL_VND2_PHYSR_DUPLEX BIT(3) 140 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4) 141 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9) 142 #define RTL_VND2_PHYSR_MASTER BIT(11) 143 #define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH) 144 145 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 146 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 147 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 148 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 149 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 150 #define RTL_MDIO_PMA_SPEED 0xa616 151 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 152 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 153 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 154 155 #define RTL_GENERIC_PHYID 0x001cc800 156 #define RTL_8211FVD_PHYID 0x001cc878 157 #define RTL_8221B 0x001cc840 158 #define RTL_8221B_VB_CG 0x001cc849 159 #define RTL_8221B_VN_CG 0x001cc84a 160 #define RTL_8251B 0x001cc862 161 #define RTL_8261C 0x001cc890 162 163 /* RTL8211E and RTL8211F support up to three LEDs */ 164 #define RTL8211x_LED_COUNT 3 165 166 MODULE_DESCRIPTION("Realtek PHY driver"); 167 MODULE_AUTHOR("Johnson Leung"); 168 MODULE_LICENSE("GPL"); 169 170 struct rtl821x_priv { 171 u16 phycr1; 172 u16 phycr2; 173 bool has_phycr2; 174 struct clk *clk; 175 u32 saved_wolopts; 176 }; 177 178 static int rtl821x_read_page(struct phy_device *phydev) 179 { 180 return __phy_read(phydev, RTL821x_PAGE_SELECT); 181 } 182 183 static int rtl821x_write_page(struct phy_device *phydev, int page) 184 { 185 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 186 } 187 188 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 189 u32 regnum) 190 { 191 int oldpage, ret = 0; 192 193 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 194 if (oldpage >= 0) { 195 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 196 if (ret == 0) 197 ret = __phy_read(phydev, regnum); 198 } 199 200 return phy_restore_page(phydev, oldpage, ret); 201 } 202 203 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 204 u32 regnum, u16 mask, u16 set) 205 { 206 int oldpage, ret = 0; 207 208 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 209 if (oldpage >= 0) { 210 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 211 if (ret == 0) 212 ret = __phy_modify(phydev, regnum, mask, set); 213 } 214 215 return phy_restore_page(phydev, oldpage, ret); 216 } 217 218 static int rtl821x_probe(struct phy_device *phydev) 219 { 220 struct device *dev = &phydev->mdio.dev; 221 struct rtl821x_priv *priv; 222 u32 phy_id = phydev->drv->phy_id; 223 int ret; 224 225 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 226 if (!priv) 227 return -ENOMEM; 228 229 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 230 if (IS_ERR(priv->clk)) 231 return dev_err_probe(dev, PTR_ERR(priv->clk), 232 "failed to get phy clock\n"); 233 234 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1); 235 if (ret < 0) 236 return ret; 237 238 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF); 239 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable")) 240 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF; 241 242 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID); 243 if (priv->has_phycr2) { 244 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2); 245 if (ret < 0) 246 return ret; 247 248 priv->phycr2 = ret & RTL8211F_CLKOUT_EN; 249 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) 250 priv->phycr2 &= ~RTL8211F_CLKOUT_EN; 251 } 252 253 phydev->priv = priv; 254 255 return 0; 256 } 257 258 static int rtl8201_ack_interrupt(struct phy_device *phydev) 259 { 260 int err; 261 262 err = phy_read(phydev, RTL8201F_ISR); 263 264 return (err < 0) ? err : 0; 265 } 266 267 static int rtl821x_ack_interrupt(struct phy_device *phydev) 268 { 269 int err; 270 271 err = phy_read(phydev, RTL821x_INSR); 272 273 return (err < 0) ? err : 0; 274 } 275 276 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 277 { 278 int err; 279 280 err = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 281 282 return (err < 0) ? err : 0; 283 } 284 285 static int rtl8201_config_intr(struct phy_device *phydev) 286 { 287 u16 val; 288 int err; 289 290 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 291 err = rtl8201_ack_interrupt(phydev); 292 if (err) 293 return err; 294 295 val = BIT(13) | BIT(12) | BIT(11); 296 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 297 } else { 298 val = 0; 299 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 300 if (err) 301 return err; 302 303 err = rtl8201_ack_interrupt(phydev); 304 } 305 306 return err; 307 } 308 309 static int rtl8211b_config_intr(struct phy_device *phydev) 310 { 311 int err; 312 313 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 314 err = rtl821x_ack_interrupt(phydev); 315 if (err) 316 return err; 317 318 err = phy_write(phydev, RTL821x_INER, 319 RTL8211B_INER_INIT); 320 } else { 321 err = phy_write(phydev, RTL821x_INER, 0); 322 if (err) 323 return err; 324 325 err = rtl821x_ack_interrupt(phydev); 326 } 327 328 return err; 329 } 330 331 static int rtl8211e_config_intr(struct phy_device *phydev) 332 { 333 int err; 334 335 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 336 err = rtl821x_ack_interrupt(phydev); 337 if (err) 338 return err; 339 340 err = phy_write(phydev, RTL821x_INER, 341 RTL8211E_INER_LINK_STATUS); 342 } else { 343 err = phy_write(phydev, RTL821x_INER, 0); 344 if (err) 345 return err; 346 347 err = rtl821x_ack_interrupt(phydev); 348 } 349 350 return err; 351 } 352 353 static int rtl8211f_config_intr(struct phy_device *phydev) 354 { 355 u16 val; 356 int err; 357 358 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 359 err = rtl8211f_ack_interrupt(phydev); 360 if (err) 361 return err; 362 363 val = RTL8211F_INER_LINK_STATUS; 364 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 365 } else { 366 val = 0; 367 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 368 if (err) 369 return err; 370 371 err = rtl8211f_ack_interrupt(phydev); 372 } 373 374 return err; 375 } 376 377 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 378 { 379 int irq_status; 380 381 irq_status = phy_read(phydev, RTL8201F_ISR); 382 if (irq_status < 0) { 383 phy_error(phydev); 384 return IRQ_NONE; 385 } 386 387 if (!(irq_status & RTL8201F_ISR_MASK)) 388 return IRQ_NONE; 389 390 phy_trigger_machine(phydev); 391 392 return IRQ_HANDLED; 393 } 394 395 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 396 { 397 int irq_status, irq_enabled; 398 399 irq_status = phy_read(phydev, RTL821x_INSR); 400 if (irq_status < 0) { 401 phy_error(phydev); 402 return IRQ_NONE; 403 } 404 405 irq_enabled = phy_read(phydev, RTL821x_INER); 406 if (irq_enabled < 0) { 407 phy_error(phydev); 408 return IRQ_NONE; 409 } 410 411 if (!(irq_status & irq_enabled)) 412 return IRQ_NONE; 413 414 phy_trigger_machine(phydev); 415 416 return IRQ_HANDLED; 417 } 418 419 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 420 { 421 int irq_status; 422 423 irq_status = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 424 if (irq_status < 0) { 425 phy_error(phydev); 426 return IRQ_NONE; 427 } 428 429 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 430 return IRQ_NONE; 431 432 phy_trigger_machine(phydev); 433 434 return IRQ_HANDLED; 435 } 436 437 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 438 { 439 wol->supported = WAKE_MAGIC; 440 if (phy_read_paged(dev, RTL8211F_WOL_SETTINGS_PAGE, RTL8211F_WOL_SETTINGS_EVENTS) 441 & RTL8211F_WOL_EVENT_MAGIC) 442 wol->wolopts = WAKE_MAGIC; 443 } 444 445 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 446 { 447 const u8 *mac_addr = dev->attached_dev->dev_addr; 448 int oldpage; 449 450 oldpage = phy_save_page(dev); 451 if (oldpage < 0) 452 goto err; 453 454 if (wol->wolopts & WAKE_MAGIC) { 455 /* Store the device address for the magic packet */ 456 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 457 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 458 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 459 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 460 461 /* Enable magic packet matching and reset WOL status */ 462 rtl821x_write_page(dev, RTL8211F_WOL_SETTINGS_PAGE); 463 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 464 __phy_write(dev, RTL8211F_WOL_SETTINGS_STATUS, RTL8211F_WOL_STATUS_RESET); 465 466 /* Enable the WOL interrupt */ 467 rtl821x_write_page(dev, RTL8211F_INTBCR_PAGE); 468 __phy_set_bits(dev, RTL8211F_INTBCR, RTL8211F_INTBCR_INTB_PMEB); 469 } else { 470 /* Disable the WOL interrupt */ 471 rtl821x_write_page(dev, RTL8211F_INTBCR_PAGE); 472 __phy_clear_bits(dev, RTL8211F_INTBCR, RTL8211F_INTBCR_INTB_PMEB); 473 474 /* Disable magic packet matching and reset WOL status */ 475 rtl821x_write_page(dev, RTL8211F_WOL_SETTINGS_PAGE); 476 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 477 __phy_write(dev, RTL8211F_WOL_SETTINGS_STATUS, RTL8211F_WOL_STATUS_RESET); 478 } 479 480 err: 481 return phy_restore_page(dev, oldpage, 0); 482 } 483 484 static int rtl8211_config_aneg(struct phy_device *phydev) 485 { 486 int ret; 487 488 ret = genphy_config_aneg(phydev); 489 if (ret < 0) 490 return ret; 491 492 /* Quirk was copied from vendor driver. Unfortunately it includes no 493 * description of the magic numbers. 494 */ 495 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 496 phy_write(phydev, 0x17, 0x2138); 497 phy_write(phydev, 0x0e, 0x0260); 498 } else { 499 phy_write(phydev, 0x17, 0x2108); 500 phy_write(phydev, 0x0e, 0x0000); 501 } 502 503 return 0; 504 } 505 506 static int rtl8211c_config_init(struct phy_device *phydev) 507 { 508 /* RTL8211C has an issue when operating in Gigabit slave mode */ 509 return phy_set_bits(phydev, MII_CTRL1000, 510 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 511 } 512 513 static int rtl8211f_config_init(struct phy_device *phydev) 514 { 515 struct rtl821x_priv *priv = phydev->priv; 516 struct device *dev = &phydev->mdio.dev; 517 u16 val_txdly, val_rxdly; 518 int ret; 519 520 ret = phy_modify_paged_changed(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1, 521 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF, 522 priv->phycr1); 523 if (ret < 0) { 524 dev_err(dev, "aldps mode configuration failed: %pe\n", 525 ERR_PTR(ret)); 526 return ret; 527 } 528 529 switch (phydev->interface) { 530 case PHY_INTERFACE_MODE_RGMII: 531 val_txdly = 0; 532 val_rxdly = 0; 533 break; 534 535 case PHY_INTERFACE_MODE_RGMII_RXID: 536 val_txdly = 0; 537 val_rxdly = RTL8211F_RX_DELAY; 538 break; 539 540 case PHY_INTERFACE_MODE_RGMII_TXID: 541 val_txdly = RTL8211F_TX_DELAY; 542 val_rxdly = 0; 543 break; 544 545 case PHY_INTERFACE_MODE_RGMII_ID: 546 val_txdly = RTL8211F_TX_DELAY; 547 val_rxdly = RTL8211F_RX_DELAY; 548 break; 549 550 default: /* the rest of the modes imply leaving delay as is. */ 551 return 0; 552 } 553 554 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 555 RTL8211F_TXCR, RTL8211F_TX_DELAY, 556 val_txdly); 557 if (ret < 0) { 558 dev_err(dev, "Failed to update the TX delay register\n"); 559 return ret; 560 } else if (ret) { 561 dev_dbg(dev, 562 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 563 str_enable_disable(val_txdly)); 564 } else { 565 dev_dbg(dev, 566 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 567 str_enabled_disabled(val_txdly)); 568 } 569 570 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 571 RTL8211F_RXCR, RTL8211F_RX_DELAY, 572 val_rxdly); 573 if (ret < 0) { 574 dev_err(dev, "Failed to update the RX delay register\n"); 575 return ret; 576 } else if (ret) { 577 dev_dbg(dev, 578 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 579 str_enable_disable(val_rxdly)); 580 } else { 581 dev_dbg(dev, 582 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 583 str_enabled_disabled(val_rxdly)); 584 } 585 586 /* Disable PHY-mode EEE so LPI is passed to the MAC */ 587 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2, 588 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 589 if (ret) 590 return ret; 591 592 if (priv->has_phycr2) { 593 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, 594 RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 595 priv->phycr2); 596 if (ret < 0) { 597 dev_err(dev, "clkout configuration failed: %pe\n", 598 ERR_PTR(ret)); 599 return ret; 600 } 601 602 return genphy_soft_reset(phydev); 603 } 604 605 return 0; 606 } 607 608 static int rtl821x_suspend(struct phy_device *phydev) 609 { 610 struct rtl821x_priv *priv = phydev->priv; 611 int ret = 0; 612 613 if (!phydev->wol_enabled) { 614 ret = genphy_suspend(phydev); 615 616 if (ret) 617 return ret; 618 619 clk_disable_unprepare(priv->clk); 620 } 621 622 return ret; 623 } 624 625 static int rtl821x_resume(struct phy_device *phydev) 626 { 627 struct rtl821x_priv *priv = phydev->priv; 628 int ret; 629 630 if (!phydev->wol_enabled) 631 clk_prepare_enable(priv->clk); 632 633 ret = genphy_resume(phydev); 634 if (ret < 0) 635 return ret; 636 637 msleep(20); 638 639 return 0; 640 } 641 642 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 643 unsigned long rules) 644 { 645 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) | 646 BIT(TRIGGER_NETDEV_LINK_100) | 647 BIT(TRIGGER_NETDEV_LINK_1000) | 648 BIT(TRIGGER_NETDEV_RX) | 649 BIT(TRIGGER_NETDEV_TX); 650 651 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 652 * - Link: Configurable subset of 10/100/1000 link rates 653 * - Active: Blink on activity, RX or TX is not differentiated 654 * The Active option has two modes, A and B: 655 * - A: Link and Active indication at configurable, but matching, 656 * subset of 10/100/1000 link rates 657 * - B: Link indication at configurable subset of 10/100/1000 link 658 * rates and Active indication always at all three 10+100+1000 659 * link rates. 660 * This code currently uses mode B only. 661 * 662 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 663 */ 664 665 if (index >= RTL8211x_LED_COUNT) 666 return -EINVAL; 667 668 /* Filter out any other unsupported triggers. */ 669 if (rules & ~mask) 670 return -EOPNOTSUPP; 671 672 /* RX and TX are not differentiated, either both are set or not set. */ 673 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 674 return -EOPNOTSUPP; 675 676 return 0; 677 } 678 679 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 680 unsigned long *rules) 681 { 682 int val; 683 684 if (index >= RTL8211x_LED_COUNT) 685 return -EINVAL; 686 687 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); 688 if (val < 0) 689 return val; 690 691 val >>= RTL8211F_LEDCR_SHIFT * index; 692 val &= RTL8211F_LEDCR_MASK; 693 694 if (val & RTL8211F_LEDCR_LINK_10) 695 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 696 697 if (val & RTL8211F_LEDCR_LINK_100) 698 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 699 700 if (val & RTL8211F_LEDCR_LINK_1000) 701 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 702 703 if (val & RTL8211F_LEDCR_ACT_TXRX) { 704 __set_bit(TRIGGER_NETDEV_RX, rules); 705 __set_bit(TRIGGER_NETDEV_TX, rules); 706 } 707 708 return 0; 709 } 710 711 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 712 unsigned long rules) 713 { 714 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 715 u16 reg = 0; 716 717 if (index >= RTL8211x_LED_COUNT) 718 return -EINVAL; 719 720 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 721 reg |= RTL8211F_LEDCR_LINK_10; 722 723 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 724 reg |= RTL8211F_LEDCR_LINK_100; 725 726 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 727 reg |= RTL8211F_LEDCR_LINK_1000; 728 729 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 730 test_bit(TRIGGER_NETDEV_TX, &rules)) { 731 reg |= RTL8211F_LEDCR_ACT_TXRX; 732 } 733 734 reg <<= RTL8211F_LEDCR_SHIFT * index; 735 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 736 737 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg); 738 } 739 740 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 741 unsigned long *rules) 742 { 743 int ret; 744 u16 cr1, cr2; 745 746 if (index >= RTL8211x_LED_COUNT) 747 return -EINVAL; 748 749 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 750 RTL8211E_LEDCR1); 751 if (ret < 0) 752 return ret; 753 754 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 755 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 756 __set_bit(TRIGGER_NETDEV_RX, rules); 757 __set_bit(TRIGGER_NETDEV_TX, rules); 758 } 759 760 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 761 RTL8211E_LEDCR2); 762 if (ret < 0) 763 return ret; 764 765 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 766 if (cr2 & RTL8211E_LEDCR2_LINK_10) 767 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 768 769 if (cr2 & RTL8211E_LEDCR2_LINK_100) 770 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 771 772 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 773 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 774 775 return ret; 776 } 777 778 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 779 unsigned long rules) 780 { 781 const u16 cr1mask = 782 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 783 const u16 cr2mask = 784 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 785 u16 cr1 = 0, cr2 = 0; 786 int ret; 787 788 if (index >= RTL8211x_LED_COUNT) 789 return -EINVAL; 790 791 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 792 test_bit(TRIGGER_NETDEV_TX, &rules)) { 793 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 794 } 795 796 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 797 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 798 RTL8211E_LEDCR1, cr1mask, cr1); 799 if (ret < 0) 800 return ret; 801 802 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 803 cr2 |= RTL8211E_LEDCR2_LINK_10; 804 805 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 806 cr2 |= RTL8211E_LEDCR2_LINK_100; 807 808 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 809 cr2 |= RTL8211E_LEDCR2_LINK_1000; 810 811 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 812 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 813 RTL8211E_LEDCR2, cr2mask, cr2); 814 815 return ret; 816 } 817 818 static int rtl8211e_config_init(struct phy_device *phydev) 819 { 820 u16 val; 821 822 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 823 switch (phydev->interface) { 824 case PHY_INTERFACE_MODE_RGMII: 825 val = RTL8211E_CTRL_DELAY | 0; 826 break; 827 case PHY_INTERFACE_MODE_RGMII_ID: 828 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 829 break; 830 case PHY_INTERFACE_MODE_RGMII_RXID: 831 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 832 break; 833 case PHY_INTERFACE_MODE_RGMII_TXID: 834 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 835 break; 836 default: /* the rest of the modes imply leaving delays as is. */ 837 return 0; 838 } 839 840 /* According to a sample driver there is a 0x1c config register on the 841 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 842 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 843 * The configuration register definition: 844 * 14 = reserved 845 * 13 = Force Tx RX Delay controlled by bit12 bit11, 846 * 12 = RX Delay, 11 = TX Delay 847 * 10:0 = Test && debug settings reserved by realtek 848 */ 849 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 850 RTL8211E_RGMII_DELAY, 851 RTL8211E_DELAY_MASK, val); 852 } 853 854 static int rtl8211b_suspend(struct phy_device *phydev) 855 { 856 phy_write(phydev, MII_MMD_DATA, BIT(9)); 857 858 return genphy_suspend(phydev); 859 } 860 861 static int rtl8211b_resume(struct phy_device *phydev) 862 { 863 phy_write(phydev, MII_MMD_DATA, 0); 864 865 return genphy_resume(phydev); 866 } 867 868 static int rtl8366rb_config_init(struct phy_device *phydev) 869 { 870 int ret; 871 872 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 873 RTL8366RB_POWER_SAVE_ON); 874 if (ret) { 875 dev_err(&phydev->mdio.dev, 876 "error enabling power management\n"); 877 } 878 879 return ret; 880 } 881 882 /* get actual speed to cover the downshift case */ 883 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 884 { 885 /* bit 3 886 * 0: Half Duplex 887 * 1: Full Duplex 888 */ 889 if (val & RTL_VND2_PHYSR_DUPLEX) 890 phydev->duplex = DUPLEX_FULL; 891 else 892 phydev->duplex = DUPLEX_HALF; 893 894 switch (val & RTL_VND2_PHYSR_SPEED_MASK) { 895 case 0x0000: 896 phydev->speed = SPEED_10; 897 break; 898 case 0x0010: 899 phydev->speed = SPEED_100; 900 break; 901 case 0x0020: 902 phydev->speed = SPEED_1000; 903 break; 904 case 0x0200: 905 phydev->speed = SPEED_10000; 906 break; 907 case 0x0210: 908 phydev->speed = SPEED_2500; 909 break; 910 case 0x0220: 911 phydev->speed = SPEED_5000; 912 break; 913 default: 914 break; 915 } 916 917 /* bit 11 918 * 0: Slave Mode 919 * 1: Master Mode 920 */ 921 if (phydev->speed >= 1000) { 922 if (val & RTL_VND2_PHYSR_MASTER) 923 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 924 else 925 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 926 } else { 927 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 928 } 929 } 930 931 static int rtlgen_read_status(struct phy_device *phydev) 932 { 933 int ret, val; 934 935 ret = genphy_read_status(phydev); 936 if (ret < 0) 937 return ret; 938 939 if (!phydev->link) 940 return 0; 941 942 val = phy_read_paged(phydev, 0xa43, 0x12); 943 if (val < 0) 944 return val; 945 946 rtlgen_decode_physr(phydev, val); 947 948 return 0; 949 } 950 951 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 952 { 953 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 954 } 955 956 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 957 { 958 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 959 val); 960 } 961 962 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 963 { 964 int ret; 965 966 if (devnum == MDIO_MMD_VEND2) 967 ret = rtlgen_read_vend2(phydev, regnum); 968 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 969 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 970 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 971 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 972 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 973 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 974 else 975 ret = -EOPNOTSUPP; 976 977 return ret; 978 } 979 980 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 981 u16 val) 982 { 983 int ret; 984 985 if (devnum == MDIO_MMD_VEND2) 986 ret = rtlgen_write_vend2(phydev, regnum, val); 987 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 988 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 989 else 990 ret = -EOPNOTSUPP; 991 992 return ret; 993 } 994 995 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 996 { 997 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 998 999 if (ret != -EOPNOTSUPP) 1000 return ret; 1001 1002 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1003 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1004 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1005 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1006 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1007 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1008 1009 return ret; 1010 } 1011 1012 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1013 u16 val) 1014 { 1015 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1016 1017 if (ret != -EOPNOTSUPP) 1018 return ret; 1019 1020 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1021 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1022 1023 return ret; 1024 } 1025 1026 static int rtl822x_probe(struct phy_device *phydev) 1027 { 1028 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1029 phydev->phy_id != RTL_GENERIC_PHYID) 1030 return rtl822x_hwmon_init(phydev); 1031 1032 return 0; 1033 } 1034 1035 static int rtl822xb_config_init(struct phy_device *phydev) 1036 { 1037 bool has_2500, has_sgmii; 1038 u16 mode; 1039 int ret; 1040 1041 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 1042 phydev->host_interfaces) || 1043 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 1044 1045 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 1046 phydev->host_interfaces) || 1047 phydev->interface == PHY_INTERFACE_MODE_SGMII; 1048 1049 /* fill in possible interfaces */ 1050 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 1051 has_2500); 1052 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 1053 has_sgmii); 1054 1055 if (!has_2500 && !has_sgmii) 1056 return 0; 1057 1058 /* determine SerDes option mode */ 1059 if (has_2500 && !has_sgmii) { 1060 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 1061 phydev->rate_matching = RATE_MATCH_PAUSE; 1062 } else { 1063 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 1064 phydev->rate_matching = RATE_MATCH_NONE; 1065 } 1066 1067 /* the following sequence with magic numbers sets up the SerDes 1068 * option mode 1069 */ 1070 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 1071 if (ret < 0) 1072 return ret; 1073 1074 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 1075 RTL822X_VND1_SERDES_OPTION, 1076 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 1077 mode); 1078 if (ret < 0) 1079 return ret; 1080 1081 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 1082 if (ret < 0) 1083 return ret; 1084 1085 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 1086 if (ret < 0) 1087 return ret; 1088 1089 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 1090 } 1091 1092 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 1093 phy_interface_t iface) 1094 { 1095 int val; 1096 1097 /* Only rate matching at 2500base-x */ 1098 if (iface != PHY_INTERFACE_MODE_2500BASEX) 1099 return RATE_MATCH_NONE; 1100 1101 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 1102 if (val < 0) 1103 return val; 1104 1105 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 1106 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 1107 return RATE_MATCH_PAUSE; 1108 1109 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 1110 return RATE_MATCH_NONE; 1111 } 1112 1113 static int rtl822x_get_features(struct phy_device *phydev) 1114 { 1115 int val; 1116 1117 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 1118 if (val < 0) 1119 return val; 1120 1121 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1122 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 1123 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1124 phydev->supported, val & MDIO_PMA_SPEED_5G); 1125 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1126 phydev->supported, val & MDIO_SPEED_10G); 1127 1128 return genphy_read_abilities(phydev); 1129 } 1130 1131 static int rtl822x_config_aneg(struct phy_device *phydev) 1132 { 1133 int ret = 0; 1134 1135 if (phydev->autoneg == AUTONEG_ENABLE) { 1136 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1137 1138 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1139 RTL_MDIO_AN_10GBT_CTRL, 1140 MDIO_AN_10GBT_CTRL_ADV2_5G | 1141 MDIO_AN_10GBT_CTRL_ADV5G, adv); 1142 if (ret < 0) 1143 return ret; 1144 } 1145 1146 return __genphy_config_aneg(phydev, ret); 1147 } 1148 1149 static void rtl822xb_update_interface(struct phy_device *phydev) 1150 { 1151 int val; 1152 1153 if (!phydev->link) 1154 return; 1155 1156 /* Change interface according to serdes mode */ 1157 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 1158 if (val < 0) 1159 return; 1160 1161 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 1162 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 1163 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1164 break; 1165 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 1166 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1167 break; 1168 } 1169 } 1170 1171 static int rtl822x_read_status(struct phy_device *phydev) 1172 { 1173 int lpadv, ret; 1174 1175 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1176 1177 ret = rtlgen_read_status(phydev); 1178 if (ret < 0) 1179 return ret; 1180 1181 if (phydev->autoneg == AUTONEG_DISABLE || 1182 !phydev->autoneg_complete) 1183 return 0; 1184 1185 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 1186 if (lpadv < 0) 1187 return lpadv; 1188 1189 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 1190 1191 return 0; 1192 } 1193 1194 static int rtl822xb_read_status(struct phy_device *phydev) 1195 { 1196 int ret; 1197 1198 ret = rtl822x_read_status(phydev); 1199 if (ret < 0) 1200 return ret; 1201 1202 rtl822xb_update_interface(phydev); 1203 1204 return 0; 1205 } 1206 1207 static int rtl822x_c45_get_features(struct phy_device *phydev) 1208 { 1209 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1210 phydev->supported); 1211 1212 return genphy_c45_pma_read_abilities(phydev); 1213 } 1214 1215 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1216 { 1217 bool changed = false; 1218 int ret, val; 1219 1220 if (phydev->autoneg == AUTONEG_DISABLE) 1221 return genphy_c45_pma_setup_forced(phydev); 1222 1223 ret = genphy_c45_an_config_aneg(phydev); 1224 if (ret < 0) 1225 return ret; 1226 if (ret > 0) 1227 changed = true; 1228 1229 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1230 1231 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1232 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1233 RTL822X_VND2_C22_REG(MII_CTRL1000), 1234 ADVERTISE_1000FULL, val); 1235 if (ret < 0) 1236 return ret; 1237 if (ret > 0) 1238 changed = true; 1239 1240 return genphy_c45_check_and_restart_aneg(phydev, changed); 1241 } 1242 1243 static int rtl822x_c45_read_status(struct phy_device *phydev) 1244 { 1245 int ret, val; 1246 1247 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1248 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1249 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1250 RTL822X_VND2_C22_REG(MII_STAT1000)); 1251 if (val < 0) 1252 return val; 1253 } else { 1254 val = 0; 1255 } 1256 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1257 1258 ret = genphy_c45_read_status(phydev); 1259 if (ret < 0) 1260 return ret; 1261 1262 if (!phydev->link) { 1263 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1264 return 0; 1265 } 1266 1267 /* Read actual speed from vendor register. */ 1268 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR); 1269 if (val < 0) 1270 return val; 1271 1272 rtlgen_decode_physr(phydev, val); 1273 1274 return 0; 1275 } 1276 1277 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1278 { 1279 int ret; 1280 1281 ret = rtl822x_c45_read_status(phydev); 1282 if (ret < 0) 1283 return ret; 1284 1285 rtl822xb_update_interface(phydev); 1286 1287 return 0; 1288 } 1289 1290 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 1291 { 1292 int val; 1293 1294 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 1295 val = phy_read(phydev, 0x13); 1296 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 1297 1298 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 1299 } 1300 1301 /* On internal PHY's MMD reads over C22 always return 0. 1302 * Check a MMD register which is known to be non-zero. 1303 */ 1304 static bool rtlgen_supports_mmd(struct phy_device *phydev) 1305 { 1306 int val; 1307 1308 phy_lock_mdio_bus(phydev); 1309 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 1310 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 1311 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 1312 val = __phy_read(phydev, MII_MMD_DATA); 1313 phy_unlock_mdio_bus(phydev); 1314 1315 return val > 0; 1316 } 1317 1318 static int rtlgen_match_phy_device(struct phy_device *phydev, 1319 const struct phy_driver *phydrv) 1320 { 1321 return phydev->phy_id == RTL_GENERIC_PHYID && 1322 !rtlgen_supports_2_5gbps(phydev); 1323 } 1324 1325 static int rtl8226_match_phy_device(struct phy_device *phydev, 1326 const struct phy_driver *phydrv) 1327 { 1328 return phydev->phy_id == RTL_GENERIC_PHYID && 1329 rtlgen_supports_2_5gbps(phydev) && 1330 rtlgen_supports_mmd(phydev); 1331 } 1332 1333 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 1334 bool is_c45) 1335 { 1336 if (phydev->is_c45) 1337 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 1338 else 1339 return !is_c45 && (id == phydev->phy_id); 1340 } 1341 1342 static int rtl8221b_match_phy_device(struct phy_device *phydev, 1343 const struct phy_driver *phydrv) 1344 { 1345 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 1346 } 1347 1348 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev, 1349 const struct phy_driver *phydrv) 1350 { 1351 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 1352 } 1353 1354 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev, 1355 const struct phy_driver *phydrv) 1356 { 1357 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true); 1358 } 1359 1360 static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev, 1361 const struct phy_driver *phydrv) 1362 { 1363 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false); 1364 } 1365 1366 static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev, 1367 const struct phy_driver *phydrv) 1368 { 1369 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true); 1370 } 1371 1372 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, 1373 const struct phy_driver *phydrv) 1374 { 1375 if (phydev->is_c45) 1376 return false; 1377 1378 switch (phydev->phy_id) { 1379 case RTL_GENERIC_PHYID: 1380 case RTL_8221B: 1381 case RTL_8251B: 1382 case RTL_8261C: 1383 case 0x001cc841: 1384 break; 1385 default: 1386 return false; 1387 } 1388 1389 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 1390 } 1391 1392 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, 1393 const struct phy_driver *phydrv) 1394 { 1395 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 1396 } 1397 1398 static int rtlgen_resume(struct phy_device *phydev) 1399 { 1400 int ret = genphy_resume(phydev); 1401 1402 /* Internal PHY's from RTL8168h up may not be instantly ready */ 1403 msleep(20); 1404 1405 return ret; 1406 } 1407 1408 static int rtlgen_c45_resume(struct phy_device *phydev) 1409 { 1410 int ret = genphy_c45_pma_resume(phydev); 1411 1412 msleep(20); 1413 1414 return ret; 1415 } 1416 1417 static int rtl9000a_config_init(struct phy_device *phydev) 1418 { 1419 phydev->autoneg = AUTONEG_DISABLE; 1420 phydev->speed = SPEED_100; 1421 phydev->duplex = DUPLEX_FULL; 1422 1423 return 0; 1424 } 1425 1426 static int rtl9000a_config_aneg(struct phy_device *phydev) 1427 { 1428 int ret; 1429 u16 ctl = 0; 1430 1431 switch (phydev->master_slave_set) { 1432 case MASTER_SLAVE_CFG_MASTER_FORCE: 1433 ctl |= CTL1000_AS_MASTER; 1434 break; 1435 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1436 break; 1437 case MASTER_SLAVE_CFG_UNKNOWN: 1438 case MASTER_SLAVE_CFG_UNSUPPORTED: 1439 return 0; 1440 default: 1441 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1442 return -EOPNOTSUPP; 1443 } 1444 1445 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 1446 if (ret == 1) 1447 ret = genphy_soft_reset(phydev); 1448 1449 return ret; 1450 } 1451 1452 static int rtl9000a_read_status(struct phy_device *phydev) 1453 { 1454 int ret; 1455 1456 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1457 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1458 1459 ret = genphy_update_link(phydev); 1460 if (ret) 1461 return ret; 1462 1463 ret = phy_read(phydev, MII_CTRL1000); 1464 if (ret < 0) 1465 return ret; 1466 if (ret & CTL1000_AS_MASTER) 1467 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1468 else 1469 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1470 1471 ret = phy_read(phydev, MII_STAT1000); 1472 if (ret < 0) 1473 return ret; 1474 if (ret & LPA_1000MSRES) 1475 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1476 else 1477 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1478 1479 return 0; 1480 } 1481 1482 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 1483 { 1484 int err; 1485 1486 err = phy_read(phydev, RTL8211F_INSR); 1487 1488 return (err < 0) ? err : 0; 1489 } 1490 1491 static int rtl9000a_config_intr(struct phy_device *phydev) 1492 { 1493 u16 val; 1494 int err; 1495 1496 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1497 err = rtl9000a_ack_interrupt(phydev); 1498 if (err) 1499 return err; 1500 1501 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 1502 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1503 } else { 1504 val = ~0; 1505 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1506 if (err) 1507 return err; 1508 1509 err = rtl9000a_ack_interrupt(phydev); 1510 } 1511 1512 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1513 } 1514 1515 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 1516 { 1517 int irq_status; 1518 1519 irq_status = phy_read(phydev, RTL8211F_INSR); 1520 if (irq_status < 0) { 1521 phy_error(phydev); 1522 return IRQ_NONE; 1523 } 1524 1525 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 1526 return IRQ_NONE; 1527 1528 phy_trigger_machine(phydev); 1529 1530 return IRQ_HANDLED; 1531 } 1532 1533 static struct phy_driver realtek_drvs[] = { 1534 { 1535 PHY_ID_MATCH_EXACT(0x00008201), 1536 .name = "RTL8201CP Ethernet", 1537 .read_page = rtl821x_read_page, 1538 .write_page = rtl821x_write_page, 1539 }, { 1540 PHY_ID_MATCH_EXACT(0x001cc816), 1541 .name = "RTL8201F Fast Ethernet", 1542 .config_intr = &rtl8201_config_intr, 1543 .handle_interrupt = rtl8201_handle_interrupt, 1544 .suspend = genphy_suspend, 1545 .resume = genphy_resume, 1546 .read_page = rtl821x_read_page, 1547 .write_page = rtl821x_write_page, 1548 }, { 1549 PHY_ID_MATCH_MODEL(0x001cc880), 1550 .name = "RTL8208 Fast Ethernet", 1551 .read_mmd = genphy_read_mmd_unsupported, 1552 .write_mmd = genphy_write_mmd_unsupported, 1553 .suspend = genphy_suspend, 1554 .resume = genphy_resume, 1555 .read_page = rtl821x_read_page, 1556 .write_page = rtl821x_write_page, 1557 }, { 1558 PHY_ID_MATCH_EXACT(0x001cc910), 1559 .name = "RTL8211 Gigabit Ethernet", 1560 .config_aneg = rtl8211_config_aneg, 1561 .read_mmd = &genphy_read_mmd_unsupported, 1562 .write_mmd = &genphy_write_mmd_unsupported, 1563 .read_page = rtl821x_read_page, 1564 .write_page = rtl821x_write_page, 1565 }, { 1566 PHY_ID_MATCH_EXACT(0x001cc912), 1567 .name = "RTL8211B Gigabit Ethernet", 1568 .config_intr = &rtl8211b_config_intr, 1569 .handle_interrupt = rtl821x_handle_interrupt, 1570 .read_mmd = &genphy_read_mmd_unsupported, 1571 .write_mmd = &genphy_write_mmd_unsupported, 1572 .suspend = rtl8211b_suspend, 1573 .resume = rtl8211b_resume, 1574 .read_page = rtl821x_read_page, 1575 .write_page = rtl821x_write_page, 1576 }, { 1577 PHY_ID_MATCH_EXACT(0x001cc913), 1578 .name = "RTL8211C Gigabit Ethernet", 1579 .config_init = rtl8211c_config_init, 1580 .read_mmd = &genphy_read_mmd_unsupported, 1581 .write_mmd = &genphy_write_mmd_unsupported, 1582 .read_page = rtl821x_read_page, 1583 .write_page = rtl821x_write_page, 1584 }, { 1585 PHY_ID_MATCH_EXACT(0x001cc914), 1586 .name = "RTL8211DN Gigabit Ethernet", 1587 .config_intr = rtl8211e_config_intr, 1588 .handle_interrupt = rtl821x_handle_interrupt, 1589 .suspend = genphy_suspend, 1590 .resume = genphy_resume, 1591 .read_page = rtl821x_read_page, 1592 .write_page = rtl821x_write_page, 1593 }, { 1594 PHY_ID_MATCH_EXACT(0x001cc915), 1595 .name = "RTL8211E Gigabit Ethernet", 1596 .config_init = &rtl8211e_config_init, 1597 .config_intr = &rtl8211e_config_intr, 1598 .handle_interrupt = rtl821x_handle_interrupt, 1599 .suspend = genphy_suspend, 1600 .resume = genphy_resume, 1601 .read_page = rtl821x_read_page, 1602 .write_page = rtl821x_write_page, 1603 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 1604 .led_hw_control_get = rtl8211e_led_hw_control_get, 1605 .led_hw_control_set = rtl8211e_led_hw_control_set, 1606 }, { 1607 PHY_ID_MATCH_EXACT(0x001cc916), 1608 .name = "RTL8211F Gigabit Ethernet", 1609 .probe = rtl821x_probe, 1610 .config_init = &rtl8211f_config_init, 1611 .read_status = rtlgen_read_status, 1612 .config_intr = &rtl8211f_config_intr, 1613 .handle_interrupt = rtl8211f_handle_interrupt, 1614 .set_wol = rtl8211f_set_wol, 1615 .get_wol = rtl8211f_get_wol, 1616 .suspend = rtl821x_suspend, 1617 .resume = rtl821x_resume, 1618 .read_page = rtl821x_read_page, 1619 .write_page = rtl821x_write_page, 1620 .flags = PHY_ALWAYS_CALL_SUSPEND, 1621 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 1622 .led_hw_control_get = rtl8211f_led_hw_control_get, 1623 .led_hw_control_set = rtl8211f_led_hw_control_set, 1624 }, { 1625 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 1626 .name = "RTL8211F-VD Gigabit Ethernet", 1627 .probe = rtl821x_probe, 1628 .config_init = &rtl8211f_config_init, 1629 .read_status = rtlgen_read_status, 1630 .config_intr = &rtl8211f_config_intr, 1631 .handle_interrupt = rtl8211f_handle_interrupt, 1632 .suspend = rtl821x_suspend, 1633 .resume = rtl821x_resume, 1634 .read_page = rtl821x_read_page, 1635 .write_page = rtl821x_write_page, 1636 .flags = PHY_ALWAYS_CALL_SUSPEND, 1637 }, { 1638 .name = "Generic FE-GE Realtek PHY", 1639 .match_phy_device = rtlgen_match_phy_device, 1640 .read_status = rtlgen_read_status, 1641 .suspend = genphy_suspend, 1642 .resume = rtlgen_resume, 1643 .read_page = rtl821x_read_page, 1644 .write_page = rtl821x_write_page, 1645 .read_mmd = rtlgen_read_mmd, 1646 .write_mmd = rtlgen_write_mmd, 1647 }, { 1648 .name = "RTL8226 2.5Gbps PHY", 1649 .match_phy_device = rtl8226_match_phy_device, 1650 .get_features = rtl822x_get_features, 1651 .config_aneg = rtl822x_config_aneg, 1652 .read_status = rtl822x_read_status, 1653 .suspend = genphy_suspend, 1654 .resume = rtlgen_resume, 1655 .read_page = rtl821x_read_page, 1656 .write_page = rtl821x_write_page, 1657 }, { 1658 .match_phy_device = rtl8221b_match_phy_device, 1659 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 1660 .get_features = rtl822x_get_features, 1661 .config_aneg = rtl822x_config_aneg, 1662 .config_init = rtl822xb_config_init, 1663 .get_rate_matching = rtl822xb_get_rate_matching, 1664 .read_status = rtl822xb_read_status, 1665 .suspend = genphy_suspend, 1666 .resume = rtlgen_resume, 1667 .read_page = rtl821x_read_page, 1668 .write_page = rtl821x_write_page, 1669 }, { 1670 PHY_ID_MATCH_EXACT(0x001cc838), 1671 .name = "RTL8226-CG 2.5Gbps PHY", 1672 .get_features = rtl822x_get_features, 1673 .config_aneg = rtl822x_config_aneg, 1674 .read_status = rtl822x_read_status, 1675 .suspend = genphy_suspend, 1676 .resume = rtlgen_resume, 1677 .read_page = rtl821x_read_page, 1678 .write_page = rtl821x_write_page, 1679 }, { 1680 PHY_ID_MATCH_EXACT(0x001cc848), 1681 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 1682 .get_features = rtl822x_get_features, 1683 .config_aneg = rtl822x_config_aneg, 1684 .config_init = rtl822xb_config_init, 1685 .get_rate_matching = rtl822xb_get_rate_matching, 1686 .read_status = rtl822xb_read_status, 1687 .suspend = genphy_suspend, 1688 .resume = rtlgen_resume, 1689 .read_page = rtl821x_read_page, 1690 .write_page = rtl821x_write_page, 1691 }, { 1692 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, 1693 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", 1694 .probe = rtl822x_probe, 1695 .get_features = rtl822x_get_features, 1696 .config_aneg = rtl822x_config_aneg, 1697 .config_init = rtl822xb_config_init, 1698 .get_rate_matching = rtl822xb_get_rate_matching, 1699 .read_status = rtl822xb_read_status, 1700 .suspend = genphy_suspend, 1701 .resume = rtlgen_resume, 1702 .read_page = rtl821x_read_page, 1703 .write_page = rtl821x_write_page, 1704 }, { 1705 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, 1706 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", 1707 .probe = rtl822x_probe, 1708 .config_init = rtl822xb_config_init, 1709 .get_rate_matching = rtl822xb_get_rate_matching, 1710 .get_features = rtl822x_c45_get_features, 1711 .config_aneg = rtl822x_c45_config_aneg, 1712 .read_status = rtl822xb_c45_read_status, 1713 .suspend = genphy_c45_pma_suspend, 1714 .resume = rtlgen_c45_resume, 1715 }, { 1716 .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device, 1717 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", 1718 .probe = rtl822x_probe, 1719 .get_features = rtl822x_get_features, 1720 .config_aneg = rtl822x_config_aneg, 1721 .config_init = rtl822xb_config_init, 1722 .get_rate_matching = rtl822xb_get_rate_matching, 1723 .read_status = rtl822xb_read_status, 1724 .suspend = genphy_suspend, 1725 .resume = rtlgen_resume, 1726 .read_page = rtl821x_read_page, 1727 .write_page = rtl821x_write_page, 1728 }, { 1729 .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device, 1730 .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)", 1731 .probe = rtl822x_probe, 1732 .config_init = rtl822xb_config_init, 1733 .get_rate_matching = rtl822xb_get_rate_matching, 1734 .get_features = rtl822x_c45_get_features, 1735 .config_aneg = rtl822x_c45_config_aneg, 1736 .read_status = rtl822xb_c45_read_status, 1737 .suspend = genphy_c45_pma_suspend, 1738 .resume = rtlgen_c45_resume, 1739 }, { 1740 .match_phy_device = rtl8251b_c45_match_phy_device, 1741 .name = "RTL8251B 5Gbps PHY", 1742 .probe = rtl822x_probe, 1743 .get_features = rtl822x_get_features, 1744 .config_aneg = rtl822x_config_aneg, 1745 .read_status = rtl822x_read_status, 1746 .suspend = genphy_suspend, 1747 .resume = rtlgen_resume, 1748 .read_page = rtl821x_read_page, 1749 .write_page = rtl821x_write_page, 1750 }, { 1751 .match_phy_device = rtl_internal_nbaset_match_phy_device, 1752 .name = "Realtek Internal NBASE-T PHY", 1753 .flags = PHY_IS_INTERNAL, 1754 .probe = rtl822x_probe, 1755 .get_features = rtl822x_get_features, 1756 .config_aneg = rtl822x_config_aneg, 1757 .read_status = rtl822x_read_status, 1758 .suspend = genphy_suspend, 1759 .resume = rtlgen_resume, 1760 .read_page = rtl821x_read_page, 1761 .write_page = rtl821x_write_page, 1762 .read_mmd = rtl822x_read_mmd, 1763 .write_mmd = rtl822x_write_mmd, 1764 }, { 1765 PHY_ID_MATCH_EXACT(0x001ccad0), 1766 .name = "RTL8224 2.5Gbps PHY", 1767 .get_features = rtl822x_c45_get_features, 1768 .config_aneg = rtl822x_c45_config_aneg, 1769 .read_status = rtl822x_c45_read_status, 1770 .suspend = genphy_c45_pma_suspend, 1771 .resume = rtlgen_c45_resume, 1772 }, { 1773 PHY_ID_MATCH_EXACT(0x001cc961), 1774 .name = "RTL8366RB Gigabit Ethernet", 1775 .config_init = &rtl8366rb_config_init, 1776 /* These interrupts are handled by the irq controller 1777 * embedded inside the RTL8366RB, they get unmasked when the 1778 * irq is requested and ACKed by reading the status register, 1779 * which is done by the irqchip code. 1780 */ 1781 .config_intr = genphy_no_config_intr, 1782 .handle_interrupt = genphy_handle_interrupt_no_ack, 1783 .suspend = genphy_suspend, 1784 .resume = genphy_resume, 1785 }, { 1786 PHY_ID_MATCH_EXACT(0x001ccb00), 1787 .name = "RTL9000AA_RTL9000AN Ethernet", 1788 .features = PHY_BASIC_T1_FEATURES, 1789 .config_init = rtl9000a_config_init, 1790 .config_aneg = rtl9000a_config_aneg, 1791 .read_status = rtl9000a_read_status, 1792 .config_intr = rtl9000a_config_intr, 1793 .handle_interrupt = rtl9000a_handle_interrupt, 1794 .suspend = genphy_suspend, 1795 .resume = genphy_resume, 1796 .read_page = rtl821x_read_page, 1797 .write_page = rtl821x_write_page, 1798 }, { 1799 PHY_ID_MATCH_EXACT(0x001cc942), 1800 .name = "RTL8365MB-VC Gigabit Ethernet", 1801 /* Interrupt handling analogous to RTL8366RB */ 1802 .config_intr = genphy_no_config_intr, 1803 .handle_interrupt = genphy_handle_interrupt_no_ack, 1804 .suspend = genphy_suspend, 1805 .resume = genphy_resume, 1806 }, { 1807 PHY_ID_MATCH_EXACT(0x001cc960), 1808 .name = "RTL8366S Gigabit Ethernet", 1809 .suspend = genphy_suspend, 1810 .resume = genphy_resume, 1811 .read_mmd = genphy_read_mmd_unsupported, 1812 .write_mmd = genphy_write_mmd_unsupported, 1813 }, 1814 }; 1815 1816 module_phy_driver(realtek_drvs); 1817 1818 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 1819 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 1820 { } 1821 }; 1822 1823 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 1824