1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Core PHY library, taken from phy.c 4 */ 5 #include <linux/export.h> 6 #include <linux/phy.h> 7 #include <linux/of.h> 8 9 /** 10 * phy_speed_to_str - Return a string representing the PHY link speed 11 * 12 * @speed: Speed of the link 13 */ 14 const char *phy_speed_to_str(int speed) 15 { 16 BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 121, 17 "Enum ethtool_link_mode_bit_indices and phylib are out of sync. " 18 "If a speed or mode has been added please update phy_speed_to_str " 19 "and the PHY settings array.\n"); 20 21 switch (speed) { 22 case SPEED_10: 23 return "10Mbps"; 24 case SPEED_100: 25 return "100Mbps"; 26 case SPEED_1000: 27 return "1Gbps"; 28 case SPEED_2500: 29 return "2.5Gbps"; 30 case SPEED_5000: 31 return "5Gbps"; 32 case SPEED_10000: 33 return "10Gbps"; 34 case SPEED_14000: 35 return "14Gbps"; 36 case SPEED_20000: 37 return "20Gbps"; 38 case SPEED_25000: 39 return "25Gbps"; 40 case SPEED_40000: 41 return "40Gbps"; 42 case SPEED_50000: 43 return "50Gbps"; 44 case SPEED_56000: 45 return "56Gbps"; 46 case SPEED_100000: 47 return "100Gbps"; 48 case SPEED_200000: 49 return "200Gbps"; 50 case SPEED_400000: 51 return "400Gbps"; 52 case SPEED_800000: 53 return "800Gbps"; 54 case SPEED_UNKNOWN: 55 return "Unknown"; 56 default: 57 return "Unsupported (update phy-core.c)"; 58 } 59 } 60 EXPORT_SYMBOL_GPL(phy_speed_to_str); 61 62 /** 63 * phy_duplex_to_str - Return string describing the duplex 64 * 65 * @duplex: Duplex setting to describe 66 */ 67 const char *phy_duplex_to_str(unsigned int duplex) 68 { 69 if (duplex == DUPLEX_HALF) 70 return "Half"; 71 if (duplex == DUPLEX_FULL) 72 return "Full"; 73 if (duplex == DUPLEX_UNKNOWN) 74 return "Unknown"; 75 return "Unsupported (update phy-core.c)"; 76 } 77 EXPORT_SYMBOL_GPL(phy_duplex_to_str); 78 79 /** 80 * phy_rate_matching_to_str - Return a string describing the rate matching 81 * 82 * @rate_matching: Type of rate matching to describe 83 */ 84 const char *phy_rate_matching_to_str(int rate_matching) 85 { 86 switch (rate_matching) { 87 case RATE_MATCH_NONE: 88 return "none"; 89 case RATE_MATCH_PAUSE: 90 return "pause"; 91 case RATE_MATCH_CRS: 92 return "crs"; 93 case RATE_MATCH_OPEN_LOOP: 94 return "open-loop"; 95 } 96 return "Unsupported (update phy-core.c)"; 97 } 98 EXPORT_SYMBOL_GPL(phy_rate_matching_to_str); 99 100 /** 101 * phy_interface_num_ports - Return the number of links that can be carried by 102 * a given MAC-PHY physical link. Returns 0 if this is 103 * unknown, the number of links else. 104 * 105 * @interface: The interface mode we want to get the number of ports 106 */ 107 int phy_interface_num_ports(phy_interface_t interface) 108 { 109 switch (interface) { 110 case PHY_INTERFACE_MODE_NA: 111 return 0; 112 case PHY_INTERFACE_MODE_INTERNAL: 113 case PHY_INTERFACE_MODE_MII: 114 case PHY_INTERFACE_MODE_GMII: 115 case PHY_INTERFACE_MODE_TBI: 116 case PHY_INTERFACE_MODE_REVMII: 117 case PHY_INTERFACE_MODE_RMII: 118 case PHY_INTERFACE_MODE_REVRMII: 119 case PHY_INTERFACE_MODE_RGMII: 120 case PHY_INTERFACE_MODE_RGMII_ID: 121 case PHY_INTERFACE_MODE_RGMII_RXID: 122 case PHY_INTERFACE_MODE_RGMII_TXID: 123 case PHY_INTERFACE_MODE_RTBI: 124 case PHY_INTERFACE_MODE_XGMII: 125 case PHY_INTERFACE_MODE_XLGMII: 126 case PHY_INTERFACE_MODE_MOCA: 127 case PHY_INTERFACE_MODE_TRGMII: 128 case PHY_INTERFACE_MODE_USXGMII: 129 case PHY_INTERFACE_MODE_SGMII: 130 case PHY_INTERFACE_MODE_SMII: 131 case PHY_INTERFACE_MODE_1000BASEX: 132 case PHY_INTERFACE_MODE_2500BASEX: 133 case PHY_INTERFACE_MODE_5GBASER: 134 case PHY_INTERFACE_MODE_10GBASER: 135 case PHY_INTERFACE_MODE_25GBASER: 136 case PHY_INTERFACE_MODE_10GKR: 137 case PHY_INTERFACE_MODE_100BASEX: 138 case PHY_INTERFACE_MODE_RXAUI: 139 case PHY_INTERFACE_MODE_XAUI: 140 case PHY_INTERFACE_MODE_1000BASEKX: 141 return 1; 142 case PHY_INTERFACE_MODE_QSGMII: 143 case PHY_INTERFACE_MODE_QUSGMII: 144 case PHY_INTERFACE_MODE_10G_QXGMII: 145 return 4; 146 case PHY_INTERFACE_MODE_PSGMII: 147 return 5; 148 case PHY_INTERFACE_MODE_MAX: 149 WARN_ONCE(1, "PHY_INTERFACE_MODE_MAX isn't a valid interface mode"); 150 return 0; 151 } 152 return 0; 153 } 154 EXPORT_SYMBOL_GPL(phy_interface_num_ports); 155 156 /* A mapping of all SUPPORTED settings to speed/duplex. This table 157 * must be grouped by speed and sorted in descending match priority 158 * - iow, descending speed. 159 */ 160 161 #define PHY_SETTING(s, d, b) { .speed = SPEED_ ## s, .duplex = DUPLEX_ ## d, \ 162 .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT} 163 164 static const struct phy_setting settings[] = { 165 /* 800G */ 166 PHY_SETTING( 800000, FULL, 800000baseCR8_Full ), 167 PHY_SETTING( 800000, FULL, 800000baseKR8_Full ), 168 PHY_SETTING( 800000, FULL, 800000baseDR8_Full ), 169 PHY_SETTING( 800000, FULL, 800000baseDR8_2_Full ), 170 PHY_SETTING( 800000, FULL, 800000baseSR8_Full ), 171 PHY_SETTING( 800000, FULL, 800000baseVR8_Full ), 172 PHY_SETTING( 800000, FULL, 800000baseCR4_Full ), 173 PHY_SETTING( 800000, FULL, 800000baseKR4_Full ), 174 PHY_SETTING( 800000, FULL, 800000baseDR4_Full ), 175 PHY_SETTING( 800000, FULL, 800000baseDR4_2_Full ), 176 PHY_SETTING( 800000, FULL, 800000baseSR4_Full ), 177 PHY_SETTING( 800000, FULL, 800000baseVR4_Full ), 178 /* 400G */ 179 PHY_SETTING( 400000, FULL, 400000baseCR8_Full ), 180 PHY_SETTING( 400000, FULL, 400000baseKR8_Full ), 181 PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full ), 182 PHY_SETTING( 400000, FULL, 400000baseDR8_Full ), 183 PHY_SETTING( 400000, FULL, 400000baseSR8_Full ), 184 PHY_SETTING( 400000, FULL, 400000baseCR4_Full ), 185 PHY_SETTING( 400000, FULL, 400000baseKR4_Full ), 186 PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full ), 187 PHY_SETTING( 400000, FULL, 400000baseDR4_Full ), 188 PHY_SETTING( 400000, FULL, 400000baseSR4_Full ), 189 PHY_SETTING( 400000, FULL, 400000baseCR2_Full ), 190 PHY_SETTING( 400000, FULL, 400000baseKR2_Full ), 191 PHY_SETTING( 400000, FULL, 400000baseDR2_Full ), 192 PHY_SETTING( 400000, FULL, 400000baseDR2_2_Full ), 193 PHY_SETTING( 400000, FULL, 400000baseSR2_Full ), 194 PHY_SETTING( 400000, FULL, 400000baseVR2_Full ), 195 /* 200G */ 196 PHY_SETTING( 200000, FULL, 200000baseCR4_Full ), 197 PHY_SETTING( 200000, FULL, 200000baseKR4_Full ), 198 PHY_SETTING( 200000, FULL, 200000baseLR4_ER4_FR4_Full ), 199 PHY_SETTING( 200000, FULL, 200000baseDR4_Full ), 200 PHY_SETTING( 200000, FULL, 200000baseSR4_Full ), 201 PHY_SETTING( 200000, FULL, 200000baseCR2_Full ), 202 PHY_SETTING( 200000, FULL, 200000baseKR2_Full ), 203 PHY_SETTING( 200000, FULL, 200000baseLR2_ER2_FR2_Full ), 204 PHY_SETTING( 200000, FULL, 200000baseDR2_Full ), 205 PHY_SETTING( 200000, FULL, 200000baseSR2_Full ), 206 PHY_SETTING( 200000, FULL, 200000baseCR_Full ), 207 PHY_SETTING( 200000, FULL, 200000baseKR_Full ), 208 PHY_SETTING( 200000, FULL, 200000baseDR_Full ), 209 PHY_SETTING( 200000, FULL, 200000baseDR_2_Full ), 210 PHY_SETTING( 200000, FULL, 200000baseSR_Full ), 211 PHY_SETTING( 200000, FULL, 200000baseVR_Full ), 212 /* 100G */ 213 PHY_SETTING( 100000, FULL, 100000baseCR4_Full ), 214 PHY_SETTING( 100000, FULL, 100000baseKR4_Full ), 215 PHY_SETTING( 100000, FULL, 100000baseLR4_ER4_Full ), 216 PHY_SETTING( 100000, FULL, 100000baseSR4_Full ), 217 PHY_SETTING( 100000, FULL, 100000baseCR2_Full ), 218 PHY_SETTING( 100000, FULL, 100000baseKR2_Full ), 219 PHY_SETTING( 100000, FULL, 100000baseLR2_ER2_FR2_Full ), 220 PHY_SETTING( 100000, FULL, 100000baseDR2_Full ), 221 PHY_SETTING( 100000, FULL, 100000baseSR2_Full ), 222 PHY_SETTING( 100000, FULL, 100000baseCR_Full ), 223 PHY_SETTING( 100000, FULL, 100000baseKR_Full ), 224 PHY_SETTING( 100000, FULL, 100000baseLR_ER_FR_Full ), 225 PHY_SETTING( 100000, FULL, 100000baseDR_Full ), 226 PHY_SETTING( 100000, FULL, 100000baseSR_Full ), 227 /* 56G */ 228 PHY_SETTING( 56000, FULL, 56000baseCR4_Full ), 229 PHY_SETTING( 56000, FULL, 56000baseKR4_Full ), 230 PHY_SETTING( 56000, FULL, 56000baseLR4_Full ), 231 PHY_SETTING( 56000, FULL, 56000baseSR4_Full ), 232 /* 50G */ 233 PHY_SETTING( 50000, FULL, 50000baseCR2_Full ), 234 PHY_SETTING( 50000, FULL, 50000baseKR2_Full ), 235 PHY_SETTING( 50000, FULL, 50000baseSR2_Full ), 236 PHY_SETTING( 50000, FULL, 50000baseCR_Full ), 237 PHY_SETTING( 50000, FULL, 50000baseKR_Full ), 238 PHY_SETTING( 50000, FULL, 50000baseLR_ER_FR_Full ), 239 PHY_SETTING( 50000, FULL, 50000baseDR_Full ), 240 PHY_SETTING( 50000, FULL, 50000baseSR_Full ), 241 /* 40G */ 242 PHY_SETTING( 40000, FULL, 40000baseCR4_Full ), 243 PHY_SETTING( 40000, FULL, 40000baseKR4_Full ), 244 PHY_SETTING( 40000, FULL, 40000baseLR4_Full ), 245 PHY_SETTING( 40000, FULL, 40000baseSR4_Full ), 246 /* 25G */ 247 PHY_SETTING( 25000, FULL, 25000baseCR_Full ), 248 PHY_SETTING( 25000, FULL, 25000baseKR_Full ), 249 PHY_SETTING( 25000, FULL, 25000baseSR_Full ), 250 /* 20G */ 251 PHY_SETTING( 20000, FULL, 20000baseKR2_Full ), 252 PHY_SETTING( 20000, FULL, 20000baseMLD2_Full ), 253 /* 10G */ 254 PHY_SETTING( 10000, FULL, 10000baseCR_Full ), 255 PHY_SETTING( 10000, FULL, 10000baseER_Full ), 256 PHY_SETTING( 10000, FULL, 10000baseKR_Full ), 257 PHY_SETTING( 10000, FULL, 10000baseKX4_Full ), 258 PHY_SETTING( 10000, FULL, 10000baseLR_Full ), 259 PHY_SETTING( 10000, FULL, 10000baseLRM_Full ), 260 PHY_SETTING( 10000, FULL, 10000baseR_FEC ), 261 PHY_SETTING( 10000, FULL, 10000baseSR_Full ), 262 PHY_SETTING( 10000, FULL, 10000baseT_Full ), 263 /* 5G */ 264 PHY_SETTING( 5000, FULL, 5000baseT_Full ), 265 /* 2.5G */ 266 PHY_SETTING( 2500, FULL, 2500baseT_Full ), 267 PHY_SETTING( 2500, FULL, 2500baseX_Full ), 268 /* 1G */ 269 PHY_SETTING( 1000, FULL, 1000baseT_Full ), 270 PHY_SETTING( 1000, HALF, 1000baseT_Half ), 271 PHY_SETTING( 1000, FULL, 1000baseT1_Full ), 272 PHY_SETTING( 1000, FULL, 1000baseX_Full ), 273 PHY_SETTING( 1000, FULL, 1000baseKX_Full ), 274 /* 100M */ 275 PHY_SETTING( 100, FULL, 100baseT_Full ), 276 PHY_SETTING( 100, FULL, 100baseT1_Full ), 277 PHY_SETTING( 100, HALF, 100baseT_Half ), 278 PHY_SETTING( 100, HALF, 100baseFX_Half ), 279 PHY_SETTING( 100, FULL, 100baseFX_Full ), 280 /* 10M */ 281 PHY_SETTING( 10, FULL, 10baseT_Full ), 282 PHY_SETTING( 10, HALF, 10baseT_Half ), 283 PHY_SETTING( 10, FULL, 10baseT1L_Full ), 284 PHY_SETTING( 10, FULL, 10baseT1S_Full ), 285 PHY_SETTING( 10, HALF, 10baseT1S_Half ), 286 PHY_SETTING( 10, HALF, 10baseT1S_P2MP_Half ), 287 PHY_SETTING( 10, FULL, 10baseT1BRR_Full ), 288 }; 289 #undef PHY_SETTING 290 291 /** 292 * phy_lookup_setting - lookup a PHY setting 293 * @speed: speed to match 294 * @duplex: duplex to match 295 * @mask: allowed link modes 296 * @exact: an exact match is required 297 * 298 * Search the settings array for a setting that matches the speed and 299 * duplex, and which is supported. 300 * 301 * If @exact is unset, either an exact match or %NULL for no match will 302 * be returned. 303 * 304 * If @exact is set, an exact match, the fastest supported setting at 305 * or below the specified speed, the slowest supported setting, or if 306 * they all fail, %NULL will be returned. 307 */ 308 const struct phy_setting * 309 phy_lookup_setting(int speed, int duplex, const unsigned long *mask, bool exact) 310 { 311 const struct phy_setting *p, *match = NULL, *last = NULL; 312 int i; 313 314 for (i = 0, p = settings; i < ARRAY_SIZE(settings); i++, p++) { 315 if (p->bit < __ETHTOOL_LINK_MODE_MASK_NBITS && 316 test_bit(p->bit, mask)) { 317 last = p; 318 if (p->speed == speed && p->duplex == duplex) { 319 /* Exact match for speed and duplex */ 320 match = p; 321 break; 322 } else if (!exact) { 323 if (!match && p->speed <= speed) 324 /* Candidate */ 325 match = p; 326 327 if (p->speed < speed) 328 break; 329 } 330 } 331 } 332 333 if (!match && !exact) 334 match = last; 335 336 return match; 337 } 338 EXPORT_SYMBOL_GPL(phy_lookup_setting); 339 340 size_t phy_speeds(unsigned int *speeds, size_t size, 341 unsigned long *mask) 342 { 343 size_t count; 344 int i; 345 346 for (i = 0, count = 0; i < ARRAY_SIZE(settings) && count < size; i++) 347 if (settings[i].bit < __ETHTOOL_LINK_MODE_MASK_NBITS && 348 test_bit(settings[i].bit, mask) && 349 (count == 0 || speeds[count - 1] != settings[i].speed)) 350 speeds[count++] = settings[i].speed; 351 352 return count; 353 } 354 355 static void __set_linkmode_max_speed(u32 max_speed, unsigned long *addr) 356 { 357 const struct phy_setting *p; 358 int i; 359 360 for (i = 0, p = settings; i < ARRAY_SIZE(settings); i++, p++) { 361 if (p->speed > max_speed) 362 linkmode_clear_bit(p->bit, addr); 363 else 364 break; 365 } 366 } 367 368 static void __set_phy_supported(struct phy_device *phydev, u32 max_speed) 369 { 370 __set_linkmode_max_speed(max_speed, phydev->supported); 371 } 372 373 /** 374 * phy_set_max_speed - Set the maximum speed the PHY should support 375 * 376 * @phydev: The phy_device struct 377 * @max_speed: Maximum speed 378 * 379 * The PHY might be more capable than the MAC. For example a Fast Ethernet 380 * is connected to a 1G PHY. This function allows the MAC to indicate its 381 * maximum speed, and so limit what the PHY will advertise. 382 */ 383 void phy_set_max_speed(struct phy_device *phydev, u32 max_speed) 384 { 385 __set_phy_supported(phydev, max_speed); 386 387 phy_advertise_supported(phydev); 388 } 389 EXPORT_SYMBOL(phy_set_max_speed); 390 391 void of_set_phy_supported(struct phy_device *phydev) 392 { 393 struct device_node *node = phydev->mdio.dev.of_node; 394 u32 max_speed; 395 396 if (!IS_ENABLED(CONFIG_OF_MDIO)) 397 return; 398 399 if (!node) 400 return; 401 402 if (!of_property_read_u32(node, "max-speed", &max_speed)) 403 __set_phy_supported(phydev, max_speed); 404 } 405 406 void of_set_phy_eee_broken(struct phy_device *phydev) 407 { 408 struct device_node *node = phydev->mdio.dev.of_node; 409 unsigned long *modes = phydev->eee_disabled_modes; 410 411 if (!IS_ENABLED(CONFIG_OF_MDIO) || !node) 412 return; 413 414 linkmode_zero(modes); 415 416 if (of_property_read_bool(node, "eee-broken-100tx")) 417 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, modes); 418 if (of_property_read_bool(node, "eee-broken-1000t")) 419 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, modes); 420 if (of_property_read_bool(node, "eee-broken-10gt")) 421 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, modes); 422 if (of_property_read_bool(node, "eee-broken-1000kx")) 423 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, modes); 424 if (of_property_read_bool(node, "eee-broken-10gkx4")) 425 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, modes); 426 if (of_property_read_bool(node, "eee-broken-10gkr")) 427 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, modes); 428 } 429 430 /** 431 * of_set_phy_timing_role - Set the master/slave mode of the PHY 432 * 433 * @phydev: The phy_device struct 434 * 435 * Set master/slave configuration of the PHY based on the device tree. 436 */ 437 void of_set_phy_timing_role(struct phy_device *phydev) 438 { 439 struct device_node *node = phydev->mdio.dev.of_node; 440 const char *master; 441 442 if (!IS_ENABLED(CONFIG_OF_MDIO)) 443 return; 444 445 if (!node) 446 return; 447 448 if (of_property_read_string(node, "timing-role", &master)) 449 return; 450 451 if (strcmp(master, "forced-master") == 0) 452 phydev->master_slave_set = MASTER_SLAVE_CFG_MASTER_FORCE; 453 else if (strcmp(master, "forced-slave") == 0) 454 phydev->master_slave_set = MASTER_SLAVE_CFG_SLAVE_FORCE; 455 else if (strcmp(master, "preferred-master") == 0) 456 phydev->master_slave_set = MASTER_SLAVE_CFG_MASTER_PREFERRED; 457 else if (strcmp(master, "preferred-slave") == 0) 458 phydev->master_slave_set = MASTER_SLAVE_CFG_SLAVE_PREFERRED; 459 else 460 phydev_warn(phydev, "Unknown master-slave mode %s\n", master); 461 } 462 463 /** 464 * phy_resolve_aneg_pause - Determine pause autoneg results 465 * 466 * @phydev: The phy_device struct 467 * 468 * Once autoneg has completed the local pause settings can be 469 * resolved. Determine if pause and asymmetric pause should be used 470 * by the MAC. 471 */ 472 473 void phy_resolve_aneg_pause(struct phy_device *phydev) 474 { 475 if (phydev->duplex == DUPLEX_FULL) { 476 phydev->pause = linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, 477 phydev->lp_advertising); 478 phydev->asym_pause = linkmode_test_bit( 479 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 480 phydev->lp_advertising); 481 } 482 } 483 EXPORT_SYMBOL_GPL(phy_resolve_aneg_pause); 484 485 /** 486 * phy_resolve_aneg_linkmode - resolve the advertisements into PHY settings 487 * @phydev: The phy_device struct 488 * 489 * Resolve our and the link partner advertisements into their corresponding 490 * speed and duplex. If full duplex was negotiated, extract the pause mode 491 * from the link partner mask. 492 */ 493 void phy_resolve_aneg_linkmode(struct phy_device *phydev) 494 { 495 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 496 int i; 497 498 linkmode_and(common, phydev->lp_advertising, phydev->advertising); 499 500 for (i = 0; i < ARRAY_SIZE(settings); i++) 501 if (test_bit(settings[i].bit, common)) { 502 phydev->speed = settings[i].speed; 503 phydev->duplex = settings[i].duplex; 504 break; 505 } 506 507 phy_resolve_aneg_pause(phydev); 508 } 509 EXPORT_SYMBOL_GPL(phy_resolve_aneg_linkmode); 510 511 /** 512 * phy_check_downshift - check whether downshift occurred 513 * @phydev: The phy_device struct 514 * 515 * Check whether a downshift to a lower speed occurred. If this should be the 516 * case warn the user. 517 * Prerequisite for detecting downshift is that PHY driver implements the 518 * read_status callback and sets phydev->speed to the actual link speed. 519 */ 520 void phy_check_downshift(struct phy_device *phydev) 521 { 522 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 523 int i, speed = SPEED_UNKNOWN; 524 525 phydev->downshifted_rate = 0; 526 527 if (phydev->autoneg == AUTONEG_DISABLE || 528 phydev->speed == SPEED_UNKNOWN) 529 return; 530 531 linkmode_and(common, phydev->lp_advertising, phydev->advertising); 532 533 for (i = 0; i < ARRAY_SIZE(settings); i++) 534 if (test_bit(settings[i].bit, common)) { 535 speed = settings[i].speed; 536 break; 537 } 538 539 if (speed == SPEED_UNKNOWN || phydev->speed >= speed) 540 return; 541 542 phydev_warn(phydev, "Downshift occurred from negotiated speed %s to actual speed %s, check cabling!\n", 543 phy_speed_to_str(speed), phy_speed_to_str(phydev->speed)); 544 545 phydev->downshifted_rate = 1; 546 } 547 EXPORT_SYMBOL_GPL(phy_check_downshift); 548 549 static int phy_resolve_min_speed(struct phy_device *phydev, bool fdx_only) 550 { 551 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 552 int i = ARRAY_SIZE(settings); 553 554 linkmode_and(common, phydev->lp_advertising, phydev->advertising); 555 556 while (--i >= 0) { 557 if (test_bit(settings[i].bit, common)) { 558 if (fdx_only && settings[i].duplex != DUPLEX_FULL) 559 continue; 560 return settings[i].speed; 561 } 562 } 563 564 return SPEED_UNKNOWN; 565 } 566 567 int phy_speed_down_core(struct phy_device *phydev) 568 { 569 int min_common_speed = phy_resolve_min_speed(phydev, true); 570 571 if (min_common_speed == SPEED_UNKNOWN) 572 return -EINVAL; 573 574 __set_linkmode_max_speed(min_common_speed, phydev->advertising); 575 576 return 0; 577 } 578 579 static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad, 580 u16 regnum) 581 { 582 /* Write the desired MMD Devad */ 583 __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devad); 584 585 /* Write the desired MMD register address */ 586 __mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum); 587 588 /* Select the Function : DATA with no post increment */ 589 __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, 590 devad | MII_MMD_CTRL_NOINCR); 591 } 592 593 static int mmd_phy_read(struct mii_bus *bus, int phy_addr, bool is_c45, 594 int devad, u32 regnum) 595 { 596 if (is_c45) 597 return __mdiobus_c45_read(bus, phy_addr, devad, regnum); 598 599 mmd_phy_indirect(bus, phy_addr, devad, regnum); 600 /* Read the content of the MMD's selected register */ 601 return __mdiobus_read(bus, phy_addr, MII_MMD_DATA); 602 } 603 604 static int mmd_phy_write(struct mii_bus *bus, int phy_addr, bool is_c45, 605 int devad, u32 regnum, u16 val) 606 { 607 if (is_c45) 608 return __mdiobus_c45_write(bus, phy_addr, devad, regnum, val); 609 610 mmd_phy_indirect(bus, phy_addr, devad, regnum); 611 /* Write the data into MMD's selected register */ 612 return __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val); 613 } 614 615 /** 616 * __phy_read_mmd - Convenience function for reading a register 617 * from an MMD on a given PHY. 618 * @phydev: The phy_device struct 619 * @devad: The MMD to read from (0..31) 620 * @regnum: The register on the MMD to read (0..65535) 621 * 622 * Same rules as for __phy_read(); 623 */ 624 int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum) 625 { 626 if (regnum > (u16)~0 || devad > 32) 627 return -EINVAL; 628 629 if (phydev->drv && phydev->drv->read_mmd) 630 return phydev->drv->read_mmd(phydev, devad, regnum); 631 632 return mmd_phy_read(phydev->mdio.bus, phydev->mdio.addr, 633 phydev->is_c45, devad, regnum); 634 } 635 EXPORT_SYMBOL(__phy_read_mmd); 636 637 /** 638 * phy_read_mmd - Convenience function for reading a register 639 * from an MMD on a given PHY. 640 * @phydev: The phy_device struct 641 * @devad: The MMD to read from 642 * @regnum: The register on the MMD to read 643 * 644 * Same rules as for phy_read(); 645 */ 646 int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum) 647 { 648 int ret; 649 650 phy_lock_mdio_bus(phydev); 651 ret = __phy_read_mmd(phydev, devad, regnum); 652 phy_unlock_mdio_bus(phydev); 653 654 return ret; 655 } 656 EXPORT_SYMBOL(phy_read_mmd); 657 658 /** 659 * __phy_write_mmd - Convenience function for writing a register 660 * on an MMD on a given PHY. 661 * @phydev: The phy_device struct 662 * @devad: The MMD to read from 663 * @regnum: The register on the MMD to read 664 * @val: value to write to @regnum 665 * 666 * Same rules as for __phy_write(); 667 */ 668 int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) 669 { 670 if (regnum > (u16)~0 || devad > 32) 671 return -EINVAL; 672 673 if (phydev->drv && phydev->drv->write_mmd) 674 return phydev->drv->write_mmd(phydev, devad, regnum, val); 675 676 return mmd_phy_write(phydev->mdio.bus, phydev->mdio.addr, 677 phydev->is_c45, devad, regnum, val); 678 } 679 EXPORT_SYMBOL(__phy_write_mmd); 680 681 /** 682 * phy_write_mmd - Convenience function for writing a register 683 * on an MMD on a given PHY. 684 * @phydev: The phy_device struct 685 * @devad: The MMD to read from 686 * @regnum: The register on the MMD to read 687 * @val: value to write to @regnum 688 * 689 * Same rules as for phy_write(); 690 */ 691 int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) 692 { 693 int ret; 694 695 phy_lock_mdio_bus(phydev); 696 ret = __phy_write_mmd(phydev, devad, regnum, val); 697 phy_unlock_mdio_bus(phydev); 698 699 return ret; 700 } 701 EXPORT_SYMBOL(phy_write_mmd); 702 703 /** 704 * __phy_package_read_mmd - read MMD reg relative to PHY package base addr 705 * @phydev: The phy_device struct 706 * @addr_offset: The offset to be added to PHY package base_addr 707 * @devad: The MMD to read from 708 * @regnum: The register on the MMD to read 709 * 710 * Convenience helper for reading a register of an MMD on a given PHY 711 * using the PHY package base address. The base address is added to 712 * the addr_offset value. 713 * 714 * Same calling rules as for __phy_read(); 715 * 716 * NOTE: It's assumed that the entire PHY package is either C22 or C45. 717 */ 718 int __phy_package_read_mmd(struct phy_device *phydev, 719 unsigned int addr_offset, int devad, 720 u32 regnum) 721 { 722 int addr = phy_package_address(phydev, addr_offset); 723 724 if (addr < 0) 725 return addr; 726 727 if (regnum > (u16)~0 || devad > 32) 728 return -EINVAL; 729 730 return mmd_phy_read(phydev->mdio.bus, addr, phydev->is_c45, devad, 731 regnum); 732 } 733 EXPORT_SYMBOL(__phy_package_read_mmd); 734 735 /** 736 * phy_package_read_mmd - read MMD reg relative to PHY package base addr 737 * @phydev: The phy_device struct 738 * @addr_offset: The offset to be added to PHY package base_addr 739 * @devad: The MMD to read from 740 * @regnum: The register on the MMD to read 741 * 742 * Convenience helper for reading a register of an MMD on a given PHY 743 * using the PHY package base address. The base address is added to 744 * the addr_offset value. 745 * 746 * Same calling rules as for phy_read(); 747 * 748 * NOTE: It's assumed that the entire PHY package is either C22 or C45. 749 */ 750 int phy_package_read_mmd(struct phy_device *phydev, 751 unsigned int addr_offset, int devad, 752 u32 regnum) 753 { 754 int addr = phy_package_address(phydev, addr_offset); 755 int val; 756 757 if (addr < 0) 758 return addr; 759 760 if (regnum > (u16)~0 || devad > 32) 761 return -EINVAL; 762 763 phy_lock_mdio_bus(phydev); 764 val = mmd_phy_read(phydev->mdio.bus, addr, phydev->is_c45, devad, 765 regnum); 766 phy_unlock_mdio_bus(phydev); 767 768 return val; 769 } 770 EXPORT_SYMBOL(phy_package_read_mmd); 771 772 /** 773 * __phy_package_write_mmd - write MMD reg relative to PHY package base addr 774 * @phydev: The phy_device struct 775 * @addr_offset: The offset to be added to PHY package base_addr 776 * @devad: The MMD to write to 777 * @regnum: The register on the MMD to write 778 * @val: value to write to @regnum 779 * 780 * Convenience helper for writing a register of an MMD on a given PHY 781 * using the PHY package base address. The base address is added to 782 * the addr_offset value. 783 * 784 * Same calling rules as for __phy_write(); 785 * 786 * NOTE: It's assumed that the entire PHY package is either C22 or C45. 787 */ 788 int __phy_package_write_mmd(struct phy_device *phydev, 789 unsigned int addr_offset, int devad, 790 u32 regnum, u16 val) 791 { 792 int addr = phy_package_address(phydev, addr_offset); 793 794 if (addr < 0) 795 return addr; 796 797 if (regnum > (u16)~0 || devad > 32) 798 return -EINVAL; 799 800 return mmd_phy_write(phydev->mdio.bus, addr, phydev->is_c45, devad, 801 regnum, val); 802 } 803 EXPORT_SYMBOL(__phy_package_write_mmd); 804 805 /** 806 * phy_package_write_mmd - write MMD reg relative to PHY package base addr 807 * @phydev: The phy_device struct 808 * @addr_offset: The offset to be added to PHY package base_addr 809 * @devad: The MMD to write to 810 * @regnum: The register on the MMD to write 811 * @val: value to write to @regnum 812 * 813 * Convenience helper for writing a register of an MMD on a given PHY 814 * using the PHY package base address. The base address is added to 815 * the addr_offset value. 816 * 817 * Same calling rules as for phy_write(); 818 * 819 * NOTE: It's assumed that the entire PHY package is either C22 or C45. 820 */ 821 int phy_package_write_mmd(struct phy_device *phydev, 822 unsigned int addr_offset, int devad, 823 u32 regnum, u16 val) 824 { 825 int addr = phy_package_address(phydev, addr_offset); 826 int ret; 827 828 if (addr < 0) 829 return addr; 830 831 if (regnum > (u16)~0 || devad > 32) 832 return -EINVAL; 833 834 phy_lock_mdio_bus(phydev); 835 ret = mmd_phy_write(phydev->mdio.bus, addr, phydev->is_c45, devad, 836 regnum, val); 837 phy_unlock_mdio_bus(phydev); 838 839 return ret; 840 } 841 EXPORT_SYMBOL(phy_package_write_mmd); 842 843 /** 844 * phy_modify_changed - Function for modifying a PHY register 845 * @phydev: the phy_device struct 846 * @regnum: register number to modify 847 * @mask: bit mask of bits to clear 848 * @set: new value of bits set in mask to write to @regnum 849 * 850 * NOTE: MUST NOT be called from interrupt context, 851 * because the bus read/write functions may wait for an interrupt 852 * to conclude the operation. 853 * 854 * Returns negative errno, 0 if there was no change, and 1 in case of change 855 */ 856 int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask, u16 set) 857 { 858 int ret; 859 860 phy_lock_mdio_bus(phydev); 861 ret = __phy_modify_changed(phydev, regnum, mask, set); 862 phy_unlock_mdio_bus(phydev); 863 864 return ret; 865 } 866 EXPORT_SYMBOL_GPL(phy_modify_changed); 867 868 /** 869 * __phy_modify - Convenience function for modifying a PHY register 870 * @phydev: the phy_device struct 871 * @regnum: register number to modify 872 * @mask: bit mask of bits to clear 873 * @set: new value of bits set in mask to write to @regnum 874 * 875 * NOTE: MUST NOT be called from interrupt context, 876 * because the bus read/write functions may wait for an interrupt 877 * to conclude the operation. 878 */ 879 int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set) 880 { 881 int ret; 882 883 ret = __phy_modify_changed(phydev, regnum, mask, set); 884 885 return ret < 0 ? ret : 0; 886 } 887 EXPORT_SYMBOL_GPL(__phy_modify); 888 889 /** 890 * phy_modify - Convenience function for modifying a given PHY register 891 * @phydev: the phy_device struct 892 * @regnum: register number to write 893 * @mask: bit mask of bits to clear 894 * @set: new value of bits set in mask to write to @regnum 895 * 896 * NOTE: MUST NOT be called from interrupt context, 897 * because the bus read/write functions may wait for an interrupt 898 * to conclude the operation. 899 */ 900 int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set) 901 { 902 int ret; 903 904 phy_lock_mdio_bus(phydev); 905 ret = __phy_modify(phydev, regnum, mask, set); 906 phy_unlock_mdio_bus(phydev); 907 908 return ret; 909 } 910 EXPORT_SYMBOL_GPL(phy_modify); 911 912 /** 913 * __phy_modify_mmd_changed - Function for modifying a register on MMD 914 * @phydev: the phy_device struct 915 * @devad: the MMD containing register to modify 916 * @regnum: register number to modify 917 * @mask: bit mask of bits to clear 918 * @set: new value of bits set in mask to write to @regnum 919 * 920 * Unlocked helper function which allows a MMD register to be modified as 921 * new register value = (old register value & ~mask) | set 922 * 923 * Returns negative errno, 0 if there was no change, and 1 in case of change 924 */ 925 int __phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum, 926 u16 mask, u16 set) 927 { 928 int new, ret; 929 930 ret = __phy_read_mmd(phydev, devad, regnum); 931 if (ret < 0) 932 return ret; 933 934 new = (ret & ~mask) | set; 935 if (new == ret) 936 return 0; 937 938 ret = __phy_write_mmd(phydev, devad, regnum, new); 939 940 return ret < 0 ? ret : 1; 941 } 942 EXPORT_SYMBOL_GPL(__phy_modify_mmd_changed); 943 944 /** 945 * phy_modify_mmd_changed - Function for modifying a register on MMD 946 * @phydev: the phy_device struct 947 * @devad: the MMD containing register to modify 948 * @regnum: register number to modify 949 * @mask: bit mask of bits to clear 950 * @set: new value of bits set in mask to write to @regnum 951 * 952 * NOTE: MUST NOT be called from interrupt context, 953 * because the bus read/write functions may wait for an interrupt 954 * to conclude the operation. 955 * 956 * Returns negative errno, 0 if there was no change, and 1 in case of change 957 */ 958 int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum, 959 u16 mask, u16 set) 960 { 961 int ret; 962 963 phy_lock_mdio_bus(phydev); 964 ret = __phy_modify_mmd_changed(phydev, devad, regnum, mask, set); 965 phy_unlock_mdio_bus(phydev); 966 967 return ret; 968 } 969 EXPORT_SYMBOL_GPL(phy_modify_mmd_changed); 970 971 /** 972 * __phy_modify_mmd - Convenience function for modifying a register on MMD 973 * @phydev: the phy_device struct 974 * @devad: the MMD containing register to modify 975 * @regnum: register number to modify 976 * @mask: bit mask of bits to clear 977 * @set: new value of bits set in mask to write to @regnum 978 * 979 * NOTE: MUST NOT be called from interrupt context, 980 * because the bus read/write functions may wait for an interrupt 981 * to conclude the operation. 982 */ 983 int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum, 984 u16 mask, u16 set) 985 { 986 int ret; 987 988 ret = __phy_modify_mmd_changed(phydev, devad, regnum, mask, set); 989 990 return ret < 0 ? ret : 0; 991 } 992 EXPORT_SYMBOL_GPL(__phy_modify_mmd); 993 994 /** 995 * phy_modify_mmd - Convenience function for modifying a register on MMD 996 * @phydev: the phy_device struct 997 * @devad: the MMD containing register to modify 998 * @regnum: register number to modify 999 * @mask: bit mask of bits to clear 1000 * @set: new value of bits set in mask to write to @regnum 1001 * 1002 * NOTE: MUST NOT be called from interrupt context, 1003 * because the bus read/write functions may wait for an interrupt 1004 * to conclude the operation. 1005 */ 1006 int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum, 1007 u16 mask, u16 set) 1008 { 1009 int ret; 1010 1011 phy_lock_mdio_bus(phydev); 1012 ret = __phy_modify_mmd(phydev, devad, regnum, mask, set); 1013 phy_unlock_mdio_bus(phydev); 1014 1015 return ret; 1016 } 1017 EXPORT_SYMBOL_GPL(phy_modify_mmd); 1018 1019 static int __phy_read_page(struct phy_device *phydev) 1020 { 1021 if (WARN_ONCE(!phydev->drv->read_page, "read_page callback not available, PHY driver not loaded?\n")) 1022 return -EOPNOTSUPP; 1023 1024 return phydev->drv->read_page(phydev); 1025 } 1026 1027 static int __phy_write_page(struct phy_device *phydev, int page) 1028 { 1029 if (WARN_ONCE(!phydev->drv->write_page, "write_page callback not available, PHY driver not loaded?\n")) 1030 return -EOPNOTSUPP; 1031 1032 return phydev->drv->write_page(phydev, page); 1033 } 1034 1035 /** 1036 * phy_save_page() - take the bus lock and save the current page 1037 * @phydev: a pointer to a &struct phy_device 1038 * 1039 * Take the MDIO bus lock, and return the current page number. On error, 1040 * returns a negative errno. phy_restore_page() must always be called 1041 * after this, irrespective of success or failure of this call. 1042 */ 1043 int phy_save_page(struct phy_device *phydev) 1044 { 1045 phy_lock_mdio_bus(phydev); 1046 return __phy_read_page(phydev); 1047 } 1048 EXPORT_SYMBOL_GPL(phy_save_page); 1049 1050 /** 1051 * phy_select_page() - take the bus lock, save the current page, and set a page 1052 * @phydev: a pointer to a &struct phy_device 1053 * @page: desired page 1054 * 1055 * Take the MDIO bus lock to protect against concurrent access, save the 1056 * current PHY page, and set the current page. On error, returns a 1057 * negative errno, otherwise returns the previous page number. 1058 * phy_restore_page() must always be called after this, irrespective 1059 * of success or failure of this call. 1060 */ 1061 int phy_select_page(struct phy_device *phydev, int page) 1062 { 1063 int ret, oldpage; 1064 1065 oldpage = ret = phy_save_page(phydev); 1066 if (ret < 0) 1067 return ret; 1068 1069 if (oldpage != page) { 1070 ret = __phy_write_page(phydev, page); 1071 if (ret < 0) 1072 return ret; 1073 } 1074 1075 return oldpage; 1076 } 1077 EXPORT_SYMBOL_GPL(phy_select_page); 1078 1079 /** 1080 * phy_restore_page() - restore the page register and release the bus lock 1081 * @phydev: a pointer to a &struct phy_device 1082 * @oldpage: the old page, return value from phy_save_page() or phy_select_page() 1083 * @ret: operation's return code 1084 * 1085 * Release the MDIO bus lock, restoring @oldpage if it is a valid page. 1086 * This function propagates the earliest error code from the group of 1087 * operations. 1088 * 1089 * Returns: 1090 * @oldpage if it was a negative value, otherwise 1091 * @ret if it was a negative errno value, otherwise 1092 * phy_write_page()'s negative value if it were in error, otherwise 1093 * @ret. 1094 */ 1095 int phy_restore_page(struct phy_device *phydev, int oldpage, int ret) 1096 { 1097 int r; 1098 1099 if (oldpage >= 0) { 1100 r = __phy_write_page(phydev, oldpage); 1101 1102 /* Propagate the operation return code if the page write 1103 * was successful. 1104 */ 1105 if (ret >= 0 && r < 0) 1106 ret = r; 1107 } else { 1108 /* Propagate the phy page selection error code */ 1109 ret = oldpage; 1110 } 1111 1112 phy_unlock_mdio_bus(phydev); 1113 1114 return ret; 1115 } 1116 EXPORT_SYMBOL_GPL(phy_restore_page); 1117 1118 /** 1119 * phy_read_paged() - Convenience function for reading a paged register 1120 * @phydev: a pointer to a &struct phy_device 1121 * @page: the page for the phy 1122 * @regnum: register number 1123 * 1124 * Same rules as for phy_read(). 1125 */ 1126 int phy_read_paged(struct phy_device *phydev, int page, u32 regnum) 1127 { 1128 int ret = 0, oldpage; 1129 1130 oldpage = phy_select_page(phydev, page); 1131 if (oldpage >= 0) 1132 ret = __phy_read(phydev, regnum); 1133 1134 return phy_restore_page(phydev, oldpage, ret); 1135 } 1136 EXPORT_SYMBOL(phy_read_paged); 1137 1138 /** 1139 * phy_write_paged() - Convenience function for writing a paged register 1140 * @phydev: a pointer to a &struct phy_device 1141 * @page: the page for the phy 1142 * @regnum: register number 1143 * @val: value to write 1144 * 1145 * Same rules as for phy_write(). 1146 */ 1147 int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val) 1148 { 1149 int ret = 0, oldpage; 1150 1151 oldpage = phy_select_page(phydev, page); 1152 if (oldpage >= 0) 1153 ret = __phy_write(phydev, regnum, val); 1154 1155 return phy_restore_page(phydev, oldpage, ret); 1156 } 1157 EXPORT_SYMBOL(phy_write_paged); 1158 1159 /** 1160 * phy_modify_paged_changed() - Function for modifying a paged register 1161 * @phydev: a pointer to a &struct phy_device 1162 * @page: the page for the phy 1163 * @regnum: register number 1164 * @mask: bit mask of bits to clear 1165 * @set: bit mask of bits to set 1166 * 1167 * Returns negative errno, 0 if there was no change, and 1 in case of change 1168 */ 1169 int phy_modify_paged_changed(struct phy_device *phydev, int page, u32 regnum, 1170 u16 mask, u16 set) 1171 { 1172 int ret = 0, oldpage; 1173 1174 oldpage = phy_select_page(phydev, page); 1175 if (oldpage >= 0) 1176 ret = __phy_modify_changed(phydev, regnum, mask, set); 1177 1178 return phy_restore_page(phydev, oldpage, ret); 1179 } 1180 EXPORT_SYMBOL(phy_modify_paged_changed); 1181 1182 /** 1183 * phy_modify_paged() - Convenience function for modifying a paged register 1184 * @phydev: a pointer to a &struct phy_device 1185 * @page: the page for the phy 1186 * @regnum: register number 1187 * @mask: bit mask of bits to clear 1188 * @set: bit mask of bits to set 1189 * 1190 * Same rules as for phy_read() and phy_write(). 1191 */ 1192 int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum, 1193 u16 mask, u16 set) 1194 { 1195 int ret = phy_modify_paged_changed(phydev, page, regnum, mask, set); 1196 1197 return ret < 0 ? ret : 0; 1198 } 1199 EXPORT_SYMBOL(phy_modify_paged); 1200