185e97f0bSBjarni Jonasson /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 285e97f0bSBjarni Jonasson /* 385e97f0bSBjarni Jonasson * Driver for Microsemi VSC85xx PHYs 485e97f0bSBjarni Jonasson * 585e97f0bSBjarni Jonasson * Copyright (c) 2021 Microsemi Corporation 685e97f0bSBjarni Jonasson */ 785e97f0bSBjarni Jonasson 885e97f0bSBjarni Jonasson #ifndef _MSCC_SERDES_PHY_H_ 985e97f0bSBjarni Jonasson #define _MSCC_SERDES_PHY_H_ 1085e97f0bSBjarni Jonasson 1185e97f0bSBjarni Jonasson #define PHY_S6G_PLL5G_CFG2_GAIN_MASK GENMASK(9, 5) 1285e97f0bSBjarni Jonasson #define PHY_S6G_PLL5G_CFG2_ENA_GAIN 1 1385e97f0bSBjarni Jonasson 1485e97f0bSBjarni Jonasson #define PHY_S6G_DES_PHY_CTRL_POS 13 1585e97f0bSBjarni Jonasson #define PHY_S6G_DES_MBTR_CTRL_POS 10 1685e97f0bSBjarni Jonasson #define PHY_S6G_DES_CPMD_SEL_POS 8 1785e97f0bSBjarni Jonasson #define PHY_S6G_DES_BW_HYST_POS 5 1885e97f0bSBjarni Jonasson #define PHY_S6G_DES_BW_ANA_POS 1 1985e97f0bSBjarni Jonasson #define PHY_S6G_DES_CFG 0x21 2085e97f0bSBjarni Jonasson #define PHY_S6G_IB_CFG0 0x22 2185e97f0bSBjarni Jonasson #define PHY_S6G_IB_CFG1 0x23 2285e97f0bSBjarni Jonasson #define PHY_S6G_IB_CFG2 0x24 2385e97f0bSBjarni Jonasson #define PHY_S6G_IB_CFG3 0x25 2485e97f0bSBjarni Jonasson #define PHY_S6G_IB_CFG4 0x26 2585e97f0bSBjarni Jonasson #define PHY_S6G_GP_CFG 0x2E 2685e97f0bSBjarni Jonasson #define PHY_S6G_DFT_CFG0 0x35 2785e97f0bSBjarni Jonasson #define PHY_S6G_IB_DFT_CFG2 0x37 2885e97f0bSBjarni Jonasson 2985e97f0bSBjarni Jonasson int vsc85xx_sd6g_config_v2(struct phy_device *phydev); 3085e97f0bSBjarni Jonasson 3185e97f0bSBjarni Jonasson #endif /* _MSCC_PHY_SERDES_H_ */ 32