1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for the National Semiconductor DP83640 PHYTER 4 * 5 * Copyright (C) 2010 OMICRON electronics GmbH 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/crc32.h> 11 #include <linux/ethtool.h> 12 #include <linux/kernel.h> 13 #include <linux/list.h> 14 #include <linux/mii.h> 15 #include <linux/module.h> 16 #include <linux/net_tstamp.h> 17 #include <linux/netdevice.h> 18 #include <linux/if_vlan.h> 19 #include <linux/phy.h> 20 #include <linux/ptp_classify.h> 21 #include <linux/ptp_clock_kernel.h> 22 23 #include "dp83640_reg.h" 24 25 #define DP83640_PHY_ID 0x20005ce1 26 #define PAGESEL 0x13 27 #define MAX_RXTS 64 28 #define N_EXT_TS 6 29 #define N_PER_OUT 7 30 #define PSF_PTPVER 2 31 #define PSF_EVNT 0x4000 32 #define PSF_RX 0x2000 33 #define PSF_TX 0x1000 34 #define EXT_EVENT 1 35 #define CAL_EVENT 7 36 #define CAL_TRIGGER 1 37 #define DP83640_N_PINS 12 38 39 #define MII_DP83640_MICR 0x11 40 #define MII_DP83640_MISR 0x12 41 42 #define MII_DP83640_MICR_OE 0x1 43 #define MII_DP83640_MICR_IE 0x2 44 45 #define MII_DP83640_MISR_RHF_INT_EN 0x01 46 #define MII_DP83640_MISR_FHF_INT_EN 0x02 47 #define MII_DP83640_MISR_ANC_INT_EN 0x04 48 #define MII_DP83640_MISR_DUP_INT_EN 0x08 49 #define MII_DP83640_MISR_SPD_INT_EN 0x10 50 #define MII_DP83640_MISR_LINK_INT_EN 0x20 51 #define MII_DP83640_MISR_ED_INT_EN 0x40 52 #define MII_DP83640_MISR_LQ_INT_EN 0x80 53 #define MII_DP83640_MISR_ANC_INT 0x400 54 #define MII_DP83640_MISR_DUP_INT 0x800 55 #define MII_DP83640_MISR_SPD_INT 0x1000 56 #define MII_DP83640_MISR_LINK_INT 0x2000 57 #define MII_DP83640_MISR_INT_MASK (MII_DP83640_MISR_ANC_INT |\ 58 MII_DP83640_MISR_DUP_INT |\ 59 MII_DP83640_MISR_SPD_INT |\ 60 MII_DP83640_MISR_LINK_INT) 61 62 /* phyter seems to miss the mark by 16 ns */ 63 #define ADJTIME_FIX 16 64 65 #define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */ 66 67 #if defined(__BIG_ENDIAN) 68 #define ENDIAN_FLAG 0 69 #elif defined(__LITTLE_ENDIAN) 70 #define ENDIAN_FLAG PSF_ENDIAN 71 #endif 72 73 struct dp83640_skb_info { 74 int ptp_type; 75 unsigned long tmo; 76 }; 77 78 struct phy_rxts { 79 u16 ns_lo; /* ns[15:0] */ 80 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 81 u16 sec_lo; /* sec[15:0] */ 82 u16 sec_hi; /* sec[31:16] */ 83 u16 seqid; /* sequenceId[15:0] */ 84 u16 msgtype; /* messageType[3:0], hash[11:0] */ 85 }; 86 87 struct phy_txts { 88 u16 ns_lo; /* ns[15:0] */ 89 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 90 u16 sec_lo; /* sec[15:0] */ 91 u16 sec_hi; /* sec[31:16] */ 92 }; 93 94 struct rxts { 95 struct list_head list; 96 unsigned long tmo; 97 u64 ns; 98 u16 seqid; 99 u8 msgtype; 100 u16 hash; 101 }; 102 103 struct dp83640_clock; 104 105 struct dp83640_private { 106 struct list_head list; 107 struct dp83640_clock *clock; 108 struct phy_device *phydev; 109 struct mii_timestamper mii_ts; 110 struct delayed_work ts_work; 111 int hwts_tx_en; 112 int hwts_rx_en; 113 int layer; 114 int version; 115 /* remember state of cfg0 during calibration */ 116 int cfg0; 117 /* remember the last event time stamp */ 118 struct phy_txts edata; 119 /* list of rx timestamps */ 120 struct list_head rxts; 121 struct list_head rxpool; 122 struct rxts rx_pool_data[MAX_RXTS]; 123 /* protects above three fields from concurrent access */ 124 spinlock_t rx_lock; 125 /* queues of incoming and outgoing packets */ 126 struct sk_buff_head rx_queue; 127 struct sk_buff_head tx_queue; 128 }; 129 130 struct dp83640_clock { 131 /* keeps the instance in the 'phyter_clocks' list */ 132 struct list_head list; 133 /* we create one clock instance per MII bus */ 134 struct mii_bus *bus; 135 /* protects extended registers from concurrent access */ 136 struct mutex extreg_lock; 137 /* remembers which page was last selected */ 138 int page; 139 /* our advertised capabilities */ 140 struct ptp_clock_info caps; 141 /* protects the three fields below from concurrent access */ 142 struct mutex clock_lock; 143 /* the one phyter from which we shall read */ 144 struct dp83640_private *chosen; 145 /* list of the other attached phyters, not chosen */ 146 struct list_head phylist; 147 /* reference to our PTP hardware clock */ 148 struct ptp_clock *ptp_clock; 149 }; 150 151 /* globals */ 152 153 enum { 154 CALIBRATE_GPIO, 155 PEROUT_GPIO, 156 EXTTS0_GPIO, 157 EXTTS1_GPIO, 158 EXTTS2_GPIO, 159 EXTTS3_GPIO, 160 EXTTS4_GPIO, 161 EXTTS5_GPIO, 162 GPIO_TABLE_SIZE 163 }; 164 165 static int chosen_phy = -1; 166 static ushort gpio_tab[GPIO_TABLE_SIZE] = { 167 1, 2, 3, 4, 8, 9, 10, 11 168 }; 169 170 module_param(chosen_phy, int, 0444); 171 module_param_array(gpio_tab, ushort, NULL, 0444); 172 173 MODULE_PARM_DESC(chosen_phy, 174 "The address of the PHY to use for the ancillary clock features"); 175 MODULE_PARM_DESC(gpio_tab, 176 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6"); 177 178 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd) 179 { 180 int i, index; 181 182 for (i = 0; i < DP83640_N_PINS; i++) { 183 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i); 184 pd[i].index = i; 185 } 186 187 for (i = 0; i < GPIO_TABLE_SIZE; i++) { 188 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) { 189 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]); 190 return; 191 } 192 } 193 194 index = gpio_tab[CALIBRATE_GPIO] - 1; 195 pd[index].func = PTP_PF_PHYSYNC; 196 pd[index].chan = 0; 197 198 index = gpio_tab[PEROUT_GPIO] - 1; 199 pd[index].func = PTP_PF_PEROUT; 200 pd[index].chan = 0; 201 202 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) { 203 index = gpio_tab[i] - 1; 204 pd[index].func = PTP_PF_EXTTS; 205 pd[index].chan = i - EXTTS0_GPIO; 206 } 207 } 208 209 /* a list of clocks and a mutex to protect it */ 210 static LIST_HEAD(phyter_clocks); 211 static DEFINE_MUTEX(phyter_clocks_lock); 212 213 static void rx_timestamp_work(struct work_struct *work); 214 215 /* extended register access functions */ 216 217 #define BROADCAST_ADDR 31 218 219 static inline int broadcast_write(struct phy_device *phydev, u32 regnum, 220 u16 val) 221 { 222 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val); 223 } 224 225 /* Caller must hold extreg_lock. */ 226 static int ext_read(struct phy_device *phydev, int page, u32 regnum) 227 { 228 struct dp83640_private *dp83640 = phydev->priv; 229 int val; 230 231 if (dp83640->clock->page != page) { 232 broadcast_write(phydev, PAGESEL, page); 233 dp83640->clock->page = page; 234 } 235 val = phy_read(phydev, regnum); 236 237 return val; 238 } 239 240 /* Caller must hold extreg_lock. */ 241 static void ext_write(int broadcast, struct phy_device *phydev, 242 int page, u32 regnum, u16 val) 243 { 244 struct dp83640_private *dp83640 = phydev->priv; 245 246 if (dp83640->clock->page != page) { 247 broadcast_write(phydev, PAGESEL, page); 248 dp83640->clock->page = page; 249 } 250 if (broadcast) 251 broadcast_write(phydev, regnum, val); 252 else 253 phy_write(phydev, regnum, val); 254 } 255 256 /* Caller must hold extreg_lock. */ 257 static int tdr_write(int bc, struct phy_device *dev, 258 const struct timespec64 *ts, u16 cmd) 259 { 260 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */ 261 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */ 262 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */ 263 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/ 264 265 ext_write(bc, dev, PAGE4, PTP_CTL, cmd); 266 267 return 0; 268 } 269 270 /* convert phy timestamps into driver timestamps */ 271 272 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts) 273 { 274 u32 sec; 275 276 sec = p->sec_lo; 277 sec |= p->sec_hi << 16; 278 279 rxts->ns = p->ns_lo; 280 rxts->ns |= (p->ns_hi & 0x3fff) << 16; 281 rxts->ns += ((u64)sec) * 1000000000ULL; 282 rxts->seqid = p->seqid; 283 rxts->msgtype = (p->msgtype >> 12) & 0xf; 284 rxts->hash = p->msgtype & 0x0fff; 285 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 286 } 287 288 static u64 phy2txts(struct phy_txts *p) 289 { 290 u64 ns; 291 u32 sec; 292 293 sec = p->sec_lo; 294 sec |= p->sec_hi << 16; 295 296 ns = p->ns_lo; 297 ns |= (p->ns_hi & 0x3fff) << 16; 298 ns += ((u64)sec) * 1000000000ULL; 299 300 return ns; 301 } 302 303 static int periodic_output(struct dp83640_clock *clock, 304 struct ptp_clock_request *clkreq, bool on, 305 int trigger) 306 { 307 struct dp83640_private *dp83640 = clock->chosen; 308 struct phy_device *phydev = dp83640->phydev; 309 u32 sec, nsec, pwidth; 310 u16 gpio, ptp_trig, val; 311 312 if (on) { 313 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, 314 trigger); 315 if (gpio < 1) 316 return -EINVAL; 317 } else { 318 gpio = 0; 319 } 320 321 ptp_trig = TRIG_WR | 322 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT | 323 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT | 324 TRIG_PER | 325 TRIG_PULSE; 326 327 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 328 329 if (!on) { 330 val |= TRIG_DIS; 331 mutex_lock(&clock->extreg_lock); 332 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 333 ext_write(0, phydev, PAGE4, PTP_CTL, val); 334 mutex_unlock(&clock->extreg_lock); 335 return 0; 336 } 337 338 sec = clkreq->perout.start.sec; 339 nsec = clkreq->perout.start.nsec; 340 pwidth = clkreq->perout.period.sec * 1000000000UL; 341 pwidth += clkreq->perout.period.nsec; 342 pwidth /= 2; 343 344 mutex_lock(&clock->extreg_lock); 345 346 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 347 348 /*load trigger*/ 349 val |= TRIG_LOAD; 350 ext_write(0, phydev, PAGE4, PTP_CTL, val); 351 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */ 352 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */ 353 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */ 354 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */ 355 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */ 356 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */ 357 /* Triggers 0 and 1 has programmable pulsewidth2 */ 358 if (trigger < 2) { 359 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); 360 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); 361 } 362 363 /*enable trigger*/ 364 val &= ~TRIG_LOAD; 365 val |= TRIG_EN; 366 ext_write(0, phydev, PAGE4, PTP_CTL, val); 367 368 mutex_unlock(&clock->extreg_lock); 369 return 0; 370 } 371 372 /* ptp clock methods */ 373 374 static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 375 { 376 struct dp83640_clock *clock = 377 container_of(ptp, struct dp83640_clock, caps); 378 struct phy_device *phydev = clock->chosen->phydev; 379 u64 rate; 380 int neg_adj = 0; 381 u16 hi, lo; 382 383 if (scaled_ppm < 0) { 384 neg_adj = 1; 385 scaled_ppm = -scaled_ppm; 386 } 387 rate = scaled_ppm; 388 rate <<= 13; 389 rate = div_u64(rate, 15625); 390 391 hi = (rate >> 16) & PTP_RATE_HI_MASK; 392 if (neg_adj) 393 hi |= PTP_RATE_DIR; 394 395 lo = rate & 0xffff; 396 397 mutex_lock(&clock->extreg_lock); 398 399 ext_write(1, phydev, PAGE4, PTP_RATEH, hi); 400 ext_write(1, phydev, PAGE4, PTP_RATEL, lo); 401 402 mutex_unlock(&clock->extreg_lock); 403 404 return 0; 405 } 406 407 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta) 408 { 409 struct dp83640_clock *clock = 410 container_of(ptp, struct dp83640_clock, caps); 411 struct phy_device *phydev = clock->chosen->phydev; 412 struct timespec64 ts; 413 int err; 414 415 delta += ADJTIME_FIX; 416 417 ts = ns_to_timespec64(delta); 418 419 mutex_lock(&clock->extreg_lock); 420 421 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK); 422 423 mutex_unlock(&clock->extreg_lock); 424 425 return err; 426 } 427 428 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, 429 struct timespec64 *ts) 430 { 431 struct dp83640_clock *clock = 432 container_of(ptp, struct dp83640_clock, caps); 433 struct phy_device *phydev = clock->chosen->phydev; 434 unsigned int val[4]; 435 436 mutex_lock(&clock->extreg_lock); 437 438 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK); 439 440 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */ 441 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */ 442 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */ 443 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */ 444 445 mutex_unlock(&clock->extreg_lock); 446 447 ts->tv_nsec = val[0] | (val[1] << 16); 448 ts->tv_sec = val[2] | (val[3] << 16); 449 450 return 0; 451 } 452 453 static int ptp_dp83640_settime(struct ptp_clock_info *ptp, 454 const struct timespec64 *ts) 455 { 456 struct dp83640_clock *clock = 457 container_of(ptp, struct dp83640_clock, caps); 458 struct phy_device *phydev = clock->chosen->phydev; 459 int err; 460 461 mutex_lock(&clock->extreg_lock); 462 463 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK); 464 465 mutex_unlock(&clock->extreg_lock); 466 467 return err; 468 } 469 470 static int ptp_dp83640_enable(struct ptp_clock_info *ptp, 471 struct ptp_clock_request *rq, int on) 472 { 473 struct dp83640_clock *clock = 474 container_of(ptp, struct dp83640_clock, caps); 475 struct phy_device *phydev = clock->chosen->phydev; 476 unsigned int index; 477 u16 evnt, event_num, gpio_num; 478 479 switch (rq->type) { 480 case PTP_CLK_REQ_EXTTS: 481 /* Reject requests to enable time stamping on both edges. */ 482 if ((rq->extts.flags & PTP_STRICT_FLAGS) && 483 (rq->extts.flags & PTP_ENABLE_FEATURE) && 484 (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES) 485 return -EOPNOTSUPP; 486 487 index = rq->extts.index; 488 if (index >= N_EXT_TS) 489 return -EINVAL; 490 event_num = EXT_EVENT + index; 491 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 492 if (on) { 493 gpio_num = 1 + ptp_find_pin(clock->ptp_clock, 494 PTP_PF_EXTTS, index); 495 if (gpio_num < 1) 496 return -EINVAL; 497 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 498 if (rq->extts.flags & PTP_FALLING_EDGE) 499 evnt |= EVNT_FALL; 500 else 501 evnt |= EVNT_RISE; 502 } 503 mutex_lock(&clock->extreg_lock); 504 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt); 505 mutex_unlock(&clock->extreg_lock); 506 return 0; 507 508 case PTP_CLK_REQ_PEROUT: 509 if (rq->perout.index >= N_PER_OUT) 510 return -EINVAL; 511 return periodic_output(clock, rq, on, rq->perout.index); 512 513 default: 514 break; 515 } 516 517 return -EOPNOTSUPP; 518 } 519 520 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin, 521 enum ptp_pin_function func, unsigned int chan) 522 { 523 struct dp83640_clock *clock = 524 container_of(ptp, struct dp83640_clock, caps); 525 526 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC && 527 !list_empty(&clock->phylist)) 528 return 1; 529 530 if (func == PTP_PF_PHYSYNC) 531 return 1; 532 533 return 0; 534 } 535 536 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 }; 537 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F }; 538 539 static void enable_status_frames(struct phy_device *phydev, bool on) 540 { 541 struct dp83640_private *dp83640 = phydev->priv; 542 struct dp83640_clock *clock = dp83640->clock; 543 u16 cfg0 = 0, ver; 544 545 if (on) 546 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; 547 548 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT; 549 550 mutex_lock(&clock->extreg_lock); 551 552 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); 553 ext_write(0, phydev, PAGE6, PSF_CFG1, ver); 554 555 mutex_unlock(&clock->extreg_lock); 556 557 if (!phydev->attached_dev) { 558 phydev_warn(phydev, 559 "expected to find an attached netdevice\n"); 560 return; 561 } 562 563 if (on) { 564 if (dev_mc_add(phydev->attached_dev, status_frame_dst)) 565 phydev_warn(phydev, "failed to add mc address\n"); 566 } else { 567 if (dev_mc_del(phydev->attached_dev, status_frame_dst)) 568 phydev_warn(phydev, "failed to delete mc address\n"); 569 } 570 } 571 572 static bool is_status_frame(struct sk_buff *skb, int type) 573 { 574 struct ethhdr *h = eth_hdr(skb); 575 576 if (PTP_CLASS_V2_L2 == type && 577 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src))) 578 return true; 579 else 580 return false; 581 } 582 583 static int expired(struct rxts *rxts) 584 { 585 return time_after(jiffies, rxts->tmo); 586 } 587 588 /* Caller must hold rx_lock. */ 589 static void prune_rx_ts(struct dp83640_private *dp83640) 590 { 591 struct list_head *this, *next; 592 struct rxts *rxts; 593 594 list_for_each_safe(this, next, &dp83640->rxts) { 595 rxts = list_entry(this, struct rxts, list); 596 if (expired(rxts)) { 597 list_del_init(&rxts->list); 598 list_add(&rxts->list, &dp83640->rxpool); 599 } 600 } 601 } 602 603 /* synchronize the phyters so they act as one clock */ 604 605 static void enable_broadcast(struct phy_device *phydev, int init_page, int on) 606 { 607 int val; 608 609 phy_write(phydev, PAGESEL, 0); 610 val = phy_read(phydev, PHYCR2); 611 if (on) 612 val |= BC_WRITE; 613 else 614 val &= ~BC_WRITE; 615 phy_write(phydev, PHYCR2, val); 616 phy_write(phydev, PAGESEL, init_page); 617 } 618 619 static void recalibrate(struct dp83640_clock *clock) 620 { 621 s64 now, diff; 622 struct phy_txts event_ts; 623 struct timespec64 ts; 624 struct dp83640_private *tmp; 625 struct phy_device *master = clock->chosen->phydev; 626 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; 627 628 trigger = CAL_TRIGGER; 629 cal_gpio = 1 + ptp_find_pin_unlocked(clock->ptp_clock, PTP_PF_PHYSYNC, 0); 630 if (cal_gpio < 1) { 631 pr_err("PHY calibration pin not available - PHY is not calibrated."); 632 return; 633 } 634 635 mutex_lock(&clock->extreg_lock); 636 637 /* 638 * enable broadcast, disable status frames, enable ptp clock 639 */ 640 list_for_each_entry(tmp, &clock->phylist, list) { 641 enable_broadcast(tmp->phydev, clock->page, 1); 642 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); 643 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0); 644 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE); 645 } 646 enable_broadcast(master, clock->page, 1); 647 cfg0 = ext_read(master, PAGE5, PSF_CFG0); 648 ext_write(0, master, PAGE5, PSF_CFG0, 0); 649 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE); 650 651 /* 652 * enable an event timestamp 653 */ 654 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE; 655 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 656 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 657 658 list_for_each_entry(tmp, &clock->phylist, list) 659 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt); 660 ext_write(0, master, PAGE5, PTP_EVNT, evnt); 661 662 /* 663 * configure a trigger 664 */ 665 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE; 666 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT; 667 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT; 668 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig); 669 670 /* load trigger */ 671 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 672 val |= TRIG_LOAD; 673 ext_write(0, master, PAGE4, PTP_CTL, val); 674 675 /* enable trigger */ 676 val &= ~TRIG_LOAD; 677 val |= TRIG_EN; 678 ext_write(0, master, PAGE4, PTP_CTL, val); 679 680 /* disable trigger */ 681 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 682 val |= TRIG_DIS; 683 ext_write(0, master, PAGE4, PTP_CTL, val); 684 685 /* 686 * read out and correct offsets 687 */ 688 val = ext_read(master, PAGE4, PTP_STS); 689 phydev_info(master, "master PTP_STS 0x%04hx\n", val); 690 val = ext_read(master, PAGE4, PTP_ESTS); 691 phydev_info(master, "master PTP_ESTS 0x%04hx\n", val); 692 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA); 693 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA); 694 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA); 695 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA); 696 now = phy2txts(&event_ts); 697 698 list_for_each_entry(tmp, &clock->phylist, list) { 699 val = ext_read(tmp->phydev, PAGE4, PTP_STS); 700 phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val); 701 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS); 702 phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val); 703 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 704 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 705 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 706 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 707 diff = now - (s64) phy2txts(&event_ts); 708 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n", 709 diff); 710 diff += ADJTIME_FIX; 711 ts = ns_to_timespec64(diff); 712 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK); 713 } 714 715 /* 716 * restore status frames 717 */ 718 list_for_each_entry(tmp, &clock->phylist, list) 719 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); 720 ext_write(0, master, PAGE5, PSF_CFG0, cfg0); 721 722 mutex_unlock(&clock->extreg_lock); 723 } 724 725 /* time stamping methods */ 726 727 static inline u16 exts_chan_to_edata(int ch) 728 { 729 return 1 << ((ch + EXT_EVENT) * 2); 730 } 731 732 static int decode_evnt(struct dp83640_private *dp83640, 733 void *data, int len, u16 ests) 734 { 735 struct phy_txts *phy_txts; 736 struct ptp_clock_event event; 737 int i, parsed; 738 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK; 739 u16 ext_status = 0; 740 741 /* calculate length of the event timestamp status message */ 742 if (ests & MULT_EVNT) 743 parsed = (words + 2) * sizeof(u16); 744 else 745 parsed = (words + 1) * sizeof(u16); 746 747 /* check if enough data is available */ 748 if (len < parsed) 749 return len; 750 751 if (ests & MULT_EVNT) { 752 ext_status = *(u16 *) data; 753 data += sizeof(ext_status); 754 } 755 756 phy_txts = data; 757 758 switch (words) { 759 case 3: 760 dp83640->edata.sec_hi = phy_txts->sec_hi; 761 fallthrough; 762 case 2: 763 dp83640->edata.sec_lo = phy_txts->sec_lo; 764 fallthrough; 765 case 1: 766 dp83640->edata.ns_hi = phy_txts->ns_hi; 767 fallthrough; 768 case 0: 769 dp83640->edata.ns_lo = phy_txts->ns_lo; 770 } 771 772 if (!ext_status) { 773 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT; 774 ext_status = exts_chan_to_edata(i); 775 } 776 777 event.type = PTP_CLOCK_EXTTS; 778 event.timestamp = phy2txts(&dp83640->edata); 779 780 /* Compensate for input path and synchronization delays */ 781 event.timestamp -= 35; 782 783 for (i = 0; i < N_EXT_TS; i++) { 784 if (ext_status & exts_chan_to_edata(i)) { 785 event.index = i; 786 ptp_clock_event(dp83640->clock->ptp_clock, &event); 787 } 788 } 789 790 return parsed; 791 } 792 793 #define DP83640_PACKET_HASH_LEN 10 794 795 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts) 796 { 797 struct ptp_header *hdr; 798 u8 msgtype; 799 u16 seqid; 800 u16 hash; 801 802 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */ 803 804 hdr = ptp_parse_header(skb, type); 805 if (!hdr) 806 return 0; 807 808 msgtype = ptp_get_msgtype(hdr, type); 809 810 if (rxts->msgtype != (msgtype & 0xf)) 811 return 0; 812 813 seqid = be16_to_cpu(hdr->sequence_id); 814 if (rxts->seqid != seqid) 815 return 0; 816 817 hash = ether_crc(DP83640_PACKET_HASH_LEN, 818 (unsigned char *)&hdr->source_port_identity) >> 20; 819 if (rxts->hash != hash) 820 return 0; 821 822 return 1; 823 } 824 825 static void decode_rxts(struct dp83640_private *dp83640, 826 struct phy_rxts *phy_rxts) 827 { 828 struct rxts *rxts; 829 struct skb_shared_hwtstamps *shhwtstamps = NULL; 830 struct sk_buff *skb; 831 unsigned long flags; 832 u8 overflow; 833 834 overflow = (phy_rxts->ns_hi >> 14) & 0x3; 835 if (overflow) 836 pr_debug("rx timestamp queue overflow, count %d\n", overflow); 837 838 spin_lock_irqsave(&dp83640->rx_lock, flags); 839 840 prune_rx_ts(dp83640); 841 842 if (list_empty(&dp83640->rxpool)) { 843 pr_debug("rx timestamp pool is empty\n"); 844 goto out; 845 } 846 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list); 847 list_del_init(&rxts->list); 848 phy2rxts(phy_rxts, rxts); 849 850 spin_lock(&dp83640->rx_queue.lock); 851 skb_queue_walk(&dp83640->rx_queue, skb) { 852 struct dp83640_skb_info *skb_info; 853 854 skb_info = (struct dp83640_skb_info *)skb->cb; 855 if (match(skb, skb_info->ptp_type, rxts)) { 856 __skb_unlink(skb, &dp83640->rx_queue); 857 shhwtstamps = skb_hwtstamps(skb); 858 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 859 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 860 list_add(&rxts->list, &dp83640->rxpool); 861 break; 862 } 863 } 864 spin_unlock(&dp83640->rx_queue.lock); 865 866 if (!shhwtstamps) 867 list_add_tail(&rxts->list, &dp83640->rxts); 868 out: 869 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 870 871 if (shhwtstamps) 872 netif_rx(skb); 873 } 874 875 static void decode_txts(struct dp83640_private *dp83640, 876 struct phy_txts *phy_txts) 877 { 878 struct skb_shared_hwtstamps shhwtstamps; 879 struct dp83640_skb_info *skb_info; 880 struct sk_buff *skb; 881 u8 overflow; 882 u64 ns; 883 884 /* We must already have the skb that triggered this. */ 885 again: 886 skb = skb_dequeue(&dp83640->tx_queue); 887 if (!skb) { 888 pr_debug("have timestamp but tx_queue empty\n"); 889 return; 890 } 891 892 overflow = (phy_txts->ns_hi >> 14) & 0x3; 893 if (overflow) { 894 pr_debug("tx timestamp queue overflow, count %d\n", overflow); 895 while (skb) { 896 kfree_skb(skb); 897 skb = skb_dequeue(&dp83640->tx_queue); 898 } 899 return; 900 } 901 skb_info = (struct dp83640_skb_info *)skb->cb; 902 if (time_after(jiffies, skb_info->tmo)) { 903 kfree_skb(skb); 904 goto again; 905 } 906 907 ns = phy2txts(phy_txts); 908 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 909 shhwtstamps.hwtstamp = ns_to_ktime(ns); 910 skb_complete_tx_timestamp(skb, &shhwtstamps); 911 } 912 913 static void decode_status_frame(struct dp83640_private *dp83640, 914 struct sk_buff *skb) 915 { 916 struct phy_rxts *phy_rxts; 917 struct phy_txts *phy_txts; 918 u8 *ptr; 919 int len, size; 920 u16 ests, type; 921 922 ptr = skb->data + 2; 923 924 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) { 925 926 type = *(u16 *)ptr; 927 ests = type & 0x0fff; 928 type = type & 0xf000; 929 len -= sizeof(type); 930 ptr += sizeof(type); 931 932 if (PSF_RX == type && len >= sizeof(*phy_rxts)) { 933 934 phy_rxts = (struct phy_rxts *) ptr; 935 decode_rxts(dp83640, phy_rxts); 936 size = sizeof(*phy_rxts); 937 938 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) { 939 940 phy_txts = (struct phy_txts *) ptr; 941 decode_txts(dp83640, phy_txts); 942 size = sizeof(*phy_txts); 943 944 } else if (PSF_EVNT == type) { 945 946 size = decode_evnt(dp83640, ptr, len, ests); 947 948 } else { 949 size = 0; 950 break; 951 } 952 ptr += size; 953 } 954 } 955 956 static void dp83640_free_clocks(void) 957 { 958 struct dp83640_clock *clock; 959 struct list_head *this, *next; 960 961 mutex_lock(&phyter_clocks_lock); 962 963 list_for_each_safe(this, next, &phyter_clocks) { 964 clock = list_entry(this, struct dp83640_clock, list); 965 if (!list_empty(&clock->phylist)) { 966 pr_warn("phy list non-empty while unloading\n"); 967 BUG(); 968 } 969 list_del(&clock->list); 970 mutex_destroy(&clock->extreg_lock); 971 mutex_destroy(&clock->clock_lock); 972 put_device(&clock->bus->dev); 973 kfree(clock->caps.pin_config); 974 kfree(clock); 975 } 976 977 mutex_unlock(&phyter_clocks_lock); 978 } 979 980 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus) 981 { 982 INIT_LIST_HEAD(&clock->list); 983 clock->bus = bus; 984 mutex_init(&clock->extreg_lock); 985 mutex_init(&clock->clock_lock); 986 INIT_LIST_HEAD(&clock->phylist); 987 clock->caps.owner = THIS_MODULE; 988 sprintf(clock->caps.name, "dp83640 timer"); 989 clock->caps.max_adj = 1953124; 990 clock->caps.n_alarm = 0; 991 clock->caps.n_ext_ts = N_EXT_TS; 992 clock->caps.n_per_out = N_PER_OUT; 993 clock->caps.n_pins = DP83640_N_PINS; 994 clock->caps.pps = 0; 995 clock->caps.supported_extts_flags = PTP_RISING_EDGE | 996 PTP_FALLING_EDGE | 997 PTP_STRICT_FLAGS; 998 clock->caps.adjfine = ptp_dp83640_adjfine; 999 clock->caps.adjtime = ptp_dp83640_adjtime; 1000 clock->caps.gettime64 = ptp_dp83640_gettime; 1001 clock->caps.settime64 = ptp_dp83640_settime; 1002 clock->caps.enable = ptp_dp83640_enable; 1003 clock->caps.verify = ptp_dp83640_verify; 1004 /* 1005 * Convert the module param defaults into a dynamic pin configuration. 1006 */ 1007 dp83640_gpio_defaults(clock->caps.pin_config); 1008 /* 1009 * Get a reference to this bus instance. 1010 */ 1011 get_device(&bus->dev); 1012 } 1013 1014 static int choose_this_phy(struct dp83640_clock *clock, 1015 struct phy_device *phydev) 1016 { 1017 if (chosen_phy == -1 && !clock->chosen) 1018 return 1; 1019 1020 if (chosen_phy == phydev->mdio.addr) 1021 return 1; 1022 1023 return 0; 1024 } 1025 1026 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock) 1027 { 1028 if (clock) 1029 mutex_lock(&clock->clock_lock); 1030 return clock; 1031 } 1032 1033 /* 1034 * Look up and lock a clock by bus instance. 1035 * If there is no clock for this bus, then create it first. 1036 */ 1037 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus) 1038 { 1039 struct dp83640_clock *clock = NULL, *tmp; 1040 struct list_head *this; 1041 1042 mutex_lock(&phyter_clocks_lock); 1043 1044 list_for_each(this, &phyter_clocks) { 1045 tmp = list_entry(this, struct dp83640_clock, list); 1046 if (tmp->bus == bus) { 1047 clock = tmp; 1048 break; 1049 } 1050 } 1051 if (clock) 1052 goto out; 1053 1054 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL); 1055 if (!clock) 1056 goto out; 1057 1058 clock->caps.pin_config = kcalloc(DP83640_N_PINS, 1059 sizeof(struct ptp_pin_desc), 1060 GFP_KERNEL); 1061 if (!clock->caps.pin_config) { 1062 kfree(clock); 1063 clock = NULL; 1064 goto out; 1065 } 1066 dp83640_clock_init(clock, bus); 1067 list_add_tail(&clock->list, &phyter_clocks); 1068 out: 1069 mutex_unlock(&phyter_clocks_lock); 1070 1071 return dp83640_clock_get(clock); 1072 } 1073 1074 static void dp83640_clock_put(struct dp83640_clock *clock) 1075 { 1076 mutex_unlock(&clock->clock_lock); 1077 } 1078 1079 static int dp83640_soft_reset(struct phy_device *phydev) 1080 { 1081 int ret; 1082 1083 ret = genphy_soft_reset(phydev); 1084 if (ret < 0) 1085 return ret; 1086 1087 /* From DP83640 datasheet: "Software driver code must wait 3 us 1088 * following a software reset before allowing further serial MII 1089 * operations with the DP83640." 1090 */ 1091 udelay(10); /* Taking udelay inaccuracy into account */ 1092 1093 return 0; 1094 } 1095 1096 static int dp83640_config_init(struct phy_device *phydev) 1097 { 1098 struct dp83640_private *dp83640 = phydev->priv; 1099 struct dp83640_clock *clock = dp83640->clock; 1100 1101 if (clock->chosen && !list_empty(&clock->phylist)) 1102 recalibrate(clock); 1103 else { 1104 mutex_lock(&clock->extreg_lock); 1105 enable_broadcast(phydev, clock->page, 1); 1106 mutex_unlock(&clock->extreg_lock); 1107 } 1108 1109 enable_status_frames(phydev, true); 1110 1111 mutex_lock(&clock->extreg_lock); 1112 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE); 1113 mutex_unlock(&clock->extreg_lock); 1114 1115 return 0; 1116 } 1117 1118 static int dp83640_ack_interrupt(struct phy_device *phydev) 1119 { 1120 int err = phy_read(phydev, MII_DP83640_MISR); 1121 1122 if (err < 0) 1123 return err; 1124 1125 return 0; 1126 } 1127 1128 static int dp83640_config_intr(struct phy_device *phydev) 1129 { 1130 int micr; 1131 int misr; 1132 int err; 1133 1134 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1135 err = dp83640_ack_interrupt(phydev); 1136 if (err) 1137 return err; 1138 1139 misr = phy_read(phydev, MII_DP83640_MISR); 1140 if (misr < 0) 1141 return misr; 1142 misr |= 1143 (MII_DP83640_MISR_ANC_INT_EN | 1144 MII_DP83640_MISR_DUP_INT_EN | 1145 MII_DP83640_MISR_SPD_INT_EN | 1146 MII_DP83640_MISR_LINK_INT_EN); 1147 err = phy_write(phydev, MII_DP83640_MISR, misr); 1148 if (err < 0) 1149 return err; 1150 1151 micr = phy_read(phydev, MII_DP83640_MICR); 1152 if (micr < 0) 1153 return micr; 1154 micr |= 1155 (MII_DP83640_MICR_OE | 1156 MII_DP83640_MICR_IE); 1157 return phy_write(phydev, MII_DP83640_MICR, micr); 1158 } else { 1159 micr = phy_read(phydev, MII_DP83640_MICR); 1160 if (micr < 0) 1161 return micr; 1162 micr &= 1163 ~(MII_DP83640_MICR_OE | 1164 MII_DP83640_MICR_IE); 1165 err = phy_write(phydev, MII_DP83640_MICR, micr); 1166 if (err < 0) 1167 return err; 1168 1169 misr = phy_read(phydev, MII_DP83640_MISR); 1170 if (misr < 0) 1171 return misr; 1172 misr &= 1173 ~(MII_DP83640_MISR_ANC_INT_EN | 1174 MII_DP83640_MISR_DUP_INT_EN | 1175 MII_DP83640_MISR_SPD_INT_EN | 1176 MII_DP83640_MISR_LINK_INT_EN); 1177 err = phy_write(phydev, MII_DP83640_MISR, misr); 1178 if (err) 1179 return err; 1180 1181 return dp83640_ack_interrupt(phydev); 1182 } 1183 } 1184 1185 static irqreturn_t dp83640_handle_interrupt(struct phy_device *phydev) 1186 { 1187 int irq_status; 1188 1189 irq_status = phy_read(phydev, MII_DP83640_MISR); 1190 if (irq_status < 0) { 1191 phy_error(phydev); 1192 return IRQ_NONE; 1193 } 1194 1195 if (!(irq_status & MII_DP83640_MISR_INT_MASK)) 1196 return IRQ_NONE; 1197 1198 phy_trigger_machine(phydev); 1199 1200 return IRQ_HANDLED; 1201 } 1202 1203 static int dp83640_hwtstamp(struct mii_timestamper *mii_ts, 1204 struct kernel_hwtstamp_config *cfg, 1205 struct netlink_ext_ack *extack) 1206 { 1207 struct dp83640_private *dp83640 = 1208 container_of(mii_ts, struct dp83640_private, mii_ts); 1209 u16 txcfg0, rxcfg0; 1210 1211 if (cfg->tx_type < 0 || cfg->tx_type > HWTSTAMP_TX_ONESTEP_SYNC) 1212 return -ERANGE; 1213 1214 dp83640->hwts_tx_en = cfg->tx_type; 1215 1216 switch (cfg->rx_filter) { 1217 case HWTSTAMP_FILTER_NONE: 1218 dp83640->hwts_rx_en = 0; 1219 dp83640->layer = 0; 1220 dp83640->version = 0; 1221 break; 1222 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1223 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1224 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1225 dp83640->hwts_rx_en = 1; 1226 dp83640->layer = PTP_CLASS_L4; 1227 dp83640->version = PTP_CLASS_V1; 1228 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 1229 break; 1230 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1231 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1232 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1233 dp83640->hwts_rx_en = 1; 1234 dp83640->layer = PTP_CLASS_L4; 1235 dp83640->version = PTP_CLASS_V2; 1236 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 1237 break; 1238 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1239 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1240 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1241 dp83640->hwts_rx_en = 1; 1242 dp83640->layer = PTP_CLASS_L2; 1243 dp83640->version = PTP_CLASS_V2; 1244 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1245 break; 1246 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1247 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1248 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1249 dp83640->hwts_rx_en = 1; 1250 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2; 1251 dp83640->version = PTP_CLASS_V2; 1252 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1253 break; 1254 default: 1255 return -ERANGE; 1256 } 1257 1258 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1259 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1260 1261 if (dp83640->layer & PTP_CLASS_L2) { 1262 txcfg0 |= TX_L2_EN; 1263 rxcfg0 |= RX_L2_EN; 1264 } 1265 if (dp83640->layer & PTP_CLASS_L4) { 1266 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN; 1267 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN; 1268 } 1269 1270 if (dp83640->hwts_tx_en) 1271 txcfg0 |= TX_TS_EN; 1272 1273 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC) 1274 txcfg0 |= SYNC_1STEP | CHK_1STEP; 1275 1276 if (dp83640->hwts_rx_en) 1277 rxcfg0 |= RX_TS_EN; 1278 1279 mutex_lock(&dp83640->clock->extreg_lock); 1280 1281 ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0); 1282 ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0); 1283 1284 mutex_unlock(&dp83640->clock->extreg_lock); 1285 1286 return 0; 1287 } 1288 1289 static void rx_timestamp_work(struct work_struct *work) 1290 { 1291 struct dp83640_private *dp83640 = 1292 container_of(work, struct dp83640_private, ts_work.work); 1293 struct sk_buff *skb; 1294 1295 /* Deliver expired packets. */ 1296 while ((skb = skb_dequeue(&dp83640->rx_queue))) { 1297 struct dp83640_skb_info *skb_info; 1298 1299 skb_info = (struct dp83640_skb_info *)skb->cb; 1300 if (!time_after(jiffies, skb_info->tmo)) { 1301 skb_queue_head(&dp83640->rx_queue, skb); 1302 break; 1303 } 1304 1305 netif_rx(skb); 1306 } 1307 1308 if (!skb_queue_empty(&dp83640->rx_queue)) 1309 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); 1310 } 1311 1312 static bool dp83640_rxtstamp(struct mii_timestamper *mii_ts, 1313 struct sk_buff *skb, int type) 1314 { 1315 struct dp83640_private *dp83640 = 1316 container_of(mii_ts, struct dp83640_private, mii_ts); 1317 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; 1318 struct list_head *this, *next; 1319 struct rxts *rxts; 1320 struct skb_shared_hwtstamps *shhwtstamps = NULL; 1321 unsigned long flags; 1322 1323 if (is_status_frame(skb, type)) { 1324 decode_status_frame(dp83640, skb); 1325 kfree_skb(skb); 1326 return true; 1327 } 1328 1329 if (!dp83640->hwts_rx_en) 1330 return false; 1331 1332 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0) 1333 return false; 1334 1335 spin_lock_irqsave(&dp83640->rx_lock, flags); 1336 prune_rx_ts(dp83640); 1337 list_for_each_safe(this, next, &dp83640->rxts) { 1338 rxts = list_entry(this, struct rxts, list); 1339 if (match(skb, type, rxts)) { 1340 shhwtstamps = skb_hwtstamps(skb); 1341 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1342 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 1343 list_del_init(&rxts->list); 1344 list_add(&rxts->list, &dp83640->rxpool); 1345 break; 1346 } 1347 } 1348 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 1349 1350 if (!shhwtstamps) { 1351 skb_info->ptp_type = type; 1352 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 1353 skb_queue_tail(&dp83640->rx_queue, skb); 1354 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); 1355 } else { 1356 netif_rx(skb); 1357 } 1358 1359 return true; 1360 } 1361 1362 static void dp83640_txtstamp(struct mii_timestamper *mii_ts, 1363 struct sk_buff *skb, int type) 1364 { 1365 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; 1366 struct dp83640_private *dp83640 = 1367 container_of(mii_ts, struct dp83640_private, mii_ts); 1368 1369 switch (dp83640->hwts_tx_en) { 1370 1371 case HWTSTAMP_TX_ONESTEP_SYNC: 1372 if (ptp_msg_is_sync(skb, type)) { 1373 kfree_skb(skb); 1374 return; 1375 } 1376 fallthrough; 1377 case HWTSTAMP_TX_ON: 1378 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1379 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 1380 skb_queue_tail(&dp83640->tx_queue, skb); 1381 break; 1382 1383 case HWTSTAMP_TX_OFF: 1384 default: 1385 kfree_skb(skb); 1386 break; 1387 } 1388 } 1389 1390 static int dp83640_ts_info(struct mii_timestamper *mii_ts, 1391 struct kernel_ethtool_ts_info *info) 1392 { 1393 struct dp83640_private *dp83640 = 1394 container_of(mii_ts, struct dp83640_private, mii_ts); 1395 1396 info->so_timestamping = 1397 SOF_TIMESTAMPING_TX_HARDWARE | 1398 SOF_TIMESTAMPING_RX_HARDWARE | 1399 SOF_TIMESTAMPING_RAW_HARDWARE; 1400 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock); 1401 info->tx_types = 1402 (1 << HWTSTAMP_TX_OFF) | 1403 (1 << HWTSTAMP_TX_ON) | 1404 (1 << HWTSTAMP_TX_ONESTEP_SYNC); 1405 info->rx_filters = 1406 (1 << HWTSTAMP_FILTER_NONE) | 1407 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1408 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1409 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1410 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 1411 return 0; 1412 } 1413 1414 static int dp83640_probe(struct phy_device *phydev) 1415 { 1416 struct dp83640_clock *clock; 1417 struct dp83640_private *dp83640; 1418 int err = -ENOMEM, i; 1419 1420 if (phydev->mdio.addr == BROADCAST_ADDR) 1421 return 0; 1422 1423 clock = dp83640_clock_get_bus(phydev->mdio.bus); 1424 if (!clock) 1425 goto no_clock; 1426 1427 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL); 1428 if (!dp83640) 1429 goto no_memory; 1430 1431 dp83640->phydev = phydev; 1432 dp83640->mii_ts.rxtstamp = dp83640_rxtstamp; 1433 dp83640->mii_ts.txtstamp = dp83640_txtstamp; 1434 dp83640->mii_ts.hwtstamp = dp83640_hwtstamp; 1435 dp83640->mii_ts.ts_info = dp83640_ts_info; 1436 1437 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work); 1438 INIT_LIST_HEAD(&dp83640->rxts); 1439 INIT_LIST_HEAD(&dp83640->rxpool); 1440 for (i = 0; i < MAX_RXTS; i++) 1441 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool); 1442 1443 /* Timestamp selected by default to keep legacy API */ 1444 phydev->default_timestamp = true; 1445 phydev->mii_ts = &dp83640->mii_ts; 1446 phydev->priv = dp83640; 1447 1448 spin_lock_init(&dp83640->rx_lock); 1449 skb_queue_head_init(&dp83640->rx_queue); 1450 skb_queue_head_init(&dp83640->tx_queue); 1451 1452 dp83640->clock = clock; 1453 1454 if (choose_this_phy(clock, phydev)) { 1455 clock->chosen = dp83640; 1456 clock->ptp_clock = ptp_clock_register(&clock->caps, 1457 &phydev->mdio.dev); 1458 if (IS_ERR(clock->ptp_clock)) { 1459 err = PTR_ERR(clock->ptp_clock); 1460 goto no_register; 1461 } 1462 } else 1463 list_add_tail(&dp83640->list, &clock->phylist); 1464 1465 dp83640_clock_put(clock); 1466 return 0; 1467 1468 no_register: 1469 clock->chosen = NULL; 1470 kfree(dp83640); 1471 no_memory: 1472 dp83640_clock_put(clock); 1473 no_clock: 1474 return err; 1475 } 1476 1477 static void dp83640_remove(struct phy_device *phydev) 1478 { 1479 struct dp83640_clock *clock; 1480 struct list_head *this, *next; 1481 struct dp83640_private *tmp, *dp83640 = phydev->priv; 1482 1483 if (phydev->mdio.addr == BROADCAST_ADDR) 1484 return; 1485 1486 phydev->mii_ts = NULL; 1487 1488 enable_status_frames(phydev, false); 1489 cancel_delayed_work_sync(&dp83640->ts_work); 1490 1491 skb_queue_purge(&dp83640->rx_queue); 1492 skb_queue_purge(&dp83640->tx_queue); 1493 1494 clock = dp83640_clock_get(dp83640->clock); 1495 1496 if (dp83640 == clock->chosen) { 1497 ptp_clock_unregister(clock->ptp_clock); 1498 clock->chosen = NULL; 1499 } else { 1500 list_for_each_safe(this, next, &clock->phylist) { 1501 tmp = list_entry(this, struct dp83640_private, list); 1502 if (tmp == dp83640) { 1503 list_del_init(&tmp->list); 1504 break; 1505 } 1506 } 1507 } 1508 1509 dp83640_clock_put(clock); 1510 kfree(dp83640); 1511 } 1512 1513 static struct phy_driver dp83640_driver = { 1514 .phy_id = DP83640_PHY_ID, 1515 .phy_id_mask = 0xfffffff0, 1516 .name = "NatSemi DP83640", 1517 /* PHY_BASIC_FEATURES */ 1518 .probe = dp83640_probe, 1519 .remove = dp83640_remove, 1520 .soft_reset = dp83640_soft_reset, 1521 .config_init = dp83640_config_init, 1522 .config_intr = dp83640_config_intr, 1523 .handle_interrupt = dp83640_handle_interrupt, 1524 }; 1525 1526 static int __init dp83640_init(void) 1527 { 1528 return phy_driver_register(&dp83640_driver, THIS_MODULE); 1529 } 1530 1531 static void __exit dp83640_exit(void) 1532 { 1533 dp83640_free_clocks(); 1534 phy_driver_unregister(&dp83640_driver); 1535 } 1536 1537 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver"); 1538 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); 1539 MODULE_LICENSE("GPL"); 1540 1541 module_init(dp83640_init); 1542 module_exit(dp83640_exit); 1543 1544 static const struct mdio_device_id __maybe_unused dp83640_tbl[] = { 1545 { DP83640_PHY_ID, 0xfffffff0 }, 1546 { } 1547 }; 1548 1549 MODULE_DEVICE_TABLE(mdio, dp83640_tbl); 1550