1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates. 4 * Synopsys DesignWare XPCS helpers 5 * 6 * Author: Jose Abreu <Jose.Abreu@synopsys.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/pcs/pcs-xpcs.h> 12 #include <linux/mdio.h> 13 #include <linux/phy.h> 14 #include <linux/phylink.h> 15 #include <linux/property.h> 16 17 #include "pcs-xpcs.h" 18 19 #define phylink_pcs_to_xpcs(pl_pcs) \ 20 container_of((pl_pcs), struct dw_xpcs, pcs) 21 22 static const int xpcs_usxgmii_features[] = { 23 ETHTOOL_LINK_MODE_Pause_BIT, 24 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 25 ETHTOOL_LINK_MODE_Autoneg_BIT, 26 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 27 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 28 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 29 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 30 __ETHTOOL_LINK_MODE_MASK_NBITS, 31 }; 32 33 static const int xpcs_10gkr_features[] = { 34 ETHTOOL_LINK_MODE_Pause_BIT, 35 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 36 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 37 __ETHTOOL_LINK_MODE_MASK_NBITS, 38 }; 39 40 static const int xpcs_xlgmii_features[] = { 41 ETHTOOL_LINK_MODE_Pause_BIT, 42 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 43 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 44 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 45 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 46 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 47 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 48 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 49 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 50 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 51 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 52 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 53 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 54 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 55 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 56 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 57 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT, 58 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 59 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 60 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 61 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 62 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 63 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 64 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 65 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 66 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT, 67 __ETHTOOL_LINK_MODE_MASK_NBITS, 68 }; 69 70 static const int xpcs_10gbaser_features[] = { 71 ETHTOOL_LINK_MODE_Pause_BIT, 72 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 73 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 74 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 75 ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 76 ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 77 __ETHTOOL_LINK_MODE_MASK_NBITS, 78 }; 79 80 static const int xpcs_sgmii_features[] = { 81 ETHTOOL_LINK_MODE_Pause_BIT, 82 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 83 ETHTOOL_LINK_MODE_Autoneg_BIT, 84 ETHTOOL_LINK_MODE_10baseT_Half_BIT, 85 ETHTOOL_LINK_MODE_10baseT_Full_BIT, 86 ETHTOOL_LINK_MODE_100baseT_Half_BIT, 87 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 88 ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 89 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 90 __ETHTOOL_LINK_MODE_MASK_NBITS, 91 }; 92 93 static const int xpcs_1000basex_features[] = { 94 ETHTOOL_LINK_MODE_Pause_BIT, 95 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 96 ETHTOOL_LINK_MODE_Autoneg_BIT, 97 ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 98 __ETHTOOL_LINK_MODE_MASK_NBITS, 99 }; 100 101 static const int xpcs_2500basex_features[] = { 102 ETHTOOL_LINK_MODE_Pause_BIT, 103 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 104 ETHTOOL_LINK_MODE_Autoneg_BIT, 105 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 106 ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 107 __ETHTOOL_LINK_MODE_MASK_NBITS, 108 }; 109 110 struct dw_xpcs_compat { 111 phy_interface_t interface; 112 const int *supported; 113 int an_mode; 114 int (*pma_config)(struct dw_xpcs *xpcs); 115 }; 116 117 struct dw_xpcs_desc { 118 u32 id; 119 u32 mask; 120 const struct dw_xpcs_compat *compat; 121 }; 122 123 static const struct dw_xpcs_compat * 124 xpcs_find_compat(struct dw_xpcs *xpcs, phy_interface_t interface) 125 { 126 const struct dw_xpcs_compat *compat; 127 128 for (compat = xpcs->desc->compat; compat->supported; compat++) 129 if (compat->interface == interface) 130 return compat; 131 132 return NULL; 133 } 134 135 struct phylink_pcs *xpcs_to_phylink_pcs(struct dw_xpcs *xpcs) 136 { 137 return &xpcs->pcs; 138 } 139 EXPORT_SYMBOL_GPL(xpcs_to_phylink_pcs); 140 141 int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface) 142 { 143 const struct dw_xpcs_compat *compat; 144 145 compat = xpcs_find_compat(xpcs, interface); 146 if (!compat) 147 return -ENODEV; 148 149 return compat->an_mode; 150 } 151 EXPORT_SYMBOL_GPL(xpcs_get_an_mode); 152 153 static bool __xpcs_linkmode_supported(const struct dw_xpcs_compat *compat, 154 enum ethtool_link_mode_bit_indices linkmode) 155 { 156 int i; 157 158 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) 159 if (compat->supported[i] == linkmode) 160 return true; 161 162 return false; 163 } 164 165 #define xpcs_linkmode_supported(compat, mode) \ 166 __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT) 167 168 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg) 169 { 170 return mdiodev_c45_read(xpcs->mdiodev, dev, reg); 171 } 172 173 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val) 174 { 175 return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val); 176 } 177 178 int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set) 179 { 180 return mdiodev_c45_modify(xpcs->mdiodev, dev, reg, mask, set); 181 } 182 183 static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg, 184 u16 mask, u16 set) 185 { 186 return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set); 187 } 188 189 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg) 190 { 191 return xpcs_read(xpcs, dev, DW_VENDOR | reg); 192 } 193 194 static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg, 195 u16 val) 196 { 197 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val); 198 } 199 200 static int xpcs_modify_vendor(struct dw_xpcs *xpcs, int dev, int reg, u16 mask, 201 u16 set) 202 { 203 return xpcs_modify(xpcs, dev, DW_VENDOR | reg, mask, set); 204 } 205 206 int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg) 207 { 208 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg); 209 } 210 211 int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val) 212 { 213 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val); 214 } 215 216 static int xpcs_modify_vpcs(struct dw_xpcs *xpcs, int reg, u16 mask, u16 val) 217 { 218 return xpcs_modify_vendor(xpcs, MDIO_MMD_PCS, reg, mask, val); 219 } 220 221 static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev) 222 { 223 int ret, val; 224 225 ret = read_poll_timeout(xpcs_read, val, 226 val < 0 || !(val & BMCR_RESET), 227 50000, 600000, true, xpcs, dev, MII_BMCR); 228 if (val < 0) 229 ret = val; 230 231 return ret; 232 } 233 234 static int xpcs_soft_reset(struct dw_xpcs *xpcs, 235 const struct dw_xpcs_compat *compat) 236 { 237 int ret, dev; 238 239 switch (compat->an_mode) { 240 case DW_AN_C73: 241 case DW_10GBASER: 242 dev = MDIO_MMD_PCS; 243 break; 244 case DW_AN_C37_SGMII: 245 case DW_2500BASEX: 246 case DW_AN_C37_1000BASEX: 247 dev = MDIO_MMD_VEND2; 248 break; 249 default: 250 return -EINVAL; 251 } 252 253 ret = xpcs_write(xpcs, dev, MII_BMCR, BMCR_RESET); 254 if (ret < 0) 255 return ret; 256 257 return xpcs_poll_reset(xpcs, dev); 258 } 259 260 #define xpcs_warn(__xpcs, __state, __args...) \ 261 ({ \ 262 if ((__state)->link) \ 263 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \ 264 }) 265 266 static int xpcs_read_fault_c73(struct dw_xpcs *xpcs, 267 struct phylink_link_state *state, 268 u16 pcs_stat1) 269 { 270 int ret; 271 272 if (pcs_stat1 & MDIO_STAT1_FAULT) { 273 xpcs_warn(xpcs, state, "Link fault condition detected!\n"); 274 return -EFAULT; 275 } 276 277 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2); 278 if (ret < 0) 279 return ret; 280 281 if (ret & MDIO_STAT2_RXFAULT) 282 xpcs_warn(xpcs, state, "Receiver fault detected!\n"); 283 if (ret & MDIO_STAT2_TXFAULT) 284 xpcs_warn(xpcs, state, "Transmitter fault detected!\n"); 285 286 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS); 287 if (ret < 0) 288 return ret; 289 290 if (ret & DW_RXFIFO_ERR) { 291 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n"); 292 return -EFAULT; 293 } 294 295 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); 296 if (ret < 0) 297 return ret; 298 299 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK)) 300 xpcs_warn(xpcs, state, "Link is not locked!\n"); 301 302 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2); 303 if (ret < 0) 304 return ret; 305 306 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) { 307 xpcs_warn(xpcs, state, "Link has errors!\n"); 308 return -EFAULT; 309 } 310 311 return 0; 312 } 313 314 static void xpcs_link_up_usxgmii(struct dw_xpcs *xpcs, int speed) 315 { 316 int ret, speed_sel; 317 318 switch (speed) { 319 case SPEED_10: 320 speed_sel = DW_USXGMII_10; 321 break; 322 case SPEED_100: 323 speed_sel = DW_USXGMII_100; 324 break; 325 case SPEED_1000: 326 speed_sel = DW_USXGMII_1000; 327 break; 328 case SPEED_2500: 329 speed_sel = DW_USXGMII_2500; 330 break; 331 case SPEED_5000: 332 speed_sel = DW_USXGMII_5000; 333 break; 334 case SPEED_10000: 335 speed_sel = DW_USXGMII_10000; 336 break; 337 default: 338 /* Nothing to do here */ 339 return; 340 } 341 342 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_EN, DW_USXGMII_EN); 343 if (ret < 0) 344 goto out; 345 346 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, DW_USXGMII_SS_MASK, 347 speed_sel | DW_USXGMII_FULL); 348 if (ret < 0) 349 goto out; 350 351 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_RST, 352 DW_USXGMII_RST); 353 if (ret < 0) 354 goto out; 355 356 return; 357 358 out: 359 dev_err(&xpcs->mdiodev->dev, "%s: XPCS access returned %pe\n", 360 __func__, ERR_PTR(ret)); 361 } 362 363 static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs, 364 const struct dw_xpcs_compat *compat) 365 { 366 int ret, adv; 367 368 /* By default, in USXGMII mode XPCS operates at 10G baud and 369 * replicates data to achieve lower speeds. Hereby, in this 370 * default configuration we need to advertise all supported 371 * modes and not only the ones we want to use. 372 */ 373 374 /* SR_AN_ADV3 */ 375 adv = 0; 376 if (xpcs_linkmode_supported(compat, 2500baseX_Full)) 377 adv |= DW_C73_2500KX; 378 379 /* TODO: 5000baseKR */ 380 381 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv); 382 if (ret < 0) 383 return ret; 384 385 /* SR_AN_ADV2 */ 386 adv = 0; 387 if (xpcs_linkmode_supported(compat, 1000baseKX_Full)) 388 adv |= DW_C73_1000KX; 389 if (xpcs_linkmode_supported(compat, 10000baseKX4_Full)) 390 adv |= DW_C73_10000KX4; 391 if (xpcs_linkmode_supported(compat, 10000baseKR_Full)) 392 adv |= DW_C73_10000KR; 393 394 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv); 395 if (ret < 0) 396 return ret; 397 398 /* SR_AN_ADV1 */ 399 adv = DW_C73_AN_ADV_SF; 400 if (xpcs_linkmode_supported(compat, Pause)) 401 adv |= DW_C73_PAUSE; 402 if (xpcs_linkmode_supported(compat, Asym_Pause)) 403 adv |= DW_C73_ASYM_PAUSE; 404 405 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv); 406 } 407 408 static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs, 409 const struct dw_xpcs_compat *compat) 410 { 411 int ret; 412 413 ret = _xpcs_config_aneg_c73(xpcs, compat); 414 if (ret < 0) 415 return ret; 416 417 return xpcs_modify(xpcs, MDIO_MMD_AN, MDIO_CTRL1, 418 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART, 419 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 420 } 421 422 static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs, 423 struct phylink_link_state *state, 424 const struct dw_xpcs_compat *compat, u16 an_stat1) 425 { 426 int ret; 427 428 if (an_stat1 & MDIO_AN_STAT1_COMPLETE) { 429 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA); 430 if (ret < 0) 431 return ret; 432 433 /* Check if Aneg outcome is valid */ 434 if (!(ret & DW_C73_AN_ADV_SF)) { 435 xpcs_config_aneg_c73(xpcs, compat); 436 return 0; 437 } 438 439 return 1; 440 } 441 442 return 0; 443 } 444 445 static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs, 446 struct phylink_link_state *state, u16 an_stat1) 447 { 448 u16 lpa[3]; 449 int i, ret; 450 451 if (!(an_stat1 & MDIO_AN_STAT1_LPABLE)) { 452 phylink_clear(state->lp_advertising, Autoneg); 453 return 0; 454 } 455 456 phylink_set(state->lp_advertising, Autoneg); 457 458 /* Read Clause 73 link partner advertisement */ 459 for (i = ARRAY_SIZE(lpa); --i >= 0; ) { 460 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i); 461 if (ret < 0) 462 return ret; 463 464 lpa[i] = ret; 465 } 466 467 mii_c73_mod_linkmode(state->lp_advertising, lpa); 468 469 return 0; 470 } 471 472 static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs, 473 struct phylink_link_state *state) 474 { 475 unsigned long *adv = state->advertising; 476 int speed = SPEED_UNKNOWN; 477 int bit; 478 479 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) { 480 int new_speed = SPEED_UNKNOWN; 481 482 switch (bit) { 483 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT: 484 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT: 485 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT: 486 new_speed = SPEED_25000; 487 break; 488 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT: 489 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT: 490 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT: 491 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT: 492 new_speed = SPEED_40000; 493 break; 494 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT: 495 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT: 496 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT: 497 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT: 498 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT: 499 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT: 500 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT: 501 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT: 502 new_speed = SPEED_50000; 503 break; 504 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT: 505 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT: 506 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT: 507 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT: 508 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT: 509 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT: 510 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT: 511 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT: 512 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT: 513 new_speed = SPEED_100000; 514 break; 515 default: 516 continue; 517 } 518 519 if (new_speed > speed) 520 speed = new_speed; 521 } 522 523 return speed; 524 } 525 526 static void xpcs_resolve_pma(struct dw_xpcs *xpcs, 527 struct phylink_link_state *state) 528 { 529 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX; 530 state->duplex = DUPLEX_FULL; 531 532 switch (state->interface) { 533 case PHY_INTERFACE_MODE_10GKR: 534 state->speed = SPEED_10000; 535 break; 536 case PHY_INTERFACE_MODE_XLGMII: 537 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state); 538 break; 539 default: 540 state->speed = SPEED_UNKNOWN; 541 break; 542 } 543 } 544 545 static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported, 546 const struct phylink_link_state *state) 547 { 548 __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported) = { 0, }; 549 const struct dw_xpcs_compat *compat; 550 struct dw_xpcs *xpcs; 551 int i; 552 553 xpcs = phylink_pcs_to_xpcs(pcs); 554 compat = xpcs_find_compat(xpcs, state->interface); 555 if (!compat) 556 return -EINVAL; 557 558 /* Populate the supported link modes for this PHY interface type. 559 * FIXME: what about the port modes and autoneg bit? This masks 560 * all those away. 561 */ 562 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) 563 set_bit(compat->supported[i], xpcs_supported); 564 565 linkmode_and(supported, supported, xpcs_supported); 566 567 return 0; 568 } 569 570 static unsigned int xpcs_inband_caps(struct phylink_pcs *pcs, 571 phy_interface_t interface) 572 { 573 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 574 const struct dw_xpcs_compat *compat; 575 576 compat = xpcs_find_compat(xpcs, interface); 577 if (!compat) 578 return 0; 579 580 switch (compat->an_mode) { 581 case DW_AN_C73: 582 return LINK_INBAND_ENABLE; 583 584 case DW_AN_C37_SGMII: 585 case DW_AN_C37_1000BASEX: 586 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; 587 588 case DW_10GBASER: 589 case DW_2500BASEX: 590 return LINK_INBAND_DISABLE; 591 592 default: 593 return 0; 594 } 595 } 596 597 static void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces) 598 { 599 const struct dw_xpcs_compat *compat; 600 601 for (compat = xpcs->desc->compat; compat->supported; compat++) 602 __set_bit(compat->interface, interfaces); 603 } 604 605 static int xpcs_switch_interface_mode(struct dw_xpcs *xpcs, 606 phy_interface_t interface) 607 { 608 int ret = 0; 609 610 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 611 ret = txgbe_xpcs_switch_mode(xpcs, interface); 612 } else if (xpcs->interface != interface) { 613 if (interface == PHY_INTERFACE_MODE_SGMII) 614 xpcs->need_reset = true; 615 xpcs->interface = interface; 616 } 617 618 return ret; 619 } 620 621 static void xpcs_pre_config(struct phylink_pcs *pcs, phy_interface_t interface) 622 { 623 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 624 const struct dw_xpcs_compat *compat; 625 int ret; 626 627 ret = xpcs_switch_interface_mode(xpcs, interface); 628 if (ret) 629 dev_err(&xpcs->mdiodev->dev, "switch interface failed: %pe\n", 630 ERR_PTR(ret)); 631 632 if (!xpcs->need_reset) 633 return; 634 635 compat = xpcs_find_compat(xpcs, interface); 636 if (!compat) { 637 dev_err(&xpcs->mdiodev->dev, "unsupported interface %s\n", 638 phy_modes(interface)); 639 return; 640 } 641 642 ret = xpcs_soft_reset(xpcs, compat); 643 if (ret) 644 dev_err(&xpcs->mdiodev->dev, "soft reset failed: %pe\n", 645 ERR_PTR(ret)); 646 647 xpcs->need_reset = false; 648 } 649 650 static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, 651 unsigned int neg_mode) 652 { 653 int ret, mdio_ctrl, tx_conf; 654 u16 mask, val; 655 656 /* For AN for C37 SGMII mode, the settings are :- 657 * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case 658 it is already enabled) 659 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN) 660 * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII) 661 * DW xPCS used with DW EQoS MAC is always MAC side SGMII. 662 * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic 663 * speed/duplex mode change by HW after SGMII AN complete) 664 * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN) 665 * 666 * Note that VR_MII_MMD_CTRL is MII_BMCR. 667 * 668 * Note: Since it is MAC side SGMII, there is no need to set 669 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from 670 * PHY about the link state change after C28 AN is completed 671 * between PHY and Link Partner. There is also no need to 672 * trigger AN restart for MAC-side SGMII. 673 */ 674 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); 675 if (mdio_ctrl < 0) 676 return mdio_ctrl; 677 678 if (mdio_ctrl & BMCR_ANENABLE) { 679 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 680 mdio_ctrl & ~BMCR_ANENABLE); 681 if (ret < 0) 682 return ret; 683 } 684 685 mask = DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK; 686 val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 687 DW_VR_MII_PCS_MODE_C37_SGMII); 688 689 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 690 mask |= DW_VR_MII_AN_CTRL_8BIT; 691 val |= DW_VR_MII_AN_CTRL_8BIT; 692 /* Hardware requires it to be PHY side SGMII */ 693 tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII; 694 } else { 695 tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII; 696 } 697 698 val |= FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, tx_conf); 699 700 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); 701 if (ret < 0) 702 return ret; 703 704 val = 0; 705 mask = DW_VR_MII_DIG_CTRL1_2G5_EN | DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 706 707 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 708 val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 709 710 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 711 mask |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; 712 val |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; 713 } 714 715 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, mask, val); 716 if (ret < 0) 717 return ret; 718 719 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 720 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 721 mdio_ctrl | BMCR_ANENABLE); 722 723 return ret; 724 } 725 726 static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs, 727 unsigned int neg_mode, 728 const unsigned long *advertising) 729 { 730 phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX; 731 int ret, mdio_ctrl, adv; 732 bool changed = 0; 733 u16 mask, val; 734 735 /* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must 736 * be disabled first:- 737 * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b 738 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37) 739 * 740 * Note that VR_MII_MMD_CTRL is MII_BMCR. 741 */ 742 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); 743 if (mdio_ctrl < 0) 744 return mdio_ctrl; 745 746 if (mdio_ctrl & BMCR_ANENABLE) { 747 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 748 mdio_ctrl & ~BMCR_ANENABLE); 749 if (ret < 0) 750 return ret; 751 } 752 753 mask = DW_VR_MII_PCS_MODE_MASK; 754 val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 755 DW_VR_MII_PCS_MODE_C37_1000BASEX); 756 757 if (!xpcs->pcs.poll) { 758 mask |= DW_VR_MII_AN_INTR_EN; 759 val |= DW_VR_MII_AN_INTR_EN; 760 } 761 762 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); 763 if (ret < 0) 764 return ret; 765 766 /* Check for advertising changes and update the C45 MII ADV 767 * register accordingly. 768 */ 769 adv = phylink_mii_c22_pcs_encode_advertisement(interface, 770 advertising); 771 if (adv >= 0) { 772 ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2, 773 MII_ADVERTISE, 0xffff, adv); 774 if (ret < 0) 775 return ret; 776 777 changed = ret; 778 } 779 780 /* Clear CL37 AN complete status */ 781 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); 782 if (ret < 0) 783 return ret; 784 785 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { 786 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 787 mdio_ctrl | BMCR_ANENABLE); 788 if (ret < 0) 789 return ret; 790 } 791 792 return changed; 793 } 794 795 static int xpcs_config_2500basex(struct dw_xpcs *xpcs) 796 { 797 int ret; 798 799 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, 800 DW_VR_MII_DIG_CTRL1_2G5_EN | 801 DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW, 802 DW_VR_MII_DIG_CTRL1_2G5_EN); 803 if (ret < 0) 804 return ret; 805 806 return xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, 807 BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_SPEED100, 808 BMCR_SPEED1000); 809 } 810 811 static int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, 812 const unsigned long *advertising, 813 unsigned int neg_mode) 814 { 815 const struct dw_xpcs_compat *compat; 816 int ret; 817 818 compat = xpcs_find_compat(xpcs, interface); 819 if (!compat) 820 return -ENODEV; 821 822 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 823 /* Wangxun devices need backplane CL37 AN enabled for 824 * SGMII and 1000base-X 825 */ 826 if (interface == PHY_INTERFACE_MODE_SGMII || 827 interface == PHY_INTERFACE_MODE_1000BASEX) 828 xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, 829 DW_CL37_BP | DW_EN_VSMMD1); 830 } 831 832 switch (compat->an_mode) { 833 case DW_10GBASER: 834 break; 835 case DW_AN_C73: 836 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { 837 ret = xpcs_config_aneg_c73(xpcs, compat); 838 if (ret) 839 return ret; 840 } 841 break; 842 case DW_AN_C37_SGMII: 843 ret = xpcs_config_aneg_c37_sgmii(xpcs, neg_mode); 844 if (ret) 845 return ret; 846 break; 847 case DW_AN_C37_1000BASEX: 848 ret = xpcs_config_aneg_c37_1000basex(xpcs, neg_mode, 849 advertising); 850 if (ret) 851 return ret; 852 break; 853 case DW_2500BASEX: 854 ret = xpcs_config_2500basex(xpcs); 855 if (ret) 856 return ret; 857 break; 858 default: 859 return -EINVAL; 860 } 861 862 if (compat->pma_config) { 863 ret = compat->pma_config(xpcs); 864 if (ret) 865 return ret; 866 } 867 868 return 0; 869 } 870 871 static int xpcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 872 phy_interface_t interface, 873 const unsigned long *advertising, 874 bool permit_pause_to_mac) 875 { 876 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 877 878 return xpcs_do_config(xpcs, interface, advertising, neg_mode); 879 } 880 881 static int xpcs_get_state_c73(struct dw_xpcs *xpcs, 882 struct phylink_link_state *state, 883 const struct dw_xpcs_compat *compat) 884 { 885 bool an_enabled; 886 int pcs_stat1; 887 int an_stat1; 888 int ret; 889 890 /* The link status bit is latching-low, so it is important to 891 * avoid unnecessary re-reads of this register to avoid missing 892 * a link-down event. 893 */ 894 pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1); 895 if (pcs_stat1 < 0) { 896 state->link = false; 897 return pcs_stat1; 898 } 899 900 /* Link needs to be read first ... */ 901 state->link = !!(pcs_stat1 & MDIO_STAT1_LSTATUS); 902 903 /* ... and then we check the faults. */ 904 ret = xpcs_read_fault_c73(xpcs, state, pcs_stat1); 905 if (ret) { 906 ret = xpcs_soft_reset(xpcs, compat); 907 if (ret) 908 return ret; 909 910 state->link = 0; 911 912 return xpcs_do_config(xpcs, state->interface, NULL, 913 PHYLINK_PCS_NEG_INBAND_ENABLED); 914 } 915 916 /* There is no point doing anything else if the link is down. */ 917 if (!state->link) 918 return 0; 919 920 an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 921 state->advertising); 922 if (an_enabled) { 923 /* The link status bit is latching-low, so it is important to 924 * avoid unnecessary re-reads of this register to avoid missing 925 * a link-down event. 926 */ 927 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); 928 if (an_stat1 < 0) { 929 state->link = false; 930 return an_stat1; 931 } 932 933 state->an_complete = xpcs_aneg_done_c73(xpcs, state, compat, 934 an_stat1); 935 if (!state->an_complete) { 936 state->link = false; 937 return 0; 938 } 939 940 ret = xpcs_read_lpa_c73(xpcs, state, an_stat1); 941 if (ret < 0) { 942 state->link = false; 943 return ret; 944 } 945 946 phylink_resolve_c73(state); 947 } else { 948 xpcs_resolve_pma(xpcs, state); 949 } 950 951 return 0; 952 } 953 954 static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs, 955 struct phylink_link_state *state) 956 { 957 int ret; 958 959 /* Reset link_state */ 960 state->link = false; 961 state->speed = SPEED_UNKNOWN; 962 state->duplex = DUPLEX_UNKNOWN; 963 state->pause = 0; 964 965 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link 966 * status, speed and duplex. 967 */ 968 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); 969 if (ret < 0) 970 return ret; 971 972 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) { 973 int speed_value; 974 975 state->link = true; 976 977 speed_value = FIELD_GET(DW_VR_MII_AN_STS_C37_ANSGM_SP, ret); 978 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000) 979 state->speed = SPEED_1000; 980 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100) 981 state->speed = SPEED_100; 982 else 983 state->speed = SPEED_10; 984 985 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD) 986 state->duplex = DUPLEX_FULL; 987 else 988 state->duplex = DUPLEX_HALF; 989 } else if (ret == DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) { 990 int speed, duplex; 991 992 state->link = true; 993 994 speed = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); 995 if (speed < 0) 996 return speed; 997 998 speed &= BMCR_SPEED100 | BMCR_SPEED1000; 999 if (speed == BMCR_SPEED1000) 1000 state->speed = SPEED_1000; 1001 else if (speed == BMCR_SPEED100) 1002 state->speed = SPEED_100; 1003 else if (speed == 0) 1004 state->speed = SPEED_10; 1005 1006 duplex = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE); 1007 if (duplex < 0) 1008 return duplex; 1009 1010 if (duplex & ADVERTISE_1000XFULL) 1011 state->duplex = DUPLEX_FULL; 1012 else if (duplex & ADVERTISE_1000XHALF) 1013 state->duplex = DUPLEX_HALF; 1014 1015 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); 1016 } 1017 1018 return 0; 1019 } 1020 1021 static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs, 1022 unsigned int neg_mode, 1023 struct phylink_link_state *state) 1024 { 1025 int lpa, bmsr; 1026 1027 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1028 state->advertising)) { 1029 /* Reset link state */ 1030 state->link = false; 1031 1032 lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA); 1033 if (lpa < 0 || lpa & LPA_RFAULT) 1034 return lpa; 1035 1036 bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); 1037 if (bmsr < 0) 1038 return bmsr; 1039 1040 /* Clear AN complete interrupt */ 1041 if (!xpcs->pcs.poll) { 1042 int an_intr; 1043 1044 an_intr = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); 1045 if (an_intr & DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) { 1046 an_intr &= ~DW_VR_MII_AN_STS_C37_ANCMPLT_INTR; 1047 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, an_intr); 1048 } 1049 } 1050 1051 phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa); 1052 } 1053 1054 return 0; 1055 } 1056 1057 static int xpcs_get_state_2500basex(struct dw_xpcs *xpcs, 1058 struct phylink_link_state *state) 1059 { 1060 int ret; 1061 1062 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); 1063 if (ret < 0) { 1064 state->link = 0; 1065 return ret; 1066 } 1067 1068 state->link = !!(ret & BMSR_LSTATUS); 1069 if (!state->link) 1070 return 0; 1071 1072 state->speed = SPEED_2500; 1073 state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX; 1074 state->duplex = DUPLEX_FULL; 1075 1076 return 0; 1077 } 1078 1079 static void xpcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, 1080 struct phylink_link_state *state) 1081 { 1082 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1083 const struct dw_xpcs_compat *compat; 1084 int ret; 1085 1086 compat = xpcs_find_compat(xpcs, state->interface); 1087 if (!compat) 1088 return; 1089 1090 switch (compat->an_mode) { 1091 case DW_10GBASER: 1092 phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state); 1093 break; 1094 case DW_AN_C73: 1095 ret = xpcs_get_state_c73(xpcs, state, compat); 1096 if (ret) 1097 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1098 "xpcs_get_state_c73", ERR_PTR(ret)); 1099 break; 1100 case DW_AN_C37_SGMII: 1101 ret = xpcs_get_state_c37_sgmii(xpcs, state); 1102 if (ret) 1103 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1104 "xpcs_get_state_c37_sgmii", ERR_PTR(ret)); 1105 break; 1106 case DW_AN_C37_1000BASEX: 1107 ret = xpcs_get_state_c37_1000basex(xpcs, neg_mode, state); 1108 if (ret) 1109 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1110 "xpcs_get_state_c37_1000basex", ERR_PTR(ret)); 1111 break; 1112 case DW_2500BASEX: 1113 ret = xpcs_get_state_2500basex(xpcs, state); 1114 if (ret) 1115 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1116 "xpcs_get_state_2500basex", ERR_PTR(ret)); 1117 break; 1118 default: 1119 return; 1120 } 1121 } 1122 1123 static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs, 1124 unsigned int neg_mode, 1125 phy_interface_t interface, 1126 int speed, int duplex) 1127 { 1128 int ret; 1129 1130 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 1131 return; 1132 1133 if (interface == PHY_INTERFACE_MODE_1000BASEX) { 1134 if (speed != SPEED_1000) { 1135 dev_err(&xpcs->mdiodev->dev, 1136 "%s: speed %dMbps not supported\n", 1137 __func__, speed); 1138 return; 1139 } 1140 1141 if (duplex != DUPLEX_FULL) 1142 dev_err(&xpcs->mdiodev->dev, 1143 "%s: half duplex not supported\n", 1144 __func__); 1145 } 1146 1147 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 1148 mii_bmcr_encode_fixed(speed, duplex)); 1149 if (ret) 1150 dev_err(&xpcs->mdiodev->dev, "%s: xpcs_write returned %pe\n", 1151 __func__, ERR_PTR(ret)); 1152 } 1153 1154 static void xpcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, 1155 phy_interface_t interface, int speed, int duplex) 1156 { 1157 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1158 1159 switch (interface) { 1160 case PHY_INTERFACE_MODE_USXGMII: 1161 xpcs_link_up_usxgmii(xpcs, speed); 1162 break; 1163 1164 case PHY_INTERFACE_MODE_SGMII: 1165 case PHY_INTERFACE_MODE_1000BASEX: 1166 xpcs_link_up_sgmii_1000basex(xpcs, neg_mode, interface, speed, 1167 duplex); 1168 break; 1169 1170 default: 1171 break; 1172 } 1173 } 1174 1175 static void xpcs_an_restart(struct phylink_pcs *pcs) 1176 { 1177 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1178 1179 xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, BMCR_ANRESTART, 1180 BMCR_ANRESTART); 1181 } 1182 1183 static int xpcs_config_eee(struct dw_xpcs *xpcs, bool enable) 1184 { 1185 u16 mask, val; 1186 int ret; 1187 1188 mask = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 1189 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 1190 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 1191 DW_VR_MII_EEE_MULT_FACT_100NS; 1192 1193 if (enable) 1194 val = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 1195 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 1196 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 1197 FIELD_PREP(DW_VR_MII_EEE_MULT_FACT_100NS, 1198 xpcs->eee_mult_fact); 1199 else 1200 val = 0; 1201 1202 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, mask, 1203 val); 1204 if (ret < 0) 1205 return ret; 1206 1207 return xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, 1208 DW_VR_MII_EEE_TRN_LPI, 1209 enable ? DW_VR_MII_EEE_TRN_LPI : 0); 1210 } 1211 1212 static void xpcs_disable_eee(struct phylink_pcs *pcs) 1213 { 1214 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1215 1216 xpcs_config_eee(xpcs, false); 1217 } 1218 1219 static void xpcs_enable_eee(struct phylink_pcs *pcs) 1220 { 1221 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1222 1223 xpcs_config_eee(xpcs, true); 1224 } 1225 1226 /** 1227 * xpcs_config_eee_mult_fact() - set the EEE clock multiplying factor 1228 * @xpcs: pointer to a &struct dw_xpcs instance 1229 * @mult_fact: the multiplying factor 1230 * 1231 * Configure the EEE clock multiplying factor. This value should be such that 1232 * clk_eee_time_period * (mult_fact + 1) is within the range 80 to 120ns. 1233 */ 1234 void xpcs_config_eee_mult_fact(struct dw_xpcs *xpcs, u8 mult_fact) 1235 { 1236 xpcs->eee_mult_fact = mult_fact; 1237 } 1238 EXPORT_SYMBOL_GPL(xpcs_config_eee_mult_fact); 1239 1240 static int xpcs_read_ids(struct dw_xpcs *xpcs) 1241 { 1242 int ret; 1243 u32 id; 1244 1245 /* First, search C73 PCS using PCS MMD 3. Return ENODEV if communication 1246 * failed indicating that device couldn't be reached. 1247 */ 1248 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1); 1249 if (ret < 0) 1250 return -ENODEV; 1251 1252 id = ret << 16; 1253 1254 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2); 1255 if (ret < 0) 1256 return ret; 1257 1258 id |= ret; 1259 1260 /* If Device IDs are not all zeros or ones, then 10GBase-X/R or C73 1261 * KR/KX4 PCS found. Otherwise fallback to detecting 1000Base-X or C37 1262 * PCS in MII MMD 31. 1263 */ 1264 if (!id || id == 0xffffffff) { 1265 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1); 1266 if (ret < 0) 1267 return ret; 1268 1269 id = ret << 16; 1270 1271 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2); 1272 if (ret < 0) 1273 return ret; 1274 1275 id |= ret; 1276 } 1277 1278 /* Set the PCS ID if it hasn't been pre-initialized */ 1279 if (xpcs->info.pcs == DW_XPCS_ID_NATIVE) 1280 xpcs->info.pcs = id; 1281 1282 /* Find out PMA/PMD ID from MMD 1 device ID registers */ 1283 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID1); 1284 if (ret < 0) 1285 return ret; 1286 1287 id = ret; 1288 1289 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID2); 1290 if (ret < 0) 1291 return ret; 1292 1293 /* Note the inverted dword order and masked out Model/Revision numbers 1294 * with respect to what is done with the PCS ID... 1295 */ 1296 ret = (ret >> 10) & 0x3F; 1297 id |= ret << 16; 1298 1299 /* Set the PMA ID if it hasn't been pre-initialized */ 1300 if (xpcs->info.pma == DW_XPCS_PMA_ID_NATIVE) 1301 xpcs->info.pma = id; 1302 1303 return 0; 1304 } 1305 1306 static const struct dw_xpcs_compat synopsys_xpcs_compat[] = { 1307 { 1308 .interface = PHY_INTERFACE_MODE_USXGMII, 1309 .supported = xpcs_usxgmii_features, 1310 .an_mode = DW_AN_C73, 1311 }, { 1312 .interface = PHY_INTERFACE_MODE_10GKR, 1313 .supported = xpcs_10gkr_features, 1314 .an_mode = DW_AN_C73, 1315 }, { 1316 .interface = PHY_INTERFACE_MODE_XLGMII, 1317 .supported = xpcs_xlgmii_features, 1318 .an_mode = DW_AN_C73, 1319 }, { 1320 .interface = PHY_INTERFACE_MODE_10GBASER, 1321 .supported = xpcs_10gbaser_features, 1322 .an_mode = DW_10GBASER, 1323 }, { 1324 .interface = PHY_INTERFACE_MODE_SGMII, 1325 .supported = xpcs_sgmii_features, 1326 .an_mode = DW_AN_C37_SGMII, 1327 }, { 1328 .interface = PHY_INTERFACE_MODE_1000BASEX, 1329 .supported = xpcs_1000basex_features, 1330 .an_mode = DW_AN_C37_1000BASEX, 1331 }, { 1332 .interface = PHY_INTERFACE_MODE_2500BASEX, 1333 .supported = xpcs_2500basex_features, 1334 .an_mode = DW_2500BASEX, 1335 }, { 1336 } 1337 }; 1338 1339 static const struct dw_xpcs_compat nxp_sja1105_xpcs_compat[] = { 1340 { 1341 .interface = PHY_INTERFACE_MODE_SGMII, 1342 .supported = xpcs_sgmii_features, 1343 .an_mode = DW_AN_C37_SGMII, 1344 .pma_config = nxp_sja1105_sgmii_pma_config, 1345 }, { 1346 } 1347 }; 1348 1349 static const struct dw_xpcs_compat nxp_sja1110_xpcs_compat[] = { 1350 { 1351 .interface = PHY_INTERFACE_MODE_SGMII, 1352 .supported = xpcs_sgmii_features, 1353 .an_mode = DW_AN_C37_SGMII, 1354 .pma_config = nxp_sja1110_sgmii_pma_config, 1355 }, { 1356 .interface = PHY_INTERFACE_MODE_2500BASEX, 1357 .supported = xpcs_2500basex_features, 1358 .an_mode = DW_2500BASEX, 1359 .pma_config = nxp_sja1110_2500basex_pma_config, 1360 }, { 1361 } 1362 }; 1363 1364 static const struct dw_xpcs_desc xpcs_desc_list[] = { 1365 { 1366 .id = DW_XPCS_ID, 1367 .mask = DW_XPCS_ID_MASK, 1368 .compat = synopsys_xpcs_compat, 1369 }, { 1370 .id = NXP_SJA1105_XPCS_ID, 1371 .mask = DW_XPCS_ID_MASK, 1372 .compat = nxp_sja1105_xpcs_compat, 1373 }, { 1374 .id = NXP_SJA1110_XPCS_ID, 1375 .mask = DW_XPCS_ID_MASK, 1376 .compat = nxp_sja1110_xpcs_compat, 1377 }, 1378 }; 1379 1380 static const struct phylink_pcs_ops xpcs_phylink_ops = { 1381 .pcs_validate = xpcs_validate, 1382 .pcs_inband_caps = xpcs_inband_caps, 1383 .pcs_pre_config = xpcs_pre_config, 1384 .pcs_config = xpcs_config, 1385 .pcs_get_state = xpcs_get_state, 1386 .pcs_an_restart = xpcs_an_restart, 1387 .pcs_link_up = xpcs_link_up, 1388 .pcs_disable_eee = xpcs_disable_eee, 1389 .pcs_enable_eee = xpcs_enable_eee, 1390 }; 1391 1392 static int xpcs_identify(struct dw_xpcs *xpcs) 1393 { 1394 int i, ret; 1395 1396 ret = xpcs_read_ids(xpcs); 1397 if (ret < 0) 1398 return ret; 1399 1400 for (i = 0; i < ARRAY_SIZE(xpcs_desc_list); i++) { 1401 const struct dw_xpcs_desc *entry = &xpcs_desc_list[i]; 1402 1403 if ((xpcs->info.pcs & entry->mask) == entry->id) { 1404 xpcs->desc = entry; 1405 return 0; 1406 } 1407 } 1408 1409 return -ENODEV; 1410 } 1411 1412 static struct dw_xpcs *xpcs_create_data(struct mdio_device *mdiodev) 1413 { 1414 struct dw_xpcs *xpcs; 1415 1416 xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL); 1417 if (!xpcs) 1418 return ERR_PTR(-ENOMEM); 1419 1420 mdio_device_get(mdiodev); 1421 xpcs->mdiodev = mdiodev; 1422 xpcs->pcs.ops = &xpcs_phylink_ops; 1423 xpcs->pcs.poll = true; 1424 1425 return xpcs; 1426 } 1427 1428 static void xpcs_free_data(struct dw_xpcs *xpcs) 1429 { 1430 mdio_device_put(xpcs->mdiodev); 1431 kfree(xpcs); 1432 } 1433 1434 static int xpcs_init_clks(struct dw_xpcs *xpcs) 1435 { 1436 static const char *ids[DW_XPCS_NUM_CLKS] = { 1437 [DW_XPCS_CORE_CLK] = "core", 1438 [DW_XPCS_PAD_CLK] = "pad", 1439 }; 1440 struct device *dev = &xpcs->mdiodev->dev; 1441 int ret, i; 1442 1443 for (i = 0; i < DW_XPCS_NUM_CLKS; ++i) 1444 xpcs->clks[i].id = ids[i]; 1445 1446 ret = clk_bulk_get_optional(dev, DW_XPCS_NUM_CLKS, xpcs->clks); 1447 if (ret) 1448 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1449 1450 ret = clk_bulk_prepare_enable(DW_XPCS_NUM_CLKS, xpcs->clks); 1451 if (ret) 1452 return dev_err_probe(dev, ret, "Failed to enable clocks\n"); 1453 1454 return 0; 1455 } 1456 1457 static void xpcs_clear_clks(struct dw_xpcs *xpcs) 1458 { 1459 clk_bulk_disable_unprepare(DW_XPCS_NUM_CLKS, xpcs->clks); 1460 1461 clk_bulk_put(DW_XPCS_NUM_CLKS, xpcs->clks); 1462 } 1463 1464 static int xpcs_init_id(struct dw_xpcs *xpcs) 1465 { 1466 const struct dw_xpcs_info *info; 1467 1468 info = dev_get_platdata(&xpcs->mdiodev->dev); 1469 if (!info) { 1470 xpcs->info.pcs = DW_XPCS_ID_NATIVE; 1471 xpcs->info.pma = DW_XPCS_PMA_ID_NATIVE; 1472 } else { 1473 xpcs->info = *info; 1474 } 1475 1476 return xpcs_identify(xpcs); 1477 } 1478 1479 static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev) 1480 { 1481 struct dw_xpcs *xpcs; 1482 int ret; 1483 1484 xpcs = xpcs_create_data(mdiodev); 1485 if (IS_ERR(xpcs)) 1486 return xpcs; 1487 1488 ret = xpcs_init_clks(xpcs); 1489 if (ret) 1490 goto out_free_data; 1491 1492 ret = xpcs_init_id(xpcs); 1493 if (ret) 1494 goto out_clear_clks; 1495 1496 xpcs_get_interfaces(xpcs, xpcs->pcs.supported_interfaces); 1497 1498 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) 1499 xpcs->pcs.poll = false; 1500 else 1501 xpcs->need_reset = true; 1502 1503 return xpcs; 1504 1505 out_clear_clks: 1506 xpcs_clear_clks(xpcs); 1507 1508 out_free_data: 1509 xpcs_free_data(xpcs); 1510 1511 return ERR_PTR(ret); 1512 } 1513 1514 /** 1515 * xpcs_create_mdiodev() - create a DW xPCS instance with the MDIO @addr 1516 * @bus: pointer to the MDIO-bus descriptor for the device to be looked at 1517 * @addr: device MDIO-bus ID 1518 * 1519 * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if 1520 * the PCS device couldn't be found on the bus and other negative errno related 1521 * to the data allocation and MDIO-bus communications. 1522 */ 1523 struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr) 1524 { 1525 struct mdio_device *mdiodev; 1526 struct dw_xpcs *xpcs; 1527 1528 mdiodev = mdio_device_create(bus, addr); 1529 if (IS_ERR(mdiodev)) 1530 return ERR_CAST(mdiodev); 1531 1532 xpcs = xpcs_create(mdiodev); 1533 1534 /* xpcs_create() has taken a refcount on the mdiodev if it was 1535 * successful. If xpcs_create() fails, this will free the mdio 1536 * device here. In any case, we don't need to hold our reference 1537 * anymore, and putting it here will allow mdio_device_put() in 1538 * xpcs_destroy() to automatically free the mdio device. 1539 */ 1540 mdio_device_put(mdiodev); 1541 1542 return xpcs; 1543 } 1544 EXPORT_SYMBOL_GPL(xpcs_create_mdiodev); 1545 1546 struct phylink_pcs *xpcs_create_pcs_mdiodev(struct mii_bus *bus, int addr) 1547 { 1548 struct dw_xpcs *xpcs; 1549 1550 xpcs = xpcs_create_mdiodev(bus, addr); 1551 if (IS_ERR(xpcs)) 1552 return ERR_CAST(xpcs); 1553 1554 return &xpcs->pcs; 1555 } 1556 EXPORT_SYMBOL_GPL(xpcs_create_pcs_mdiodev); 1557 1558 /** 1559 * xpcs_create_fwnode() - Create a DW xPCS instance from @fwnode 1560 * @fwnode: fwnode handle poining to the DW XPCS device 1561 * 1562 * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if 1563 * the fwnode device is unavailable or the PCS device couldn't be found on the 1564 * bus, -EPROBE_DEFER if the respective MDIO-device instance couldn't be found, 1565 * other negative errno related to the data allocations and MDIO-bus 1566 * communications. 1567 */ 1568 struct dw_xpcs *xpcs_create_fwnode(struct fwnode_handle *fwnode) 1569 { 1570 struct mdio_device *mdiodev; 1571 struct dw_xpcs *xpcs; 1572 1573 if (!fwnode_device_is_available(fwnode)) 1574 return ERR_PTR(-ENODEV); 1575 1576 mdiodev = fwnode_mdio_find_device(fwnode); 1577 if (!mdiodev) 1578 return ERR_PTR(-EPROBE_DEFER); 1579 1580 xpcs = xpcs_create(mdiodev); 1581 1582 /* xpcs_create() has taken a refcount on the mdiodev if it was 1583 * successful. If xpcs_create() fails, this will free the mdio 1584 * device here. In any case, we don't need to hold our reference 1585 * anymore, and putting it here will allow mdio_device_put() in 1586 * xpcs_destroy() to automatically free the mdio device. 1587 */ 1588 mdio_device_put(mdiodev); 1589 1590 return xpcs; 1591 } 1592 EXPORT_SYMBOL_GPL(xpcs_create_fwnode); 1593 1594 void xpcs_destroy(struct dw_xpcs *xpcs) 1595 { 1596 if (!xpcs) 1597 return; 1598 1599 xpcs_clear_clks(xpcs); 1600 1601 xpcs_free_data(xpcs); 1602 } 1603 EXPORT_SYMBOL_GPL(xpcs_destroy); 1604 1605 void xpcs_destroy_pcs(struct phylink_pcs *pcs) 1606 { 1607 xpcs_destroy(phylink_pcs_to_xpcs(pcs)); 1608 } 1609 EXPORT_SYMBOL_GPL(xpcs_destroy_pcs); 1610 1611 MODULE_DESCRIPTION("Synopsys DesignWare XPCS library"); 1612 MODULE_LICENSE("GPL v2"); 1613