1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022 Schneider Electric 4 * 5 * Clément Léger <clement.leger@bootlin.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/device.h> 10 #include <linux/mdio.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/pcs-rzn1-miic.h> 14 #include <linux/phylink.h> 15 #include <linux/pm_runtime.h> 16 #include <dt-bindings/net/pcs-rzn1-miic.h> 17 18 #define MIIC_PRCMD 0x0 19 #define MIIC_ESID_CODE 0x4 20 21 #define MIIC_MODCTRL 0x20 22 #define MIIC_MODCTRL_SW_MODE GENMASK(4, 0) 23 24 #define MIIC_CONVCTRL(port) (0x100 + (port) * 4) 25 26 #define MIIC_CONVCTRL_CONV_SPEED GENMASK(1, 0) 27 #define CONV_MODE_10MBPS 0 28 #define CONV_MODE_100MBPS 1 29 #define CONV_MODE_1000MBPS 2 30 31 #define MIIC_CONVCTRL_CONV_MODE GENMASK(3, 2) 32 #define CONV_MODE_MII 0 33 #define CONV_MODE_RMII 1 34 #define CONV_MODE_RGMII 2 35 36 #define MIIC_CONVCTRL_FULLD BIT(8) 37 #define MIIC_CONVCTRL_RGMII_LINK BIT(12) 38 #define MIIC_CONVCTRL_RGMII_DUPLEX BIT(13) 39 #define MIIC_CONVCTRL_RGMII_SPEED GENMASK(15, 14) 40 41 #define MIIC_CONVRST 0x114 42 #define MIIC_CONVRST_PHYIF_RST(port) BIT(port) 43 #define MIIC_CONVRST_PHYIF_RST_MASK GENMASK(4, 0) 44 45 #define MIIC_SWCTRL 0x304 46 #define MIIC_SWDUPC 0x308 47 48 #define MIIC_MAX_NR_PORTS 5 49 50 #define MIIC_MODCTRL_CONF_CONV_NUM 6 51 #define MIIC_MODCTRL_CONF_NONE -1 52 53 /** 54 * struct modctrl_match - Matching table entry for convctrl configuration 55 * See section 8.2.1 of manual. 56 * @mode_cfg: Configuration value for convctrl 57 * @conv: Configuration of ethernet port muxes. First index is SWITCH_PORTIN, 58 * then index 1 - 5 are CONV1 - CONV5. 59 */ 60 struct modctrl_match { 61 u32 mode_cfg; 62 u8 conv[MIIC_MODCTRL_CONF_CONV_NUM]; 63 }; 64 65 static struct modctrl_match modctrl_match_table[] = { 66 {0x0, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 67 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 68 {0x1, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 69 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 70 {0x2, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 71 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 72 {0x3, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 73 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}, 74 75 {0x8, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 76 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 77 {0x9, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 78 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 79 {0xA, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 80 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 81 {0xB, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 82 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}, 83 84 {0x10, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 85 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 86 {0x11, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 87 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 88 {0x12, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 89 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 90 {0x13, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 91 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}} 92 }; 93 94 static const char * const conf_to_string[] = { 95 [MIIC_GMAC1_PORT] = "GMAC1_PORT", 96 [MIIC_GMAC2_PORT] = "GMAC2_PORT", 97 [MIIC_RTOS_PORT] = "RTOS_PORT", 98 [MIIC_SERCOS_PORTA] = "SERCOS_PORTA", 99 [MIIC_SERCOS_PORTB] = "SERCOS_PORTB", 100 [MIIC_ETHERCAT_PORTA] = "ETHERCAT_PORTA", 101 [MIIC_ETHERCAT_PORTB] = "ETHERCAT_PORTB", 102 [MIIC_ETHERCAT_PORTC] = "ETHERCAT_PORTC", 103 [MIIC_SWITCH_PORTA] = "SWITCH_PORTA", 104 [MIIC_SWITCH_PORTB] = "SWITCH_PORTB", 105 [MIIC_SWITCH_PORTC] = "SWITCH_PORTC", 106 [MIIC_SWITCH_PORTD] = "SWITCH_PORTD", 107 [MIIC_HSR_PORTA] = "HSR_PORTA", 108 [MIIC_HSR_PORTB] = "HSR_PORTB", 109 }; 110 111 static const char *index_to_string[MIIC_MODCTRL_CONF_CONV_NUM] = { 112 "SWITCH_PORTIN", 113 "CONV1", 114 "CONV2", 115 "CONV3", 116 "CONV4", 117 "CONV5", 118 }; 119 120 /** 121 * struct miic - MII converter structure 122 * @base: base address of the MII converter 123 * @dev: Device associated to the MII converter 124 * @lock: Lock used for read-modify-write access 125 */ 126 struct miic { 127 void __iomem *base; 128 struct device *dev; 129 spinlock_t lock; 130 }; 131 132 /** 133 * struct miic_port - Per port MII converter struct 134 * @miic: backiling to MII converter structure 135 * @pcs: PCS structure associated to the port 136 * @port: port number 137 * @interface: interface mode of the port 138 */ 139 struct miic_port { 140 struct miic *miic; 141 struct phylink_pcs pcs; 142 int port; 143 phy_interface_t interface; 144 }; 145 146 static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs) 147 { 148 return container_of(pcs, struct miic_port, pcs); 149 } 150 151 static void miic_reg_writel(struct miic *miic, int offset, u32 value) 152 { 153 writel(value, miic->base + offset); 154 } 155 156 static u32 miic_reg_readl(struct miic *miic, int offset) 157 { 158 return readl(miic->base + offset); 159 } 160 161 static void miic_reg_rmw(struct miic *miic, int offset, u32 mask, u32 val) 162 { 163 u32 reg; 164 165 spin_lock(&miic->lock); 166 167 reg = miic_reg_readl(miic, offset); 168 reg &= ~mask; 169 reg |= val; 170 miic_reg_writel(miic, offset, reg); 171 172 spin_unlock(&miic->lock); 173 } 174 175 static void miic_converter_enable(struct miic *miic, int port, int enable) 176 { 177 u32 val = 0; 178 179 if (enable) 180 val = MIIC_CONVRST_PHYIF_RST(port); 181 182 miic_reg_rmw(miic, MIIC_CONVRST, MIIC_CONVRST_PHYIF_RST(port), val); 183 } 184 185 static int miic_config(struct phylink_pcs *pcs, unsigned int mode, 186 phy_interface_t interface, 187 const unsigned long *advertising, bool permit) 188 { 189 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 190 struct miic *miic = miic_port->miic; 191 u32 speed, conv_mode, val, mask; 192 int port = miic_port->port; 193 194 switch (interface) { 195 case PHY_INTERFACE_MODE_RMII: 196 conv_mode = CONV_MODE_RMII; 197 speed = CONV_MODE_100MBPS; 198 break; 199 case PHY_INTERFACE_MODE_RGMII: 200 case PHY_INTERFACE_MODE_RGMII_ID: 201 case PHY_INTERFACE_MODE_RGMII_TXID: 202 case PHY_INTERFACE_MODE_RGMII_RXID: 203 conv_mode = CONV_MODE_RGMII; 204 speed = CONV_MODE_1000MBPS; 205 break; 206 case PHY_INTERFACE_MODE_MII: 207 conv_mode = CONV_MODE_MII; 208 /* When in MII mode, speed should be set to 0 (which is actually 209 * CONV_MODE_10MBPS) 210 */ 211 speed = CONV_MODE_10MBPS; 212 break; 213 default: 214 return -EOPNOTSUPP; 215 } 216 217 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, conv_mode); 218 mask = MIIC_CONVCTRL_CONV_MODE; 219 220 /* Update speed only if we are going to change the interface because 221 * the link might already be up and it would break it if the speed is 222 * changed. 223 */ 224 if (interface != miic_port->interface) { 225 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, speed); 226 mask |= MIIC_CONVCTRL_CONV_SPEED; 227 miic_port->interface = interface; 228 } 229 230 miic_reg_rmw(miic, MIIC_CONVCTRL(port), mask, val); 231 miic_converter_enable(miic, miic_port->port, 1); 232 233 return 0; 234 } 235 236 static void miic_link_up(struct phylink_pcs *pcs, unsigned int mode, 237 phy_interface_t interface, int speed, int duplex) 238 { 239 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 240 struct miic *miic = miic_port->miic; 241 u32 conv_speed = 0, val = 0; 242 int port = miic_port->port; 243 244 if (duplex == DUPLEX_FULL) 245 val |= MIIC_CONVCTRL_FULLD; 246 247 /* No speed in MII through-mode */ 248 if (interface != PHY_INTERFACE_MODE_MII) { 249 switch (speed) { 250 case SPEED_1000: 251 conv_speed = CONV_MODE_1000MBPS; 252 break; 253 case SPEED_100: 254 conv_speed = CONV_MODE_100MBPS; 255 break; 256 case SPEED_10: 257 conv_speed = CONV_MODE_10MBPS; 258 break; 259 default: 260 return; 261 } 262 } 263 264 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, conv_speed); 265 266 miic_reg_rmw(miic, MIIC_CONVCTRL(port), 267 (MIIC_CONVCTRL_CONV_SPEED | MIIC_CONVCTRL_FULLD), val); 268 } 269 270 static int miic_validate(struct phylink_pcs *pcs, unsigned long *supported, 271 const struct phylink_link_state *state) 272 { 273 if (phy_interface_mode_is_rgmii(state->interface) || 274 state->interface == PHY_INTERFACE_MODE_RMII || 275 state->interface == PHY_INTERFACE_MODE_MII) 276 return 1; 277 278 return -EINVAL; 279 } 280 281 static const struct phylink_pcs_ops miic_phylink_ops = { 282 .pcs_validate = miic_validate, 283 .pcs_config = miic_config, 284 .pcs_link_up = miic_link_up, 285 }; 286 287 struct phylink_pcs *miic_create(struct device *dev, struct device_node *np) 288 { 289 struct platform_device *pdev; 290 struct miic_port *miic_port; 291 struct device_node *pcs_np; 292 struct miic *miic; 293 u32 port; 294 295 if (!of_device_is_available(np)) 296 return ERR_PTR(-ENODEV); 297 298 if (of_property_read_u32(np, "reg", &port)) 299 return ERR_PTR(-EINVAL); 300 301 if (port > MIIC_MAX_NR_PORTS || port < 1) 302 return ERR_PTR(-EINVAL); 303 304 /* The PCS pdev is attached to the parent node */ 305 pcs_np = of_get_parent(np); 306 if (!pcs_np) 307 return ERR_PTR(-ENODEV); 308 309 if (!of_device_is_available(pcs_np)) { 310 of_node_put(pcs_np); 311 return ERR_PTR(-ENODEV); 312 } 313 314 pdev = of_find_device_by_node(pcs_np); 315 of_node_put(pcs_np); 316 if (!pdev || !platform_get_drvdata(pdev)) { 317 if (pdev) 318 put_device(&pdev->dev); 319 return ERR_PTR(-EPROBE_DEFER); 320 } 321 322 miic_port = kzalloc(sizeof(*miic_port), GFP_KERNEL); 323 if (!miic_port) { 324 put_device(&pdev->dev); 325 return ERR_PTR(-ENOMEM); 326 } 327 328 miic = platform_get_drvdata(pdev); 329 device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER); 330 put_device(&pdev->dev); 331 332 miic_port->miic = miic; 333 miic_port->port = port - 1; 334 miic_port->pcs.ops = &miic_phylink_ops; 335 336 return &miic_port->pcs; 337 } 338 EXPORT_SYMBOL(miic_create); 339 340 void miic_destroy(struct phylink_pcs *pcs) 341 { 342 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 343 344 miic_converter_enable(miic_port->miic, miic_port->port, 0); 345 kfree(miic_port); 346 } 347 EXPORT_SYMBOL(miic_destroy); 348 349 static int miic_init_hw(struct miic *miic, u32 cfg_mode) 350 { 351 int port; 352 353 /* Unlock write access to accessory registers (cf datasheet). If this 354 * is going to be used in conjunction with the Cortex-M3, this sequence 355 * will have to be moved in register write 356 */ 357 miic_reg_writel(miic, MIIC_PRCMD, 0x00A5); 358 miic_reg_writel(miic, MIIC_PRCMD, 0x0001); 359 miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE); 360 miic_reg_writel(miic, MIIC_PRCMD, 0x0001); 361 362 miic_reg_writel(miic, MIIC_MODCTRL, 363 FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode)); 364 365 for (port = 0; port < MIIC_MAX_NR_PORTS; port++) { 366 miic_converter_enable(miic, port, 0); 367 /* Disable speed/duplex control from these registers, datasheet 368 * says switch registers should be used to setup switch port 369 * speed and duplex. 370 */ 371 miic_reg_writel(miic, MIIC_SWCTRL, 0x0); 372 miic_reg_writel(miic, MIIC_SWDUPC, 0x0); 373 } 374 375 return 0; 376 } 377 378 static bool miic_modctrl_match(s8 table_val[MIIC_MODCTRL_CONF_CONV_NUM], 379 s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM]) 380 { 381 int i; 382 383 for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) { 384 if (dt_val[i] == MIIC_MODCTRL_CONF_NONE) 385 continue; 386 387 if (dt_val[i] != table_val[i]) 388 return false; 389 } 390 391 return true; 392 } 393 394 static void miic_dump_conf(struct device *dev, 395 s8 conf[MIIC_MODCTRL_CONF_CONV_NUM]) 396 { 397 const char *conf_name; 398 int i; 399 400 for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) { 401 if (conf[i] != MIIC_MODCTRL_CONF_NONE) 402 conf_name = conf_to_string[conf[i]]; 403 else 404 conf_name = "NONE"; 405 406 dev_err(dev, "%s: %s\n", index_to_string[i], conf_name); 407 } 408 } 409 410 static int miic_match_dt_conf(struct device *dev, 411 s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM], 412 u32 *mode_cfg) 413 { 414 struct modctrl_match *table_entry; 415 int i; 416 417 for (i = 0; i < ARRAY_SIZE(modctrl_match_table); i++) { 418 table_entry = &modctrl_match_table[i]; 419 420 if (miic_modctrl_match(table_entry->conv, dt_val)) { 421 *mode_cfg = table_entry->mode_cfg; 422 return 0; 423 } 424 } 425 426 dev_err(dev, "Failed to apply requested configuration\n"); 427 miic_dump_conf(dev, dt_val); 428 429 return -EINVAL; 430 } 431 432 static int miic_parse_dt(struct device *dev, u32 *mode_cfg) 433 { 434 s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM]; 435 struct device_node *np = dev->of_node; 436 struct device_node *conv; 437 u32 conf; 438 int port; 439 440 memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(dt_val)); 441 442 if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0) 443 dt_val[0] = conf; 444 445 for_each_child_of_node(np, conv) { 446 if (of_property_read_u32(conv, "reg", &port)) 447 continue; 448 449 if (!of_device_is_available(conv)) 450 continue; 451 452 if (of_property_read_u32(conv, "renesas,miic-input", &conf) == 0) 453 dt_val[port] = conf; 454 } 455 456 return miic_match_dt_conf(dev, dt_val, mode_cfg); 457 } 458 459 static int miic_probe(struct platform_device *pdev) 460 { 461 struct device *dev = &pdev->dev; 462 struct miic *miic; 463 u32 mode_cfg; 464 int ret; 465 466 ret = miic_parse_dt(dev, &mode_cfg); 467 if (ret < 0) 468 return ret; 469 470 miic = devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL); 471 if (!miic) 472 return -ENOMEM; 473 474 spin_lock_init(&miic->lock); 475 miic->dev = dev; 476 miic->base = devm_platform_ioremap_resource(pdev, 0); 477 if (IS_ERR(miic->base)) 478 return PTR_ERR(miic->base); 479 480 ret = devm_pm_runtime_enable(dev); 481 if (ret < 0) 482 return ret; 483 484 ret = pm_runtime_resume_and_get(dev); 485 if (ret < 0) 486 return ret; 487 488 ret = miic_init_hw(miic, mode_cfg); 489 if (ret) 490 goto disable_runtime_pm; 491 492 /* miic_create() relies on that fact that data are attached to the 493 * platform device to determine if the driver is ready so this needs to 494 * be the last thing to be done after everything is initialized 495 * properly. 496 */ 497 platform_set_drvdata(pdev, miic); 498 499 return 0; 500 501 disable_runtime_pm: 502 pm_runtime_put(dev); 503 504 return ret; 505 } 506 507 static int miic_remove(struct platform_device *pdev) 508 { 509 pm_runtime_put(&pdev->dev); 510 511 return 0; 512 } 513 514 static const struct of_device_id miic_of_mtable[] = { 515 { .compatible = "renesas,rzn1-miic" }, 516 { /* sentinel */ }, 517 }; 518 MODULE_DEVICE_TABLE(of, miic_of_mtable); 519 520 static struct platform_driver miic_driver = { 521 .driver = { 522 .name = "rzn1_miic", 523 .suppress_bind_attrs = true, 524 .of_match_table = miic_of_mtable, 525 }, 526 .probe = miic_probe, 527 .remove = miic_remove, 528 }; 529 module_platform_driver(miic_driver); 530 531 MODULE_LICENSE("GPL"); 532 MODULE_DESCRIPTION("Renesas MII converter PCS driver"); 533 MODULE_AUTHOR("Clément Léger <clement.leger@bootlin.com>"); 534