1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2023-2024 Linaro Ltd. */ 4 5 #include <linux/array_size.h> 6 #include <linux/bits.h> 7 #include <linux/kernel.h> 8 #include <linux/types.h> 9 #include <linux/bits.h> 10 11 #include "../ipa_reg.h" 12 #include "../ipa_version.h" 13 14 static const u32 reg_flavor_0_fmask[] = { 15 [MAX_PIPES] = GENMASK(7, 0), 16 [MAX_CONS_PIPES] = GENMASK(15, 8), 17 [MAX_PROD_PIPES] = GENMASK(23, 16), 18 [PROD_LOWEST] = GENMASK(31, 24), 19 }; 20 21 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000); 22 23 static const u32 reg_comp_cfg_fmask[] = { 24 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0), 25 [GSI_SNOC_BYPASS_DIS] = BIT(1), 26 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 27 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 28 /* Bit 4 reserved */ 29 [IPA_QMB_SELECT_CONS_EN] = BIT(5), 30 [IPA_QMB_SELECT_PROD_EN] = BIT(6), 31 [GSI_MULTI_INORDER_RD_DIS] = BIT(7), 32 [GSI_MULTI_INORDER_WR_DIS] = BIT(8), 33 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), 34 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), 35 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), 36 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), 37 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), 38 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), 39 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), 40 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), 41 /* Bits 17-18 reserved */ 42 [QMB_RAM_RD_CACHE_DISABLE] = BIT(19), 43 [GENQMB_AOOOWR] = BIT(20), 44 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21), 45 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(27, 22), 46 /* Bits 28-29 reserved */ 47 [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30), 48 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31), 49 }; 50 51 REG_FIELDS(COMP_CFG, comp_cfg, 0x00000048); 52 53 static const u32 reg_clkon_cfg_fmask[] = { 54 [CLKON_RX] = BIT(0), 55 [CLKON_PROC] = BIT(1), 56 [TX_WRAPPER] = BIT(2), 57 [CLKON_MISC] = BIT(3), 58 [RAM_ARB] = BIT(4), 59 [FTCH_HPS] = BIT(5), 60 [FTCH_DPS] = BIT(6), 61 [CLKON_HPS] = BIT(7), 62 [CLKON_DPS] = BIT(8), 63 [RX_HPS_CMDQS] = BIT(9), 64 [HPS_DPS_CMDQS] = BIT(10), 65 [DPS_TX_CMDQS] = BIT(11), 66 [RSRC_MNGR] = BIT(12), 67 [CTX_HANDLER] = BIT(13), 68 [ACK_MNGR] = BIT(14), 69 [D_DCPH] = BIT(15), 70 [H_DCPH] = BIT(16), 71 /* Bit 17 reserved */ 72 [NTF_TX_CMDQS] = BIT(18), 73 [CLKON_TX_0] = BIT(19), 74 [CLKON_TX_1] = BIT(20), 75 [CLKON_FNR] = BIT(21), 76 [QSB2AXI_CMDQ_L] = BIT(22), 77 [AGGR_WRAPPER] = BIT(23), 78 [RAM_SLAVEWAY] = BIT(24), 79 [CLKON_QMB] = BIT(25), 80 [WEIGHT_ARB] = BIT(26), 81 [GSI_IF] = BIT(27), 82 [CLKON_GLOBAL] = BIT(28), 83 [GLOBAL_2X_CLK] = BIT(29), 84 [DPL_FIFO] = BIT(30), 85 [DRBIP] = BIT(31), 86 }; 87 88 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000050); 89 90 static const u32 reg_route_fmask[] = { 91 [ROUTE_DEF_PIPE] = GENMASK(7, 0), 92 [ROUTE_FRAG_DEF_PIPE] = GENMASK(15, 8), 93 [ROUTE_DEF_HDR_OFST] = GENMASK(25, 16), 94 [ROUTE_DEF_HDR_TABLE] = BIT(26), 95 [ROUTE_DEF_RETAIN_HDR] = BIT(27), 96 [ROUTE_DIS] = BIT(28), 97 /* Bits 29-31 reserved */ 98 }; 99 100 REG_FIELDS(ROUTE, route, 0x00000054); 101 102 static const u32 reg_shared_mem_size_fmask[] = { 103 [MEM_SIZE] = GENMASK(15, 0), 104 [MEM_BADDR] = GENMASK(31, 16), 105 }; 106 107 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x0000005c); 108 109 static const u32 reg_qsb_max_writes_fmask[] = { 110 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 111 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 112 /* Bits 8-31 reserved */ 113 }; 114 115 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000070); 116 117 static const u32 reg_qsb_max_reads_fmask[] = { 118 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 119 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 120 /* Bits 8-15 reserved */ 121 [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), 122 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), 123 }; 124 125 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000074); 126 127 /* Valid bits defined by ipa->available */ 128 129 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x00000120, 0x0004); 130 131 static const u32 reg_filt_rout_cache_flush_fmask[] = { 132 [ROUTER_CACHE] = BIT(0), 133 /* Bits 1-3 reserved */ 134 [FILTER_CACHE] = BIT(4), 135 /* Bits 5-31 reserved */ 136 }; 137 138 REG_FIELDS(FILT_ROUT_CACHE_FLUSH, filt_rout_cache_flush, 0x0000404); 139 140 static const u32 reg_local_pkt_proc_cntxt_fmask[] = { 141 [IPA_BASE_ADDR] = GENMASK(17, 0), 142 /* Bits 18-31 reserved */ 143 }; 144 145 /* Offset must be a multiple of 8 */ 146 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x00000478); 147 148 static const u32 reg_ipa_tx_cfg_fmask[] = { 149 /* Bits 0-1 reserved */ 150 [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), 151 [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), 152 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), 153 [DMAW_MAX_BEATS_256_DIS] = BIT(11), 154 [PA_MASK_EN] = BIT(12), 155 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), 156 [DUAL_TX_ENABLE] = BIT(17), 157 [SSPND_PA_NO_START_STATE] = BIT(18), 158 /* Bit 19 reserved */ 159 [HOLB_STICKY_DROP_EN] = BIT(20), 160 /* Bits 21-31 reserved */ 161 }; 162 163 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x00000488); 164 165 static const u32 reg_idle_indication_cfg_fmask[] = { 166 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 167 [CONST_NON_IDLE_ENABLE] = BIT(16), 168 /* Bits 17-31 reserved */ 169 }; 170 171 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x000004a8); 172 173 static const u32 reg_qtime_timestamp_cfg_fmask[] = { 174 /* Bits 0-7 reserved */ 175 [TAG_TIMESTAMP_LSB] = GENMASK(12, 8), 176 /* Bits 13-15 reserved */ 177 [NAT_TIMESTAMP_LSB] = GENMASK(20, 16), 178 /* Bits 21-31 reserved */ 179 }; 180 181 REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x000004ac); 182 183 static const u32 reg_timers_xo_clk_div_cfg_fmask[] = { 184 [DIV_VALUE] = GENMASK(8, 0), 185 /* Bits 9-30 reserved */ 186 [DIV_ENABLE] = BIT(31), 187 }; 188 189 REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x000004b0); 190 191 static const u32 reg_timers_pulse_gran_cfg_fmask[] = { 192 [PULSE_GRAN_0] = GENMASK(2, 0), 193 [PULSE_GRAN_1] = GENMASK(5, 3), 194 [PULSE_GRAN_2] = GENMASK(8, 6), 195 [PULSE_GRAN_3] = GENMASK(11, 9), 196 /* Bits 12-31 reserved */ 197 }; 198 199 REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x000004b4); 200 201 static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 202 [X_MIN_LIM] = GENMASK(5, 0), 203 /* Bits 6-7 reserved */ 204 [X_MAX_LIM] = GENMASK(13, 8), 205 /* Bits 14-15 reserved */ 206 [Y_MIN_LIM] = GENMASK(21, 16), 207 /* Bits 22-23 reserved */ 208 [Y_MAX_LIM] = GENMASK(29, 24), 209 /* Bits 30-31 reserved */ 210 }; 211 212 REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 213 0x00000500, 0x0020); 214 215 static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 216 [X_MIN_LIM] = GENMASK(5, 0), 217 /* Bits 6-7 reserved */ 218 [X_MAX_LIM] = GENMASK(13, 8), 219 /* Bits 14-15 reserved */ 220 [Y_MIN_LIM] = GENMASK(21, 16), 221 /* Bits 22-23 reserved */ 222 [Y_MAX_LIM] = GENMASK(29, 24), 223 /* Bits 30-31 reserved */ 224 }; 225 226 REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 227 0x00000504, 0x0020); 228 229 static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = { 230 [X_MIN_LIM] = GENMASK(5, 0), 231 /* Bits 6-7 reserved */ 232 [X_MAX_LIM] = GENMASK(13, 8), 233 /* Bits 14-15 reserved */ 234 [Y_MIN_LIM] = GENMASK(21, 16), 235 /* Bits 22-23 reserved */ 236 [Y_MAX_LIM] = GENMASK(29, 24), 237 /* Bits 30-31 reserved */ 238 }; 239 240 REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, 241 0x00000508, 0x0020); 242 243 static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = { 244 [X_MIN_LIM] = GENMASK(5, 0), 245 /* Bits 6-7 reserved */ 246 [X_MAX_LIM] = GENMASK(13, 8), 247 /* Bits 14-15 reserved */ 248 [Y_MIN_LIM] = GENMASK(21, 16), 249 /* Bits 22-23 reserved */ 250 [Y_MAX_LIM] = GENMASK(29, 24), 251 /* Bits 30-31 reserved */ 252 }; 253 254 REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type, 255 0x0000050c, 0x0020); 256 257 static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 258 [X_MIN_LIM] = GENMASK(5, 0), 259 /* Bits 6-7 reserved */ 260 [X_MAX_LIM] = GENMASK(13, 8), 261 /* Bits 14-15 reserved */ 262 [Y_MIN_LIM] = GENMASK(21, 16), 263 /* Bits 22-23 reserved */ 264 [Y_MAX_LIM] = GENMASK(29, 24), 265 /* Bits 30-31 reserved */ 266 }; 267 268 REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 269 0x00000600, 0x0020); 270 271 static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 272 [X_MIN_LIM] = GENMASK(5, 0), 273 /* Bits 6-7 reserved */ 274 [X_MAX_LIM] = GENMASK(13, 8), 275 /* Bits 14-15 reserved */ 276 [Y_MIN_LIM] = GENMASK(21, 16), 277 /* Bits 22-23 reserved */ 278 [Y_MAX_LIM] = GENMASK(29, 24), 279 /* Bits 30-31 reserved */ 280 }; 281 282 REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 283 0x00000604, 0x0020); 284 285 static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { 286 [X_MIN_LIM] = GENMASK(5, 0), 287 /* Bits 6-7 reserved */ 288 [X_MAX_LIM] = GENMASK(13, 8), 289 /* Bits 14-15 reserved */ 290 [Y_MIN_LIM] = GENMASK(21, 16), 291 /* Bits 22-23 reserved */ 292 [Y_MAX_LIM] = GENMASK(29, 24), 293 /* Bits 30-31 reserved */ 294 }; 295 296 REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, 297 0x00000608, 0x0020); 298 299 static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = { 300 [X_MIN_LIM] = GENMASK(5, 0), 301 /* Bits 6-7 reserved */ 302 [X_MAX_LIM] = GENMASK(13, 8), 303 /* Bits 14-15 reserved */ 304 [Y_MIN_LIM] = GENMASK(21, 16), 305 /* Bits 22-23 reserved */ 306 [Y_MAX_LIM] = GENMASK(29, 24), 307 /* Bits 30-31 reserved */ 308 }; 309 310 REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type, 311 0x0000060c, 0x0020); 312 313 /* Valid bits defined by ipa->available */ 314 315 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000006b0, 0x0004); 316 317 static const u32 reg_endp_init_cfg_fmask[] = { 318 [FRAG_OFFLOAD_EN] = BIT(0), 319 [CS_OFFLOAD_EN] = GENMASK(2, 1), 320 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 321 /* Bit 7 reserved */ 322 [CS_GEN_QMB_MASTER_SEL] = BIT(8), 323 [PIPE_REPLICATE_EN] = BIT(9), 324 /* Bits 10-31 reserved */ 325 }; 326 327 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00001008, 0x0080); 328 329 static const u32 reg_endp_init_nat_fmask[] = { 330 [NAT_EN] = GENMASK(1, 0), 331 /* Bits 2-31 reserved */ 332 }; 333 334 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000100c, 0x0080); 335 336 static const u32 reg_endp_init_hdr_fmask[] = { 337 [HDR_LEN] = GENMASK(5, 0), 338 [HDR_OFST_METADATA_VALID] = BIT(6), 339 [HDR_OFST_METADATA] = GENMASK(12, 7), 340 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 341 [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 342 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 343 /* Bit 26 reserved */ 344 [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 345 [HDR_LEN_MSB] = GENMASK(29, 28), 346 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), 347 }; 348 349 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00001010, 0x0080); 350 351 static const u32 reg_endp_init_hdr_ext_fmask[] = { 352 [HDR_ENDIANNESS] = BIT(0), 353 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 354 [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 355 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 356 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 357 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 358 /* Bits 14-15 reserved */ 359 [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16), 360 [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18), 361 [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20), 362 [HDR_BYTES_TO_REMOVE_VALID] = BIT(22), 363 /* Bit 23 reserved */ 364 [HDR_BYTES_TO_REMOVE] = GENMASK(31, 24), 365 }; 366 367 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00001014, 0x0080); 368 369 REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 370 0x00001018, 0x0080); 371 372 static const u32 reg_endp_init_mode_fmask[] = { 373 [ENDP_MODE] = GENMASK(2, 0), 374 [DCPH_ENABLE] = BIT(3), 375 [DEST_PIPE_INDEX] = GENMASK(11, 4), 376 [BYTE_THRESHOLD] = GENMASK(27, 12), 377 /* Bit 28 reserved */ 378 [PAD_EN] = BIT(29), 379 [DRBIP_ACL_ENABLE] = BIT(30), 380 /* Bit 31 reserved */ 381 }; 382 383 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00001020, 0x0080); 384 385 static const u32 reg_endp_init_aggr_fmask[] = { 386 [AGGR_EN] = GENMASK(1, 0), 387 [AGGR_TYPE] = GENMASK(4, 2), 388 [BYTE_LIMIT] = GENMASK(10, 5), 389 /* Bit 11 reserved */ 390 [TIME_LIMIT] = GENMASK(16, 12), 391 [PKT_LIMIT] = GENMASK(22, 17), 392 [SW_EOF_ACTIVE] = BIT(23), 393 [FORCE_CLOSE] = BIT(24), 394 /* Bit 25 reserved */ 395 [HARD_BYTE_LIMIT_EN] = BIT(26), 396 [AGGR_GRAN_SEL] = BIT(27), 397 [AGGR_COAL_L2] = BIT(28), 398 /* Bits 27-31 reserved */ 399 }; 400 401 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00001024, 0x0080); 402 403 static const u32 reg_endp_init_hol_block_en_fmask[] = { 404 [HOL_BLOCK_EN] = BIT(0), 405 /* Bits 1-31 reserved */ 406 }; 407 408 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 409 0x0000102c, 0x0080); 410 411 static const u32 reg_endp_init_hol_block_timer_fmask[] = { 412 [TIMER_LIMIT] = GENMASK(4, 0), 413 /* Bits 5-7 reserved */ 414 [TIMER_GRAN_SEL] = GENMASK(9, 8), 415 /* Bits 10-31 reserved */ 416 }; 417 418 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 419 0x00001030, 0x0080); 420 421 static const u32 reg_endp_init_deaggr_fmask[] = { 422 [DEAGGR_HDR_LEN] = GENMASK(5, 0), 423 [SYSPIPE_ERR_DETECTION] = BIT(6), 424 [PACKET_OFFSET_VALID] = BIT(7), 425 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 426 [IGNORE_MIN_PKT_ERR] = BIT(14), 427 /* Bit 15 reserved */ 428 [MAX_PACKET_LEN] = GENMASK(31, 16), 429 }; 430 431 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00001034, 0x0080); 432 433 static const u32 reg_endp_init_rsrc_grp_fmask[] = { 434 [ENDP_RSRC_GRP] = GENMASK(2, 0), 435 /* Bits 3-31 reserved */ 436 }; 437 438 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00001038, 0x0080); 439 440 static const u32 reg_endp_init_seq_fmask[] = { 441 [SEQ_TYPE] = GENMASK(7, 0), 442 /* Bits 8-31 reserved */ 443 }; 444 445 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000103c, 0x0080); 446 447 static const u32 reg_endp_status_fmask[] = { 448 [STATUS_EN] = BIT(0), 449 [STATUS_ENDP] = GENMASK(8, 1), 450 [STATUS_PKT_SUPPRESS] = BIT(9), 451 /* Bits 10-31 reserved */ 452 }; 453 454 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00001040, 0x0080); 455 456 static const u32 reg_endp_filter_cache_cfg_fmask[] = { 457 [CACHE_MSK_SRC_ID] = BIT(0), 458 [CACHE_MSK_SRC_IP] = BIT(1), 459 [CACHE_MSK_DST_IP] = BIT(2), 460 [CACHE_MSK_SRC_PORT] = BIT(3), 461 [CACHE_MSK_DST_PORT] = BIT(4), 462 [CACHE_MSK_PROTOCOL] = BIT(5), 463 [CACHE_MSK_METADATA] = BIT(6), 464 /* Bits 7-31 reserved */ 465 }; 466 467 REG_STRIDE_FIELDS(ENDP_FILTER_CACHE_CFG, endp_filter_cache_cfg, 468 0x0000105c, 0x0080); 469 470 static const u32 reg_endp_router_cache_cfg_fmask[] = { 471 [CACHE_MSK_SRC_ID] = BIT(0), 472 [CACHE_MSK_SRC_IP] = BIT(1), 473 [CACHE_MSK_DST_IP] = BIT(2), 474 [CACHE_MSK_SRC_PORT] = BIT(3), 475 [CACHE_MSK_DST_PORT] = BIT(4), 476 [CACHE_MSK_PROTOCOL] = BIT(5), 477 [CACHE_MSK_METADATA] = BIT(6), 478 /* Bits 7-31 reserved */ 479 }; 480 481 REG_STRIDE_FIELDS(ENDP_ROUTER_CACHE_CFG, endp_router_cache_cfg, 482 0x00001060, 0x0080); 483 484 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 485 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x0000c008 + 0x1000 * GSI_EE_AP); 486 487 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 488 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000c00c + 0x1000 * GSI_EE_AP); 489 490 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 491 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x0000c010 + 0x1000 * GSI_EE_AP); 492 493 static const u32 reg_ipa_irq_uc_fmask[] = { 494 [UC_INTR] = BIT(0), 495 /* Bits 1-31 reserved */ 496 }; 497 498 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000c01c + 0x1000 * GSI_EE_AP); 499 500 /* Valid bits defined by ipa->available */ 501 502 REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, 503 0x0000c030 + 0x1000 * GSI_EE_AP, 0x0004); 504 505 /* Valid bits defined by ipa->available */ 506 507 REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, 508 0x0000c050 + 0x1000 * GSI_EE_AP, 0x0004); 509 510 /* Valid bits defined by ipa->available */ 511 512 REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, 513 0x0000c070 + 0x1000 * GSI_EE_AP, 0x0004); 514 515 static const struct reg *reg_array[] = { 516 [COMP_CFG] = ®_comp_cfg, 517 [CLKON_CFG] = ®_clkon_cfg, 518 [ROUTE] = ®_route, 519 [SHARED_MEM_SIZE] = ®_shared_mem_size, 520 [QSB_MAX_WRITES] = ®_qsb_max_writes, 521 [QSB_MAX_READS] = ®_qsb_max_reads, 522 [FILT_ROUT_CACHE_FLUSH] = ®_filt_rout_cache_flush, 523 [STATE_AGGR_ACTIVE] = ®_state_aggr_active, 524 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, 525 [AGGR_FORCE_CLOSE] = ®_aggr_force_close, 526 [IPA_TX_CFG] = ®_ipa_tx_cfg, 527 [FLAVOR_0] = ®_flavor_0, 528 [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, 529 [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg, 530 [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg, 531 [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg, 532 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, 533 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, 534 [SRC_RSRC_GRP_45_RSRC_TYPE] = ®_src_rsrc_grp_45_rsrc_type, 535 [SRC_RSRC_GRP_67_RSRC_TYPE] = ®_src_rsrc_grp_67_rsrc_type, 536 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, 537 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, 538 [DST_RSRC_GRP_45_RSRC_TYPE] = ®_dst_rsrc_grp_45_rsrc_type, 539 [DST_RSRC_GRP_67_RSRC_TYPE] = ®_dst_rsrc_grp_67_rsrc_type, 540 [ENDP_INIT_CFG] = ®_endp_init_cfg, 541 [ENDP_INIT_NAT] = ®_endp_init_nat, 542 [ENDP_INIT_HDR] = ®_endp_init_hdr, 543 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, 544 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, 545 [ENDP_INIT_MODE] = ®_endp_init_mode, 546 [ENDP_INIT_AGGR] = ®_endp_init_aggr, 547 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, 548 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, 549 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, 550 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, 551 [ENDP_INIT_SEQ] = ®_endp_init_seq, 552 [ENDP_STATUS] = ®_endp_status, 553 [ENDP_FILTER_CACHE_CFG] = ®_endp_filter_cache_cfg, 554 [ENDP_ROUTER_CACHE_CFG] = ®_endp_router_cache_cfg, 555 [IPA_IRQ_STTS] = ®_ipa_irq_stts, 556 [IPA_IRQ_EN] = ®_ipa_irq_en, 557 [IPA_IRQ_CLR] = ®_ipa_irq_clr, 558 [IPA_IRQ_UC] = ®_ipa_irq_uc, 559 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, 560 [IRQ_SUSPEND_EN] = ®_irq_suspend_en, 561 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, 562 }; 563 564 const struct regs ipa_regs_v5_5 = { 565 .reg_count = ARRAY_SIZE(reg_array), 566 .reg = reg_array, 567 }; 568