1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/gpio/machine.h> 5 #include <linux/gpio/driver.h> 6 #include <linux/gpio/property.h> 7 #include <linux/clk-provider.h> 8 #include <linux/clkdev.h> 9 #include <linux/i2c.h> 10 #include <linux/pci.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 #include <linux/pcs/pcs-xpcs.h> 14 #include <linux/phylink.h> 15 16 #include "../libwx/wx_type.h" 17 #include "../libwx/wx_lib.h" 18 #include "../libwx/wx_ptp.h" 19 #include "../libwx/wx_sriov.h" 20 #include "../libwx/wx_mbx.h" 21 #include "../libwx/wx_hw.h" 22 #include "txgbe_type.h" 23 #include "txgbe_phy.h" 24 #include "txgbe_hw.h" 25 26 static int txgbe_swnodes_register(struct txgbe *txgbe) 27 { 28 struct txgbe_nodes *nodes = &txgbe->nodes; 29 struct pci_dev *pdev = txgbe->wx->pdev; 30 struct software_node *swnodes; 31 u32 id; 32 33 id = pci_dev_id(pdev); 34 35 snprintf(nodes->gpio_name, sizeof(nodes->gpio_name), "txgbe_gpio-%x", id); 36 snprintf(nodes->i2c_name, sizeof(nodes->i2c_name), "txgbe_i2c-%x", id); 37 snprintf(nodes->sfp_name, sizeof(nodes->sfp_name), "txgbe_sfp-%x", id); 38 snprintf(nodes->phylink_name, sizeof(nodes->phylink_name), "txgbe_phylink-%x", id); 39 40 swnodes = nodes->swnodes; 41 42 /* GPIO 0: tx fault 43 * GPIO 1: tx disable 44 * GPIO 2: sfp module absent 45 * GPIO 3: rx signal lost 46 * GPIO 4: rate select, 1G(0) 10G(1) 47 * GPIO 5: rate select, 1G(0) 10G(1) 48 */ 49 nodes->gpio_props[0] = PROPERTY_ENTRY_STRING("pinctrl-names", "default"); 50 swnodes[SWNODE_GPIO] = NODE_PROP(nodes->gpio_name, nodes->gpio_props); 51 nodes->gpio0_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 0, GPIO_ACTIVE_HIGH); 52 nodes->gpio1_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 1, GPIO_ACTIVE_HIGH); 53 nodes->gpio2_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 2, GPIO_ACTIVE_LOW); 54 nodes->gpio3_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 3, GPIO_ACTIVE_HIGH); 55 nodes->gpio4_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 4, GPIO_ACTIVE_HIGH); 56 nodes->gpio5_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 5, GPIO_ACTIVE_HIGH); 57 58 nodes->i2c_props[0] = PROPERTY_ENTRY_STRING("compatible", "snps,designware-i2c"); 59 nodes->i2c_props[1] = PROPERTY_ENTRY_BOOL("wx,i2c-snps-model"); 60 nodes->i2c_props[2] = PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ); 61 swnodes[SWNODE_I2C] = NODE_PROP(nodes->i2c_name, nodes->i2c_props); 62 nodes->i2c_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_I2C]); 63 64 nodes->sfp_props[0] = PROPERTY_ENTRY_STRING("compatible", "sff,sfp"); 65 nodes->sfp_props[1] = PROPERTY_ENTRY_REF_ARRAY("i2c-bus", nodes->i2c_ref); 66 nodes->sfp_props[2] = PROPERTY_ENTRY_REF_ARRAY("tx-fault-gpios", nodes->gpio0_ref); 67 nodes->sfp_props[3] = PROPERTY_ENTRY_REF_ARRAY("tx-disable-gpios", nodes->gpio1_ref); 68 nodes->sfp_props[4] = PROPERTY_ENTRY_REF_ARRAY("mod-def0-gpios", nodes->gpio2_ref); 69 nodes->sfp_props[5] = PROPERTY_ENTRY_REF_ARRAY("los-gpios", nodes->gpio3_ref); 70 nodes->sfp_props[6] = PROPERTY_ENTRY_REF_ARRAY("rate-select1-gpios", nodes->gpio4_ref); 71 nodes->sfp_props[7] = PROPERTY_ENTRY_REF_ARRAY("rate-select0-gpios", nodes->gpio5_ref); 72 swnodes[SWNODE_SFP] = NODE_PROP(nodes->sfp_name, nodes->sfp_props); 73 nodes->sfp_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_SFP]); 74 75 nodes->phylink_props[0] = PROPERTY_ENTRY_STRING("managed", "in-band-status"); 76 nodes->phylink_props[1] = PROPERTY_ENTRY_REF_ARRAY("sfp", nodes->sfp_ref); 77 swnodes[SWNODE_PHYLINK] = NODE_PROP(nodes->phylink_name, nodes->phylink_props); 78 79 nodes->group[SWNODE_GPIO] = &swnodes[SWNODE_GPIO]; 80 nodes->group[SWNODE_I2C] = &swnodes[SWNODE_I2C]; 81 nodes->group[SWNODE_SFP] = &swnodes[SWNODE_SFP]; 82 nodes->group[SWNODE_PHYLINK] = &swnodes[SWNODE_PHYLINK]; 83 84 return software_node_register_node_group(nodes->group); 85 } 86 87 static int txgbe_pcs_read(struct mii_bus *bus, int addr, int devnum, int regnum) 88 { 89 struct wx *wx = bus->priv; 90 u32 offset, val; 91 92 if (addr) 93 return -EOPNOTSUPP; 94 95 offset = devnum << 16 | regnum; 96 97 /* Set the LAN port indicator to IDA_ADDR */ 98 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset); 99 100 /* Read the data from IDA_DATA register */ 101 val = rd32(wx, TXGBE_XPCS_IDA_DATA); 102 103 return (u16)val; 104 } 105 106 static int txgbe_pcs_write(struct mii_bus *bus, int addr, int devnum, int regnum, u16 val) 107 { 108 struct wx *wx = bus->priv; 109 u32 offset; 110 111 if (addr) 112 return -EOPNOTSUPP; 113 114 offset = devnum << 16 | regnum; 115 116 /* Set the LAN port indicator to IDA_ADDR */ 117 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset); 118 119 /* Write the data to IDA_DATA register */ 120 wr32(wx, TXGBE_XPCS_IDA_DATA, val); 121 122 return 0; 123 } 124 125 static int txgbe_mdio_pcs_init(struct txgbe *txgbe) 126 { 127 struct mii_bus *mii_bus; 128 struct phylink_pcs *pcs; 129 struct pci_dev *pdev; 130 struct wx *wx; 131 int ret = 0; 132 133 wx = txgbe->wx; 134 pdev = wx->pdev; 135 136 mii_bus = devm_mdiobus_alloc(&pdev->dev); 137 if (!mii_bus) 138 return -ENOMEM; 139 140 mii_bus->name = "txgbe_pcs_mdio_bus"; 141 mii_bus->read_c45 = &txgbe_pcs_read; 142 mii_bus->write_c45 = &txgbe_pcs_write; 143 mii_bus->parent = &pdev->dev; 144 mii_bus->phy_mask = ~0; 145 mii_bus->priv = wx; 146 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe_pcs-%x", 147 pci_dev_id(pdev)); 148 149 ret = devm_mdiobus_register(&pdev->dev, mii_bus); 150 if (ret) 151 return ret; 152 153 pcs = xpcs_create_pcs_mdiodev(mii_bus, 0); 154 if (IS_ERR(pcs)) 155 return PTR_ERR(pcs); 156 157 txgbe->pcs = pcs; 158 159 return 0; 160 } 161 162 static struct phylink_pcs *txgbe_phylink_mac_select(struct phylink_config *config, 163 phy_interface_t interface) 164 { 165 struct wx *wx = phylink_to_wx(config); 166 struct txgbe *txgbe = wx->priv; 167 168 if (wx->media_type != sp_media_copper) 169 return txgbe->pcs; 170 171 return NULL; 172 } 173 174 static void txgbe_mac_config(struct phylink_config *config, unsigned int mode, 175 const struct phylink_link_state *state) 176 { 177 } 178 179 static void txgbe_mac_link_down(struct phylink_config *config, 180 unsigned int mode, phy_interface_t interface) 181 { 182 struct wx *wx = phylink_to_wx(config); 183 184 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0); 185 186 wx->speed = SPEED_UNKNOWN; 187 if (test_bit(WX_STATE_PTP_RUNNING, wx->state)) 188 wx_ptp_reset_cyclecounter(wx); 189 /* ping all the active vfs to let them know we are going down */ 190 wx_ping_all_vfs_with_link_status(wx, false); 191 } 192 193 static void txgbe_mac_link_up(struct phylink_config *config, 194 struct phy_device *phy, 195 unsigned int mode, phy_interface_t interface, 196 int speed, int duplex, 197 bool tx_pause, bool rx_pause) 198 { 199 struct wx *wx = phylink_to_wx(config); 200 u32 txcfg, wdg; 201 202 wx_fc_enable(wx, tx_pause, rx_pause); 203 204 txcfg = rd32(wx, WX_MAC_TX_CFG); 205 txcfg &= ~WX_MAC_TX_CFG_SPEED_MASK; 206 207 switch (speed) { 208 case SPEED_10000: 209 txcfg |= WX_MAC_TX_CFG_SPEED_10G; 210 break; 211 case SPEED_1000: 212 case SPEED_100: 213 case SPEED_10: 214 txcfg |= WX_MAC_TX_CFG_SPEED_1G; 215 break; 216 default: 217 break; 218 } 219 220 wr32(wx, WX_MAC_TX_CFG, txcfg | WX_MAC_TX_CFG_TE); 221 222 /* Re configure MAC Rx */ 223 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE); 224 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR); 225 wdg = rd32(wx, WX_MAC_WDG_TIMEOUT); 226 wr32(wx, WX_MAC_WDG_TIMEOUT, wdg); 227 228 wx->speed = speed; 229 wx->last_rx_ptp_check = jiffies; 230 if (test_bit(WX_STATE_PTP_RUNNING, wx->state)) 231 wx_ptp_reset_cyclecounter(wx); 232 /* ping all the active vfs to let them know we are going up */ 233 wx_ping_all_vfs_with_link_status(wx, true); 234 } 235 236 static int txgbe_mac_prepare(struct phylink_config *config, unsigned int mode, 237 phy_interface_t interface) 238 { 239 struct wx *wx = phylink_to_wx(config); 240 241 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0); 242 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, 0); 243 244 return txgbe_disable_sec_tx_path(wx); 245 } 246 247 static int txgbe_mac_finish(struct phylink_config *config, unsigned int mode, 248 phy_interface_t interface) 249 { 250 struct wx *wx = phylink_to_wx(config); 251 252 txgbe_enable_sec_tx_path(wx); 253 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE); 254 255 return 0; 256 } 257 258 static const struct phylink_mac_ops txgbe_mac_ops = { 259 .mac_select_pcs = txgbe_phylink_mac_select, 260 .mac_prepare = txgbe_mac_prepare, 261 .mac_finish = txgbe_mac_finish, 262 .mac_config = txgbe_mac_config, 263 .mac_link_down = txgbe_mac_link_down, 264 .mac_link_up = txgbe_mac_link_up, 265 }; 266 267 static int txgbe_phylink_init(struct txgbe *txgbe) 268 { 269 struct fwnode_handle *fwnode = NULL; 270 struct phylink_config *config; 271 struct wx *wx = txgbe->wx; 272 phy_interface_t phy_mode; 273 struct phylink *phylink; 274 275 config = &wx->phylink_config; 276 config->dev = &wx->netdev->dev; 277 config->type = PHYLINK_NETDEV; 278 config->mac_capabilities = MAC_10000FD | MAC_1000FD | MAC_100FD | 279 MAC_SYM_PAUSE | MAC_ASYM_PAUSE; 280 281 if (wx->media_type == sp_media_copper) { 282 phy_mode = PHY_INTERFACE_MODE_XAUI; 283 __set_bit(PHY_INTERFACE_MODE_XAUI, config->supported_interfaces); 284 } else { 285 phy_mode = PHY_INTERFACE_MODE_10GBASER; 286 fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_PHYLINK]); 287 __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces); 288 __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces); 289 __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); 290 } 291 292 phylink = phylink_create(config, fwnode, phy_mode, &txgbe_mac_ops); 293 if (IS_ERR(phylink)) 294 return PTR_ERR(phylink); 295 296 if (wx->phydev) { 297 int ret; 298 299 ret = phylink_connect_phy(phylink, wx->phydev); 300 if (ret) { 301 phylink_destroy(phylink); 302 return ret; 303 } 304 } 305 306 wx->phylink = phylink; 307 308 return 0; 309 } 310 311 irqreturn_t txgbe_link_irq_handler(int irq, void *data) 312 { 313 struct txgbe *txgbe = data; 314 struct wx *wx = txgbe->wx; 315 u32 status; 316 bool up; 317 318 status = rd32(wx, TXGBE_CFG_PORT_ST); 319 up = !!(status & TXGBE_CFG_PORT_ST_LINK_UP); 320 321 phylink_pcs_change(txgbe->pcs, up); 322 323 return IRQ_HANDLED; 324 } 325 326 static int txgbe_gpio_get(struct gpio_chip *chip, unsigned int offset) 327 { 328 struct wx *wx = gpiochip_get_data(chip); 329 int val; 330 331 val = rd32m(wx, WX_GPIO_EXT, BIT(offset)); 332 333 return !!(val & BIT(offset)); 334 } 335 336 static int txgbe_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 337 { 338 struct wx *wx = gpiochip_get_data(chip); 339 u32 val; 340 341 val = rd32(wx, WX_GPIO_DDR); 342 if (BIT(offset) & val) 343 return GPIO_LINE_DIRECTION_OUT; 344 345 return GPIO_LINE_DIRECTION_IN; 346 } 347 348 static int txgbe_gpio_direction_in(struct gpio_chip *chip, unsigned int offset) 349 { 350 struct wx *wx = gpiochip_get_data(chip); 351 unsigned long flags; 352 353 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 354 wr32m(wx, WX_GPIO_DDR, BIT(offset), 0); 355 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 356 357 return 0; 358 } 359 360 static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset, 361 int val) 362 { 363 struct wx *wx = gpiochip_get_data(chip); 364 unsigned long flags; 365 u32 set; 366 367 set = val ? BIT(offset) : 0; 368 369 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 370 wr32m(wx, WX_GPIO_DR, BIT(offset), set); 371 wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset)); 372 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 373 374 return 0; 375 } 376 377 static int txgbe_gpio_init(struct txgbe *txgbe) 378 { 379 struct gpio_chip *gc; 380 struct device *dev; 381 struct wx *wx; 382 int ret; 383 384 wx = txgbe->wx; 385 dev = &wx->pdev->dev; 386 387 raw_spin_lock_init(&wx->gpio_lock); 388 389 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 390 if (!gc) 391 return -ENOMEM; 392 393 gc->label = devm_kasprintf(dev, GFP_KERNEL, "txgbe_gpio-%x", 394 pci_dev_id(wx->pdev)); 395 if (!gc->label) 396 return -ENOMEM; 397 398 gc->base = -1; 399 gc->ngpio = 6; 400 gc->owner = THIS_MODULE; 401 gc->parent = dev; 402 gc->fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_GPIO]); 403 gc->get = txgbe_gpio_get; 404 gc->get_direction = txgbe_gpio_get_direction; 405 gc->direction_input = txgbe_gpio_direction_in; 406 gc->direction_output = txgbe_gpio_direction_out; 407 408 ret = devm_gpiochip_add_data(dev, gc, wx); 409 if (ret) 410 return ret; 411 412 txgbe->gpio = gc; 413 414 return 0; 415 } 416 417 static int txgbe_clock_register(struct txgbe *txgbe) 418 { 419 struct pci_dev *pdev = txgbe->wx->pdev; 420 struct clk_lookup *clock; 421 char clk_name[32]; 422 struct clk *clk; 423 424 snprintf(clk_name, sizeof(clk_name), "i2c_designware.%d", 425 pci_dev_id(pdev)); 426 427 clk = clk_register_fixed_rate(NULL, clk_name, NULL, 0, 156250000); 428 if (IS_ERR(clk)) 429 return PTR_ERR(clk); 430 431 clock = clkdev_create(clk, NULL, "%s", clk_name); 432 if (!clock) { 433 clk_unregister(clk); 434 return -ENOMEM; 435 } 436 437 txgbe->clk = clk; 438 txgbe->clock = clock; 439 440 return 0; 441 } 442 443 static int txgbe_i2c_read(void *context, unsigned int reg, unsigned int *val) 444 { 445 struct wx *wx = context; 446 447 *val = rd32(wx, reg + TXGBE_I2C_BASE); 448 449 return 0; 450 } 451 452 static int txgbe_i2c_write(void *context, unsigned int reg, unsigned int val) 453 { 454 struct wx *wx = context; 455 456 wr32(wx, reg + TXGBE_I2C_BASE, val); 457 458 return 0; 459 } 460 461 static const struct regmap_config i2c_regmap_config = { 462 .reg_bits = 32, 463 .val_bits = 32, 464 .reg_read = txgbe_i2c_read, 465 .reg_write = txgbe_i2c_write, 466 .fast_io = true, 467 }; 468 469 static int txgbe_i2c_register(struct txgbe *txgbe) 470 { 471 struct platform_device_info info = {}; 472 struct platform_device *i2c_dev; 473 struct regmap *i2c_regmap; 474 struct pci_dev *pdev; 475 struct wx *wx; 476 477 wx = txgbe->wx; 478 pdev = wx->pdev; 479 i2c_regmap = devm_regmap_init(&pdev->dev, NULL, wx, &i2c_regmap_config); 480 if (IS_ERR(i2c_regmap)) { 481 wx_err(wx, "failed to init I2C regmap\n"); 482 return PTR_ERR(i2c_regmap); 483 } 484 485 info.parent = &pdev->dev; 486 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_I2C]); 487 info.name = "i2c_designware"; 488 info.id = pci_dev_id(pdev); 489 490 info.res = &DEFINE_RES_IRQ(pdev->irq); 491 info.num_res = 1; 492 i2c_dev = platform_device_register_full(&info); 493 if (IS_ERR(i2c_dev)) 494 return PTR_ERR(i2c_dev); 495 496 txgbe->i2c_dev = i2c_dev; 497 498 return 0; 499 } 500 501 static int txgbe_sfp_register(struct txgbe *txgbe) 502 { 503 struct pci_dev *pdev = txgbe->wx->pdev; 504 struct platform_device_info info = {}; 505 struct platform_device *sfp_dev; 506 507 info.parent = &pdev->dev; 508 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_SFP]); 509 info.name = "sfp"; 510 info.id = pci_dev_id(pdev); 511 sfp_dev = platform_device_register_full(&info); 512 if (IS_ERR(sfp_dev)) 513 return PTR_ERR(sfp_dev); 514 515 txgbe->sfp_dev = sfp_dev; 516 517 return 0; 518 } 519 520 static int txgbe_ext_phy_init(struct txgbe *txgbe) 521 { 522 struct phy_device *phydev; 523 struct mii_bus *mii_bus; 524 struct pci_dev *pdev; 525 struct wx *wx; 526 int ret = 0; 527 528 wx = txgbe->wx; 529 pdev = wx->pdev; 530 531 mii_bus = devm_mdiobus_alloc(&pdev->dev); 532 if (!mii_bus) 533 return -ENOMEM; 534 535 mii_bus->name = "txgbe_mii_bus"; 536 mii_bus->read_c45 = &wx_phy_read_reg_mdi_c45; 537 mii_bus->write_c45 = &wx_phy_write_reg_mdi_c45; 538 mii_bus->parent = &pdev->dev; 539 mii_bus->phy_mask = GENMASK(31, 1); 540 mii_bus->priv = wx; 541 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe-%x", pci_dev_id(pdev)); 542 543 ret = devm_mdiobus_register(&pdev->dev, mii_bus); 544 if (ret) { 545 wx_err(wx, "failed to register MDIO bus: %d\n", ret); 546 return ret; 547 } 548 549 phydev = phy_find_first(mii_bus); 550 if (!phydev) { 551 wx_err(wx, "no PHY found\n"); 552 return -ENODEV; 553 } 554 555 phy_attached_info(phydev); 556 557 wx->link = 0; 558 wx->speed = 0; 559 wx->duplex = 0; 560 wx->phydev = phydev; 561 562 ret = txgbe_phylink_init(txgbe); 563 if (ret) { 564 wx_err(wx, "failed to init phylink: %d\n", ret); 565 return ret; 566 } 567 568 return 0; 569 } 570 571 int txgbe_init_phy(struct txgbe *txgbe) 572 { 573 struct wx *wx = txgbe->wx; 574 int ret; 575 576 if (wx->mac.type == wx_mac_aml) 577 return 0; 578 579 if (txgbe->wx->media_type == sp_media_copper) 580 return txgbe_ext_phy_init(txgbe); 581 582 ret = txgbe_swnodes_register(txgbe); 583 if (ret) { 584 wx_err(wx, "failed to register software nodes\n"); 585 return ret; 586 } 587 588 ret = txgbe_mdio_pcs_init(txgbe); 589 if (ret) { 590 wx_err(wx, "failed to init mdio pcs: %d\n", ret); 591 goto err_unregister_swnode; 592 } 593 594 ret = txgbe_phylink_init(txgbe); 595 if (ret) { 596 wx_err(wx, "failed to init phylink\n"); 597 goto err_destroy_xpcs; 598 } 599 600 ret = txgbe_gpio_init(txgbe); 601 if (ret) { 602 wx_err(wx, "failed to init gpio\n"); 603 goto err_destroy_phylink; 604 } 605 606 ret = txgbe_clock_register(txgbe); 607 if (ret) { 608 wx_err(wx, "failed to register clock: %d\n", ret); 609 goto err_destroy_phylink; 610 } 611 612 ret = txgbe_i2c_register(txgbe); 613 if (ret) { 614 wx_err(wx, "failed to init i2c interface: %d\n", ret); 615 goto err_unregister_clk; 616 } 617 618 ret = txgbe_sfp_register(txgbe); 619 if (ret) { 620 wx_err(wx, "failed to register sfp\n"); 621 goto err_unregister_i2c; 622 } 623 624 return 0; 625 626 err_unregister_i2c: 627 platform_device_unregister(txgbe->i2c_dev); 628 err_unregister_clk: 629 clkdev_drop(txgbe->clock); 630 clk_unregister(txgbe->clk); 631 err_destroy_phylink: 632 phylink_destroy(wx->phylink); 633 err_destroy_xpcs: 634 xpcs_destroy_pcs(txgbe->pcs); 635 err_unregister_swnode: 636 software_node_unregister_node_group(txgbe->nodes.group); 637 638 return ret; 639 } 640 641 void txgbe_remove_phy(struct txgbe *txgbe) 642 { 643 if (txgbe->wx->mac.type == wx_mac_aml) 644 return; 645 646 if (txgbe->wx->media_type == sp_media_copper) { 647 phylink_disconnect_phy(txgbe->wx->phylink); 648 phylink_destroy(txgbe->wx->phylink); 649 return; 650 } 651 652 platform_device_unregister(txgbe->sfp_dev); 653 platform_device_unregister(txgbe->i2c_dev); 654 clkdev_drop(txgbe->clock); 655 clk_unregister(txgbe->clk); 656 phylink_destroy(txgbe->wx->phylink); 657 xpcs_destroy_pcs(txgbe->pcs); 658 software_node_unregister_node_group(txgbe->nodes.group); 659 } 660