1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/gpio/machine.h> 5 #include <linux/gpio/driver.h> 6 #include <linux/gpio/property.h> 7 #include <linux/clk-provider.h> 8 #include <linux/clkdev.h> 9 #include <linux/i2c.h> 10 #include <linux/pci.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 #include <linux/pcs/pcs-xpcs.h> 14 #include <linux/phylink.h> 15 16 #include "../libwx/wx_type.h" 17 #include "../libwx/wx_lib.h" 18 #include "../libwx/wx_ptp.h" 19 #include "../libwx/wx_hw.h" 20 #include "txgbe_type.h" 21 #include "txgbe_phy.h" 22 #include "txgbe_hw.h" 23 24 static int txgbe_swnodes_register(struct txgbe *txgbe) 25 { 26 struct txgbe_nodes *nodes = &txgbe->nodes; 27 struct pci_dev *pdev = txgbe->wx->pdev; 28 struct software_node *swnodes; 29 u32 id; 30 31 id = pci_dev_id(pdev); 32 33 snprintf(nodes->gpio_name, sizeof(nodes->gpio_name), "txgbe_gpio-%x", id); 34 snprintf(nodes->i2c_name, sizeof(nodes->i2c_name), "txgbe_i2c-%x", id); 35 snprintf(nodes->sfp_name, sizeof(nodes->sfp_name), "txgbe_sfp-%x", id); 36 snprintf(nodes->phylink_name, sizeof(nodes->phylink_name), "txgbe_phylink-%x", id); 37 38 swnodes = nodes->swnodes; 39 40 /* GPIO 0: tx fault 41 * GPIO 1: tx disable 42 * GPIO 2: sfp module absent 43 * GPIO 3: rx signal lost 44 * GPIO 4: rate select, 1G(0) 10G(1) 45 * GPIO 5: rate select, 1G(0) 10G(1) 46 */ 47 nodes->gpio_props[0] = PROPERTY_ENTRY_STRING("pinctrl-names", "default"); 48 swnodes[SWNODE_GPIO] = NODE_PROP(nodes->gpio_name, nodes->gpio_props); 49 nodes->gpio0_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 0, GPIO_ACTIVE_HIGH); 50 nodes->gpio1_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 1, GPIO_ACTIVE_HIGH); 51 nodes->gpio2_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 2, GPIO_ACTIVE_LOW); 52 nodes->gpio3_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 3, GPIO_ACTIVE_HIGH); 53 nodes->gpio4_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 4, GPIO_ACTIVE_HIGH); 54 nodes->gpio5_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 5, GPIO_ACTIVE_HIGH); 55 56 nodes->i2c_props[0] = PROPERTY_ENTRY_STRING("compatible", "snps,designware-i2c"); 57 nodes->i2c_props[1] = PROPERTY_ENTRY_BOOL("wx,i2c-snps-model"); 58 nodes->i2c_props[2] = PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ); 59 swnodes[SWNODE_I2C] = NODE_PROP(nodes->i2c_name, nodes->i2c_props); 60 nodes->i2c_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_I2C]); 61 62 nodes->sfp_props[0] = PROPERTY_ENTRY_STRING("compatible", "sff,sfp"); 63 nodes->sfp_props[1] = PROPERTY_ENTRY_REF_ARRAY("i2c-bus", nodes->i2c_ref); 64 nodes->sfp_props[2] = PROPERTY_ENTRY_REF_ARRAY("tx-fault-gpios", nodes->gpio0_ref); 65 nodes->sfp_props[3] = PROPERTY_ENTRY_REF_ARRAY("tx-disable-gpios", nodes->gpio1_ref); 66 nodes->sfp_props[4] = PROPERTY_ENTRY_REF_ARRAY("mod-def0-gpios", nodes->gpio2_ref); 67 nodes->sfp_props[5] = PROPERTY_ENTRY_REF_ARRAY("los-gpios", nodes->gpio3_ref); 68 nodes->sfp_props[6] = PROPERTY_ENTRY_REF_ARRAY("rate-select1-gpios", nodes->gpio4_ref); 69 nodes->sfp_props[7] = PROPERTY_ENTRY_REF_ARRAY("rate-select0-gpios", nodes->gpio5_ref); 70 swnodes[SWNODE_SFP] = NODE_PROP(nodes->sfp_name, nodes->sfp_props); 71 nodes->sfp_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_SFP]); 72 73 nodes->phylink_props[0] = PROPERTY_ENTRY_STRING("managed", "in-band-status"); 74 nodes->phylink_props[1] = PROPERTY_ENTRY_REF_ARRAY("sfp", nodes->sfp_ref); 75 swnodes[SWNODE_PHYLINK] = NODE_PROP(nodes->phylink_name, nodes->phylink_props); 76 77 nodes->group[SWNODE_GPIO] = &swnodes[SWNODE_GPIO]; 78 nodes->group[SWNODE_I2C] = &swnodes[SWNODE_I2C]; 79 nodes->group[SWNODE_SFP] = &swnodes[SWNODE_SFP]; 80 nodes->group[SWNODE_PHYLINK] = &swnodes[SWNODE_PHYLINK]; 81 82 return software_node_register_node_group(nodes->group); 83 } 84 85 static int txgbe_pcs_read(struct mii_bus *bus, int addr, int devnum, int regnum) 86 { 87 struct wx *wx = bus->priv; 88 u32 offset, val; 89 90 if (addr) 91 return -EOPNOTSUPP; 92 93 offset = devnum << 16 | regnum; 94 95 /* Set the LAN port indicator to IDA_ADDR */ 96 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset); 97 98 /* Read the data from IDA_DATA register */ 99 val = rd32(wx, TXGBE_XPCS_IDA_DATA); 100 101 return (u16)val; 102 } 103 104 static int txgbe_pcs_write(struct mii_bus *bus, int addr, int devnum, int regnum, u16 val) 105 { 106 struct wx *wx = bus->priv; 107 u32 offset; 108 109 if (addr) 110 return -EOPNOTSUPP; 111 112 offset = devnum << 16 | regnum; 113 114 /* Set the LAN port indicator to IDA_ADDR */ 115 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset); 116 117 /* Write the data to IDA_DATA register */ 118 wr32(wx, TXGBE_XPCS_IDA_DATA, val); 119 120 return 0; 121 } 122 123 static int txgbe_mdio_pcs_init(struct txgbe *txgbe) 124 { 125 struct mii_bus *mii_bus; 126 struct phylink_pcs *pcs; 127 struct pci_dev *pdev; 128 struct wx *wx; 129 int ret = 0; 130 131 wx = txgbe->wx; 132 pdev = wx->pdev; 133 134 mii_bus = devm_mdiobus_alloc(&pdev->dev); 135 if (!mii_bus) 136 return -ENOMEM; 137 138 mii_bus->name = "txgbe_pcs_mdio_bus"; 139 mii_bus->read_c45 = &txgbe_pcs_read; 140 mii_bus->write_c45 = &txgbe_pcs_write; 141 mii_bus->parent = &pdev->dev; 142 mii_bus->phy_mask = ~0; 143 mii_bus->priv = wx; 144 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe_pcs-%x", 145 pci_dev_id(pdev)); 146 147 ret = devm_mdiobus_register(&pdev->dev, mii_bus); 148 if (ret) 149 return ret; 150 151 pcs = xpcs_create_pcs_mdiodev(mii_bus, 0); 152 if (IS_ERR(pcs)) 153 return PTR_ERR(pcs); 154 155 txgbe->pcs = pcs; 156 157 return 0; 158 } 159 160 static struct phylink_pcs *txgbe_phylink_mac_select(struct phylink_config *config, 161 phy_interface_t interface) 162 { 163 struct wx *wx = phylink_to_wx(config); 164 struct txgbe *txgbe = wx->priv; 165 166 if (wx->media_type != sp_media_copper) 167 return txgbe->pcs; 168 169 return NULL; 170 } 171 172 static void txgbe_mac_config(struct phylink_config *config, unsigned int mode, 173 const struct phylink_link_state *state) 174 { 175 } 176 177 static void txgbe_mac_link_down(struct phylink_config *config, 178 unsigned int mode, phy_interface_t interface) 179 { 180 struct wx *wx = phylink_to_wx(config); 181 182 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0); 183 184 wx->speed = SPEED_UNKNOWN; 185 if (test_bit(WX_STATE_PTP_RUNNING, wx->state)) 186 wx_ptp_reset_cyclecounter(wx); 187 } 188 189 static void txgbe_mac_link_up(struct phylink_config *config, 190 struct phy_device *phy, 191 unsigned int mode, phy_interface_t interface, 192 int speed, int duplex, 193 bool tx_pause, bool rx_pause) 194 { 195 struct wx *wx = phylink_to_wx(config); 196 u32 txcfg, wdg; 197 198 wx_fc_enable(wx, tx_pause, rx_pause); 199 200 txcfg = rd32(wx, WX_MAC_TX_CFG); 201 txcfg &= ~WX_MAC_TX_CFG_SPEED_MASK; 202 203 switch (speed) { 204 case SPEED_10000: 205 txcfg |= WX_MAC_TX_CFG_SPEED_10G; 206 break; 207 case SPEED_1000: 208 case SPEED_100: 209 case SPEED_10: 210 txcfg |= WX_MAC_TX_CFG_SPEED_1G; 211 break; 212 default: 213 break; 214 } 215 216 wr32(wx, WX_MAC_TX_CFG, txcfg | WX_MAC_TX_CFG_TE); 217 218 /* Re configure MAC Rx */ 219 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE); 220 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR); 221 wdg = rd32(wx, WX_MAC_WDG_TIMEOUT); 222 wr32(wx, WX_MAC_WDG_TIMEOUT, wdg); 223 224 wx->speed = speed; 225 wx->last_rx_ptp_check = jiffies; 226 if (test_bit(WX_STATE_PTP_RUNNING, wx->state)) 227 wx_ptp_reset_cyclecounter(wx); 228 } 229 230 static int txgbe_mac_prepare(struct phylink_config *config, unsigned int mode, 231 phy_interface_t interface) 232 { 233 struct wx *wx = phylink_to_wx(config); 234 235 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0); 236 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, 0); 237 238 return txgbe_disable_sec_tx_path(wx); 239 } 240 241 static int txgbe_mac_finish(struct phylink_config *config, unsigned int mode, 242 phy_interface_t interface) 243 { 244 struct wx *wx = phylink_to_wx(config); 245 246 txgbe_enable_sec_tx_path(wx); 247 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE); 248 249 return 0; 250 } 251 252 static const struct phylink_mac_ops txgbe_mac_ops = { 253 .mac_select_pcs = txgbe_phylink_mac_select, 254 .mac_prepare = txgbe_mac_prepare, 255 .mac_finish = txgbe_mac_finish, 256 .mac_config = txgbe_mac_config, 257 .mac_link_down = txgbe_mac_link_down, 258 .mac_link_up = txgbe_mac_link_up, 259 }; 260 261 static int txgbe_phylink_init(struct txgbe *txgbe) 262 { 263 struct fwnode_handle *fwnode = NULL; 264 struct phylink_config *config; 265 struct wx *wx = txgbe->wx; 266 phy_interface_t phy_mode; 267 struct phylink *phylink; 268 269 config = &wx->phylink_config; 270 config->dev = &wx->netdev->dev; 271 config->type = PHYLINK_NETDEV; 272 config->mac_capabilities = MAC_10000FD | MAC_1000FD | MAC_100FD | 273 MAC_SYM_PAUSE | MAC_ASYM_PAUSE; 274 275 if (wx->media_type == sp_media_copper) { 276 phy_mode = PHY_INTERFACE_MODE_XAUI; 277 __set_bit(PHY_INTERFACE_MODE_XAUI, config->supported_interfaces); 278 } else { 279 phy_mode = PHY_INTERFACE_MODE_10GBASER; 280 fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_PHYLINK]); 281 __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces); 282 __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces); 283 __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); 284 } 285 286 phylink = phylink_create(config, fwnode, phy_mode, &txgbe_mac_ops); 287 if (IS_ERR(phylink)) 288 return PTR_ERR(phylink); 289 290 if (wx->phydev) { 291 int ret; 292 293 ret = phylink_connect_phy(phylink, wx->phydev); 294 if (ret) { 295 phylink_destroy(phylink); 296 return ret; 297 } 298 } 299 300 wx->phylink = phylink; 301 302 return 0; 303 } 304 305 irqreturn_t txgbe_link_irq_handler(int irq, void *data) 306 { 307 struct txgbe *txgbe = data; 308 struct wx *wx = txgbe->wx; 309 u32 status; 310 bool up; 311 312 status = rd32(wx, TXGBE_CFG_PORT_ST); 313 up = !!(status & TXGBE_CFG_PORT_ST_LINK_UP); 314 315 phylink_pcs_change(txgbe->pcs, up); 316 317 return IRQ_HANDLED; 318 } 319 320 static int txgbe_gpio_get(struct gpio_chip *chip, unsigned int offset) 321 { 322 struct wx *wx = gpiochip_get_data(chip); 323 int val; 324 325 val = rd32m(wx, WX_GPIO_EXT, BIT(offset)); 326 327 return !!(val & BIT(offset)); 328 } 329 330 static int txgbe_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 331 { 332 struct wx *wx = gpiochip_get_data(chip); 333 u32 val; 334 335 val = rd32(wx, WX_GPIO_DDR); 336 if (BIT(offset) & val) 337 return GPIO_LINE_DIRECTION_OUT; 338 339 return GPIO_LINE_DIRECTION_IN; 340 } 341 342 static int txgbe_gpio_direction_in(struct gpio_chip *chip, unsigned int offset) 343 { 344 struct wx *wx = gpiochip_get_data(chip); 345 unsigned long flags; 346 347 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 348 wr32m(wx, WX_GPIO_DDR, BIT(offset), 0); 349 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 350 351 return 0; 352 } 353 354 static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset, 355 int val) 356 { 357 struct wx *wx = gpiochip_get_data(chip); 358 unsigned long flags; 359 u32 set; 360 361 set = val ? BIT(offset) : 0; 362 363 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 364 wr32m(wx, WX_GPIO_DR, BIT(offset), set); 365 wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset)); 366 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 367 368 return 0; 369 } 370 371 static int txgbe_gpio_init(struct txgbe *txgbe) 372 { 373 struct gpio_chip *gc; 374 struct device *dev; 375 struct wx *wx; 376 int ret; 377 378 wx = txgbe->wx; 379 dev = &wx->pdev->dev; 380 381 raw_spin_lock_init(&wx->gpio_lock); 382 383 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 384 if (!gc) 385 return -ENOMEM; 386 387 gc->label = devm_kasprintf(dev, GFP_KERNEL, "txgbe_gpio-%x", 388 pci_dev_id(wx->pdev)); 389 if (!gc->label) 390 return -ENOMEM; 391 392 gc->base = -1; 393 gc->ngpio = 6; 394 gc->owner = THIS_MODULE; 395 gc->parent = dev; 396 gc->fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_GPIO]); 397 gc->get = txgbe_gpio_get; 398 gc->get_direction = txgbe_gpio_get_direction; 399 gc->direction_input = txgbe_gpio_direction_in; 400 gc->direction_output = txgbe_gpio_direction_out; 401 402 ret = devm_gpiochip_add_data(dev, gc, wx); 403 if (ret) 404 return ret; 405 406 txgbe->gpio = gc; 407 408 return 0; 409 } 410 411 static int txgbe_clock_register(struct txgbe *txgbe) 412 { 413 struct pci_dev *pdev = txgbe->wx->pdev; 414 struct clk_lookup *clock; 415 char clk_name[32]; 416 struct clk *clk; 417 418 snprintf(clk_name, sizeof(clk_name), "i2c_designware.%d", 419 pci_dev_id(pdev)); 420 421 clk = clk_register_fixed_rate(NULL, clk_name, NULL, 0, 156250000); 422 if (IS_ERR(clk)) 423 return PTR_ERR(clk); 424 425 clock = clkdev_create(clk, NULL, "%s", clk_name); 426 if (!clock) { 427 clk_unregister(clk); 428 return -ENOMEM; 429 } 430 431 txgbe->clk = clk; 432 txgbe->clock = clock; 433 434 return 0; 435 } 436 437 static int txgbe_i2c_read(void *context, unsigned int reg, unsigned int *val) 438 { 439 struct wx *wx = context; 440 441 *val = rd32(wx, reg + TXGBE_I2C_BASE); 442 443 return 0; 444 } 445 446 static int txgbe_i2c_write(void *context, unsigned int reg, unsigned int val) 447 { 448 struct wx *wx = context; 449 450 wr32(wx, reg + TXGBE_I2C_BASE, val); 451 452 return 0; 453 } 454 455 static const struct regmap_config i2c_regmap_config = { 456 .reg_bits = 32, 457 .val_bits = 32, 458 .reg_read = txgbe_i2c_read, 459 .reg_write = txgbe_i2c_write, 460 .fast_io = true, 461 }; 462 463 static int txgbe_i2c_register(struct txgbe *txgbe) 464 { 465 struct platform_device_info info = {}; 466 struct platform_device *i2c_dev; 467 struct regmap *i2c_regmap; 468 struct pci_dev *pdev; 469 struct wx *wx; 470 471 wx = txgbe->wx; 472 pdev = wx->pdev; 473 i2c_regmap = devm_regmap_init(&pdev->dev, NULL, wx, &i2c_regmap_config); 474 if (IS_ERR(i2c_regmap)) { 475 wx_err(wx, "failed to init I2C regmap\n"); 476 return PTR_ERR(i2c_regmap); 477 } 478 479 info.parent = &pdev->dev; 480 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_I2C]); 481 info.name = "i2c_designware"; 482 info.id = pci_dev_id(pdev); 483 484 info.res = &DEFINE_RES_IRQ(pdev->irq); 485 info.num_res = 1; 486 i2c_dev = platform_device_register_full(&info); 487 if (IS_ERR(i2c_dev)) 488 return PTR_ERR(i2c_dev); 489 490 txgbe->i2c_dev = i2c_dev; 491 492 return 0; 493 } 494 495 static int txgbe_sfp_register(struct txgbe *txgbe) 496 { 497 struct pci_dev *pdev = txgbe->wx->pdev; 498 struct platform_device_info info = {}; 499 struct platform_device *sfp_dev; 500 501 info.parent = &pdev->dev; 502 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_SFP]); 503 info.name = "sfp"; 504 info.id = pci_dev_id(pdev); 505 sfp_dev = platform_device_register_full(&info); 506 if (IS_ERR(sfp_dev)) 507 return PTR_ERR(sfp_dev); 508 509 txgbe->sfp_dev = sfp_dev; 510 511 return 0; 512 } 513 514 static int txgbe_ext_phy_init(struct txgbe *txgbe) 515 { 516 struct phy_device *phydev; 517 struct mii_bus *mii_bus; 518 struct pci_dev *pdev; 519 struct wx *wx; 520 int ret = 0; 521 522 wx = txgbe->wx; 523 pdev = wx->pdev; 524 525 mii_bus = devm_mdiobus_alloc(&pdev->dev); 526 if (!mii_bus) 527 return -ENOMEM; 528 529 mii_bus->name = "txgbe_mii_bus"; 530 mii_bus->read_c45 = &wx_phy_read_reg_mdi_c45; 531 mii_bus->write_c45 = &wx_phy_write_reg_mdi_c45; 532 mii_bus->parent = &pdev->dev; 533 mii_bus->phy_mask = GENMASK(31, 1); 534 mii_bus->priv = wx; 535 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe-%x", pci_dev_id(pdev)); 536 537 ret = devm_mdiobus_register(&pdev->dev, mii_bus); 538 if (ret) { 539 wx_err(wx, "failed to register MDIO bus: %d\n", ret); 540 return ret; 541 } 542 543 phydev = phy_find_first(mii_bus); 544 if (!phydev) { 545 wx_err(wx, "no PHY found\n"); 546 return -ENODEV; 547 } 548 549 phy_attached_info(phydev); 550 551 wx->link = 0; 552 wx->speed = 0; 553 wx->duplex = 0; 554 wx->phydev = phydev; 555 556 ret = txgbe_phylink_init(txgbe); 557 if (ret) { 558 wx_err(wx, "failed to init phylink: %d\n", ret); 559 return ret; 560 } 561 562 return 0; 563 } 564 565 int txgbe_init_phy(struct txgbe *txgbe) 566 { 567 struct wx *wx = txgbe->wx; 568 int ret; 569 570 if (wx->mac.type == wx_mac_aml) 571 return 0; 572 573 if (txgbe->wx->media_type == sp_media_copper) 574 return txgbe_ext_phy_init(txgbe); 575 576 ret = txgbe_swnodes_register(txgbe); 577 if (ret) { 578 wx_err(wx, "failed to register software nodes\n"); 579 return ret; 580 } 581 582 ret = txgbe_mdio_pcs_init(txgbe); 583 if (ret) { 584 wx_err(wx, "failed to init mdio pcs: %d\n", ret); 585 goto err_unregister_swnode; 586 } 587 588 ret = txgbe_phylink_init(txgbe); 589 if (ret) { 590 wx_err(wx, "failed to init phylink\n"); 591 goto err_destroy_xpcs; 592 } 593 594 ret = txgbe_gpio_init(txgbe); 595 if (ret) { 596 wx_err(wx, "failed to init gpio\n"); 597 goto err_destroy_phylink; 598 } 599 600 ret = txgbe_clock_register(txgbe); 601 if (ret) { 602 wx_err(wx, "failed to register clock: %d\n", ret); 603 goto err_destroy_phylink; 604 } 605 606 ret = txgbe_i2c_register(txgbe); 607 if (ret) { 608 wx_err(wx, "failed to init i2c interface: %d\n", ret); 609 goto err_unregister_clk; 610 } 611 612 ret = txgbe_sfp_register(txgbe); 613 if (ret) { 614 wx_err(wx, "failed to register sfp\n"); 615 goto err_unregister_i2c; 616 } 617 618 return 0; 619 620 err_unregister_i2c: 621 platform_device_unregister(txgbe->i2c_dev); 622 err_unregister_clk: 623 clkdev_drop(txgbe->clock); 624 clk_unregister(txgbe->clk); 625 err_destroy_phylink: 626 phylink_destroy(wx->phylink); 627 err_destroy_xpcs: 628 xpcs_destroy_pcs(txgbe->pcs); 629 err_unregister_swnode: 630 software_node_unregister_node_group(txgbe->nodes.group); 631 632 return ret; 633 } 634 635 void txgbe_remove_phy(struct txgbe *txgbe) 636 { 637 if (txgbe->wx->mac.type == wx_mac_aml) 638 return; 639 640 if (txgbe->wx->media_type == sp_media_copper) { 641 phylink_disconnect_phy(txgbe->wx->phylink); 642 phylink_destroy(txgbe->wx->phylink); 643 return; 644 } 645 646 platform_device_unregister(txgbe->sfp_dev); 647 platform_device_unregister(txgbe->i2c_dev); 648 clkdev_drop(txgbe->clock); 649 clk_unregister(txgbe->clk); 650 phylink_destroy(txgbe->wx->phylink); 651 xpcs_destroy_pcs(txgbe->pcs); 652 software_node_unregister_node_group(txgbe->nodes.group); 653 } 654