1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/iopoll.h> 10 #include <linux/phy/phy.h> 11 #include <net/pkt_sched.h> 12 #include <soc/mscc/ocelot_hsio.h> 13 #include <soc/mscc/ocelot_vcap.h> 14 #include "ocelot.h" 15 #include "ocelot_vcap.h" 16 17 #define TABLE_UPDATE_SLEEP_US 10 18 #define TABLE_UPDATE_TIMEOUT_US 100000 19 #define MEM_INIT_SLEEP_US 1000 20 #define MEM_INIT_TIMEOUT_US 100000 21 22 #define OCELOT_RSV_VLAN_RANGE_START 4000 23 24 struct ocelot_mact_entry { 25 u8 mac[ETH_ALEN]; 26 u16 vid; 27 enum macaccess_entry_type type; 28 }; 29 30 /* Caller must hold &ocelot->mact_lock */ 31 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 32 { 33 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 34 } 35 36 /* Caller must hold &ocelot->mact_lock */ 37 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 38 { 39 u32 val; 40 41 return readx_poll_timeout(ocelot_mact_read_macaccess, 42 ocelot, val, 43 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 44 MACACCESS_CMD_IDLE, 45 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 46 } 47 48 /* Caller must hold &ocelot->mact_lock */ 49 static void ocelot_mact_select(struct ocelot *ocelot, 50 const unsigned char mac[ETH_ALEN], 51 unsigned int vid) 52 { 53 u32 macl = 0, mach = 0; 54 55 /* Set the MAC address to handle and the vlan associated in a format 56 * understood by the hardware. 57 */ 58 mach |= vid << 16; 59 mach |= mac[0] << 8; 60 mach |= mac[1] << 0; 61 macl |= mac[2] << 24; 62 macl |= mac[3] << 16; 63 macl |= mac[4] << 8; 64 macl |= mac[5] << 0; 65 66 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 67 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 68 69 } 70 71 static int __ocelot_mact_learn(struct ocelot *ocelot, int port, 72 const unsigned char mac[ETH_ALEN], 73 unsigned int vid, enum macaccess_entry_type type) 74 { 75 u32 cmd = ANA_TABLES_MACACCESS_VALID | 76 ANA_TABLES_MACACCESS_DEST_IDX(port) | 77 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 78 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 79 unsigned int mc_ports; 80 int err; 81 82 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 83 if (type == ENTRYTYPE_MACv4) 84 mc_ports = (mac[1] << 8) | mac[2]; 85 else if (type == ENTRYTYPE_MACv6) 86 mc_ports = (mac[0] << 8) | mac[1]; 87 else 88 mc_ports = 0; 89 90 if (mc_ports & BIT(ocelot->num_phys_ports)) 91 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 92 93 ocelot_mact_select(ocelot, mac, vid); 94 95 /* Issue a write command */ 96 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 97 98 err = ocelot_mact_wait_for_completion(ocelot); 99 100 return err; 101 } 102 103 int ocelot_mact_learn(struct ocelot *ocelot, int port, 104 const unsigned char mac[ETH_ALEN], 105 unsigned int vid, enum macaccess_entry_type type) 106 { 107 int ret; 108 109 mutex_lock(&ocelot->mact_lock); 110 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type); 111 mutex_unlock(&ocelot->mact_lock); 112 113 return ret; 114 } 115 EXPORT_SYMBOL(ocelot_mact_learn); 116 117 int ocelot_mact_forget(struct ocelot *ocelot, 118 const unsigned char mac[ETH_ALEN], unsigned int vid) 119 { 120 int err; 121 122 mutex_lock(&ocelot->mact_lock); 123 124 ocelot_mact_select(ocelot, mac, vid); 125 126 /* Issue a forget command */ 127 ocelot_write(ocelot, 128 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 129 ANA_TABLES_MACACCESS); 130 131 err = ocelot_mact_wait_for_completion(ocelot); 132 133 mutex_unlock(&ocelot->mact_lock); 134 135 return err; 136 } 137 EXPORT_SYMBOL(ocelot_mact_forget); 138 139 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx, 140 const unsigned char mac[ETH_ALEN], 141 unsigned int vid, enum macaccess_entry_type *type) 142 { 143 int val; 144 145 mutex_lock(&ocelot->mact_lock); 146 147 ocelot_mact_select(ocelot, mac, vid); 148 149 /* Issue a read command with MACACCESS_VALID=1. */ 150 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 151 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 152 ANA_TABLES_MACACCESS); 153 154 if (ocelot_mact_wait_for_completion(ocelot)) { 155 mutex_unlock(&ocelot->mact_lock); 156 return -ETIMEDOUT; 157 } 158 159 /* Read back the entry flags */ 160 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 161 162 mutex_unlock(&ocelot->mact_lock); 163 164 if (!(val & ANA_TABLES_MACACCESS_VALID)) 165 return -ENOENT; 166 167 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val); 168 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val); 169 170 return 0; 171 } 172 EXPORT_SYMBOL(ocelot_mact_lookup); 173 174 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx, 175 const unsigned char mac[ETH_ALEN], 176 unsigned int vid, 177 enum macaccess_entry_type type, 178 int sfid, int ssid) 179 { 180 int ret; 181 182 mutex_lock(&ocelot->mact_lock); 183 184 ocelot_write(ocelot, 185 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) | 186 ANA_TABLES_STREAMDATA_SFID(sfid) | 187 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) | 188 ANA_TABLES_STREAMDATA_SSID(ssid), 189 ANA_TABLES_STREAMDATA); 190 191 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type); 192 193 mutex_unlock(&ocelot->mact_lock); 194 195 return ret; 196 } 197 EXPORT_SYMBOL(ocelot_mact_learn_streamdata); 198 199 static void ocelot_mact_init(struct ocelot *ocelot) 200 { 201 /* Configure the learning mode entries attributes: 202 * - Do not copy the frame to the CPU extraction queues. 203 * - Use the vlan and mac_cpoy for dmac lookup. 204 */ 205 ocelot_rmw(ocelot, 0, 206 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 207 | ANA_AGENCTRL_LEARN_FWD_KILL 208 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 209 ANA_AGENCTRL); 210 211 /* Clear the MAC table. We are not concurrent with anyone, so 212 * holding &ocelot->mact_lock is pointless. 213 */ 214 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 215 } 216 217 void ocelot_pll5_init(struct ocelot *ocelot) 218 { 219 /* Configure PLL5. This will need a proper CCF driver 220 * The values are coming from the VTSS API for Ocelot 221 */ 222 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, 223 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | 224 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); 225 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, 226 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | 227 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | 228 HSIO_PLL5G_CFG0_ENA_BIAS | 229 HSIO_PLL5G_CFG0_ENA_VCO_BUF | 230 HSIO_PLL5G_CFG0_ENA_CP1 | 231 HSIO_PLL5G_CFG0_SELCPI(2) | 232 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | 233 HSIO_PLL5G_CFG0_SELBGV820(4) | 234 HSIO_PLL5G_CFG0_DIV4 | 235 HSIO_PLL5G_CFG0_ENA_CLKTREE | 236 HSIO_PLL5G_CFG0_ENA_LANE); 237 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, 238 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | 239 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | 240 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | 241 HSIO_PLL5G_CFG2_ENA_AMPCTRL | 242 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | 243 HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); 244 } 245 EXPORT_SYMBOL(ocelot_pll5_init); 246 247 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 248 { 249 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 250 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 251 ANA_PORT_VCAP_S2_CFG, port); 252 253 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 254 ANA_PORT_VCAP_CFG, port); 255 256 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 257 REW_PORT_CFG_ES0_EN, 258 REW_PORT_CFG, port); 259 } 260 261 static int ocelot_single_vlan_aware_bridge(struct ocelot *ocelot, 262 struct netlink_ext_ack *extack) 263 { 264 struct net_device *bridge = NULL; 265 int port; 266 267 for (port = 0; port < ocelot->num_phys_ports; port++) { 268 struct ocelot_port *ocelot_port = ocelot->ports[port]; 269 270 if (!ocelot_port || !ocelot_port->bridge || 271 !br_vlan_enabled(ocelot_port->bridge)) 272 continue; 273 274 if (!bridge) { 275 bridge = ocelot_port->bridge; 276 continue; 277 } 278 279 if (bridge == ocelot_port->bridge) 280 continue; 281 282 NL_SET_ERR_MSG_MOD(extack, 283 "Only one VLAN-aware bridge is supported"); 284 return -EBUSY; 285 } 286 287 return 0; 288 } 289 290 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 291 { 292 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 293 } 294 295 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 296 { 297 u32 val; 298 299 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 300 ocelot, 301 val, 302 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 303 ANA_TABLES_VLANACCESS_CMD_IDLE, 304 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 305 } 306 307 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 308 { 309 /* Select the VID to configure */ 310 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 311 ANA_TABLES_VLANTIDX); 312 /* Set the vlan port members mask and issue a write command */ 313 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 314 ANA_TABLES_VLANACCESS_CMD_WRITE, 315 ANA_TABLES_VLANACCESS); 316 317 return ocelot_vlant_wait_for_completion(ocelot); 318 } 319 320 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port) 321 { 322 struct ocelot_bridge_vlan *vlan; 323 int num_untagged = 0; 324 325 list_for_each_entry(vlan, &ocelot->vlans, list) { 326 if (!(vlan->portmask & BIT(port))) 327 continue; 328 329 /* Ignore the VLAN added by ocelot_add_vlan_unaware_pvid(), 330 * because this is never active in hardware at the same time as 331 * the bridge VLANs, which only matter in VLAN-aware mode. 332 */ 333 if (vlan->vid >= OCELOT_RSV_VLAN_RANGE_START) 334 continue; 335 336 if (vlan->untagged & BIT(port)) 337 num_untagged++; 338 } 339 340 return num_untagged; 341 } 342 343 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port) 344 { 345 struct ocelot_bridge_vlan *vlan; 346 int num_tagged = 0; 347 348 list_for_each_entry(vlan, &ocelot->vlans, list) { 349 if (!(vlan->portmask & BIT(port))) 350 continue; 351 352 if (!(vlan->untagged & BIT(port))) 353 num_tagged++; 354 } 355 356 return num_tagged; 357 } 358 359 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly 360 * _one_ egress-untagged VLAN (_the_ native VLAN) 361 */ 362 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port) 363 { 364 return ocelot_port_num_tagged_vlans(ocelot, port) && 365 ocelot_port_num_untagged_vlans(ocelot, port) == 1; 366 } 367 368 static struct ocelot_bridge_vlan * 369 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port) 370 { 371 struct ocelot_bridge_vlan *vlan; 372 373 list_for_each_entry(vlan, &ocelot->vlans, list) 374 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port)) 375 return vlan; 376 377 return NULL; 378 } 379 380 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable, 381 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness 382 * state of the port. 383 */ 384 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port) 385 { 386 struct ocelot_port *ocelot_port = ocelot->ports[port]; 387 enum ocelot_port_tag_config tag_cfg; 388 bool uses_native_vlan = false; 389 390 if (ocelot_port->vlan_aware) { 391 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port); 392 393 if (uses_native_vlan) 394 tag_cfg = OCELOT_PORT_TAG_NATIVE; 395 else if (ocelot_port_num_untagged_vlans(ocelot, port)) 396 tag_cfg = OCELOT_PORT_TAG_DISABLED; 397 else 398 tag_cfg = OCELOT_PORT_TAG_TRUNK; 399 } else { 400 tag_cfg = OCELOT_PORT_TAG_DISABLED; 401 } 402 403 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg), 404 REW_TAG_CFG_TAG_CFG_M, 405 REW_TAG_CFG, port); 406 407 if (uses_native_vlan) { 408 struct ocelot_bridge_vlan *native_vlan; 409 410 /* Not having a native VLAN is impossible, because 411 * ocelot_port_num_untagged_vlans has returned 1. 412 * So there is no use in checking for NULL here. 413 */ 414 native_vlan = ocelot_port_find_native_vlan(ocelot, port); 415 416 ocelot_rmw_gix(ocelot, 417 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid), 418 REW_PORT_VLAN_CFG_PORT_VID_M, 419 REW_PORT_VLAN_CFG, port); 420 } 421 } 422 423 int ocelot_bridge_num_find(struct ocelot *ocelot, 424 const struct net_device *bridge) 425 { 426 int port; 427 428 for (port = 0; port < ocelot->num_phys_ports; port++) { 429 struct ocelot_port *ocelot_port = ocelot->ports[port]; 430 431 if (ocelot_port && ocelot_port->bridge == bridge) 432 return ocelot_port->bridge_num; 433 } 434 435 return -1; 436 } 437 EXPORT_SYMBOL_GPL(ocelot_bridge_num_find); 438 439 static u16 ocelot_vlan_unaware_pvid(struct ocelot *ocelot, 440 const struct net_device *bridge) 441 { 442 int bridge_num; 443 444 /* Standalone ports use VID 0 */ 445 if (!bridge) 446 return 0; 447 448 bridge_num = ocelot_bridge_num_find(ocelot, bridge); 449 if (WARN_ON(bridge_num < 0)) 450 return 0; 451 452 /* VLAN-unaware bridges use a reserved VID going from 4095 downwards */ 453 return VLAN_N_VID - bridge_num - 1; 454 } 455 456 /** 457 * ocelot_update_vlan_reclassify_rule() - Make switch aware only to bridge VLAN TPID 458 * 459 * @ocelot: Switch private data structure 460 * @port: Index of ingress port 461 * 462 * IEEE 802.1Q-2018 clauses "5.5 C-VLAN component conformance" and "5.6 S-VLAN 463 * component conformance" suggest that a C-VLAN component should only recognize 464 * and filter on C-Tags, and an S-VLAN component should only recognize and 465 * process based on C-Tags. 466 * 467 * In Linux, as per commit 1a0b20b25732 ("Merge branch 'bridge-next'"), C-VLAN 468 * components are largely represented by a bridge with vlan_protocol 802.1Q, 469 * and S-VLAN components by a bridge with vlan_protocol 802.1ad. 470 * 471 * Currently the driver only offloads vlan_protocol 802.1Q, but the hardware 472 * design is non-conformant, because the switch assigns each frame to a VLAN 473 * based on an entirely different question, as detailed in figure "Basic VLAN 474 * Classification Flow" from its manual and reproduced below. 475 * 476 * Set TAG_TYPE, PCP, DEI, VID to port-default values in VLAN_CFG register 477 * if VLAN_AWARE_ENA[port] and frame has outer tag then: 478 * if VLAN_INNER_TAG_ENA[port] and frame has inner tag then: 479 * TAG_TYPE = (Frame.InnerTPID <> 0x8100) 480 * Set PCP, DEI, VID to values from inner VLAN header 481 * else: 482 * TAG_TYPE = (Frame.OuterTPID <> 0x8100) 483 * Set PCP, DEI, VID to values from outer VLAN header 484 * if VID == 0 then: 485 * VID = VLAN_CFG.VLAN_VID 486 * 487 * Summarized, the switch will recognize both 802.1Q and 802.1ad TPIDs as VLAN 488 * "with equal rights", and just set the TAG_TYPE bit to 0 (if 802.1Q) or to 1 489 * (if 802.1ad). It will classify based on whichever of the tags is "outer", no 490 * matter what TPID that may have (or "inner", if VLAN_INNER_TAG_ENA[port]). 491 * 492 * In the VLAN Table, the TAG_TYPE information is not accessible - just the 493 * classified VID is - so it is as if each VLAN Table entry is for 2 VLANs: 494 * C-VLAN X, and S-VLAN X. 495 * 496 * Whereas the Linux bridge behavior is to only filter on frames with a TPID 497 * equal to the vlan_protocol, and treat everything else as VLAN-untagged. 498 * 499 * Consider an ingress packet tagged with 802.1ad VID=3 and 802.1Q VID=5, 500 * received on a bridge vlan_filtering=1 vlan_protocol=802.1Q port. This frame 501 * should be treated as 802.1Q-untagged, and classified to the PVID of that 502 * bridge port. Not to VID=3, and not to VID=5. 503 * 504 * The VCAP IS1 TCAM has everything we need to overwrite the choices made in 505 * the basic VLAN classification pipeline: it can match on TAG_TYPE in the key, 506 * and it can modify the classified VID in the action. Thus, for each port 507 * under a vlan_filtering bridge, we can insert a rule in VCAP IS1 lookup 0 to 508 * match on 802.1ad tagged frames and modify their classified VID to the 802.1Q 509 * PVID of the port. This effectively makes it appear to the outside world as 510 * if those packets were processed as VLAN-untagged. 511 * 512 * The rule needs to be updated each time the bridge PVID changes, and needs 513 * to be deleted if the bridge PVID is deleted, or if the port becomes 514 * VLAN-unaware. 515 */ 516 static int ocelot_update_vlan_reclassify_rule(struct ocelot *ocelot, int port) 517 { 518 unsigned long cookie = OCELOT_VCAP_IS1_VLAN_RECLASSIFY(ocelot, port); 519 struct ocelot_vcap_block *block_vcap_is1 = &ocelot->block[VCAP_IS1]; 520 struct ocelot_port *ocelot_port = ocelot->ports[port]; 521 const struct ocelot_bridge_vlan *pvid_vlan; 522 struct ocelot_vcap_filter *filter; 523 int err, val, pcp, dei; 524 bool vid_replace_ena; 525 u16 vid; 526 527 pvid_vlan = ocelot_port->pvid_vlan; 528 vid_replace_ena = ocelot_port->vlan_aware && pvid_vlan; 529 530 filter = ocelot_vcap_block_find_filter_by_id(block_vcap_is1, cookie, 531 false); 532 if (!vid_replace_ena) { 533 /* If the reclassification filter doesn't need to exist, delete 534 * it if it was previously installed, and exit doing nothing 535 * otherwise. 536 */ 537 if (filter) 538 return ocelot_vcap_filter_del(ocelot, filter); 539 540 return 0; 541 } 542 543 /* The reclassification rule must apply. See if it already exists 544 * or if it must be created. 545 */ 546 547 /* Treating as VLAN-untagged means using as classified VID equal to 548 * the bridge PVID, and PCP/DEI set to the port default QoS values. 549 */ 550 vid = pvid_vlan->vid; 551 val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port); 552 pcp = ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val); 553 dei = !!(val & ANA_PORT_QOS_CFG_DP_DEFAULT_VAL); 554 555 if (filter) { 556 bool changed = false; 557 558 /* Filter exists, just update it */ 559 if (filter->action.vid != vid) { 560 filter->action.vid = vid; 561 changed = true; 562 } 563 if (filter->action.pcp != pcp) { 564 filter->action.pcp = pcp; 565 changed = true; 566 } 567 if (filter->action.dei != dei) { 568 filter->action.dei = dei; 569 changed = true; 570 } 571 572 if (!changed) 573 return 0; 574 575 return ocelot_vcap_filter_replace(ocelot, filter); 576 } 577 578 /* Filter doesn't exist, create it */ 579 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 580 if (!filter) 581 return -ENOMEM; 582 583 filter->key_type = OCELOT_VCAP_KEY_ANY; 584 filter->ingress_port_mask = BIT(port); 585 filter->vlan.tpid = OCELOT_VCAP_BIT_1; 586 filter->prio = 1; 587 filter->id.cookie = cookie; 588 filter->id.tc_offload = false; 589 filter->block_id = VCAP_IS1; 590 filter->type = OCELOT_VCAP_FILTER_OFFLOAD; 591 filter->lookup = 0; 592 filter->action.vid_replace_ena = true; 593 filter->action.pcp_dei_ena = true; 594 filter->action.vid = vid; 595 filter->action.pcp = pcp; 596 filter->action.dei = dei; 597 598 err = ocelot_vcap_filter_add(ocelot, filter, NULL); 599 if (err) 600 kfree(filter); 601 602 return err; 603 } 604 605 /* Default vlan to clasify for untagged frames (may be zero) */ 606 static int ocelot_port_set_pvid(struct ocelot *ocelot, int port, 607 const struct ocelot_bridge_vlan *pvid_vlan) 608 { 609 struct ocelot_port *ocelot_port = ocelot->ports[port]; 610 u16 pvid = ocelot_vlan_unaware_pvid(ocelot, ocelot_port->bridge); 611 u32 val = 0; 612 613 ocelot_port->pvid_vlan = pvid_vlan; 614 615 if (ocelot_port->vlan_aware && pvid_vlan) 616 pvid = pvid_vlan->vid; 617 618 ocelot_rmw_gix(ocelot, 619 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 620 ANA_PORT_VLAN_CFG_VLAN_VID_M, 621 ANA_PORT_VLAN_CFG, port); 622 623 /* If there's no pvid, we should drop not only untagged traffic (which 624 * happens automatically), but also 802.1p traffic which gets 625 * classified to VLAN 0, but that is always in our RX filter, so it 626 * would get accepted were it not for this setting. 627 * 628 * Also, we only support the bridge 802.1Q VLAN protocol, so 629 * 802.1ad-tagged frames (carrying S-Tags) should be considered 630 * 802.1Q-untagged, and also dropped. 631 */ 632 if (!pvid_vlan && ocelot_port->vlan_aware) 633 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 634 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA | 635 ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA; 636 637 ocelot_rmw_gix(ocelot, val, 638 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 639 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA | 640 ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA, 641 ANA_PORT_DROP_CFG, port); 642 643 return ocelot_update_vlan_reclassify_rule(ocelot, port); 644 } 645 646 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot, 647 u16 vid) 648 { 649 struct ocelot_bridge_vlan *vlan; 650 651 list_for_each_entry(vlan, &ocelot->vlans, list) 652 if (vlan->vid == vid) 653 return vlan; 654 655 return NULL; 656 } 657 658 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid, 659 bool untagged) 660 { 661 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 662 unsigned long portmask; 663 int err; 664 665 if (vlan) { 666 portmask = vlan->portmask | BIT(port); 667 668 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 669 if (err) 670 return err; 671 672 vlan->portmask = portmask; 673 /* Bridge VLANs can be overwritten with a different 674 * egress-tagging setting, so make sure to override an untagged 675 * with a tagged VID if that's going on. 676 */ 677 if (untagged) 678 vlan->untagged |= BIT(port); 679 else 680 vlan->untagged &= ~BIT(port); 681 682 return 0; 683 } 684 685 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 686 if (!vlan) 687 return -ENOMEM; 688 689 portmask = BIT(port); 690 691 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 692 if (err) { 693 kfree(vlan); 694 return err; 695 } 696 697 vlan->vid = vid; 698 vlan->portmask = portmask; 699 if (untagged) 700 vlan->untagged = BIT(port); 701 INIT_LIST_HEAD(&vlan->list); 702 list_add_tail(&vlan->list, &ocelot->vlans); 703 704 return 0; 705 } 706 707 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid) 708 { 709 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 710 unsigned long portmask; 711 int err; 712 713 if (!vlan) 714 return 0; 715 716 portmask = vlan->portmask & ~BIT(port); 717 718 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 719 if (err) 720 return err; 721 722 vlan->portmask = portmask; 723 if (vlan->portmask) 724 return 0; 725 726 list_del(&vlan->list); 727 kfree(vlan); 728 729 return 0; 730 } 731 732 static int ocelot_add_vlan_unaware_pvid(struct ocelot *ocelot, int port, 733 const struct net_device *bridge) 734 { 735 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 736 737 return ocelot_vlan_member_add(ocelot, port, vid, true); 738 } 739 740 static int ocelot_del_vlan_unaware_pvid(struct ocelot *ocelot, int port, 741 const struct net_device *bridge) 742 { 743 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 744 745 return ocelot_vlan_member_del(ocelot, port, vid); 746 } 747 748 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 749 bool vlan_aware, struct netlink_ext_ack *extack) 750 { 751 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 752 struct ocelot_port *ocelot_port = ocelot->ports[port]; 753 struct ocelot_vcap_filter *filter; 754 int err = 0; 755 u32 val; 756 757 list_for_each_entry(filter, &block->rules, list) { 758 if (filter->ingress_port_mask & BIT(port) && 759 filter->action.vid_replace_ena) { 760 NL_SET_ERR_MSG_MOD(extack, 761 "Cannot change VLAN state with vlan modify rules active"); 762 return -EBUSY; 763 } 764 } 765 766 err = ocelot_single_vlan_aware_bridge(ocelot, extack); 767 if (err) 768 return err; 769 770 if (vlan_aware) 771 err = ocelot_del_vlan_unaware_pvid(ocelot, port, 772 ocelot_port->bridge); 773 else if (ocelot_port->bridge) 774 err = ocelot_add_vlan_unaware_pvid(ocelot, port, 775 ocelot_port->bridge); 776 if (err) 777 return err; 778 779 ocelot_port->vlan_aware = vlan_aware; 780 781 if (vlan_aware) 782 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 783 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 784 else 785 val = 0; 786 ocelot_rmw_gix(ocelot, val, 787 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 788 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 789 ANA_PORT_VLAN_CFG, port); 790 791 err = ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 792 if (err) 793 return err; 794 795 ocelot_port_manage_port_tag(ocelot, port); 796 797 return 0; 798 } 799 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 800 801 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 802 bool untagged, struct netlink_ext_ack *extack) 803 { 804 if (untagged) { 805 /* We are adding an egress-tagged VLAN */ 806 if (ocelot_port_uses_native_vlan(ocelot, port)) { 807 NL_SET_ERR_MSG_MOD(extack, 808 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN"); 809 return -EBUSY; 810 } 811 } else { 812 /* We are adding an egress-tagged VLAN */ 813 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) { 814 NL_SET_ERR_MSG_MOD(extack, 815 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs"); 816 return -EBUSY; 817 } 818 } 819 820 if (vid > OCELOT_RSV_VLAN_RANGE_START) { 821 NL_SET_ERR_MSG_MOD(extack, 822 "VLAN range 4000-4095 reserved for VLAN-unaware bridging"); 823 return -EBUSY; 824 } 825 826 return 0; 827 } 828 EXPORT_SYMBOL(ocelot_vlan_prepare); 829 830 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 831 bool untagged) 832 { 833 struct ocelot_port *ocelot_port = ocelot->ports[port]; 834 int err; 835 836 /* Ignore VID 0 added to our RX filter by the 8021q module, since 837 * that collides with OCELOT_STANDALONE_PVID and changes it from 838 * egress-untagged to egress-tagged. 839 */ 840 if (!vid) 841 return 0; 842 843 err = ocelot_vlan_member_add(ocelot, port, vid, untagged); 844 if (err) 845 return err; 846 847 /* Default ingress vlan classification */ 848 if (pvid) { 849 err = ocelot_port_set_pvid(ocelot, port, 850 ocelot_bridge_vlan_find(ocelot, vid)); 851 if (err) 852 return err; 853 } else if (ocelot_port->pvid_vlan && 854 ocelot_bridge_vlan_find(ocelot, vid) == ocelot_port->pvid_vlan) { 855 err = ocelot_port_set_pvid(ocelot, port, NULL); 856 if (err) 857 return err; 858 } 859 860 /* Untagged egress vlan clasification */ 861 ocelot_port_manage_port_tag(ocelot, port); 862 863 return 0; 864 } 865 EXPORT_SYMBOL(ocelot_vlan_add); 866 867 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 868 { 869 struct ocelot_port *ocelot_port = ocelot->ports[port]; 870 bool del_pvid = false; 871 int err; 872 873 if (!vid) 874 return 0; 875 876 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid) 877 del_pvid = true; 878 879 err = ocelot_vlan_member_del(ocelot, port, vid); 880 if (err) 881 return err; 882 883 /* Ingress */ 884 if (del_pvid) { 885 err = ocelot_port_set_pvid(ocelot, port, NULL); 886 if (err) 887 return err; 888 } 889 890 /* Egress */ 891 ocelot_port_manage_port_tag(ocelot, port); 892 893 return 0; 894 } 895 EXPORT_SYMBOL(ocelot_vlan_del); 896 897 static void ocelot_vlan_init(struct ocelot *ocelot) 898 { 899 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0); 900 u16 port, vid; 901 902 /* Clear VLAN table, by default all ports are members of all VLANs */ 903 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 904 ANA_TABLES_VLANACCESS); 905 ocelot_vlant_wait_for_completion(ocelot); 906 907 /* Configure the port VLAN memberships */ 908 for (vid = 1; vid < VLAN_N_VID; vid++) 909 ocelot_vlant_set_mask(ocelot, vid, 0); 910 911 /* We need VID 0 to get traffic on standalone ports. 912 * It is added automatically if the 8021q module is loaded, but we 913 * can't rely on that since it might not be. 914 */ 915 ocelot_vlant_set_mask(ocelot, OCELOT_STANDALONE_PVID, all_ports); 916 917 /* Set vlan ingress filter mask to all ports but the CPU port by 918 * default. 919 */ 920 ocelot_write(ocelot, all_ports, ANA_VLANMASK); 921 922 for (port = 0; port < ocelot->num_phys_ports; port++) { 923 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 924 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 925 } 926 } 927 928 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 929 { 930 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 931 } 932 933 static int ocelot_port_flush(struct ocelot *ocelot, int port) 934 { 935 unsigned int pause_ena; 936 int err, val; 937 938 /* Disable dequeuing from the egress queues */ 939 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 940 QSYS_PORT_MODE_DEQUEUE_DIS, 941 QSYS_PORT_MODE, port); 942 943 /* Disable flow control */ 944 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 945 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 946 947 /* Disable priority flow control */ 948 ocelot_fields_write(ocelot, port, 949 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 950 951 /* Wait at least the time it takes to receive a frame of maximum length 952 * at the port. 953 * Worst-case delays for 10 kilobyte jumbo frames are: 954 * 8 ms on a 10M port 955 * 800 μs on a 100M port 956 * 80 μs on a 1G port 957 * 32 μs on a 2.5G port 958 */ 959 usleep_range(8000, 10000); 960 961 /* Disable half duplex backpressure. */ 962 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 963 SYS_FRONT_PORT_MODE, port); 964 965 /* Flush the queues associated with the port. */ 966 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 967 REW_PORT_CFG, port); 968 969 /* Enable dequeuing from the egress queues. */ 970 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 971 port); 972 973 /* Wait until flushing is complete. */ 974 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 975 100, 2000000, false, ocelot, port); 976 977 /* Clear flushing again. */ 978 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 979 980 /* Re-enable flow control */ 981 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 982 983 return err; 984 } 985 986 int ocelot_port_configure_serdes(struct ocelot *ocelot, int port, 987 struct device_node *portnp) 988 { 989 struct ocelot_port *ocelot_port = ocelot->ports[port]; 990 struct device *dev = ocelot->dev; 991 int err; 992 993 /* Ensure clock signals and speed are set on all QSGMII links */ 994 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_QSGMII) 995 ocelot_port_rmwl(ocelot_port, 0, 996 DEV_CLOCK_CFG_MAC_TX_RST | 997 DEV_CLOCK_CFG_MAC_RX_RST, 998 DEV_CLOCK_CFG); 999 1000 if (ocelot_port->phy_mode != PHY_INTERFACE_MODE_INTERNAL) { 1001 struct phy *serdes = of_phy_get(portnp, NULL); 1002 1003 if (IS_ERR(serdes)) { 1004 err = PTR_ERR(serdes); 1005 dev_err_probe(dev, err, 1006 "missing SerDes phys for port %d\n", 1007 port); 1008 return err; 1009 } 1010 1011 err = phy_set_mode_ext(serdes, PHY_MODE_ETHERNET, 1012 ocelot_port->phy_mode); 1013 of_phy_put(serdes); 1014 if (err) { 1015 dev_err(dev, "Could not SerDes mode on port %d: %pe\n", 1016 port, ERR_PTR(err)); 1017 return err; 1018 } 1019 } 1020 1021 return 0; 1022 } 1023 EXPORT_SYMBOL_GPL(ocelot_port_configure_serdes); 1024 1025 void ocelot_phylink_mac_config(struct ocelot *ocelot, int port, 1026 unsigned int link_an_mode, 1027 const struct phylink_link_state *state) 1028 { 1029 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1030 1031 /* Disable HDX fast control */ 1032 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, 1033 DEV_PORT_MISC); 1034 1035 /* SGMII only for now */ 1036 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, 1037 PCS1G_MODE_CFG); 1038 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 1039 1040 /* Enable PCS */ 1041 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 1042 1043 /* No aneg on SGMII */ 1044 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); 1045 1046 /* No loopback */ 1047 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); 1048 } 1049 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_config); 1050 1051 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 1052 unsigned int link_an_mode, 1053 phy_interface_t interface, 1054 unsigned long quirks) 1055 { 1056 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1057 int err; 1058 1059 ocelot_port->speed = SPEED_UNKNOWN; 1060 1061 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 1062 DEV_MAC_ENA_CFG); 1063 1064 if (ocelot->ops->cut_through_fwd) { 1065 mutex_lock(&ocelot->fwd_domain_lock); 1066 ocelot->ops->cut_through_fwd(ocelot); 1067 mutex_unlock(&ocelot->fwd_domain_lock); 1068 } 1069 1070 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 1071 1072 err = ocelot_port_flush(ocelot, port); 1073 if (err) 1074 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 1075 port, err); 1076 1077 /* Put the port in reset. */ 1078 if (interface != PHY_INTERFACE_MODE_QSGMII || 1079 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 1080 ocelot_port_rmwl(ocelot_port, 1081 DEV_CLOCK_CFG_MAC_TX_RST | 1082 DEV_CLOCK_CFG_MAC_RX_RST, 1083 DEV_CLOCK_CFG_MAC_TX_RST | 1084 DEV_CLOCK_CFG_MAC_RX_RST, 1085 DEV_CLOCK_CFG); 1086 } 1087 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 1088 1089 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 1090 struct phy_device *phydev, 1091 unsigned int link_an_mode, 1092 phy_interface_t interface, 1093 int speed, int duplex, 1094 bool tx_pause, bool rx_pause, 1095 unsigned long quirks) 1096 { 1097 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1098 int mac_speed, mode = 0; 1099 u32 mac_fc_cfg; 1100 1101 ocelot_port->speed = speed; 1102 1103 /* The MAC might be integrated in systems where the MAC speed is fixed 1104 * and it's the PCS who is performing the rate adaptation, so we have 1105 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 1106 * (which is also its default value). 1107 */ 1108 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 1109 speed == SPEED_1000) { 1110 mac_speed = OCELOT_SPEED_1000; 1111 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 1112 } else if (speed == SPEED_2500) { 1113 mac_speed = OCELOT_SPEED_2500; 1114 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 1115 } else if (speed == SPEED_100) { 1116 mac_speed = OCELOT_SPEED_100; 1117 } else { 1118 mac_speed = OCELOT_SPEED_10; 1119 } 1120 1121 if (duplex == DUPLEX_FULL) 1122 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 1123 1124 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 1125 1126 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 1127 * PORT_RST bits in DEV_CLOCK_CFG. 1128 */ 1129 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 1130 DEV_CLOCK_CFG); 1131 1132 switch (speed) { 1133 case SPEED_10: 1134 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 1135 break; 1136 case SPEED_100: 1137 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 1138 break; 1139 case SPEED_1000: 1140 case SPEED_2500: 1141 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 1142 break; 1143 default: 1144 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 1145 port, speed); 1146 return; 1147 } 1148 1149 if (rx_pause) 1150 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 1151 1152 if (tx_pause) 1153 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 1154 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 1155 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 1156 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 1157 1158 /* Flow control. Link speed is only used here to evaluate the time 1159 * specification in incoming pause frames. 1160 */ 1161 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 1162 1163 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 1164 1165 /* Don't attempt to send PAUSE frames on the NPI port, it's broken */ 1166 if (port != ocelot->npi) 1167 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1168 tx_pause); 1169 1170 /* Undo the effects of ocelot_phylink_mac_link_down: 1171 * enable MAC module 1172 */ 1173 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 1174 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 1175 1176 /* If the port supports cut-through forwarding, update the masks before 1177 * enabling forwarding on the port. 1178 */ 1179 if (ocelot->ops->cut_through_fwd) { 1180 mutex_lock(&ocelot->fwd_domain_lock); 1181 /* Workaround for hardware bug - FP doesn't work 1182 * at all link speeds for all PHY modes. The function 1183 * below also calls ocelot->ops->cut_through_fwd(), 1184 * so we don't need to do it twice. 1185 */ 1186 ocelot_port_update_active_preemptible_tcs(ocelot, port); 1187 mutex_unlock(&ocelot->fwd_domain_lock); 1188 } 1189 1190 /* Core: Enable port for frame transfer */ 1191 ocelot_fields_write(ocelot, port, 1192 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 1193 } 1194 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 1195 1196 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 1197 u32 *rval) 1198 { 1199 u32 bytes_valid, val; 1200 1201 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1202 if (val == XTR_NOT_READY) { 1203 if (ifh) 1204 return -EIO; 1205 1206 do { 1207 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1208 } while (val == XTR_NOT_READY); 1209 } 1210 1211 switch (val) { 1212 case XTR_ABORT: 1213 return -EIO; 1214 case XTR_EOF_0: 1215 case XTR_EOF_1: 1216 case XTR_EOF_2: 1217 case XTR_EOF_3: 1218 case XTR_PRUNED: 1219 bytes_valid = XTR_VALID_BYTES(val); 1220 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1221 if (val == XTR_ESCAPE) 1222 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1223 else 1224 *rval = val; 1225 1226 return bytes_valid; 1227 case XTR_ESCAPE: 1228 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1229 1230 return 4; 1231 default: 1232 *rval = val; 1233 1234 return 4; 1235 } 1236 } 1237 1238 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 1239 { 1240 int i, err = 0; 1241 1242 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 1243 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 1244 if (err != 4) 1245 return (err < 0) ? err : -EIO; 1246 } 1247 1248 return 0; 1249 } 1250 1251 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb, 1252 u64 timestamp) 1253 { 1254 struct skb_shared_hwtstamps *shhwtstamps; 1255 u64 tod_in_ns, full_ts_in_ns; 1256 struct timespec64 ts; 1257 1258 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1259 1260 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 1261 if ((tod_in_ns & 0xffffffff) < timestamp) 1262 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 1263 timestamp; 1264 else 1265 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 1266 timestamp; 1267 1268 shhwtstamps = skb_hwtstamps(skb); 1269 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1270 shhwtstamps->hwtstamp = full_ts_in_ns; 1271 } 1272 EXPORT_SYMBOL(ocelot_ptp_rx_timestamp); 1273 1274 void ocelot_lock_inj_grp(struct ocelot *ocelot, int grp) 1275 __acquires(&ocelot->inj_lock) 1276 { 1277 spin_lock(&ocelot->inj_lock); 1278 } 1279 EXPORT_SYMBOL_GPL(ocelot_lock_inj_grp); 1280 1281 void ocelot_unlock_inj_grp(struct ocelot *ocelot, int grp) 1282 __releases(&ocelot->inj_lock) 1283 { 1284 spin_unlock(&ocelot->inj_lock); 1285 } 1286 EXPORT_SYMBOL_GPL(ocelot_unlock_inj_grp); 1287 1288 void ocelot_lock_xtr_grp(struct ocelot *ocelot, int grp) 1289 __acquires(&ocelot->inj_lock) 1290 { 1291 spin_lock(&ocelot->inj_lock); 1292 } 1293 EXPORT_SYMBOL_GPL(ocelot_lock_xtr_grp); 1294 1295 void ocelot_unlock_xtr_grp(struct ocelot *ocelot, int grp) 1296 __releases(&ocelot->inj_lock) 1297 { 1298 spin_unlock(&ocelot->inj_lock); 1299 } 1300 EXPORT_SYMBOL_GPL(ocelot_unlock_xtr_grp); 1301 1302 void ocelot_lock_xtr_grp_bh(struct ocelot *ocelot, int grp) 1303 __acquires(&ocelot->xtr_lock) 1304 { 1305 spin_lock_bh(&ocelot->xtr_lock); 1306 } 1307 EXPORT_SYMBOL_GPL(ocelot_lock_xtr_grp_bh); 1308 1309 void ocelot_unlock_xtr_grp_bh(struct ocelot *ocelot, int grp) 1310 __releases(&ocelot->xtr_lock) 1311 { 1312 spin_unlock_bh(&ocelot->xtr_lock); 1313 } 1314 EXPORT_SYMBOL_GPL(ocelot_unlock_xtr_grp_bh); 1315 1316 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 1317 { 1318 u64 timestamp, src_port, len; 1319 u32 xfh[OCELOT_TAG_LEN / 4]; 1320 struct net_device *dev; 1321 struct sk_buff *skb; 1322 int sz, buf_len; 1323 u32 val, *buf; 1324 int err; 1325 1326 lockdep_assert_held(&ocelot->xtr_lock); 1327 1328 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 1329 if (err) 1330 return err; 1331 1332 ocelot_xfh_get_src_port(xfh, &src_port); 1333 ocelot_xfh_get_len(xfh, &len); 1334 ocelot_xfh_get_rew_val(xfh, ×tamp); 1335 1336 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 1337 return -EINVAL; 1338 1339 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 1340 if (!dev) 1341 return -EINVAL; 1342 1343 skb = netdev_alloc_skb(dev, len); 1344 if (unlikely(!skb)) { 1345 netdev_err(dev, "Unable to allocate sk_buff\n"); 1346 return -ENOMEM; 1347 } 1348 1349 buf_len = len - ETH_FCS_LEN; 1350 buf = (u32 *)skb_put(skb, buf_len); 1351 1352 len = 0; 1353 do { 1354 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1355 if (sz < 0) { 1356 err = sz; 1357 goto out_free_skb; 1358 } 1359 *buf++ = val; 1360 len += sz; 1361 } while (len < buf_len); 1362 1363 /* Read the FCS */ 1364 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1365 if (sz < 0) { 1366 err = sz; 1367 goto out_free_skb; 1368 } 1369 1370 /* Update the statistics if part of the FCS was read before */ 1371 len -= ETH_FCS_LEN - sz; 1372 1373 if (unlikely(dev->features & NETIF_F_RXFCS)) { 1374 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 1375 *buf = val; 1376 } 1377 1378 if (ocelot->ptp) 1379 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp); 1380 1381 /* Everything we see on an interface that is in the HW bridge 1382 * has already been forwarded. 1383 */ 1384 if (ocelot->ports[src_port]->bridge) 1385 skb->offload_fwd_mark = 1; 1386 1387 skb->protocol = eth_type_trans(skb, dev); 1388 1389 *nskb = skb; 1390 1391 return 0; 1392 1393 out_free_skb: 1394 kfree_skb(skb); 1395 return err; 1396 } 1397 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 1398 1399 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 1400 { 1401 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 1402 1403 lockdep_assert_held(&ocelot->inj_lock); 1404 1405 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 1406 return false; 1407 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 1408 return false; 1409 1410 return true; 1411 } 1412 EXPORT_SYMBOL(ocelot_can_inject); 1413 1414 /** 1415 * ocelot_ifh_set_basic - Set basic information in Injection Frame Header 1416 * @ifh: Pointer to Injection Frame Header memory 1417 * @ocelot: Switch private data structure 1418 * @port: Egress port number 1419 * @rew_op: Egress rewriter operation for PTP 1420 * @skb: Pointer to socket buffer (packet) 1421 * 1422 * Populate the Injection Frame Header with basic information for this skb: the 1423 * analyzer bypass bit, destination port, VLAN info, egress rewriter info. 1424 */ 1425 void ocelot_ifh_set_basic(void *ifh, struct ocelot *ocelot, int port, 1426 u32 rew_op, struct sk_buff *skb) 1427 { 1428 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1429 struct net_device *dev = skb->dev; 1430 u64 vlan_tci, tag_type; 1431 int qos_class; 1432 1433 ocelot_xmit_get_vlan_info(skb, ocelot_port->bridge, &vlan_tci, 1434 &tag_type); 1435 1436 qos_class = netdev_get_num_tc(dev) ? 1437 netdev_get_prio_tc_map(dev, skb->priority) : skb->priority; 1438 1439 memset(ifh, 0, OCELOT_TAG_LEN); 1440 ocelot_ifh_set_bypass(ifh, 1); 1441 ocelot_ifh_set_src(ifh, ocelot->num_phys_ports); 1442 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 1443 ocelot_ifh_set_qos_class(ifh, qos_class); 1444 ocelot_ifh_set_tag_type(ifh, tag_type); 1445 ocelot_ifh_set_vlan_tci(ifh, vlan_tci); 1446 if (rew_op) 1447 ocelot_ifh_set_rew_op(ifh, rew_op); 1448 } 1449 EXPORT_SYMBOL(ocelot_ifh_set_basic); 1450 1451 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 1452 u32 rew_op, struct sk_buff *skb) 1453 { 1454 u32 ifh[OCELOT_TAG_LEN / 4]; 1455 unsigned int i, count, last; 1456 1457 lockdep_assert_held(&ocelot->inj_lock); 1458 1459 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1460 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 1461 1462 ocelot_ifh_set_basic(ifh, ocelot, port, rew_op, skb); 1463 1464 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 1465 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 1466 1467 count = DIV_ROUND_UP(skb->len, 4); 1468 last = skb->len % 4; 1469 for (i = 0; i < count; i++) 1470 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 1471 1472 /* Add padding */ 1473 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 1474 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1475 i++; 1476 } 1477 1478 /* Indicate EOF and valid bytes in last word */ 1479 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1480 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 1481 QS_INJ_CTRL_EOF, 1482 QS_INJ_CTRL, grp); 1483 1484 /* Add dummy CRC */ 1485 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1486 skb_tx_timestamp(skb); 1487 1488 skb->dev->stats.tx_packets++; 1489 skb->dev->stats.tx_bytes += skb->len; 1490 } 1491 EXPORT_SYMBOL(ocelot_port_inject_frame); 1492 1493 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 1494 { 1495 lockdep_assert_held(&ocelot->xtr_lock); 1496 1497 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 1498 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1499 } 1500 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 1501 1502 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr, 1503 u16 vid, const struct net_device *bridge) 1504 { 1505 if (!vid) 1506 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1507 1508 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED); 1509 } 1510 EXPORT_SYMBOL(ocelot_fdb_add); 1511 1512 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr, 1513 u16 vid, const struct net_device *bridge) 1514 { 1515 if (!vid) 1516 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1517 1518 return ocelot_mact_forget(ocelot, addr, vid); 1519 } 1520 EXPORT_SYMBOL(ocelot_fdb_del); 1521 1522 /* Caller must hold &ocelot->mact_lock */ 1523 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1524 struct ocelot_mact_entry *entry) 1525 { 1526 u32 val, dst, macl, mach; 1527 char mac[ETH_ALEN]; 1528 1529 /* Set row and column to read from */ 1530 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1531 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1532 1533 /* Issue a read command */ 1534 ocelot_write(ocelot, 1535 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1536 ANA_TABLES_MACACCESS); 1537 1538 if (ocelot_mact_wait_for_completion(ocelot)) 1539 return -ETIMEDOUT; 1540 1541 /* Read the entry flags */ 1542 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1543 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1544 return -EINVAL; 1545 1546 /* If the entry read has another port configured as its destination, 1547 * do not report it. 1548 */ 1549 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1550 if (dst != port) 1551 return -EINVAL; 1552 1553 /* Get the entry's MAC address and VLAN id */ 1554 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1555 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1556 1557 mac[0] = (mach >> 8) & 0xff; 1558 mac[1] = (mach >> 0) & 0xff; 1559 mac[2] = (macl >> 24) & 0xff; 1560 mac[3] = (macl >> 16) & 0xff; 1561 mac[4] = (macl >> 8) & 0xff; 1562 mac[5] = (macl >> 0) & 0xff; 1563 1564 entry->vid = (mach >> 16) & 0xfff; 1565 ether_addr_copy(entry->mac, mac); 1566 1567 return 0; 1568 } 1569 1570 int ocelot_mact_flush(struct ocelot *ocelot, int port) 1571 { 1572 int err; 1573 1574 mutex_lock(&ocelot->mact_lock); 1575 1576 /* Program ageing filter for a single port */ 1577 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port), 1578 ANA_ANAGEFIL); 1579 1580 /* Flushing dynamic FDB entries requires two successive age scans */ 1581 ocelot_write(ocelot, 1582 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1583 ANA_TABLES_MACACCESS); 1584 1585 err = ocelot_mact_wait_for_completion(ocelot); 1586 if (err) { 1587 mutex_unlock(&ocelot->mact_lock); 1588 return err; 1589 } 1590 1591 /* And second... */ 1592 ocelot_write(ocelot, 1593 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1594 ANA_TABLES_MACACCESS); 1595 1596 err = ocelot_mact_wait_for_completion(ocelot); 1597 1598 /* Restore ageing filter */ 1599 ocelot_write(ocelot, 0, ANA_ANAGEFIL); 1600 1601 mutex_unlock(&ocelot->mact_lock); 1602 1603 return err; 1604 } 1605 EXPORT_SYMBOL_GPL(ocelot_mact_flush); 1606 1607 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1608 dsa_fdb_dump_cb_t *cb, void *data) 1609 { 1610 int err = 0; 1611 int i, j; 1612 1613 /* We could take the lock just around ocelot_mact_read, but doing so 1614 * thousands of times in a row seems rather pointless and inefficient. 1615 */ 1616 mutex_lock(&ocelot->mact_lock); 1617 1618 /* Loop through all the mac tables entries. */ 1619 for (i = 0; i < ocelot->num_mact_rows; i++) { 1620 for (j = 0; j < 4; j++) { 1621 struct ocelot_mact_entry entry; 1622 bool is_static; 1623 1624 err = ocelot_mact_read(ocelot, port, i, j, &entry); 1625 /* If the entry is invalid (wrong port, invalid...), 1626 * skip it. 1627 */ 1628 if (err == -EINVAL) 1629 continue; 1630 else if (err) 1631 break; 1632 1633 is_static = (entry.type == ENTRYTYPE_LOCKED); 1634 1635 /* Hide the reserved VLANs used for 1636 * VLAN-unaware bridging. 1637 */ 1638 if (entry.vid > OCELOT_RSV_VLAN_RANGE_START) 1639 entry.vid = 0; 1640 1641 err = cb(entry.mac, entry.vid, is_static, data); 1642 if (err) 1643 break; 1644 } 1645 } 1646 1647 mutex_unlock(&ocelot->mact_lock); 1648 1649 return err; 1650 } 1651 EXPORT_SYMBOL(ocelot_fdb_dump); 1652 1653 int ocelot_trap_add(struct ocelot *ocelot, int port, 1654 unsigned long cookie, bool take_ts, 1655 void (*populate)(struct ocelot_vcap_filter *f)) 1656 { 1657 struct ocelot_vcap_block *block_vcap_is2; 1658 struct ocelot_vcap_filter *trap; 1659 bool new = false; 1660 int err; 1661 1662 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1663 1664 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1665 false); 1666 if (!trap) { 1667 trap = kzalloc(sizeof(*trap), GFP_KERNEL); 1668 if (!trap) 1669 return -ENOMEM; 1670 1671 populate(trap); 1672 trap->prio = 1; 1673 trap->id.cookie = cookie; 1674 trap->id.tc_offload = false; 1675 trap->block_id = VCAP_IS2; 1676 trap->type = OCELOT_VCAP_FILTER_OFFLOAD; 1677 trap->lookup = 0; 1678 trap->action.cpu_copy_ena = true; 1679 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; 1680 trap->action.port_mask = 0; 1681 trap->take_ts = take_ts; 1682 trap->is_trap = true; 1683 new = true; 1684 } 1685 1686 trap->ingress_port_mask |= BIT(port); 1687 1688 if (new) 1689 err = ocelot_vcap_filter_add(ocelot, trap, NULL); 1690 else 1691 err = ocelot_vcap_filter_replace(ocelot, trap); 1692 if (err) { 1693 trap->ingress_port_mask &= ~BIT(port); 1694 if (!trap->ingress_port_mask) 1695 kfree(trap); 1696 return err; 1697 } 1698 1699 return 0; 1700 } 1701 1702 int ocelot_trap_del(struct ocelot *ocelot, int port, unsigned long cookie) 1703 { 1704 struct ocelot_vcap_block *block_vcap_is2; 1705 struct ocelot_vcap_filter *trap; 1706 1707 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1708 1709 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1710 false); 1711 if (!trap) 1712 return 0; 1713 1714 trap->ingress_port_mask &= ~BIT(port); 1715 if (!trap->ingress_port_mask) 1716 return ocelot_vcap_filter_del(ocelot, trap); 1717 1718 return ocelot_vcap_filter_replace(ocelot, trap); 1719 } 1720 1721 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond) 1722 { 1723 u32 mask = 0; 1724 int port; 1725 1726 lockdep_assert_held(&ocelot->fwd_domain_lock); 1727 1728 for (port = 0; port < ocelot->num_phys_ports; port++) { 1729 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1730 1731 if (!ocelot_port) 1732 continue; 1733 1734 if (ocelot_port->bond == bond) 1735 mask |= BIT(port); 1736 } 1737 1738 return mask; 1739 } 1740 1741 /* The logical port number of a LAG is equal to the lowest numbered physical 1742 * port ID present in that LAG. It may change if that port ever leaves the LAG. 1743 */ 1744 int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond) 1745 { 1746 int bond_mask = ocelot_get_bond_mask(ocelot, bond); 1747 1748 if (!bond_mask) 1749 return -ENOENT; 1750 1751 return __ffs(bond_mask); 1752 } 1753 EXPORT_SYMBOL_GPL(ocelot_bond_get_id); 1754 1755 /* Returns the mask of user ports assigned to this DSA tag_8021q CPU port. 1756 * Note that when CPU ports are in a LAG, the user ports are assigned to the 1757 * 'primary' CPU port, the one whose physical port number gives the logical 1758 * port number of the LAG. 1759 * 1760 * We leave PGID_SRC poorly configured for the 'secondary' CPU port in the LAG 1761 * (to which no user port is assigned), but it appears that forwarding from 1762 * this secondary CPU port looks at the PGID_SRC associated with the logical 1763 * port ID that it's assigned to, which *is* configured properly. 1764 */ 1765 static u32 ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot *ocelot, 1766 struct ocelot_port *cpu) 1767 { 1768 u32 mask = 0; 1769 int port; 1770 1771 for (port = 0; port < ocelot->num_phys_ports; port++) { 1772 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1773 1774 if (!ocelot_port) 1775 continue; 1776 1777 if (ocelot_port->dsa_8021q_cpu == cpu) 1778 mask |= BIT(port); 1779 } 1780 1781 if (cpu->bond) 1782 mask &= ~ocelot_get_bond_mask(ocelot, cpu->bond); 1783 1784 return mask; 1785 } 1786 1787 /* Returns the DSA tag_8021q CPU port that the given port is assigned to, 1788 * or the bit mask of CPU ports if said CPU port is in a LAG. 1789 */ 1790 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port) 1791 { 1792 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1793 struct ocelot_port *cpu_port = ocelot_port->dsa_8021q_cpu; 1794 1795 if (!cpu_port) 1796 return 0; 1797 1798 if (cpu_port->bond) 1799 return ocelot_get_bond_mask(ocelot, cpu_port->bond); 1800 1801 return BIT(cpu_port->index); 1802 } 1803 EXPORT_SYMBOL_GPL(ocelot_port_assigned_dsa_8021q_cpu_mask); 1804 1805 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port) 1806 { 1807 struct ocelot_port *ocelot_port = ocelot->ports[src_port]; 1808 const struct net_device *bridge; 1809 u32 mask = 0; 1810 int port; 1811 1812 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING) 1813 return 0; 1814 1815 bridge = ocelot_port->bridge; 1816 if (!bridge) 1817 return 0; 1818 1819 for (port = 0; port < ocelot->num_phys_ports; port++) { 1820 ocelot_port = ocelot->ports[port]; 1821 1822 if (!ocelot_port) 1823 continue; 1824 1825 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1826 ocelot_port->bridge == bridge) 1827 mask |= BIT(port); 1828 } 1829 1830 return mask; 1831 } 1832 EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask); 1833 1834 static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining) 1835 { 1836 int port; 1837 1838 lockdep_assert_held(&ocelot->fwd_domain_lock); 1839 1840 /* If cut-through forwarding is supported, update the masks before a 1841 * port joins the forwarding domain, to avoid potential underruns if it 1842 * has the highest speed from the new domain. 1843 */ 1844 if (joining && ocelot->ops->cut_through_fwd) 1845 ocelot->ops->cut_through_fwd(ocelot); 1846 1847 /* Apply FWD mask. The loop is needed to add/remove the current port as 1848 * a source for the other ports. 1849 */ 1850 for (port = 0; port < ocelot->num_phys_ports; port++) { 1851 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1852 unsigned long mask; 1853 1854 if (!ocelot_port) { 1855 /* Unused ports can't send anywhere */ 1856 mask = 0; 1857 } else if (ocelot_port->is_dsa_8021q_cpu) { 1858 /* The DSA tag_8021q CPU ports need to be able to 1859 * forward packets to all ports assigned to them. 1860 */ 1861 mask = ocelot_dsa_8021q_cpu_assigned_ports(ocelot, 1862 ocelot_port); 1863 } else if (ocelot_port->bridge) { 1864 struct net_device *bond = ocelot_port->bond; 1865 1866 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 1867 mask &= ~BIT(port); 1868 1869 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 1870 port); 1871 1872 if (bond) 1873 mask &= ~ocelot_get_bond_mask(ocelot, bond); 1874 } else { 1875 /* Standalone ports forward only to DSA tag_8021q CPU 1876 * ports (if those exist), or to the hardware CPU port 1877 * module otherwise. 1878 */ 1879 mask = ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 1880 port); 1881 } 1882 1883 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1884 } 1885 1886 /* If cut-through forwarding is supported and a port is leaving, there 1887 * is a chance that cut-through was disabled on the other ports due to 1888 * the port which is leaving (it has a higher link speed). We need to 1889 * update the cut-through masks of the remaining ports no earlier than 1890 * after the port has left, to prevent underruns from happening between 1891 * the cut-through update and the forwarding domain update. 1892 */ 1893 if (!joining && ocelot->ops->cut_through_fwd) 1894 ocelot->ops->cut_through_fwd(ocelot); 1895 } 1896 1897 /* Update PGID_CPU which is the destination port mask used for whitelisting 1898 * unicast addresses filtered towards the host. In the normal and NPI modes, 1899 * this points to the analyzer entry for the CPU port module, while in DSA 1900 * tag_8021q mode, it is a bit mask of all active CPU ports. 1901 * PGID_SRC will take care of forwarding a packet from one user port to 1902 * no more than a single CPU port. 1903 */ 1904 static void ocelot_update_pgid_cpu(struct ocelot *ocelot) 1905 { 1906 int pgid_cpu = 0; 1907 int port; 1908 1909 for (port = 0; port < ocelot->num_phys_ports; port++) { 1910 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1911 1912 if (!ocelot_port || !ocelot_port->is_dsa_8021q_cpu) 1913 continue; 1914 1915 pgid_cpu |= BIT(port); 1916 } 1917 1918 if (!pgid_cpu) 1919 pgid_cpu = BIT(ocelot->num_phys_ports); 1920 1921 ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU); 1922 } 1923 1924 void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu) 1925 { 1926 struct ocelot_port *cpu_port = ocelot->ports[cpu]; 1927 u16 vid; 1928 1929 mutex_lock(&ocelot->fwd_domain_lock); 1930 1931 cpu_port->is_dsa_8021q_cpu = true; 1932 1933 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) 1934 ocelot_vlan_member_add(ocelot, cpu, vid, true); 1935 1936 ocelot_update_pgid_cpu(ocelot); 1937 1938 mutex_unlock(&ocelot->fwd_domain_lock); 1939 } 1940 EXPORT_SYMBOL_GPL(ocelot_port_setup_dsa_8021q_cpu); 1941 1942 void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu) 1943 { 1944 struct ocelot_port *cpu_port = ocelot->ports[cpu]; 1945 u16 vid; 1946 1947 mutex_lock(&ocelot->fwd_domain_lock); 1948 1949 cpu_port->is_dsa_8021q_cpu = false; 1950 1951 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) 1952 ocelot_vlan_member_del(ocelot, cpu_port->index, vid); 1953 1954 ocelot_update_pgid_cpu(ocelot); 1955 1956 mutex_unlock(&ocelot->fwd_domain_lock); 1957 } 1958 EXPORT_SYMBOL_GPL(ocelot_port_teardown_dsa_8021q_cpu); 1959 1960 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, 1961 int cpu) 1962 { 1963 struct ocelot_port *cpu_port = ocelot->ports[cpu]; 1964 1965 mutex_lock(&ocelot->fwd_domain_lock); 1966 1967 ocelot->ports[port]->dsa_8021q_cpu = cpu_port; 1968 ocelot_apply_bridge_fwd_mask(ocelot, true); 1969 1970 mutex_unlock(&ocelot->fwd_domain_lock); 1971 } 1972 EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu); 1973 1974 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port) 1975 { 1976 mutex_lock(&ocelot->fwd_domain_lock); 1977 1978 ocelot->ports[port]->dsa_8021q_cpu = NULL; 1979 ocelot_apply_bridge_fwd_mask(ocelot, true); 1980 1981 mutex_unlock(&ocelot->fwd_domain_lock); 1982 } 1983 EXPORT_SYMBOL_GPL(ocelot_port_unassign_dsa_8021q_cpu); 1984 1985 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1986 { 1987 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1988 u32 learn_ena = 0; 1989 1990 mutex_lock(&ocelot->fwd_domain_lock); 1991 1992 ocelot_port->stp_state = state; 1993 1994 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1995 ocelot_port->learn_ena) 1996 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1997 1998 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1999 ANA_PORT_PORT_CFG, port); 2000 2001 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING); 2002 2003 mutex_unlock(&ocelot->fwd_domain_lock); 2004 } 2005 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 2006 2007 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 2008 { 2009 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 2010 2011 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 2012 * which is clearly not what our intention is. So avoid that. 2013 */ 2014 if (!age_period) 2015 age_period = 1; 2016 2017 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 2018 } 2019 EXPORT_SYMBOL(ocelot_set_ageing_time); 2020 2021 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 2022 const unsigned char *addr, 2023 u16 vid) 2024 { 2025 struct ocelot_multicast *mc; 2026 2027 list_for_each_entry(mc, &ocelot->multicast, list) { 2028 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 2029 return mc; 2030 } 2031 2032 return NULL; 2033 } 2034 2035 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 2036 { 2037 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 2038 return ENTRYTYPE_MACv4; 2039 if (addr[0] == 0x33 && addr[1] == 0x33) 2040 return ENTRYTYPE_MACv6; 2041 return ENTRYTYPE_LOCKED; 2042 } 2043 2044 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 2045 unsigned long ports) 2046 { 2047 struct ocelot_pgid *pgid; 2048 2049 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 2050 if (!pgid) 2051 return ERR_PTR(-ENOMEM); 2052 2053 pgid->ports = ports; 2054 pgid->index = index; 2055 refcount_set(&pgid->refcount, 1); 2056 list_add_tail(&pgid->list, &ocelot->pgids); 2057 2058 return pgid; 2059 } 2060 2061 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 2062 { 2063 if (!refcount_dec_and_test(&pgid->refcount)) 2064 return; 2065 2066 list_del(&pgid->list); 2067 kfree(pgid); 2068 } 2069 2070 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 2071 const struct ocelot_multicast *mc) 2072 { 2073 struct ocelot_pgid *pgid; 2074 int index; 2075 2076 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 2077 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 2078 * destination mask table (PGID), the destination set is programmed as 2079 * part of the entry MAC address.", and the DEST_IDX is set to 0. 2080 */ 2081 if (mc->entry_type == ENTRYTYPE_MACv4 || 2082 mc->entry_type == ENTRYTYPE_MACv6) 2083 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 2084 2085 list_for_each_entry(pgid, &ocelot->pgids, list) { 2086 /* When searching for a nonreserved multicast PGID, ignore the 2087 * dummy PGID of zero that we have for MACv4/MACv6 entries 2088 */ 2089 if (pgid->index && pgid->ports == mc->ports) { 2090 refcount_inc(&pgid->refcount); 2091 return pgid; 2092 } 2093 } 2094 2095 /* Search for a free index in the nonreserved multicast PGID area */ 2096 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 2097 bool used = false; 2098 2099 list_for_each_entry(pgid, &ocelot->pgids, list) { 2100 if (pgid->index == index) { 2101 used = true; 2102 break; 2103 } 2104 } 2105 2106 if (!used) 2107 return ocelot_pgid_alloc(ocelot, index, mc->ports); 2108 } 2109 2110 return ERR_PTR(-ENOSPC); 2111 } 2112 2113 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 2114 struct ocelot_multicast *mc) 2115 { 2116 ether_addr_copy(addr, mc->addr); 2117 2118 if (mc->entry_type == ENTRYTYPE_MACv4) { 2119 addr[0] = 0; 2120 addr[1] = mc->ports >> 8; 2121 addr[2] = mc->ports & 0xff; 2122 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 2123 addr[0] = mc->ports >> 8; 2124 addr[1] = mc->ports & 0xff; 2125 } 2126 } 2127 2128 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 2129 const struct switchdev_obj_port_mdb *mdb, 2130 const struct net_device *bridge) 2131 { 2132 unsigned char addr[ETH_ALEN]; 2133 struct ocelot_multicast *mc; 2134 struct ocelot_pgid *pgid; 2135 u16 vid = mdb->vid; 2136 2137 if (!vid) 2138 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2139 2140 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 2141 if (!mc) { 2142 /* New entry */ 2143 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 2144 if (!mc) 2145 return -ENOMEM; 2146 2147 mc->entry_type = ocelot_classify_mdb(mdb->addr); 2148 ether_addr_copy(mc->addr, mdb->addr); 2149 mc->vid = vid; 2150 2151 list_add_tail(&mc->list, &ocelot->multicast); 2152 } else { 2153 /* Existing entry. Clean up the current port mask from 2154 * hardware now, because we'll be modifying it. 2155 */ 2156 ocelot_pgid_free(ocelot, mc->pgid); 2157 ocelot_encode_ports_to_mdb(addr, mc); 2158 ocelot_mact_forget(ocelot, addr, vid); 2159 } 2160 2161 mc->ports |= BIT(port); 2162 2163 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2164 if (IS_ERR(pgid)) { 2165 dev_err(ocelot->dev, 2166 "Cannot allocate PGID for mdb %pM vid %d\n", 2167 mc->addr, mc->vid); 2168 devm_kfree(ocelot->dev, mc); 2169 return PTR_ERR(pgid); 2170 } 2171 mc->pgid = pgid; 2172 2173 ocelot_encode_ports_to_mdb(addr, mc); 2174 2175 if (mc->entry_type != ENTRYTYPE_MACv4 && 2176 mc->entry_type != ENTRYTYPE_MACv6) 2177 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2178 pgid->index); 2179 2180 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2181 mc->entry_type); 2182 } 2183 EXPORT_SYMBOL(ocelot_port_mdb_add); 2184 2185 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 2186 const struct switchdev_obj_port_mdb *mdb, 2187 const struct net_device *bridge) 2188 { 2189 unsigned char addr[ETH_ALEN]; 2190 struct ocelot_multicast *mc; 2191 struct ocelot_pgid *pgid; 2192 u16 vid = mdb->vid; 2193 2194 if (!vid) 2195 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2196 2197 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 2198 if (!mc) 2199 return -ENOENT; 2200 2201 ocelot_encode_ports_to_mdb(addr, mc); 2202 ocelot_mact_forget(ocelot, addr, vid); 2203 2204 ocelot_pgid_free(ocelot, mc->pgid); 2205 mc->ports &= ~BIT(port); 2206 if (!mc->ports) { 2207 list_del(&mc->list); 2208 devm_kfree(ocelot->dev, mc); 2209 return 0; 2210 } 2211 2212 /* We have a PGID with fewer ports now */ 2213 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2214 if (IS_ERR(pgid)) 2215 return PTR_ERR(pgid); 2216 mc->pgid = pgid; 2217 2218 ocelot_encode_ports_to_mdb(addr, mc); 2219 2220 if (mc->entry_type != ENTRYTYPE_MACv4 && 2221 mc->entry_type != ENTRYTYPE_MACv6) 2222 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2223 pgid->index); 2224 2225 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2226 mc->entry_type); 2227 } 2228 EXPORT_SYMBOL(ocelot_port_mdb_del); 2229 2230 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 2231 struct net_device *bridge, int bridge_num, 2232 struct netlink_ext_ack *extack) 2233 { 2234 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2235 int err; 2236 2237 err = ocelot_single_vlan_aware_bridge(ocelot, extack); 2238 if (err) 2239 return err; 2240 2241 mutex_lock(&ocelot->fwd_domain_lock); 2242 2243 ocelot_port->bridge = bridge; 2244 ocelot_port->bridge_num = bridge_num; 2245 2246 ocelot_apply_bridge_fwd_mask(ocelot, true); 2247 2248 mutex_unlock(&ocelot->fwd_domain_lock); 2249 2250 if (br_vlan_enabled(bridge)) 2251 return 0; 2252 2253 return ocelot_add_vlan_unaware_pvid(ocelot, port, bridge); 2254 } 2255 EXPORT_SYMBOL(ocelot_port_bridge_join); 2256 2257 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 2258 struct net_device *bridge) 2259 { 2260 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2261 2262 mutex_lock(&ocelot->fwd_domain_lock); 2263 2264 if (!br_vlan_enabled(bridge)) 2265 ocelot_del_vlan_unaware_pvid(ocelot, port, bridge); 2266 2267 ocelot_port->bridge = NULL; 2268 ocelot_port->bridge_num = -1; 2269 2270 ocelot_port_set_pvid(ocelot, port, NULL); 2271 ocelot_port_manage_port_tag(ocelot, port); 2272 ocelot_apply_bridge_fwd_mask(ocelot, false); 2273 2274 mutex_unlock(&ocelot->fwd_domain_lock); 2275 } 2276 EXPORT_SYMBOL(ocelot_port_bridge_leave); 2277 2278 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 2279 { 2280 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 2281 int i, port, lag; 2282 2283 /* Reset destination and aggregation PGIDS */ 2284 for_each_unicast_dest_pgid(ocelot, port) 2285 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2286 2287 for_each_aggr_pgid(ocelot, i) 2288 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 2289 ANA_PGID_PGID, i); 2290 2291 /* The visited ports bitmask holds the list of ports offloading any 2292 * bonding interface. Initially we mark all these ports as unvisited, 2293 * then every time we visit a port in this bitmask, we know that it is 2294 * the lowest numbered port, i.e. the one whose logical ID == physical 2295 * port ID == LAG ID. So we mark as visited all further ports in the 2296 * bitmask that are offloading the same bonding interface. This way, 2297 * we set up the aggregation PGIDs only once per bonding interface. 2298 */ 2299 for (port = 0; port < ocelot->num_phys_ports; port++) { 2300 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2301 2302 if (!ocelot_port || !ocelot_port->bond) 2303 continue; 2304 2305 visited &= ~BIT(port); 2306 } 2307 2308 /* Now, set PGIDs for each active LAG */ 2309 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 2310 struct net_device *bond = ocelot->ports[lag]->bond; 2311 int num_active_ports = 0; 2312 unsigned long bond_mask; 2313 u8 aggr_idx[16]; 2314 2315 if (!bond || (visited & BIT(lag))) 2316 continue; 2317 2318 bond_mask = ocelot_get_bond_mask(ocelot, bond); 2319 2320 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 2321 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2322 2323 // Destination mask 2324 ocelot_write_rix(ocelot, bond_mask, 2325 ANA_PGID_PGID, port); 2326 2327 if (ocelot_port->lag_tx_active) 2328 aggr_idx[num_active_ports++] = port; 2329 } 2330 2331 for_each_aggr_pgid(ocelot, i) { 2332 u32 ac; 2333 2334 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 2335 ac &= ~bond_mask; 2336 /* Don't do division by zero if there was no active 2337 * port. Just make all aggregation codes zero. 2338 */ 2339 if (num_active_ports) 2340 ac |= BIT(aggr_idx[i % num_active_ports]); 2341 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 2342 } 2343 2344 /* Mark all ports in the same LAG as visited to avoid applying 2345 * the same config again. 2346 */ 2347 for (port = lag; port < ocelot->num_phys_ports; port++) { 2348 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2349 2350 if (!ocelot_port) 2351 continue; 2352 2353 if (ocelot_port->bond == bond) 2354 visited |= BIT(port); 2355 } 2356 } 2357 } 2358 2359 /* When offloading a bonding interface, the switch ports configured under the 2360 * same bond must have the same logical port ID, equal to the physical port ID 2361 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 2362 * bridged mode, each port has a logical port ID equal to its physical port ID. 2363 */ 2364 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 2365 { 2366 int port; 2367 2368 for (port = 0; port < ocelot->num_phys_ports; port++) { 2369 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2370 struct net_device *bond; 2371 2372 if (!ocelot_port) 2373 continue; 2374 2375 bond = ocelot_port->bond; 2376 if (bond) { 2377 int lag = ocelot_bond_get_id(ocelot, bond); 2378 2379 ocelot_rmw_gix(ocelot, 2380 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 2381 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2382 ANA_PORT_PORT_CFG, port); 2383 } else { 2384 ocelot_rmw_gix(ocelot, 2385 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2386 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2387 ANA_PORT_PORT_CFG, port); 2388 } 2389 } 2390 } 2391 2392 static int ocelot_migrate_mc(struct ocelot *ocelot, struct ocelot_multicast *mc, 2393 unsigned long from_mask, unsigned long to_mask) 2394 { 2395 unsigned char addr[ETH_ALEN]; 2396 struct ocelot_pgid *pgid; 2397 u16 vid = mc->vid; 2398 2399 dev_dbg(ocelot->dev, 2400 "Migrating multicast %pM vid %d from port mask 0x%lx to 0x%lx\n", 2401 mc->addr, mc->vid, from_mask, to_mask); 2402 2403 /* First clean up the current port mask from hardware, because 2404 * we'll be modifying it. 2405 */ 2406 ocelot_pgid_free(ocelot, mc->pgid); 2407 ocelot_encode_ports_to_mdb(addr, mc); 2408 ocelot_mact_forget(ocelot, addr, vid); 2409 2410 mc->ports &= ~from_mask; 2411 mc->ports |= to_mask; 2412 2413 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2414 if (IS_ERR(pgid)) { 2415 dev_err(ocelot->dev, 2416 "Cannot allocate PGID for mdb %pM vid %d\n", 2417 mc->addr, mc->vid); 2418 devm_kfree(ocelot->dev, mc); 2419 return PTR_ERR(pgid); 2420 } 2421 mc->pgid = pgid; 2422 2423 ocelot_encode_ports_to_mdb(addr, mc); 2424 2425 if (mc->entry_type != ENTRYTYPE_MACv4 && 2426 mc->entry_type != ENTRYTYPE_MACv6) 2427 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2428 pgid->index); 2429 2430 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2431 mc->entry_type); 2432 } 2433 2434 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask, 2435 unsigned long to_mask) 2436 { 2437 struct ocelot_multicast *mc; 2438 int err; 2439 2440 list_for_each_entry(mc, &ocelot->multicast, list) { 2441 if (!(mc->ports & from_mask)) 2442 continue; 2443 2444 err = ocelot_migrate_mc(ocelot, mc, from_mask, to_mask); 2445 if (err) 2446 return err; 2447 } 2448 2449 return 0; 2450 } 2451 EXPORT_SYMBOL_GPL(ocelot_migrate_mdbs); 2452 2453 /* Documentation for PORTID_VAL says: 2454 * Logical port number for front port. If port is not a member of a LLAG, 2455 * then PORTID must be set to the physical port number. 2456 * If port is a member of a LLAG, then PORTID must be set to the common 2457 * PORTID_VAL used for all member ports of the LLAG. 2458 * The value must not exceed the number of physical ports on the device. 2459 * 2460 * This means we have little choice but to migrate FDB entries pointing towards 2461 * a logical port when that changes. 2462 */ 2463 static void ocelot_migrate_lag_fdbs(struct ocelot *ocelot, 2464 struct net_device *bond, 2465 int lag) 2466 { 2467 struct ocelot_lag_fdb *fdb; 2468 int err; 2469 2470 lockdep_assert_held(&ocelot->fwd_domain_lock); 2471 2472 list_for_each_entry(fdb, &ocelot->lag_fdbs, list) { 2473 if (fdb->bond != bond) 2474 continue; 2475 2476 err = ocelot_mact_forget(ocelot, fdb->addr, fdb->vid); 2477 if (err) { 2478 dev_err(ocelot->dev, 2479 "failed to delete LAG %s FDB %pM vid %d: %pe\n", 2480 bond->name, fdb->addr, fdb->vid, ERR_PTR(err)); 2481 } 2482 2483 err = ocelot_mact_learn(ocelot, lag, fdb->addr, fdb->vid, 2484 ENTRYTYPE_LOCKED); 2485 if (err) { 2486 dev_err(ocelot->dev, 2487 "failed to migrate LAG %s FDB %pM vid %d: %pe\n", 2488 bond->name, fdb->addr, fdb->vid, ERR_PTR(err)); 2489 } 2490 } 2491 } 2492 2493 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 2494 struct net_device *bond, 2495 struct netdev_lag_upper_info *info, 2496 struct netlink_ext_ack *extack) 2497 { 2498 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 2499 NL_SET_ERR_MSG_MOD(extack, 2500 "Can only offload LAG using hash TX type"); 2501 return -EOPNOTSUPP; 2502 } 2503 2504 mutex_lock(&ocelot->fwd_domain_lock); 2505 2506 ocelot->ports[port]->bond = bond; 2507 2508 ocelot_setup_logical_port_ids(ocelot); 2509 ocelot_apply_bridge_fwd_mask(ocelot, true); 2510 ocelot_set_aggr_pgids(ocelot); 2511 2512 mutex_unlock(&ocelot->fwd_domain_lock); 2513 2514 return 0; 2515 } 2516 EXPORT_SYMBOL(ocelot_port_lag_join); 2517 2518 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 2519 struct net_device *bond) 2520 { 2521 int old_lag_id, new_lag_id; 2522 2523 mutex_lock(&ocelot->fwd_domain_lock); 2524 2525 old_lag_id = ocelot_bond_get_id(ocelot, bond); 2526 2527 ocelot->ports[port]->bond = NULL; 2528 2529 ocelot_setup_logical_port_ids(ocelot); 2530 ocelot_apply_bridge_fwd_mask(ocelot, false); 2531 ocelot_set_aggr_pgids(ocelot); 2532 2533 new_lag_id = ocelot_bond_get_id(ocelot, bond); 2534 2535 if (new_lag_id >= 0 && old_lag_id != new_lag_id) 2536 ocelot_migrate_lag_fdbs(ocelot, bond, new_lag_id); 2537 2538 mutex_unlock(&ocelot->fwd_domain_lock); 2539 } 2540 EXPORT_SYMBOL(ocelot_port_lag_leave); 2541 2542 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 2543 { 2544 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2545 2546 mutex_lock(&ocelot->fwd_domain_lock); 2547 2548 ocelot_port->lag_tx_active = lag_tx_active; 2549 2550 /* Rebalance the LAGs */ 2551 ocelot_set_aggr_pgids(ocelot); 2552 2553 mutex_unlock(&ocelot->fwd_domain_lock); 2554 } 2555 EXPORT_SYMBOL(ocelot_port_lag_change); 2556 2557 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond, 2558 const unsigned char *addr, u16 vid, 2559 const struct net_device *bridge) 2560 { 2561 struct ocelot_lag_fdb *fdb; 2562 int lag, err; 2563 2564 fdb = kzalloc(sizeof(*fdb), GFP_KERNEL); 2565 if (!fdb) 2566 return -ENOMEM; 2567 2568 mutex_lock(&ocelot->fwd_domain_lock); 2569 2570 if (!vid) 2571 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2572 2573 ether_addr_copy(fdb->addr, addr); 2574 fdb->vid = vid; 2575 fdb->bond = bond; 2576 2577 lag = ocelot_bond_get_id(ocelot, bond); 2578 2579 err = ocelot_mact_learn(ocelot, lag, addr, vid, ENTRYTYPE_LOCKED); 2580 if (err) { 2581 mutex_unlock(&ocelot->fwd_domain_lock); 2582 kfree(fdb); 2583 return err; 2584 } 2585 2586 list_add_tail(&fdb->list, &ocelot->lag_fdbs); 2587 mutex_unlock(&ocelot->fwd_domain_lock); 2588 2589 return 0; 2590 } 2591 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_add); 2592 2593 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond, 2594 const unsigned char *addr, u16 vid, 2595 const struct net_device *bridge) 2596 { 2597 struct ocelot_lag_fdb *fdb, *tmp; 2598 2599 mutex_lock(&ocelot->fwd_domain_lock); 2600 2601 if (!vid) 2602 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2603 2604 list_for_each_entry_safe(fdb, tmp, &ocelot->lag_fdbs, list) { 2605 if (!ether_addr_equal(fdb->addr, addr) || fdb->vid != vid || 2606 fdb->bond != bond) 2607 continue; 2608 2609 ocelot_mact_forget(ocelot, addr, vid); 2610 list_del(&fdb->list); 2611 mutex_unlock(&ocelot->fwd_domain_lock); 2612 kfree(fdb); 2613 2614 return 0; 2615 } 2616 2617 mutex_unlock(&ocelot->fwd_domain_lock); 2618 2619 return -ENOENT; 2620 } 2621 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_del); 2622 2623 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 2624 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 2625 * In the special case that it's the NPI port that we're configuring, the 2626 * length of the tag and optional prefix needs to be accounted for privately, 2627 * in order to be able to sustain communication at the requested @sdu. 2628 */ 2629 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 2630 { 2631 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2632 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 2633 int pause_start, pause_stop; 2634 int atop, atop_tot; 2635 2636 if (port == ocelot->npi) { 2637 maxlen += OCELOT_TAG_LEN; 2638 2639 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2640 maxlen += OCELOT_SHORT_PREFIX_LEN; 2641 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2642 maxlen += OCELOT_LONG_PREFIX_LEN; 2643 } 2644 2645 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 2646 2647 /* Set Pause watermark hysteresis */ 2648 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 2649 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 2650 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 2651 pause_start); 2652 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 2653 pause_stop); 2654 2655 /* Tail dropping watermarks */ 2656 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 2657 OCELOT_BUFFER_CELL_SZ; 2658 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 2659 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 2660 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 2661 } 2662 EXPORT_SYMBOL(ocelot_port_set_maxlen); 2663 2664 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 2665 { 2666 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 2667 2668 if (port == ocelot->npi) { 2669 max_mtu -= OCELOT_TAG_LEN; 2670 2671 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2672 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 2673 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2674 max_mtu -= OCELOT_LONG_PREFIX_LEN; 2675 } 2676 2677 return max_mtu; 2678 } 2679 EXPORT_SYMBOL(ocelot_get_max_mtu); 2680 2681 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 2682 bool enabled) 2683 { 2684 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2685 u32 val = 0; 2686 2687 if (enabled) 2688 val = ANA_PORT_PORT_CFG_LEARN_ENA; 2689 2690 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 2691 ANA_PORT_PORT_CFG, port); 2692 2693 ocelot_port->learn_ena = enabled; 2694 } 2695 2696 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 2697 bool enabled) 2698 { 2699 u32 val = 0; 2700 2701 if (enabled) 2702 val = BIT(port); 2703 2704 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 2705 } 2706 2707 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 2708 bool enabled) 2709 { 2710 u32 val = 0; 2711 2712 if (enabled) 2713 val = BIT(port); 2714 2715 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 2716 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV4); 2717 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV6); 2718 } 2719 2720 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 2721 bool enabled) 2722 { 2723 u32 val = 0; 2724 2725 if (enabled) 2726 val = BIT(port); 2727 2728 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 2729 } 2730 2731 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 2732 struct switchdev_brport_flags flags) 2733 { 2734 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 2735 BR_BCAST_FLOOD)) 2736 return -EINVAL; 2737 2738 return 0; 2739 } 2740 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 2741 2742 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 2743 struct switchdev_brport_flags flags) 2744 { 2745 if (flags.mask & BR_LEARNING) 2746 ocelot_port_set_learning(ocelot, port, 2747 !!(flags.val & BR_LEARNING)); 2748 2749 if (flags.mask & BR_FLOOD) 2750 ocelot_port_set_ucast_flood(ocelot, port, 2751 !!(flags.val & BR_FLOOD)); 2752 2753 if (flags.mask & BR_MCAST_FLOOD) 2754 ocelot_port_set_mcast_flood(ocelot, port, 2755 !!(flags.val & BR_MCAST_FLOOD)); 2756 2757 if (flags.mask & BR_BCAST_FLOOD) 2758 ocelot_port_set_bcast_flood(ocelot, port, 2759 !!(flags.val & BR_BCAST_FLOOD)); 2760 } 2761 EXPORT_SYMBOL(ocelot_port_bridge_flags); 2762 2763 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port) 2764 { 2765 int val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port); 2766 2767 return ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val); 2768 } 2769 EXPORT_SYMBOL_GPL(ocelot_port_get_default_prio); 2770 2771 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio) 2772 { 2773 if (prio >= OCELOT_NUM_TC) 2774 return -ERANGE; 2775 2776 ocelot_rmw_gix(ocelot, 2777 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(prio), 2778 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M, 2779 ANA_PORT_QOS_CFG, 2780 port); 2781 2782 return ocelot_update_vlan_reclassify_rule(ocelot, port); 2783 } 2784 EXPORT_SYMBOL_GPL(ocelot_port_set_default_prio); 2785 2786 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp) 2787 { 2788 int qos_cfg = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port); 2789 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2790 2791 /* Return error if DSCP prioritization isn't enabled */ 2792 if (!(qos_cfg & ANA_PORT_QOS_CFG_QOS_DSCP_ENA)) 2793 return -EOPNOTSUPP; 2794 2795 if (qos_cfg & ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA) { 2796 dscp = ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(dscp_cfg); 2797 /* Re-read ANA_DSCP_CFG for the translated DSCP */ 2798 dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2799 } 2800 2801 /* If the DSCP value is not trusted, the QoS classification falls back 2802 * to VLAN PCP or port-based default. 2803 */ 2804 if (!(dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA)) 2805 return -EOPNOTSUPP; 2806 2807 return ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg); 2808 } 2809 EXPORT_SYMBOL_GPL(ocelot_port_get_dscp_prio); 2810 2811 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio) 2812 { 2813 int mask, val; 2814 2815 if (prio >= OCELOT_NUM_TC) 2816 return -ERANGE; 2817 2818 /* There is at least one app table priority (this one), so we need to 2819 * make sure DSCP prioritization is enabled on the port. 2820 * Also make sure DSCP translation is disabled 2821 * (dcbnl doesn't support it). 2822 */ 2823 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA | 2824 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA; 2825 2826 ocelot_rmw_gix(ocelot, ANA_PORT_QOS_CFG_QOS_DSCP_ENA, mask, 2827 ANA_PORT_QOS_CFG, port); 2828 2829 /* Trust this DSCP value and map it to the given QoS class */ 2830 val = ANA_DSCP_CFG_DSCP_TRUST_ENA | ANA_DSCP_CFG_QOS_DSCP_VAL(prio); 2831 2832 ocelot_write_rix(ocelot, val, ANA_DSCP_CFG, dscp); 2833 2834 return 0; 2835 } 2836 EXPORT_SYMBOL_GPL(ocelot_port_add_dscp_prio); 2837 2838 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio) 2839 { 2840 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2841 int mask, i; 2842 2843 /* During a "dcb app replace" command, the new app table entry will be 2844 * added first, then the old one will be deleted. But the hardware only 2845 * supports one QoS class per DSCP value (duh), so if we blindly delete 2846 * the app table entry for this DSCP value, we end up deleting the 2847 * entry with the new priority. Avoid that by checking whether user 2848 * space wants to delete the priority which is currently configured, or 2849 * something else which is no longer current. 2850 */ 2851 if (ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg) != prio) 2852 return 0; 2853 2854 /* Untrust this DSCP value */ 2855 ocelot_write_rix(ocelot, 0, ANA_DSCP_CFG, dscp); 2856 2857 for (i = 0; i < 64; i++) { 2858 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, i); 2859 2860 /* There are still app table entries on the port, so we need to 2861 * keep DSCP enabled, nothing to do. 2862 */ 2863 if (dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA) 2864 return 0; 2865 } 2866 2867 /* Disable DSCP QoS classification if there isn't any trusted 2868 * DSCP value left. 2869 */ 2870 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA | 2871 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA; 2872 2873 ocelot_rmw_gix(ocelot, 0, mask, ANA_PORT_QOS_CFG, port); 2874 2875 return 0; 2876 } 2877 EXPORT_SYMBOL_GPL(ocelot_port_del_dscp_prio); 2878 2879 struct ocelot_mirror *ocelot_mirror_get(struct ocelot *ocelot, int to, 2880 struct netlink_ext_ack *extack) 2881 { 2882 struct ocelot_mirror *m = ocelot->mirror; 2883 2884 if (m) { 2885 if (m->to != to) { 2886 NL_SET_ERR_MSG_MOD(extack, 2887 "Mirroring already configured towards different egress port"); 2888 return ERR_PTR(-EBUSY); 2889 } 2890 2891 refcount_inc(&m->refcount); 2892 return m; 2893 } 2894 2895 m = kzalloc(sizeof(*m), GFP_KERNEL); 2896 if (!m) 2897 return ERR_PTR(-ENOMEM); 2898 2899 m->to = to; 2900 refcount_set(&m->refcount, 1); 2901 ocelot->mirror = m; 2902 2903 /* Program the mirror port to hardware */ 2904 ocelot_write(ocelot, BIT(to), ANA_MIRRORPORTS); 2905 2906 return m; 2907 } 2908 2909 void ocelot_mirror_put(struct ocelot *ocelot) 2910 { 2911 struct ocelot_mirror *m = ocelot->mirror; 2912 2913 if (!refcount_dec_and_test(&m->refcount)) 2914 return; 2915 2916 ocelot_write(ocelot, 0, ANA_MIRRORPORTS); 2917 ocelot->mirror = NULL; 2918 kfree(m); 2919 } 2920 2921 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to, 2922 bool ingress, struct netlink_ext_ack *extack) 2923 { 2924 struct ocelot_mirror *m = ocelot_mirror_get(ocelot, to, extack); 2925 2926 if (IS_ERR(m)) 2927 return PTR_ERR(m); 2928 2929 if (ingress) { 2930 ocelot_rmw_gix(ocelot, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 2931 ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 2932 ANA_PORT_PORT_CFG, from); 2933 } else { 2934 ocelot_rmw(ocelot, BIT(from), BIT(from), 2935 ANA_EMIRRORPORTS); 2936 } 2937 2938 return 0; 2939 } 2940 EXPORT_SYMBOL_GPL(ocelot_port_mirror_add); 2941 2942 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress) 2943 { 2944 if (ingress) { 2945 ocelot_rmw_gix(ocelot, 0, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 2946 ANA_PORT_PORT_CFG, from); 2947 } else { 2948 ocelot_rmw(ocelot, 0, BIT(from), ANA_EMIRRORPORTS); 2949 } 2950 2951 ocelot_mirror_put(ocelot); 2952 } 2953 EXPORT_SYMBOL_GPL(ocelot_port_mirror_del); 2954 2955 static void ocelot_port_reset_mqprio(struct ocelot *ocelot, int port) 2956 { 2957 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port); 2958 2959 netdev_reset_tc(dev); 2960 ocelot_port_change_fp(ocelot, port, 0); 2961 } 2962 2963 int ocelot_port_mqprio(struct ocelot *ocelot, int port, 2964 struct tc_mqprio_qopt_offload *mqprio) 2965 { 2966 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port); 2967 struct netlink_ext_ack *extack = mqprio->extack; 2968 struct tc_mqprio_qopt *qopt = &mqprio->qopt; 2969 int num_tc = qopt->num_tc; 2970 int tc, err; 2971 2972 if (!num_tc) { 2973 ocelot_port_reset_mqprio(ocelot, port); 2974 return 0; 2975 } 2976 2977 err = netdev_set_num_tc(dev, num_tc); 2978 if (err) 2979 return err; 2980 2981 for (tc = 0; tc < num_tc; tc++) { 2982 if (qopt->count[tc] != 1) { 2983 NL_SET_ERR_MSG_MOD(extack, 2984 "Only one TXQ per TC supported"); 2985 return -EINVAL; 2986 } 2987 2988 err = netdev_set_tc_queue(dev, tc, 1, qopt->offset[tc]); 2989 if (err) 2990 goto err_reset_tc; 2991 } 2992 2993 err = netif_set_real_num_tx_queues(dev, num_tc); 2994 if (err) 2995 goto err_reset_tc; 2996 2997 ocelot_port_change_fp(ocelot, port, mqprio->preemptible_tcs); 2998 2999 return 0; 3000 3001 err_reset_tc: 3002 ocelot_port_reset_mqprio(ocelot, port); 3003 return err; 3004 } 3005 EXPORT_SYMBOL_GPL(ocelot_port_mqprio); 3006 3007 void ocelot_init_port(struct ocelot *ocelot, int port) 3008 { 3009 struct ocelot_port *ocelot_port = ocelot->ports[port]; 3010 3011 skb_queue_head_init(&ocelot_port->tx_skbs); 3012 3013 /* Basic L2 initialization */ 3014 3015 /* Set MAC IFG Gaps 3016 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 3017 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 3018 */ 3019 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 3020 DEV_MAC_IFG_CFG); 3021 3022 /* Load seed (0) and set MAC HDX late collision */ 3023 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 3024 DEV_MAC_HDX_CFG_SEED_LOAD, 3025 DEV_MAC_HDX_CFG); 3026 mdelay(1); 3027 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 3028 DEV_MAC_HDX_CFG); 3029 3030 /* Set Max Length and maximum tags allowed */ 3031 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 3032 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 3033 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 3034 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 3035 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 3036 DEV_MAC_TAGS_CFG); 3037 3038 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 3039 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 3040 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 3041 3042 /* Enable transmission of pause frames */ 3043 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 3044 3045 /* Drop frames with multicast source address */ 3046 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 3047 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 3048 ANA_PORT_DROP_CFG, port); 3049 3050 /* Set default VLAN and tag type to 8021Q. */ 3051 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 3052 REW_PORT_VLAN_CFG_PORT_TPID_M, 3053 REW_PORT_VLAN_CFG, port); 3054 3055 /* Disable source address learning for standalone mode */ 3056 ocelot_port_set_learning(ocelot, port, false); 3057 3058 /* Set the port's initial logical port ID value, enable receiving 3059 * frames on it, and configure the MAC address learning type to 3060 * automatic. 3061 */ 3062 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 3063 ANA_PORT_PORT_CFG_RECV_ENA | 3064 ANA_PORT_PORT_CFG_PORTID_VAL(port), 3065 ANA_PORT_PORT_CFG, port); 3066 3067 /* Enable vcap lookups */ 3068 ocelot_vcap_enable(ocelot, port); 3069 } 3070 EXPORT_SYMBOL(ocelot_init_port); 3071 3072 /* Configure and enable the CPU port module, which is a set of queues 3073 * accessible through register MMIO, frame DMA or Ethernet (in case 3074 * NPI mode is used). 3075 */ 3076 static void ocelot_cpu_port_init(struct ocelot *ocelot) 3077 { 3078 int cpu = ocelot->num_phys_ports; 3079 3080 /* The unicast destination PGID for the CPU port module is unused */ 3081 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 3082 /* Instead set up a multicast destination PGID for traffic copied to 3083 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 3084 * addresses will be copied to the CPU via this PGID. 3085 */ 3086 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 3087 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 3088 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 3089 ANA_PORT_PORT_CFG, cpu); 3090 3091 /* Enable CPU port module */ 3092 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 3093 /* CPU port Injection/Extraction configuration */ 3094 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 3095 OCELOT_TAG_PREFIX_NONE); 3096 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 3097 OCELOT_TAG_PREFIX_NONE); 3098 3099 /* Configure the CPU port to be VLAN aware */ 3100 ocelot_write_gix(ocelot, 3101 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_STANDALONE_PVID) | 3102 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 3103 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 3104 ANA_PORT_VLAN_CFG, cpu); 3105 } 3106 3107 static void ocelot_detect_features(struct ocelot *ocelot) 3108 { 3109 int mmgt, eq_ctrl; 3110 3111 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 3112 * the number of 240-byte free memory words (aka 4-cell chunks) and not 3113 * 192 bytes as the documentation incorrectly says. 3114 */ 3115 mmgt = ocelot_read(ocelot, SYS_MMGT); 3116 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 3117 3118 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 3119 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 3120 } 3121 3122 static int ocelot_mem_init_status(struct ocelot *ocelot) 3123 { 3124 unsigned int val; 3125 int err; 3126 3127 err = regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 3128 &val); 3129 3130 return err ?: val; 3131 } 3132 3133 int ocelot_reset(struct ocelot *ocelot) 3134 { 3135 int err; 3136 u32 val; 3137 3138 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1); 3139 if (err) 3140 return err; 3141 3142 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 3143 if (err) 3144 return err; 3145 3146 /* MEM_INIT is a self-clearing bit. Wait for it to be cleared (should be 3147 * 100us) before enabling the switch core. 3148 */ 3149 err = readx_poll_timeout(ocelot_mem_init_status, ocelot, val, !val, 3150 MEM_INIT_SLEEP_US, MEM_INIT_TIMEOUT_US); 3151 if (err) 3152 return err; 3153 3154 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 3155 if (err) 3156 return err; 3157 3158 return regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 3159 } 3160 EXPORT_SYMBOL(ocelot_reset); 3161 3162 int ocelot_init(struct ocelot *ocelot) 3163 { 3164 int i, ret; 3165 u32 port; 3166 3167 if (ocelot->ops->reset) { 3168 ret = ocelot->ops->reset(ocelot); 3169 if (ret) { 3170 dev_err(ocelot->dev, "Switch reset failed\n"); 3171 return ret; 3172 } 3173 } 3174 3175 mutex_init(&ocelot->mact_lock); 3176 mutex_init(&ocelot->fwd_domain_lock); 3177 spin_lock_init(&ocelot->ptp_clock_lock); 3178 spin_lock_init(&ocelot->ts_id_lock); 3179 spin_lock_init(&ocelot->inj_lock); 3180 spin_lock_init(&ocelot->xtr_lock); 3181 3182 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 3183 if (!ocelot->owq) 3184 return -ENOMEM; 3185 3186 ret = ocelot_stats_init(ocelot); 3187 if (ret) 3188 goto err_stats_init; 3189 3190 INIT_LIST_HEAD(&ocelot->multicast); 3191 INIT_LIST_HEAD(&ocelot->pgids); 3192 INIT_LIST_HEAD(&ocelot->vlans); 3193 INIT_LIST_HEAD(&ocelot->lag_fdbs); 3194 ocelot_detect_features(ocelot); 3195 ocelot_mact_init(ocelot); 3196 ocelot_vlan_init(ocelot); 3197 ocelot_vcap_init(ocelot); 3198 ocelot_cpu_port_init(ocelot); 3199 3200 if (ocelot->ops->psfp_init) 3201 ocelot->ops->psfp_init(ocelot); 3202 3203 if (ocelot->mm_supported) { 3204 ret = ocelot_mm_init(ocelot); 3205 if (ret) 3206 goto err_mm_init; 3207 } 3208 3209 for (port = 0; port < ocelot->num_phys_ports; port++) { 3210 /* Clear all counters (5 groups) */ 3211 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 3212 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 3213 SYS_STAT_CFG); 3214 } 3215 3216 /* Only use S-Tag */ 3217 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 3218 3219 /* Aggregation mode */ 3220 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 3221 ANA_AGGR_CFG_AC_DMAC_ENA | 3222 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 3223 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 3224 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 3225 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 3226 ANA_AGGR_CFG); 3227 3228 /* Set MAC age time to default value. The entry is aged after 3229 * 2*AGE_PERIOD 3230 */ 3231 ocelot_write(ocelot, 3232 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 3233 ANA_AUTOAGE); 3234 3235 /* Disable learning for frames discarded by VLAN ingress filtering */ 3236 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 3237 3238 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 3239 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 3240 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 3241 3242 /* Setup flooding PGIDs */ 3243 for (i = 0; i < ocelot->num_flooding_pgids; i++) 3244 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 3245 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 3246 ANA_FLOODING_FLD_UNICAST(PGID_UC), 3247 ANA_FLOODING, i); 3248 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 3249 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 3250 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 3251 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 3252 ANA_FLOODING_IPMC); 3253 3254 for (port = 0; port < ocelot->num_phys_ports; port++) { 3255 /* Transmit the frame to the local port. */ 3256 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 3257 /* Do not forward BPDU frames to the front ports. */ 3258 ocelot_write_gix(ocelot, 3259 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 3260 ANA_PORT_CPU_FWD_BPDU_CFG, 3261 port); 3262 /* Ensure bridging is disabled */ 3263 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 3264 } 3265 3266 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 3267 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 3268 3269 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 3270 } 3271 3272 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 3273 3274 /* Allow broadcast and unknown L2 multicast to the CPU. */ 3275 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3276 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3277 ANA_PGID_PGID, PGID_MC); 3278 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3279 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3280 ANA_PGID_PGID, PGID_BC); 3281 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 3282 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 3283 3284 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 3285 * registers endianness. 3286 */ 3287 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 3288 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 3289 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 3290 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 3291 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 3292 ANA_CPUQ_CFG_CPUQ_LRN(2) | 3293 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 3294 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 3295 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 3296 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 3297 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 3298 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 3299 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 3300 for (i = 0; i < 16; i++) 3301 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 3302 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 3303 ANA_CPUQ_8021_CFG, i); 3304 3305 return 0; 3306 3307 err_mm_init: 3308 ocelot_stats_deinit(ocelot); 3309 err_stats_init: 3310 destroy_workqueue(ocelot->owq); 3311 return ret; 3312 } 3313 EXPORT_SYMBOL(ocelot_init); 3314 3315 void ocelot_deinit(struct ocelot *ocelot) 3316 { 3317 ocelot_stats_deinit(ocelot); 3318 destroy_workqueue(ocelot->owq); 3319 } 3320 EXPORT_SYMBOL(ocelot_deinit); 3321 3322 void ocelot_deinit_port(struct ocelot *ocelot, int port) 3323 { 3324 struct ocelot_port *ocelot_port = ocelot->ports[port]; 3325 3326 skb_queue_purge(&ocelot_port->tx_skbs); 3327 } 3328 EXPORT_SYMBOL(ocelot_deinit_port); 3329 3330 MODULE_DESCRIPTION("Microsemi Ocelot switch family library"); 3331 MODULE_LICENSE("Dual MIT/GPL"); 3332