1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/interrupt.h> 41 #include <linux/delay.h> 42 #include <linux/mlx5/driver.h> 43 #include <linux/mlx5/cq.h> 44 #include <linux/mlx5/qp.h> 45 #include <linux/debugfs.h> 46 #include <linux/kmod.h> 47 #include <linux/mlx5/mlx5_ifc.h> 48 #include <linux/mlx5/vport.h> 49 #include <linux/version.h> 50 #include <net/devlink.h> 51 #include "mlx5_core.h" 52 #include "lib/eq.h" 53 #include "fs_core.h" 54 #include "lib/mpfs.h" 55 #include "eswitch.h" 56 #include "devlink.h" 57 #include "fw_reset.h" 58 #include "lib/mlx5.h" 59 #include "lib/tout.h" 60 #include "fpga/core.h" 61 #include "en_accel/ipsec.h" 62 #include "lib/clock.h" 63 #include "lib/vxlan.h" 64 #include "lib/geneve.h" 65 #include "lib/devcom.h" 66 #include "lib/pci_vsc.h" 67 #include "diag/fw_tracer.h" 68 #include "ecpf.h" 69 #include "lib/hv_vhca.h" 70 #include "diag/rsc_dump.h" 71 #include "sf/vhca_event.h" 72 #include "sf/dev/dev.h" 73 #include "sf/sf.h" 74 #include "mlx5_irq.h" 75 #include "hwmon.h" 76 #include "lag/lag.h" 77 78 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 79 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 80 MODULE_LICENSE("Dual BSD/GPL"); 81 82 unsigned int mlx5_core_debug_mask; 83 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 84 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 85 86 static unsigned int prof_sel = MLX5_DEFAULT_PROF; 87 module_param_named(prof_sel, prof_sel, uint, 0444); 88 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 89 90 static u32 sw_owner_id[4]; 91 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1) 92 static DEFINE_IDA(sw_vhca_ida); 93 94 enum { 95 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 96 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 97 }; 98 99 #define LOG_MAX_SUPPORTED_QPS 0xff 100 101 static struct mlx5_profile profile[] = { 102 [0] = { 103 .mask = 0, 104 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 105 }, 106 [1] = { 107 .mask = MLX5_PROF_MASK_QP_SIZE, 108 .log_max_qp = 12, 109 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 110 111 }, 112 [2] = { 113 .mask = MLX5_PROF_MASK_QP_SIZE | 114 MLX5_PROF_MASK_MR_CACHE, 115 .log_max_qp = LOG_MAX_SUPPORTED_QPS, 116 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 117 .mr_cache[0] = { 118 .size = 500, 119 .limit = 250 120 }, 121 .mr_cache[1] = { 122 .size = 500, 123 .limit = 250 124 }, 125 .mr_cache[2] = { 126 .size = 500, 127 .limit = 250 128 }, 129 .mr_cache[3] = { 130 .size = 500, 131 .limit = 250 132 }, 133 .mr_cache[4] = { 134 .size = 500, 135 .limit = 250 136 }, 137 .mr_cache[5] = { 138 .size = 500, 139 .limit = 250 140 }, 141 .mr_cache[6] = { 142 .size = 500, 143 .limit = 250 144 }, 145 .mr_cache[7] = { 146 .size = 500, 147 .limit = 250 148 }, 149 .mr_cache[8] = { 150 .size = 500, 151 .limit = 250 152 }, 153 .mr_cache[9] = { 154 .size = 500, 155 .limit = 250 156 }, 157 .mr_cache[10] = { 158 .size = 500, 159 .limit = 250 160 }, 161 .mr_cache[11] = { 162 .size = 500, 163 .limit = 250 164 }, 165 .mr_cache[12] = { 166 .size = 64, 167 .limit = 32 168 }, 169 .mr_cache[13] = { 170 .size = 32, 171 .limit = 16 172 }, 173 .mr_cache[14] = { 174 .size = 16, 175 .limit = 8 176 }, 177 .mr_cache[15] = { 178 .size = 8, 179 .limit = 4 180 }, 181 }, 182 [3] = { 183 .mask = MLX5_PROF_MASK_QP_SIZE, 184 .log_max_qp = LOG_MAX_SUPPORTED_QPS, 185 .num_cmd_caches = 0, 186 }, 187 }; 188 189 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 190 u32 warn_time_mili, const char *init_state) 191 { 192 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 193 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 194 u32 fw_initializing; 195 196 do { 197 fw_initializing = ioread32be(&dev->iseg->initializing); 198 if (!(fw_initializing >> 31)) 199 break; 200 if (time_after(jiffies, end)) { 201 mlx5_core_err(dev, "Firmware over %u MS in %s state, aborting\n", 202 max_wait_mili, init_state); 203 return -ETIMEDOUT; 204 } 205 if (test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) { 206 mlx5_core_warn(dev, "device is being removed, stop waiting for FW %s\n", 207 init_state); 208 return -ENODEV; 209 } 210 if (warn_time_mili && time_after(jiffies, warn)) { 211 mlx5_core_warn(dev, "Waiting for FW %s, timeout abort in %ds (0x%x)\n", 212 init_state, jiffies_to_msecs(end - warn) / 1000, 213 fw_initializing); 214 warn = jiffies + msecs_to_jiffies(warn_time_mili); 215 } 216 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT)); 217 } while (true); 218 219 return 0; 220 } 221 222 static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 223 { 224 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 225 driver_version); 226 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 227 char *string; 228 229 if (!MLX5_CAP_GEN(dev, driver_version)) 230 return; 231 232 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 233 234 snprintf(string, driver_ver_sz, "Linux,%s,%u.%u.%u", 235 KBUILD_MODNAME, LINUX_VERSION_MAJOR, 236 LINUX_VERSION_PATCHLEVEL, LINUX_VERSION_SUBLEVEL); 237 238 /*Send the command*/ 239 MLX5_SET(set_driver_version_in, in, opcode, 240 MLX5_CMD_OP_SET_DRIVER_VERSION); 241 242 mlx5_cmd_exec_in(dev, set_driver_version, in); 243 } 244 245 static int set_dma_caps(struct pci_dev *pdev) 246 { 247 int err; 248 249 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 250 if (err) { 251 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 252 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 253 if (err) { 254 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 255 return err; 256 } 257 } 258 259 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 260 return err; 261 } 262 263 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 264 { 265 struct pci_dev *pdev = dev->pdev; 266 int err = 0; 267 268 mutex_lock(&dev->pci_status_mutex); 269 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 270 err = pci_enable_device(pdev); 271 if (!err) 272 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 273 } 274 mutex_unlock(&dev->pci_status_mutex); 275 276 return err; 277 } 278 279 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 280 { 281 struct pci_dev *pdev = dev->pdev; 282 283 mutex_lock(&dev->pci_status_mutex); 284 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 285 pci_disable_device(pdev); 286 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 287 } 288 mutex_unlock(&dev->pci_status_mutex); 289 } 290 291 static int request_bar(struct pci_dev *pdev) 292 { 293 int err = 0; 294 295 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 296 dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 297 return -ENODEV; 298 } 299 300 err = pci_request_regions(pdev, KBUILD_MODNAME); 301 if (err) 302 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 303 304 return err; 305 } 306 307 static void release_bar(struct pci_dev *pdev) 308 { 309 pci_release_regions(pdev); 310 } 311 312 struct mlx5_reg_host_endianness { 313 u8 he; 314 u8 rsvd[15]; 315 }; 316 317 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 318 { 319 switch (size) { 320 case 128: 321 return 0; 322 case 256: 323 return 1; 324 case 512: 325 return 2; 326 case 1024: 327 return 3; 328 case 2048: 329 return 4; 330 case 4096: 331 return 5; 332 default: 333 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 334 return 0; 335 } 336 } 337 338 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev) 339 { 340 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 341 dev->mlx5e_res.uplink_netdev = netdev; 342 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 343 netdev); 344 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 345 } 346 347 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev) 348 { 349 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 350 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 351 dev->mlx5e_res.uplink_netdev); 352 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 353 } 354 EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay); 355 356 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data) 357 { 358 mlx5_blocking_notifier_call_chain(dev, event, data); 359 } 360 EXPORT_SYMBOL(mlx5_core_mp_event_replay); 361 362 int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 363 enum mlx5_cap_mode cap_mode) 364 { 365 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 366 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 367 void *out, *hca_caps; 368 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 369 int err; 370 371 if (WARN_ON(!dev->caps.hca[cap_type])) 372 /* this cap_type must be added to mlx5_hca_caps_alloc() */ 373 return -EINVAL; 374 375 memset(in, 0, sizeof(in)); 376 out = kzalloc(out_sz, GFP_KERNEL); 377 if (!out) 378 return -ENOMEM; 379 380 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 381 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 382 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 383 if (err) { 384 mlx5_core_warn(dev, 385 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 386 cap_type, cap_mode, err); 387 goto query_ex; 388 } 389 390 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 391 392 switch (cap_mode) { 393 case HCA_CAP_OPMOD_GET_MAX: 394 memcpy(dev->caps.hca[cap_type]->max, hca_caps, 395 MLX5_UN_SZ_BYTES(hca_cap_union)); 396 break; 397 case HCA_CAP_OPMOD_GET_CUR: 398 memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 399 MLX5_UN_SZ_BYTES(hca_cap_union)); 400 break; 401 default: 402 mlx5_core_warn(dev, 403 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 404 cap_type, cap_mode); 405 err = -EINVAL; 406 break; 407 } 408 query_ex: 409 kfree(out); 410 return err; 411 } 412 413 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 414 { 415 int ret; 416 417 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 418 if (ret) 419 return ret; 420 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 421 } 422 423 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 424 { 425 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 426 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 427 return mlx5_cmd_exec_in(dev, set_hca_cap, in); 428 } 429 430 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 431 { 432 void *set_hca_cap; 433 int req_endianness; 434 int err; 435 436 if (!MLX5_CAP_GEN(dev, atomic)) 437 return 0; 438 439 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 440 if (err) 441 return err; 442 443 req_endianness = 444 MLX5_CAP_ATOMIC(dev, 445 supported_atomic_req_8B_endianness_mode_1); 446 447 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 448 return 0; 449 450 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 451 452 /* Set requestor to host endianness */ 453 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 454 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 455 456 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 457 } 458 459 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 460 { 461 bool do_set = false, mem_page_fault = false; 462 void *set_hca_cap; 463 int err; 464 465 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 466 !MLX5_CAP_GEN(dev, pg)) 467 return 0; 468 469 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 470 if (err) 471 return err; 472 473 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 474 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 475 MLX5_ST_SZ_BYTES(odp_cap)); 476 477 /* For best performance, enable memory scheme ODP only when 478 * it has page prefetch enabled. 479 */ 480 if (MLX5_CAP_ODP_MAX(dev, mem_page_fault) && 481 MLX5_CAP_ODP_MAX(dev, memory_page_fault_scheme_cap.page_prefetch)) { 482 mem_page_fault = true; 483 do_set = true; 484 MLX5_SET(odp_cap, set_hca_cap, mem_page_fault, mem_page_fault); 485 goto set; 486 } 487 488 #define ODP_CAP_SET_MAX(dev, field) \ 489 do { \ 490 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 491 if (_res) { \ 492 do_set = true; \ 493 MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 494 } \ 495 } while (0) 496 497 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.ud_odp_caps.srq_receive); 498 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.rc_odp_caps.srq_receive); 499 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.srq_receive); 500 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.send); 501 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.receive); 502 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.write); 503 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.read); 504 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.atomic); 505 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.srq_receive); 506 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.send); 507 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.receive); 508 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.write); 509 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.read); 510 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.atomic); 511 512 set: 513 if (do_set) 514 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 515 516 mlx5_core_dbg(dev, "Using ODP %s scheme\n", 517 mem_page_fault ? "memory" : "transport"); 518 return err; 519 } 520 521 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev) 522 { 523 struct devlink *devlink = priv_to_devlink(dev); 524 union devlink_param_value val; 525 int err; 526 527 err = devl_param_driverinit_value_get(devlink, 528 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 529 &val); 530 if (!err) 531 return val.vu32; 532 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 533 return err; 534 } 535 536 bool mlx5_is_roce_on(struct mlx5_core_dev *dev) 537 { 538 struct devlink *devlink = priv_to_devlink(dev); 539 union devlink_param_value val; 540 int err; 541 542 err = devl_param_driverinit_value_get(devlink, 543 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, 544 &val); 545 546 if (!err) 547 return val.vbool; 548 549 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 550 return MLX5_CAP_GEN(dev, roce); 551 } 552 EXPORT_SYMBOL(mlx5_is_roce_on); 553 554 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx) 555 { 556 void *set_hca_cap; 557 int err; 558 559 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2)) 560 return 0; 561 562 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2); 563 if (err) 564 return err; 565 566 if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) || 567 !(dev->priv.sw_vhca_id > 0)) 568 return 0; 569 570 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 571 capability); 572 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur, 573 MLX5_ST_SZ_BYTES(cmd_hca_cap_2)); 574 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1); 575 576 return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2); 577 } 578 579 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 580 { 581 struct mlx5_profile *prof = &dev->profile; 582 void *set_hca_cap; 583 int max_uc_list; 584 int err; 585 586 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 587 if (err) 588 return err; 589 590 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 591 capability); 592 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 593 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 594 595 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 596 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 597 128); 598 /* we limit the size of the pkey table to 128 entries for now */ 599 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 600 to_fw_pkey_sz(dev, 128)); 601 602 /* Check log_max_qp from HCA caps to set in current profile */ 603 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) { 604 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp)); 605 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 606 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 607 prof->log_max_qp, 608 MLX5_CAP_GEN_MAX(dev, log_max_qp)); 609 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 610 } 611 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 612 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 613 prof->log_max_qp); 614 615 /* disable cmdif checksum */ 616 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 617 618 /* Enable 4K UAR only when HCA supports it and page size is bigger 619 * than 4K. 620 */ 621 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 622 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 623 624 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 625 626 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 627 MLX5_SET(cmd_hca_cap, 628 set_hca_cap, 629 cache_line_128byte, 630 cache_line_size() >= 128 ? 1 : 0); 631 632 if (MLX5_CAP_GEN_MAX(dev, dct)) 633 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 634 635 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 636 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 637 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_with_driver_unload)) 638 MLX5_SET(cmd_hca_cap, set_hca_cap, 639 pci_sync_for_fw_update_with_driver_unload, 1); 640 if (MLX5_CAP_GEN_MAX(dev, pcie_reset_using_hotreset_method)) 641 MLX5_SET(cmd_hca_cap, set_hca_cap, 642 pcie_reset_using_hotreset_method, 1); 643 644 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 645 MLX5_SET(cmd_hca_cap, 646 set_hca_cap, 647 num_vhca_ports, 648 MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 649 650 if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 651 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 652 653 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 654 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 655 656 mlx5_vhca_state_cap_handle(dev, set_hca_cap); 657 658 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 659 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 660 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 661 662 if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce)) 663 MLX5_SET(cmd_hca_cap, set_hca_cap, roce, 664 mlx5_is_roce_on(dev)); 665 666 max_uc_list = max_uc_list_get_devlink_param(dev); 667 if (max_uc_list > 0) 668 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list, 669 ilog2(max_uc_list)); 670 671 /* enable absolute native port num */ 672 if (MLX5_CAP_GEN_MAX(dev, abs_native_port_num)) 673 MLX5_SET(cmd_hca_cap, set_hca_cap, abs_native_port_num, 1); 674 675 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 676 } 677 678 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the 679 * boot process. 680 * In case RoCE cap is writable in FW and user/devlink requested to change the 681 * cap, we are yet to query the final state of the above cap. 682 * Hence, the need for this function. 683 * 684 * Returns 685 * True: 686 * 1) RoCE cap is read only in FW and already disabled 687 * OR: 688 * 2) RoCE cap is writable in FW and user/devlink requested it off. 689 * 690 * In any other case, return False. 691 */ 692 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev) 693 { 694 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) || 695 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); 696 } 697 698 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 699 { 700 void *set_hca_cap; 701 int err; 702 703 if (is_roce_fw_disabled(dev)) 704 return 0; 705 706 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 707 if (err) 708 return err; 709 710 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 711 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 712 return 0; 713 714 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 715 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 716 MLX5_ST_SZ_BYTES(roce_cap)); 717 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 718 719 if (MLX5_CAP_ROCE_MAX(dev, qp_ooo_transmit_default)) 720 MLX5_SET(roce_cap, set_hca_cap, qp_ooo_transmit_default, 1); 721 722 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 723 return err; 724 } 725 726 static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev, 727 void *set_ctx) 728 { 729 void *set_hca_cap; 730 int err; 731 732 if (!MLX5_CAP_GEN(dev, port_selection_cap)) 733 return 0; 734 735 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION); 736 if (err) 737 return err; 738 739 if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) || 740 !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass)) 741 return 0; 742 743 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 744 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, 745 MLX5_ST_SZ_BYTES(port_selection_cap)); 746 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1); 747 748 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION); 749 750 return err; 751 } 752 753 static int set_hca_cap(struct mlx5_core_dev *dev) 754 { 755 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 756 void *set_ctx; 757 int err; 758 759 set_ctx = kzalloc(set_sz, GFP_KERNEL); 760 if (!set_ctx) 761 return -ENOMEM; 762 763 err = handle_hca_cap(dev, set_ctx); 764 if (err) { 765 mlx5_core_err(dev, "handle_hca_cap failed\n"); 766 goto out; 767 } 768 769 memset(set_ctx, 0, set_sz); 770 err = handle_hca_cap_atomic(dev, set_ctx); 771 if (err) { 772 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 773 goto out; 774 } 775 776 memset(set_ctx, 0, set_sz); 777 err = handle_hca_cap_odp(dev, set_ctx); 778 if (err) { 779 mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 780 goto out; 781 } 782 783 memset(set_ctx, 0, set_sz); 784 err = handle_hca_cap_roce(dev, set_ctx); 785 if (err) { 786 mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 787 goto out; 788 } 789 790 memset(set_ctx, 0, set_sz); 791 err = handle_hca_cap_2(dev, set_ctx); 792 if (err) { 793 mlx5_core_err(dev, "handle_hca_cap_2 failed\n"); 794 goto out; 795 } 796 797 memset(set_ctx, 0, set_sz); 798 err = handle_hca_cap_port_selection(dev, set_ctx); 799 if (err) { 800 mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n"); 801 goto out; 802 } 803 804 out: 805 kfree(set_ctx); 806 return err; 807 } 808 809 static int set_hca_ctrl(struct mlx5_core_dev *dev) 810 { 811 struct mlx5_reg_host_endianness he_in; 812 struct mlx5_reg_host_endianness he_out; 813 int err; 814 815 if (!mlx5_core_is_pf(dev)) 816 return 0; 817 818 memset(&he_in, 0, sizeof(he_in)); 819 he_in.he = MLX5_SET_HOST_ENDIANNESS; 820 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 821 &he_out, sizeof(he_out), 822 MLX5_REG_HOST_ENDIANNESS, 0, 1); 823 return err; 824 } 825 826 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 827 { 828 int ret = 0; 829 830 /* Disable local_lb by default */ 831 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 832 ret = mlx5_nic_vport_update_local_lb(dev, false); 833 834 return ret; 835 } 836 837 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 838 { 839 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 840 841 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 842 MLX5_SET(enable_hca_in, in, function_id, func_id); 843 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 844 dev->caps.embedded_cpu); 845 return mlx5_cmd_exec_in(dev, enable_hca, in); 846 } 847 848 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 849 { 850 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 851 852 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 853 MLX5_SET(disable_hca_in, in, function_id, func_id); 854 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 855 dev->caps.embedded_cpu); 856 return mlx5_cmd_exec_in(dev, disable_hca, in); 857 } 858 859 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 860 { 861 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 862 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 863 u32 sup_issi; 864 int err; 865 866 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 867 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 868 if (err) { 869 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome); 870 u8 status = MLX5_GET(query_issi_out, query_out, status); 871 872 if (!status || syndrome == MLX5_DRIVER_SYND) { 873 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 874 err, status, syndrome); 875 return err; 876 } 877 878 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 879 dev->issi = 0; 880 return 0; 881 } 882 883 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 884 885 if (sup_issi & (1 << 1)) { 886 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 887 888 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 889 MLX5_SET(set_issi_in, set_in, current_issi, 1); 890 err = mlx5_cmd_exec_in(dev, set_issi, set_in); 891 if (err) { 892 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 893 err); 894 return err; 895 } 896 897 dev->issi = 1; 898 899 return 0; 900 } else if (sup_issi & (1 << 0) || !sup_issi) { 901 return 0; 902 } 903 904 return -EOPNOTSUPP; 905 } 906 907 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 908 const struct pci_device_id *id) 909 { 910 int err = 0; 911 912 mutex_init(&dev->pci_status_mutex); 913 pci_set_drvdata(dev->pdev, dev); 914 915 dev->bar_addr = pci_resource_start(pdev, 0); 916 917 err = mlx5_pci_enable_device(dev); 918 if (err) { 919 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 920 return err; 921 } 922 923 err = request_bar(pdev); 924 if (err) { 925 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 926 goto err_disable; 927 } 928 929 pci_set_master(pdev); 930 931 err = set_dma_caps(pdev); 932 if (err) { 933 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 934 goto err_clr_master; 935 } 936 937 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 938 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 939 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 940 mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 941 942 dev->iseg_base = dev->bar_addr; 943 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 944 if (!dev->iseg) { 945 err = -ENOMEM; 946 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 947 goto err_clr_master; 948 } 949 950 mlx5_pci_vsc_init(dev); 951 952 pci_enable_ptm(pdev, NULL); 953 954 return 0; 955 956 err_clr_master: 957 release_bar(dev->pdev); 958 err_disable: 959 mlx5_pci_disable_device(dev); 960 return err; 961 } 962 963 static void mlx5_pci_close(struct mlx5_core_dev *dev) 964 { 965 /* health work might still be active, and it needs pci bar in 966 * order to know the NIC state. Therefore, drain the health WQ 967 * before removing the pci bars 968 */ 969 mlx5_drain_health_wq(dev); 970 pci_disable_ptm(dev->pdev); 971 iounmap(dev->iseg); 972 release_bar(dev->pdev); 973 mlx5_pci_disable_device(dev); 974 } 975 976 static void mlx5_register_hca_devcom_comp(struct mlx5_core_dev *dev) 977 { 978 /* This component is use to sync adding core_dev to lag_dev and to sync 979 * changes of mlx5_adev_devices between LAG layer and other layers. 980 */ 981 if (!mlx5_lag_is_supported(dev)) 982 return; 983 984 dev->priv.hca_devcom_comp = 985 mlx5_devcom_register_component(dev->priv.devc, MLX5_DEVCOM_HCA_PORTS, 986 mlx5_query_nic_system_image_guid(dev), 987 NULL, dev); 988 if (IS_ERR(dev->priv.hca_devcom_comp)) 989 mlx5_core_err(dev, "Failed to register devcom HCA component\n"); 990 } 991 992 static void mlx5_unregister_hca_devcom_comp(struct mlx5_core_dev *dev) 993 { 994 mlx5_devcom_unregister_component(dev->priv.hca_devcom_comp); 995 } 996 997 static int mlx5_init_once(struct mlx5_core_dev *dev) 998 { 999 int err; 1000 1001 dev->priv.devc = mlx5_devcom_register_device(dev); 1002 if (IS_ERR(dev->priv.devc)) 1003 mlx5_core_warn(dev, "failed to register devcom device %ld\n", 1004 PTR_ERR(dev->priv.devc)); 1005 mlx5_register_hca_devcom_comp(dev); 1006 1007 err = mlx5_query_board_id(dev); 1008 if (err) { 1009 mlx5_core_err(dev, "query board id failed\n"); 1010 goto err_devcom; 1011 } 1012 1013 err = mlx5_irq_table_init(dev); 1014 if (err) { 1015 mlx5_core_err(dev, "failed to initialize irq table\n"); 1016 goto err_devcom; 1017 } 1018 1019 err = mlx5_eq_table_init(dev); 1020 if (err) { 1021 mlx5_core_err(dev, "failed to initialize eq\n"); 1022 goto err_irq_cleanup; 1023 } 1024 1025 err = mlx5_events_init(dev); 1026 if (err) { 1027 mlx5_core_err(dev, "failed to initialize events\n"); 1028 goto err_eq_cleanup; 1029 } 1030 1031 err = mlx5_fw_reset_init(dev); 1032 if (err) { 1033 mlx5_core_err(dev, "failed to initialize fw reset events\n"); 1034 goto err_events_cleanup; 1035 } 1036 1037 mlx5_cq_debugfs_init(dev); 1038 1039 mlx5_init_reserved_gids(dev); 1040 1041 mlx5_init_clock(dev); 1042 1043 dev->vxlan = mlx5_vxlan_create(dev); 1044 dev->geneve = mlx5_geneve_create(dev); 1045 1046 err = mlx5_init_rl_table(dev); 1047 if (err) { 1048 mlx5_core_err(dev, "Failed to init rate limiting\n"); 1049 goto err_tables_cleanup; 1050 } 1051 1052 err = mlx5_mpfs_init(dev); 1053 if (err) { 1054 mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 1055 goto err_rl_cleanup; 1056 } 1057 1058 err = mlx5_sriov_init(dev); 1059 if (err) { 1060 mlx5_core_err(dev, "Failed to init sriov %d\n", err); 1061 goto err_mpfs_cleanup; 1062 } 1063 1064 err = mlx5_eswitch_init(dev); 1065 if (err) { 1066 mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 1067 goto err_sriov_cleanup; 1068 } 1069 1070 err = mlx5_fpga_init(dev); 1071 if (err) { 1072 mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 1073 goto err_eswitch_cleanup; 1074 } 1075 1076 err = mlx5_vhca_event_init(dev); 1077 if (err) { 1078 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 1079 goto err_fpga_cleanup; 1080 } 1081 1082 err = mlx5_sf_hw_table_init(dev); 1083 if (err) { 1084 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 1085 goto err_sf_hw_table_cleanup; 1086 } 1087 1088 err = mlx5_sf_table_init(dev); 1089 if (err) { 1090 mlx5_core_err(dev, "Failed to init SF table %d\n", err); 1091 goto err_sf_table_cleanup; 1092 } 1093 1094 err = mlx5_fs_core_alloc(dev); 1095 if (err) { 1096 mlx5_core_err(dev, "Failed to alloc flow steering\n"); 1097 goto err_fs; 1098 } 1099 1100 dev->dm = mlx5_dm_create(dev); 1101 if (IS_ERR(dev->dm)) 1102 mlx5_core_warn(dev, "Failed to init device memory %ld\n", PTR_ERR(dev->dm)); 1103 1104 dev->tracer = mlx5_fw_tracer_create(dev); 1105 dev->hv_vhca = mlx5_hv_vhca_create(dev); 1106 dev->rsc_dump = mlx5_rsc_dump_create(dev); 1107 1108 return 0; 1109 1110 err_fs: 1111 mlx5_sf_table_cleanup(dev); 1112 err_sf_table_cleanup: 1113 mlx5_sf_hw_table_cleanup(dev); 1114 err_sf_hw_table_cleanup: 1115 mlx5_vhca_event_cleanup(dev); 1116 err_fpga_cleanup: 1117 mlx5_fpga_cleanup(dev); 1118 err_eswitch_cleanup: 1119 mlx5_eswitch_cleanup(dev->priv.eswitch); 1120 err_sriov_cleanup: 1121 mlx5_sriov_cleanup(dev); 1122 err_mpfs_cleanup: 1123 mlx5_mpfs_cleanup(dev); 1124 err_rl_cleanup: 1125 mlx5_cleanup_rl_table(dev); 1126 err_tables_cleanup: 1127 mlx5_geneve_destroy(dev->geneve); 1128 mlx5_vxlan_destroy(dev->vxlan); 1129 mlx5_cleanup_clock(dev); 1130 mlx5_cleanup_reserved_gids(dev); 1131 mlx5_cq_debugfs_cleanup(dev); 1132 mlx5_fw_reset_cleanup(dev); 1133 err_events_cleanup: 1134 mlx5_events_cleanup(dev); 1135 err_eq_cleanup: 1136 mlx5_eq_table_cleanup(dev); 1137 err_irq_cleanup: 1138 mlx5_irq_table_cleanup(dev); 1139 err_devcom: 1140 mlx5_unregister_hca_devcom_comp(dev); 1141 mlx5_devcom_unregister_device(dev->priv.devc); 1142 1143 return err; 1144 } 1145 1146 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 1147 { 1148 mlx5_rsc_dump_destroy(dev); 1149 mlx5_hv_vhca_destroy(dev->hv_vhca); 1150 mlx5_fw_tracer_destroy(dev->tracer); 1151 mlx5_dm_cleanup(dev); 1152 mlx5_fs_core_free(dev); 1153 mlx5_sf_table_cleanup(dev); 1154 mlx5_sf_hw_table_cleanup(dev); 1155 mlx5_vhca_event_cleanup(dev); 1156 mlx5_fpga_cleanup(dev); 1157 mlx5_eswitch_cleanup(dev->priv.eswitch); 1158 mlx5_sriov_cleanup(dev); 1159 mlx5_mpfs_cleanup(dev); 1160 mlx5_cleanup_rl_table(dev); 1161 mlx5_geneve_destroy(dev->geneve); 1162 mlx5_vxlan_destroy(dev->vxlan); 1163 mlx5_cleanup_clock(dev); 1164 mlx5_cleanup_reserved_gids(dev); 1165 mlx5_cq_debugfs_cleanup(dev); 1166 mlx5_fw_reset_cleanup(dev); 1167 mlx5_events_cleanup(dev); 1168 mlx5_eq_table_cleanup(dev); 1169 mlx5_irq_table_cleanup(dev); 1170 mlx5_unregister_hca_devcom_comp(dev); 1171 mlx5_devcom_unregister_device(dev->priv.devc); 1172 } 1173 1174 static int mlx5_function_enable(struct mlx5_core_dev *dev, bool boot, u64 timeout) 1175 { 1176 int err; 1177 1178 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 1179 fw_rev_min(dev), fw_rev_sub(dev)); 1180 1181 /* Only PFs hold the relevant PCIe information for this query */ 1182 if (mlx5_core_is_pf(dev)) 1183 pcie_print_link_status(dev->pdev); 1184 1185 /* wait for firmware to accept initialization segments configurations 1186 */ 1187 err = wait_fw_init(dev, timeout, 1188 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL), 1189 "pre-initializing"); 1190 if (err) 1191 return err; 1192 1193 err = mlx5_cmd_enable(dev); 1194 if (err) { 1195 mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 1196 return err; 1197 } 1198 1199 mlx5_tout_query_iseg(dev); 1200 1201 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0, "initializing"); 1202 if (err) 1203 goto err_cmd_cleanup; 1204 1205 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 1206 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1207 1208 mlx5_start_health_poll(dev); 1209 1210 err = mlx5_core_enable_hca(dev, 0); 1211 if (err) { 1212 mlx5_core_err(dev, "enable hca failed\n"); 1213 goto stop_health_poll; 1214 } 1215 1216 err = mlx5_core_set_issi(dev); 1217 if (err) { 1218 mlx5_core_err(dev, "failed to set issi\n"); 1219 goto err_disable_hca; 1220 } 1221 1222 err = mlx5_satisfy_startup_pages(dev, 1); 1223 if (err) { 1224 mlx5_core_err(dev, "failed to allocate boot pages\n"); 1225 goto err_disable_hca; 1226 } 1227 1228 err = mlx5_tout_query_dtor(dev); 1229 if (err) { 1230 mlx5_core_err(dev, "failed to read dtor\n"); 1231 goto reclaim_boot_pages; 1232 } 1233 1234 return 0; 1235 1236 reclaim_boot_pages: 1237 mlx5_reclaim_startup_pages(dev); 1238 err_disable_hca: 1239 mlx5_core_disable_hca(dev, 0); 1240 stop_health_poll: 1241 mlx5_stop_health_poll(dev, boot); 1242 err_cmd_cleanup: 1243 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1244 mlx5_cmd_disable(dev); 1245 1246 return err; 1247 } 1248 1249 static void mlx5_function_disable(struct mlx5_core_dev *dev, bool boot) 1250 { 1251 mlx5_reclaim_startup_pages(dev); 1252 mlx5_core_disable_hca(dev, 0); 1253 mlx5_stop_health_poll(dev, boot); 1254 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1255 mlx5_cmd_disable(dev); 1256 } 1257 1258 static int mlx5_function_open(struct mlx5_core_dev *dev) 1259 { 1260 int err; 1261 1262 err = set_hca_ctrl(dev); 1263 if (err) { 1264 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1265 return err; 1266 } 1267 1268 err = set_hca_cap(dev); 1269 if (err) { 1270 mlx5_core_err(dev, "set_hca_cap failed\n"); 1271 return err; 1272 } 1273 1274 err = mlx5_satisfy_startup_pages(dev, 0); 1275 if (err) { 1276 mlx5_core_err(dev, "failed to allocate init pages\n"); 1277 return err; 1278 } 1279 1280 err = mlx5_cmd_init_hca(dev, sw_owner_id); 1281 if (err) { 1282 mlx5_core_err(dev, "init hca failed\n"); 1283 return err; 1284 } 1285 1286 mlx5_set_driver_version(dev); 1287 1288 err = mlx5_query_hca_caps(dev); 1289 if (err) { 1290 mlx5_core_err(dev, "query hca failed\n"); 1291 return err; 1292 } 1293 mlx5_start_health_fw_log_up(dev); 1294 return 0; 1295 } 1296 1297 static int mlx5_function_close(struct mlx5_core_dev *dev) 1298 { 1299 int err; 1300 1301 err = mlx5_cmd_teardown_hca(dev); 1302 if (err) { 1303 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1304 return err; 1305 } 1306 1307 return 0; 1308 } 1309 1310 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout) 1311 { 1312 int err; 1313 1314 err = mlx5_function_enable(dev, boot, timeout); 1315 if (err) 1316 return err; 1317 1318 err = mlx5_function_open(dev); 1319 if (err) 1320 mlx5_function_disable(dev, boot); 1321 return err; 1322 } 1323 1324 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1325 { 1326 int err = mlx5_function_close(dev); 1327 1328 if (!err) 1329 mlx5_function_disable(dev, boot); 1330 else 1331 mlx5_stop_health_poll(dev, boot); 1332 1333 return err; 1334 } 1335 1336 static int mlx5_load(struct mlx5_core_dev *dev) 1337 { 1338 int err; 1339 1340 dev->priv.uar = mlx5_get_uars_page(dev); 1341 if (IS_ERR(dev->priv.uar)) { 1342 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1343 err = PTR_ERR(dev->priv.uar); 1344 return err; 1345 } 1346 1347 mlx5_events_start(dev); 1348 mlx5_pagealloc_start(dev); 1349 1350 err = mlx5_irq_table_create(dev); 1351 if (err) { 1352 mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1353 goto err_irq_table; 1354 } 1355 1356 err = mlx5_eq_table_create(dev); 1357 if (err) { 1358 mlx5_core_err(dev, "Failed to create EQs\n"); 1359 goto err_eq_table; 1360 } 1361 1362 err = mlx5_fw_tracer_init(dev->tracer); 1363 if (err) { 1364 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); 1365 mlx5_fw_tracer_destroy(dev->tracer); 1366 dev->tracer = NULL; 1367 } 1368 1369 mlx5_fw_reset_events_start(dev); 1370 mlx5_hv_vhca_init(dev->hv_vhca); 1371 1372 err = mlx5_rsc_dump_init(dev); 1373 if (err) { 1374 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err); 1375 mlx5_rsc_dump_destroy(dev); 1376 dev->rsc_dump = NULL; 1377 } 1378 1379 err = mlx5_fpga_device_start(dev); 1380 if (err) { 1381 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1382 goto err_fpga_start; 1383 } 1384 1385 err = mlx5_fs_core_init(dev); 1386 if (err) { 1387 mlx5_core_err(dev, "Failed to init flow steering\n"); 1388 goto err_fs; 1389 } 1390 1391 err = mlx5_core_set_hca_defaults(dev); 1392 if (err) { 1393 mlx5_core_err(dev, "Failed to set hca defaults\n"); 1394 goto err_set_hca; 1395 } 1396 1397 mlx5_vhca_event_start(dev); 1398 1399 err = mlx5_sf_hw_table_create(dev); 1400 if (err) { 1401 mlx5_core_err(dev, "sf table create failed %d\n", err); 1402 goto err_vhca; 1403 } 1404 1405 err = mlx5_ec_init(dev); 1406 if (err) { 1407 mlx5_core_err(dev, "Failed to init embedded CPU\n"); 1408 goto err_ec; 1409 } 1410 1411 mlx5_lag_add_mdev(dev); 1412 err = mlx5_sriov_attach(dev); 1413 if (err) { 1414 mlx5_core_err(dev, "sriov init failed %d\n", err); 1415 goto err_sriov; 1416 } 1417 1418 mlx5_sf_dev_table_create(dev); 1419 1420 err = mlx5_devlink_traps_register(priv_to_devlink(dev)); 1421 if (err) 1422 goto err_traps_reg; 1423 1424 return 0; 1425 1426 err_traps_reg: 1427 mlx5_sf_dev_table_destroy(dev); 1428 mlx5_sriov_detach(dev); 1429 err_sriov: 1430 mlx5_lag_remove_mdev(dev); 1431 mlx5_ec_cleanup(dev); 1432 err_ec: 1433 mlx5_sf_hw_table_destroy(dev); 1434 err_vhca: 1435 mlx5_vhca_event_stop(dev); 1436 err_set_hca: 1437 mlx5_fs_core_cleanup(dev); 1438 err_fs: 1439 mlx5_fpga_device_stop(dev); 1440 err_fpga_start: 1441 mlx5_rsc_dump_cleanup(dev); 1442 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1443 mlx5_fw_reset_events_stop(dev); 1444 mlx5_fw_tracer_cleanup(dev->tracer); 1445 mlx5_eq_table_destroy(dev); 1446 err_eq_table: 1447 mlx5_irq_table_destroy(dev); 1448 err_irq_table: 1449 mlx5_pagealloc_stop(dev); 1450 mlx5_events_stop(dev); 1451 mlx5_put_uars_page(dev, dev->priv.uar); 1452 return err; 1453 } 1454 1455 static void mlx5_unload(struct mlx5_core_dev *dev) 1456 { 1457 mlx5_eswitch_disable(dev->priv.eswitch); 1458 mlx5_devlink_traps_unregister(priv_to_devlink(dev)); 1459 mlx5_sf_dev_table_destroy(dev); 1460 mlx5_sriov_detach(dev); 1461 mlx5_lag_remove_mdev(dev); 1462 mlx5_ec_cleanup(dev); 1463 mlx5_sf_hw_table_destroy(dev); 1464 mlx5_vhca_event_stop(dev); 1465 mlx5_fs_core_cleanup(dev); 1466 mlx5_fpga_device_stop(dev); 1467 mlx5_rsc_dump_cleanup(dev); 1468 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1469 mlx5_fw_reset_events_stop(dev); 1470 mlx5_fw_tracer_cleanup(dev->tracer); 1471 mlx5_eq_table_destroy(dev); 1472 mlx5_irq_table_destroy(dev); 1473 mlx5_pagealloc_stop(dev); 1474 mlx5_events_stop(dev); 1475 mlx5_put_uars_page(dev, dev->priv.uar); 1476 } 1477 1478 int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev) 1479 { 1480 bool light_probe = mlx5_dev_is_lightweight(dev); 1481 int err = 0; 1482 1483 mutex_lock(&dev->intf_state_mutex); 1484 dev->state = MLX5_DEVICE_STATE_UP; 1485 1486 err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1487 if (err) 1488 goto err_function; 1489 1490 err = mlx5_init_once(dev); 1491 if (err) { 1492 mlx5_core_err(dev, "sw objs init failed\n"); 1493 goto function_teardown; 1494 } 1495 1496 /* In case of light_probe, mlx5_devlink is already registered. 1497 * Hence, don't register devlink again. 1498 */ 1499 if (!light_probe) { 1500 err = mlx5_devlink_params_register(priv_to_devlink(dev)); 1501 if (err) 1502 goto err_devlink_params_reg; 1503 } 1504 1505 err = mlx5_load(dev); 1506 if (err) 1507 goto err_load; 1508 1509 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1510 1511 err = mlx5_register_device(dev); 1512 if (err) 1513 goto err_register; 1514 1515 err = mlx5_crdump_enable(dev); 1516 if (err) 1517 mlx5_core_err(dev, "mlx5_crdump_enable failed with error code %d\n", err); 1518 1519 err = mlx5_hwmon_dev_register(dev); 1520 if (err) 1521 mlx5_core_err(dev, "mlx5_hwmon_dev_register failed with error code %d\n", err); 1522 1523 mutex_unlock(&dev->intf_state_mutex); 1524 return 0; 1525 1526 err_register: 1527 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1528 mlx5_unload(dev); 1529 err_load: 1530 if (!light_probe) 1531 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1532 err_devlink_params_reg: 1533 mlx5_cleanup_once(dev); 1534 function_teardown: 1535 mlx5_function_teardown(dev, true); 1536 err_function: 1537 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1538 mutex_unlock(&dev->intf_state_mutex); 1539 return err; 1540 } 1541 1542 int mlx5_init_one(struct mlx5_core_dev *dev) 1543 { 1544 struct devlink *devlink = priv_to_devlink(dev); 1545 int err; 1546 1547 devl_lock(devlink); 1548 devl_register(devlink); 1549 err = mlx5_init_one_devl_locked(dev); 1550 if (err) 1551 devl_unregister(devlink); 1552 devl_unlock(devlink); 1553 return err; 1554 } 1555 1556 void mlx5_uninit_one(struct mlx5_core_dev *dev) 1557 { 1558 struct devlink *devlink = priv_to_devlink(dev); 1559 1560 devl_lock(devlink); 1561 mutex_lock(&dev->intf_state_mutex); 1562 1563 mlx5_hwmon_dev_unregister(dev); 1564 mlx5_crdump_disable(dev); 1565 mlx5_unregister_device(dev); 1566 1567 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1568 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1569 __func__); 1570 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1571 mlx5_cleanup_once(dev); 1572 goto out; 1573 } 1574 1575 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1576 mlx5_unload(dev); 1577 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1578 mlx5_cleanup_once(dev); 1579 mlx5_function_teardown(dev, true); 1580 out: 1581 mutex_unlock(&dev->intf_state_mutex); 1582 devl_unregister(devlink); 1583 devl_unlock(devlink); 1584 } 1585 1586 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery) 1587 { 1588 int err = 0; 1589 u64 timeout; 1590 1591 devl_assert_locked(priv_to_devlink(dev)); 1592 mutex_lock(&dev->intf_state_mutex); 1593 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1594 mlx5_core_warn(dev, "interface is up, NOP\n"); 1595 goto out; 1596 } 1597 /* remove any previous indication of internal error */ 1598 dev->state = MLX5_DEVICE_STATE_UP; 1599 1600 if (recovery) 1601 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT); 1602 else 1603 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT); 1604 err = mlx5_function_setup(dev, false, timeout); 1605 if (err) 1606 goto err_function; 1607 1608 err = mlx5_load(dev); 1609 if (err) 1610 goto err_load; 1611 1612 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1613 1614 err = mlx5_attach_device(dev); 1615 if (err) 1616 goto err_attach; 1617 1618 mutex_unlock(&dev->intf_state_mutex); 1619 return 0; 1620 1621 err_attach: 1622 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1623 mlx5_unload(dev); 1624 err_load: 1625 mlx5_function_teardown(dev, false); 1626 err_function: 1627 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1628 out: 1629 mutex_unlock(&dev->intf_state_mutex); 1630 return err; 1631 } 1632 1633 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery) 1634 { 1635 struct devlink *devlink = priv_to_devlink(dev); 1636 int ret; 1637 1638 devl_lock(devlink); 1639 ret = mlx5_load_one_devl_locked(dev, recovery); 1640 devl_unlock(devlink); 1641 return ret; 1642 } 1643 1644 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend) 1645 { 1646 devl_assert_locked(priv_to_devlink(dev)); 1647 mutex_lock(&dev->intf_state_mutex); 1648 1649 mlx5_detach_device(dev, suspend); 1650 1651 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1652 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1653 __func__); 1654 goto out; 1655 } 1656 1657 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1658 mlx5_unload(dev); 1659 mlx5_function_teardown(dev, false); 1660 out: 1661 mutex_unlock(&dev->intf_state_mutex); 1662 } 1663 1664 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend) 1665 { 1666 struct devlink *devlink = priv_to_devlink(dev); 1667 1668 devl_lock(devlink); 1669 mlx5_unload_one_devl_locked(dev, suspend); 1670 devl_unlock(devlink); 1671 } 1672 1673 /* In case of light probe, we don't need a full query of hca_caps, but only the bellow caps. 1674 * A full query of hca_caps will be done when the device will reload. 1675 */ 1676 static int mlx5_query_hca_caps_light(struct mlx5_core_dev *dev) 1677 { 1678 int err; 1679 1680 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 1681 if (err) 1682 return err; 1683 1684 if (MLX5_CAP_GEN(dev, eth_net_offloads)) { 1685 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS, 1686 HCA_CAP_OPMOD_GET_CUR); 1687 if (err) 1688 return err; 1689 } 1690 1691 if (MLX5_CAP_GEN(dev, nic_flow_table) || 1692 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { 1693 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE, 1694 HCA_CAP_OPMOD_GET_CUR); 1695 if (err) 1696 return err; 1697 } 1698 1699 if (MLX5_CAP_GEN_64(dev, general_obj_types) & 1700 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 1701 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION, 1702 HCA_CAP_OPMOD_GET_CUR); 1703 if (err) 1704 return err; 1705 } 1706 1707 return 0; 1708 } 1709 1710 int mlx5_init_one_light(struct mlx5_core_dev *dev) 1711 { 1712 struct devlink *devlink = priv_to_devlink(dev); 1713 int err; 1714 1715 devl_lock(devlink); 1716 devl_register(devlink); 1717 dev->state = MLX5_DEVICE_STATE_UP; 1718 err = mlx5_function_enable(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1719 if (err) { 1720 mlx5_core_warn(dev, "mlx5_function_enable err=%d\n", err); 1721 goto out; 1722 } 1723 1724 err = mlx5_query_hca_caps_light(dev); 1725 if (err) { 1726 mlx5_core_warn(dev, "mlx5_query_hca_caps_light err=%d\n", err); 1727 goto query_hca_caps_err; 1728 } 1729 1730 err = mlx5_devlink_params_register(priv_to_devlink(dev)); 1731 if (err) { 1732 mlx5_core_warn(dev, "mlx5_devlink_param_reg err = %d\n", err); 1733 goto query_hca_caps_err; 1734 } 1735 1736 devl_unlock(devlink); 1737 return 0; 1738 1739 query_hca_caps_err: 1740 mlx5_function_disable(dev, true); 1741 out: 1742 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1743 devl_unregister(devlink); 1744 devl_unlock(devlink); 1745 return err; 1746 } 1747 1748 void mlx5_uninit_one_light(struct mlx5_core_dev *dev) 1749 { 1750 struct devlink *devlink = priv_to_devlink(dev); 1751 1752 devl_lock(devlink); 1753 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1754 devl_unregister(devlink); 1755 devl_unlock(devlink); 1756 if (dev->state != MLX5_DEVICE_STATE_UP) 1757 return; 1758 mlx5_function_disable(dev, true); 1759 } 1760 1761 /* xxx_light() function are used in order to configure the device without full 1762 * init (light init). e.g.: There isn't a point in reload a device to light state. 1763 * Hence, mlx5_load_one_light() isn't needed. 1764 */ 1765 1766 void mlx5_unload_one_light(struct mlx5_core_dev *dev) 1767 { 1768 if (dev->state != MLX5_DEVICE_STATE_UP) 1769 return; 1770 mlx5_function_disable(dev, false); 1771 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1772 } 1773 1774 static const int types[] = { 1775 MLX5_CAP_GENERAL, 1776 MLX5_CAP_GENERAL_2, 1777 MLX5_CAP_ETHERNET_OFFLOADS, 1778 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1779 MLX5_CAP_ODP, 1780 MLX5_CAP_ATOMIC, 1781 MLX5_CAP_ROCE, 1782 MLX5_CAP_IPOIB_OFFLOADS, 1783 MLX5_CAP_FLOW_TABLE, 1784 MLX5_CAP_ESWITCH_FLOW_TABLE, 1785 MLX5_CAP_ESWITCH, 1786 MLX5_CAP_QOS, 1787 MLX5_CAP_DEBUG, 1788 MLX5_CAP_DEV_MEM, 1789 MLX5_CAP_DEV_EVENT, 1790 MLX5_CAP_TLS, 1791 MLX5_CAP_VDPA_EMULATION, 1792 MLX5_CAP_IPSEC, 1793 MLX5_CAP_PORT_SELECTION, 1794 MLX5_CAP_MACSEC, 1795 MLX5_CAP_ADV_VIRTUALIZATION, 1796 MLX5_CAP_CRYPTO, 1797 MLX5_CAP_SHAMPO, 1798 }; 1799 1800 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 1801 { 1802 int type; 1803 int i; 1804 1805 for (i = 0; i < ARRAY_SIZE(types); i++) { 1806 type = types[i]; 1807 kfree(dev->caps.hca[type]); 1808 } 1809 } 1810 1811 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 1812 { 1813 struct mlx5_hca_cap *cap; 1814 int type; 1815 int i; 1816 1817 for (i = 0; i < ARRAY_SIZE(types); i++) { 1818 cap = kzalloc(sizeof(*cap), GFP_KERNEL); 1819 if (!cap) 1820 goto err; 1821 type = types[i]; 1822 dev->caps.hca[type] = cap; 1823 } 1824 1825 return 0; 1826 1827 err: 1828 mlx5_hca_caps_free(dev); 1829 return -ENOMEM; 1830 } 1831 1832 static int vhca_id_show(struct seq_file *file, void *priv) 1833 { 1834 struct mlx5_core_dev *dev = file->private; 1835 1836 seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id)); 1837 return 0; 1838 } 1839 1840 DEFINE_SHOW_ATTRIBUTE(vhca_id); 1841 1842 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 1843 { 1844 struct mlx5_priv *priv = &dev->priv; 1845 int err; 1846 1847 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1848 lockdep_register_key(&dev->lock_key); 1849 mutex_init(&dev->intf_state_mutex); 1850 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key); 1851 mutex_init(&dev->mlx5e_res.uplink_netdev_lock); 1852 mutex_init(&dev->wc_state_lock); 1853 1854 mutex_init(&priv->bfregs.reg_head.lock); 1855 mutex_init(&priv->bfregs.wc_head.lock); 1856 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1857 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1858 1859 mutex_init(&priv->alloc_mutex); 1860 mutex_init(&priv->pgdir_mutex); 1861 INIT_LIST_HEAD(&priv->pgdir_list); 1862 1863 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 1864 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device), 1865 mlx5_debugfs_root); 1866 debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops); 1867 INIT_LIST_HEAD(&priv->traps); 1868 1869 err = mlx5_cmd_init(dev); 1870 if (err) { 1871 mlx5_core_err(dev, "Failed initializing cmdif SW structs, aborting\n"); 1872 goto err_cmd_init; 1873 } 1874 1875 err = mlx5_tout_init(dev); 1876 if (err) { 1877 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n"); 1878 goto err_timeout_init; 1879 } 1880 1881 err = mlx5_health_init(dev); 1882 if (err) 1883 goto err_health_init; 1884 1885 err = mlx5_pagealloc_init(dev); 1886 if (err) 1887 goto err_pagealloc_init; 1888 1889 err = mlx5_adev_init(dev); 1890 if (err) 1891 goto err_adev_init; 1892 1893 err = mlx5_hca_caps_alloc(dev); 1894 if (err) 1895 goto err_hca_caps; 1896 1897 /* The conjunction of sw_vhca_id with sw_owner_id will be a global 1898 * unique id per function which uses mlx5_core. 1899 * Those values are supplied to FW as part of the init HCA command to 1900 * be used by both driver and FW when it's applicable. 1901 */ 1902 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1, 1903 MAX_SW_VHCA_ID, 1904 GFP_KERNEL); 1905 if (dev->priv.sw_vhca_id < 0) 1906 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n", 1907 dev->priv.sw_vhca_id); 1908 1909 return 0; 1910 1911 err_hca_caps: 1912 mlx5_adev_cleanup(dev); 1913 err_adev_init: 1914 mlx5_pagealloc_cleanup(dev); 1915 err_pagealloc_init: 1916 mlx5_health_cleanup(dev); 1917 err_health_init: 1918 mlx5_tout_cleanup(dev); 1919 err_timeout_init: 1920 mlx5_cmd_cleanup(dev); 1921 err_cmd_init: 1922 debugfs_remove(dev->priv.dbg.dbg_root); 1923 mutex_destroy(&priv->pgdir_mutex); 1924 mutex_destroy(&priv->alloc_mutex); 1925 mutex_destroy(&priv->bfregs.wc_head.lock); 1926 mutex_destroy(&priv->bfregs.reg_head.lock); 1927 mutex_destroy(&dev->intf_state_mutex); 1928 lockdep_unregister_key(&dev->lock_key); 1929 return err; 1930 } 1931 1932 void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 1933 { 1934 struct mlx5_priv *priv = &dev->priv; 1935 1936 if (priv->sw_vhca_id > 0) 1937 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id); 1938 1939 mlx5_hca_caps_free(dev); 1940 mlx5_adev_cleanup(dev); 1941 mlx5_pagealloc_cleanup(dev); 1942 mlx5_health_cleanup(dev); 1943 mlx5_tout_cleanup(dev); 1944 mlx5_cmd_cleanup(dev); 1945 debugfs_remove_recursive(dev->priv.dbg.dbg_root); 1946 mutex_destroy(&priv->pgdir_mutex); 1947 mutex_destroy(&priv->alloc_mutex); 1948 mutex_destroy(&priv->bfregs.wc_head.lock); 1949 mutex_destroy(&priv->bfregs.reg_head.lock); 1950 mutex_destroy(&dev->wc_state_lock); 1951 mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock); 1952 mutex_destroy(&dev->intf_state_mutex); 1953 lockdep_unregister_key(&dev->lock_key); 1954 } 1955 1956 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 1957 { 1958 struct mlx5_core_dev *dev; 1959 struct devlink *devlink; 1960 int err; 1961 1962 devlink = mlx5_devlink_alloc(&pdev->dev); 1963 if (!devlink) { 1964 dev_err(&pdev->dev, "devlink alloc failed\n"); 1965 return -ENOMEM; 1966 } 1967 1968 dev = devlink_priv(devlink); 1969 dev->device = &pdev->dev; 1970 dev->pdev = pdev; 1971 1972 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1973 MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1974 1975 dev->priv.adev_idx = mlx5_adev_idx_alloc(); 1976 if (dev->priv.adev_idx < 0) { 1977 err = dev->priv.adev_idx; 1978 goto adev_init_err; 1979 } 1980 1981 err = mlx5_mdev_init(dev, prof_sel); 1982 if (err) 1983 goto mdev_init_err; 1984 1985 err = mlx5_pci_init(dev, pdev, id); 1986 if (err) { 1987 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 1988 err); 1989 goto pci_init_err; 1990 } 1991 1992 err = mlx5_init_one(dev); 1993 if (err) { 1994 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 1995 err); 1996 goto err_init_one; 1997 } 1998 1999 pci_save_state(pdev); 2000 return 0; 2001 2002 err_init_one: 2003 mlx5_pci_close(dev); 2004 pci_init_err: 2005 mlx5_mdev_uninit(dev); 2006 mdev_init_err: 2007 mlx5_adev_idx_free(dev->priv.adev_idx); 2008 adev_init_err: 2009 mlx5_devlink_free(devlink); 2010 2011 return err; 2012 } 2013 2014 static void remove_one(struct pci_dev *pdev) 2015 { 2016 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2017 struct devlink *devlink = priv_to_devlink(dev); 2018 2019 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 2020 mlx5_drain_fw_reset(dev); 2021 mlx5_drain_health_wq(dev); 2022 mlx5_sriov_disable(pdev, false); 2023 mlx5_uninit_one(dev); 2024 mlx5_pci_close(dev); 2025 mlx5_mdev_uninit(dev); 2026 mlx5_adev_idx_free(dev->priv.adev_idx); 2027 mlx5_devlink_free(devlink); 2028 } 2029 2030 #define mlx5_pci_trace(dev, fmt, ...) ({ \ 2031 struct mlx5_core_dev *__dev = (dev); \ 2032 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \ 2033 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \ 2034 __dev->pci_status, ##__VA_ARGS__); \ 2035 }) 2036 2037 static const char *result2str(enum pci_ers_result result) 2038 { 2039 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" : 2040 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" : 2041 result == PCI_ERS_RESULT_RECOVERED ? "recovered" : 2042 "unknown"; 2043 } 2044 2045 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 2046 pci_channel_state_t state) 2047 { 2048 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2049 enum pci_ers_result res; 2050 2051 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state); 2052 2053 mlx5_enter_error_state(dev, false); 2054 mlx5_error_sw_reset(dev); 2055 mlx5_unload_one(dev, false); 2056 mlx5_drain_health_wq(dev); 2057 mlx5_pci_disable_device(dev); 2058 2059 res = state == pci_channel_io_perm_failure ? 2060 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 2061 2062 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n", 2063 __func__, dev->state, dev->pci_status, res, result2str(res)); 2064 return res; 2065 } 2066 2067 /* wait for the device to show vital signs by waiting 2068 * for the health counter to start counting. 2069 */ 2070 static int wait_vital(struct pci_dev *pdev) 2071 { 2072 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2073 struct mlx5_core_health *health = &dev->priv.health; 2074 const int niter = 100; 2075 u32 last_count = 0; 2076 u32 count; 2077 int i; 2078 2079 for (i = 0; i < niter; i++) { 2080 count = ioread32be(health->health_counter); 2081 if (count && count != 0xffffffff) { 2082 if (last_count && last_count != count) { 2083 mlx5_core_info(dev, 2084 "wait vital counter value 0x%x after %d iterations\n", 2085 count, i); 2086 return 0; 2087 } 2088 last_count = count; 2089 } 2090 msleep(50); 2091 } 2092 2093 return -ETIMEDOUT; 2094 } 2095 2096 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 2097 { 2098 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT; 2099 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2100 int err; 2101 2102 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n", 2103 __func__, dev->state, dev->pci_status); 2104 2105 err = mlx5_pci_enable_device(dev); 2106 if (err) { 2107 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 2108 __func__, err); 2109 goto out; 2110 } 2111 2112 pci_set_master(pdev); 2113 pci_restore_state(pdev); 2114 pci_save_state(pdev); 2115 2116 err = wait_vital(pdev); 2117 if (err) { 2118 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n", 2119 __func__, err); 2120 goto out; 2121 } 2122 2123 res = PCI_ERS_RESULT_RECOVERED; 2124 out: 2125 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n", 2126 __func__, dev->state, dev->pci_status, err, res, result2str(res)); 2127 return res; 2128 } 2129 2130 static void mlx5_pci_resume(struct pci_dev *pdev) 2131 { 2132 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2133 int err; 2134 2135 mlx5_pci_trace(dev, "Enter, loading driver..\n"); 2136 2137 err = mlx5_load_one(dev, false); 2138 2139 if (!err) 2140 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter, 2141 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY); 2142 2143 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err, 2144 !err ? "recovered" : "Failed"); 2145 } 2146 2147 static const struct pci_error_handlers mlx5_err_handler = { 2148 .error_detected = mlx5_pci_err_detected, 2149 .slot_reset = mlx5_pci_slot_reset, 2150 .resume = mlx5_pci_resume 2151 }; 2152 2153 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 2154 { 2155 bool fast_teardown = false, force_teardown = false; 2156 int ret = 1; 2157 2158 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 2159 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 2160 2161 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 2162 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 2163 2164 if (!fast_teardown && !force_teardown) 2165 return -EOPNOTSUPP; 2166 2167 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 2168 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 2169 return -EAGAIN; 2170 } 2171 2172 /* Panic tear down fw command will stop the PCI bus communication 2173 * with the HCA, so the health poll is no longer needed. 2174 */ 2175 mlx5_stop_health_poll(dev, false); 2176 2177 ret = mlx5_cmd_fast_teardown_hca(dev); 2178 if (!ret) 2179 goto succeed; 2180 2181 ret = mlx5_cmd_force_teardown_hca(dev); 2182 if (!ret) 2183 goto succeed; 2184 2185 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 2186 mlx5_start_health_poll(dev); 2187 return ret; 2188 2189 succeed: 2190 mlx5_enter_error_state(dev, true); 2191 2192 /* Some platforms requiring freeing the IRQ's in the shutdown 2193 * flow. If they aren't freed they can't be allocated after 2194 * kexec. There is no need to cleanup the mlx5_core software 2195 * contexts. 2196 */ 2197 mlx5_core_eq_free_irqs(dev); 2198 2199 return 0; 2200 } 2201 2202 static void shutdown(struct pci_dev *pdev) 2203 { 2204 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2205 int err; 2206 2207 mlx5_core_info(dev, "Shutdown was called\n"); 2208 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 2209 mlx5_drain_health_wq(dev); 2210 err = mlx5_try_fast_unload(dev); 2211 if (err) 2212 mlx5_unload_one(dev, false); 2213 mlx5_pci_disable_device(dev); 2214 } 2215 2216 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 2217 { 2218 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2219 2220 mlx5_unload_one(dev, true); 2221 2222 return 0; 2223 } 2224 2225 static int mlx5_resume(struct pci_dev *pdev) 2226 { 2227 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2228 2229 return mlx5_load_one(dev, false); 2230 } 2231 2232 static const struct pci_device_id mlx5_core_pci_table[] = { 2233 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 2234 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 2235 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 2236 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 2237 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 2238 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 2239 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 2240 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 2241 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 2242 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 2243 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 2244 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 2245 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 2246 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 2247 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 2248 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 2249 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */ 2250 { PCI_VDEVICE(MELLANOX, 0x1025) }, /* ConnectX-9 */ 2251 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 2252 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 2253 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 2254 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 2255 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ 2256 { 0, } 2257 }; 2258 2259 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 2260 2261 void mlx5_disable_device(struct mlx5_core_dev *dev) 2262 { 2263 mlx5_error_sw_reset(dev); 2264 mlx5_unload_one_devl_locked(dev, false); 2265 } 2266 2267 int mlx5_recover_device(struct mlx5_core_dev *dev) 2268 { 2269 if (!mlx5_core_is_sf(dev)) { 2270 mlx5_pci_disable_device(dev); 2271 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED) 2272 return -EIO; 2273 } 2274 2275 return mlx5_load_one_devl_locked(dev, true); 2276 } 2277 2278 static struct pci_driver mlx5_core_driver = { 2279 .name = KBUILD_MODNAME, 2280 .id_table = mlx5_core_pci_table, 2281 .probe = probe_one, 2282 .remove = remove_one, 2283 .suspend = mlx5_suspend, 2284 .resume = mlx5_resume, 2285 .shutdown = shutdown, 2286 .err_handler = &mlx5_err_handler, 2287 .sriov_configure = mlx5_core_sriov_configure, 2288 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 2289 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 2290 }; 2291 2292 /** 2293 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if 2294 * mlx5_core is its driver. 2295 * @pdev: The associated PCI device. 2296 * 2297 * Upon return the interface state lock stay held to let caller uses it safely. 2298 * Caller must ensure to use the returned mlx5 device for a narrow window 2299 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over. 2300 * 2301 * Return: Pointer to the associated mlx5_core_dev or NULL. 2302 */ 2303 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev) 2304 { 2305 struct mlx5_core_dev *mdev; 2306 2307 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver); 2308 if (IS_ERR(mdev)) 2309 return NULL; 2310 2311 mutex_lock(&mdev->intf_state_mutex); 2312 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) { 2313 mutex_unlock(&mdev->intf_state_mutex); 2314 return NULL; 2315 } 2316 2317 return mdev; 2318 } 2319 EXPORT_SYMBOL(mlx5_vf_get_core_dev); 2320 2321 /** 2322 * mlx5_vf_put_core_dev - Put the mlx5 core device back. 2323 * @mdev: The mlx5 core device. 2324 * 2325 * Upon return the interface state lock is unlocked and caller should not 2326 * access the mdev any more. 2327 */ 2328 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev) 2329 { 2330 mutex_unlock(&mdev->intf_state_mutex); 2331 } 2332 EXPORT_SYMBOL(mlx5_vf_put_core_dev); 2333 2334 static void mlx5_core_verify_params(void) 2335 { 2336 if (prof_sel >= ARRAY_SIZE(profile)) { 2337 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 2338 prof_sel, 2339 ARRAY_SIZE(profile) - 1, 2340 MLX5_DEFAULT_PROF); 2341 prof_sel = MLX5_DEFAULT_PROF; 2342 } 2343 } 2344 2345 static int __init mlx5_init(void) 2346 { 2347 int err; 2348 2349 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 2350 "mlx5_core name not in sync with kernel module name"); 2351 2352 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 2353 2354 mlx5_core_verify_params(); 2355 mlx5_register_debugfs(); 2356 2357 err = mlx5e_init(); 2358 if (err) 2359 goto err_debug; 2360 2361 err = mlx5_sf_driver_register(); 2362 if (err) 2363 goto err_sf; 2364 2365 err = pci_register_driver(&mlx5_core_driver); 2366 if (err) 2367 goto err_pci; 2368 2369 return 0; 2370 2371 err_pci: 2372 mlx5_sf_driver_unregister(); 2373 err_sf: 2374 mlx5e_cleanup(); 2375 err_debug: 2376 mlx5_unregister_debugfs(); 2377 return err; 2378 } 2379 2380 static void __exit mlx5_cleanup(void) 2381 { 2382 pci_unregister_driver(&mlx5_core_driver); 2383 mlx5_sf_driver_unregister(); 2384 mlx5e_cleanup(); 2385 mlx5_unregister_debugfs(); 2386 } 2387 2388 module_init(mlx5_init); 2389 module_exit(mlx5_cleanup); 2390