1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/mlx5/driver.h> 34 #include <linux/mlx5/eswitch.h> 35 #include "mlx5_core.h" 36 #include "../../mlxfw/mlxfw.h" 37 #include "lib/tout.h" 38 39 enum { 40 MCQS_IDENTIFIER_BOOT_IMG = 0x1, 41 MCQS_IDENTIFIER_OEM_NVCONFIG = 0x4, 42 MCQS_IDENTIFIER_MLNX_NVCONFIG = 0x5, 43 MCQS_IDENTIFIER_CS_TOKEN = 0x6, 44 MCQS_IDENTIFIER_DBG_TOKEN = 0x7, 45 MCQS_IDENTIFIER_GEARBOX = 0xA, 46 }; 47 48 enum { 49 MCQS_UPDATE_STATE_IDLE, 50 MCQS_UPDATE_STATE_IN_PROGRESS, 51 MCQS_UPDATE_STATE_APPLIED, 52 MCQS_UPDATE_STATE_ACTIVE, 53 MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET, 54 MCQS_UPDATE_STATE_FAILED, 55 MCQS_UPDATE_STATE_CANCELED, 56 MCQS_UPDATE_STATE_BUSY, 57 }; 58 59 enum { 60 MCQI_INFO_TYPE_CAPABILITIES = 0x0, 61 MCQI_INFO_TYPE_VERSION = 0x1, 62 MCQI_INFO_TYPE_ACTIVATION_METHOD = 0x5, 63 }; 64 65 enum { 66 MCQI_FW_RUNNING_VERSION = 0, 67 MCQI_FW_STORED_VERSION = 1, 68 }; 69 70 int mlx5_query_board_id(struct mlx5_core_dev *dev) 71 { 72 u32 *out; 73 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out); 74 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {}; 75 int err; 76 77 out = kzalloc(outlen, GFP_KERNEL); 78 if (!out) 79 return -ENOMEM; 80 81 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER); 82 err = mlx5_cmd_exec_inout(dev, query_adapter, in, out); 83 if (err) 84 goto out; 85 86 memcpy(dev->board_id, 87 MLX5_ADDR_OF(query_adapter_out, out, 88 query_adapter_struct.vsd_contd_psid), 89 MLX5_FLD_SZ_BYTES(query_adapter_out, 90 query_adapter_struct.vsd_contd_psid)); 91 92 out: 93 kfree(out); 94 return err; 95 } 96 97 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id) 98 { 99 u32 *out; 100 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out); 101 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {}; 102 int err; 103 104 out = kzalloc(outlen, GFP_KERNEL); 105 if (!out) 106 return -ENOMEM; 107 108 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER); 109 err = mlx5_cmd_exec_inout(mdev, query_adapter, in, out); 110 if (err) 111 goto out; 112 113 *vendor_id = MLX5_GET(query_adapter_out, out, 114 query_adapter_struct.ieee_vendor_id); 115 out: 116 kfree(out); 117 return err; 118 } 119 EXPORT_SYMBOL(mlx5_core_query_vendor_id); 120 121 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev) 122 { 123 return mlx5_query_pcam_reg(dev, dev->caps.pcam, 124 MLX5_PCAM_FEATURE_ENHANCED_FEATURES, 125 MLX5_PCAM_REGS_5000_TO_507F); 126 } 127 128 static int mlx5_get_mcam_access_reg_group(struct mlx5_core_dev *dev, 129 enum mlx5_mcam_reg_groups group) 130 { 131 return mlx5_query_mcam_reg(dev, dev->caps.mcam[group], 132 MLX5_MCAM_FEATURE_ENHANCED_FEATURES, group); 133 } 134 135 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev) 136 { 137 return mlx5_query_qcam_reg(dev, dev->caps.qcam, 138 MLX5_QCAM_FEATURE_ENHANCED_FEATURES, 139 MLX5_QCAM_REGS_FIRST_128); 140 } 141 142 int mlx5_query_hca_caps(struct mlx5_core_dev *dev) 143 { 144 int err; 145 146 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR); 147 if (err) 148 return err; 149 150 if (MLX5_CAP_GEN(dev, port_selection_cap)) { 151 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_PORT_SELECTION, HCA_CAP_OPMOD_GET_CUR); 152 if (err) 153 return err; 154 } 155 156 if (MLX5_CAP_GEN(dev, hca_cap_2)) { 157 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_GENERAL_2, HCA_CAP_OPMOD_GET_CUR); 158 if (err) 159 return err; 160 } 161 162 if (MLX5_CAP_GEN(dev, eth_net_offloads)) { 163 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS, 164 HCA_CAP_OPMOD_GET_CUR); 165 if (err) 166 return err; 167 } 168 169 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { 170 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 171 HCA_CAP_OPMOD_GET_CUR); 172 if (err) 173 return err; 174 } 175 176 if (MLX5_CAP_GEN(dev, pg)) { 177 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ODP, HCA_CAP_OPMOD_GET_CUR); 178 if (err) 179 return err; 180 } 181 182 if (MLX5_CAP_GEN(dev, atomic)) { 183 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ATOMIC, HCA_CAP_OPMOD_GET_CUR); 184 if (err) 185 return err; 186 } 187 188 if (MLX5_CAP_GEN(dev, roce)) { 189 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ROCE, HCA_CAP_OPMOD_GET_CUR); 190 if (err) 191 return err; 192 } 193 194 if (MLX5_CAP_GEN(dev, nic_flow_table) || 195 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { 196 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE, HCA_CAP_OPMOD_GET_CUR); 197 if (err) 198 return err; 199 } 200 201 if (MLX5_ESWITCH_MANAGER(dev)) { 202 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ESWITCH_FLOW_TABLE, 203 HCA_CAP_OPMOD_GET_CUR); 204 if (err) 205 return err; 206 207 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ESWITCH, HCA_CAP_OPMOD_GET_CUR); 208 if (err) 209 return err; 210 } 211 212 if (MLX5_CAP_GEN(dev, qos)) { 213 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_QOS, HCA_CAP_OPMOD_GET_CUR); 214 if (err) 215 return err; 216 } 217 218 if (MLX5_CAP_GEN(dev, debug)) 219 mlx5_core_get_caps_mode(dev, MLX5_CAP_DEBUG, HCA_CAP_OPMOD_GET_CUR); 220 221 if (MLX5_CAP_GEN(dev, pcam_reg)) 222 mlx5_get_pcam_reg(dev); 223 224 if (MLX5_CAP_GEN(dev, mcam_reg)) { 225 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128); 226 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F); 227 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9180_0x91FF); 228 } 229 230 if (MLX5_CAP_GEN(dev, qcam_reg)) 231 mlx5_get_qcam_reg(dev); 232 233 if (MLX5_CAP_GEN(dev, device_memory)) { 234 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_DEV_MEM, HCA_CAP_OPMOD_GET_CUR); 235 if (err) 236 return err; 237 } 238 239 if (MLX5_CAP_GEN(dev, event_cap)) { 240 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_DEV_EVENT, HCA_CAP_OPMOD_GET_CUR); 241 if (err) 242 return err; 243 } 244 245 if (MLX5_CAP_GEN(dev, tls_tx) || MLX5_CAP_GEN(dev, tls_rx)) { 246 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_TLS, HCA_CAP_OPMOD_GET_CUR); 247 if (err) 248 return err; 249 } 250 251 if (MLX5_CAP_GEN_64(dev, general_obj_types) & 252 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 253 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION, HCA_CAP_OPMOD_GET_CUR); 254 if (err) 255 return err; 256 } 257 258 if (MLX5_CAP_GEN(dev, ipsec_offload)) { 259 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_IPSEC, HCA_CAP_OPMOD_GET_CUR); 260 if (err) 261 return err; 262 } 263 264 if (MLX5_CAP_GEN(dev, crypto)) { 265 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_CRYPTO, HCA_CAP_OPMOD_GET_CUR); 266 if (err) 267 return err; 268 } 269 270 if (MLX5_CAP_GEN_64(dev, general_obj_types) & 271 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD) { 272 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_MACSEC, HCA_CAP_OPMOD_GET_CUR); 273 if (err) 274 return err; 275 } 276 277 if (MLX5_CAP_GEN(dev, adv_virtualization)) { 278 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ADV_VIRTUALIZATION, 279 HCA_CAP_OPMOD_GET_CUR); 280 if (err) 281 return err; 282 } 283 284 if (MLX5_CAP_GEN(dev, shampo)) { 285 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_SHAMPO, HCA_CAP_OPMOD_GET_CUR); 286 if (err) 287 return err; 288 } 289 290 return 0; 291 } 292 293 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, u32 *sw_owner_id) 294 { 295 u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {}; 296 int i; 297 298 MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA); 299 300 if (MLX5_CAP_GEN(dev, sw_owner_id)) { 301 for (i = 0; i < 4; i++) 302 MLX5_ARRAY_SET(init_hca_in, in, sw_owner_id, i, 303 sw_owner_id[i]); 304 } 305 306 if (MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) && 307 dev->priv.sw_vhca_id > 0) 308 MLX5_SET(init_hca_in, in, sw_vhca_id, dev->priv.sw_vhca_id); 309 310 return mlx5_cmd_exec_in(dev, init_hca, in); 311 } 312 313 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev) 314 { 315 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {}; 316 317 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA); 318 return mlx5_cmd_exec_in(dev, teardown_hca, in); 319 } 320 321 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev) 322 { 323 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; 324 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; 325 int force_state; 326 int ret; 327 328 if (!MLX5_CAP_GEN(dev, force_teardown)) { 329 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n"); 330 return -EOPNOTSUPP; 331 } 332 333 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA); 334 MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE); 335 336 ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out)); 337 if (ret) 338 return ret; 339 340 force_state = MLX5_GET(teardown_hca_out, out, state); 341 if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) { 342 mlx5_core_warn(dev, "teardown with force mode failed, doing normal teardown\n"); 343 return -EIO; 344 } 345 346 return 0; 347 } 348 349 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev) 350 { 351 unsigned long end, delay_ms = mlx5_tout_ms(dev, TEARDOWN); 352 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {}; 353 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {}; 354 int state; 355 int ret; 356 357 if (!MLX5_CAP_GEN(dev, fast_teardown)) { 358 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n"); 359 return -EOPNOTSUPP; 360 } 361 362 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA); 363 MLX5_SET(teardown_hca_in, in, profile, 364 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN); 365 366 ret = mlx5_cmd_exec_inout(dev, teardown_hca, in, out); 367 if (ret) 368 return ret; 369 370 state = MLX5_GET(teardown_hca_out, out, state); 371 if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) { 372 mlx5_core_warn(dev, "teardown with fast mode failed\n"); 373 return -EIO; 374 } 375 376 mlx5_set_nic_state(dev, MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED); 377 378 /* Loop until device state turns to disable */ 379 end = jiffies + msecs_to_jiffies(delay_ms); 380 do { 381 if (mlx5_get_nic_state(dev) == MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED) 382 break; 383 if (pci_channel_offline(dev->pdev)) { 384 mlx5_core_err(dev, "PCI channel offline, stop waiting for NIC IFC\n"); 385 return -EACCES; 386 } 387 388 cond_resched(); 389 } while (!time_after(jiffies, end)); 390 391 if (mlx5_get_nic_state(dev) != MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED) { 392 dev_err(&dev->pdev->dev, "NIC IFC still %d after %lums.\n", 393 mlx5_get_nic_state(dev), delay_ms); 394 return -EIO; 395 } 396 397 return 0; 398 } 399 400 enum mlxsw_reg_mcc_instruction { 401 MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 402 MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 403 MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 404 MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 405 MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 406 MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08, 407 }; 408 409 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev, 410 enum mlxsw_reg_mcc_instruction instr, 411 u16 component_index, u32 update_handle, 412 u32 component_size) 413 { 414 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; 415 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; 416 417 memset(in, 0, sizeof(in)); 418 419 MLX5_SET(mcc_reg, in, instruction, instr); 420 MLX5_SET(mcc_reg, in, component_index, component_index); 421 MLX5_SET(mcc_reg, in, update_handle, update_handle); 422 MLX5_SET(mcc_reg, in, component_size, component_size); 423 424 return mlx5_core_access_reg(dev, in, sizeof(in), out, 425 sizeof(out), MLX5_REG_MCC, 0, 1); 426 } 427 428 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev, 429 u32 *update_handle, u8 *error_code, 430 u8 *control_state) 431 { 432 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; 433 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; 434 int err; 435 436 memset(in, 0, sizeof(in)); 437 memset(out, 0, sizeof(out)); 438 MLX5_SET(mcc_reg, in, update_handle, *update_handle); 439 440 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 441 sizeof(out), MLX5_REG_MCC, 0, 0); 442 if (err) 443 goto out; 444 445 *update_handle = MLX5_GET(mcc_reg, out, update_handle); 446 *error_code = MLX5_GET(mcc_reg, out, error_code); 447 *control_state = MLX5_GET(mcc_reg, out, control_state); 448 449 out: 450 return err; 451 } 452 453 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev, 454 u32 update_handle, 455 u32 offset, u16 size, 456 u8 *data) 457 { 458 int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size; 459 u32 out[MLX5_ST_SZ_DW(mcda_reg)]; 460 int i, j, dw_size = size >> 2; 461 __be32 data_element; 462 u32 *in; 463 464 in = kzalloc(in_size, GFP_KERNEL); 465 if (!in) 466 return -ENOMEM; 467 468 MLX5_SET(mcda_reg, in, update_handle, update_handle); 469 MLX5_SET(mcda_reg, in, offset, offset); 470 MLX5_SET(mcda_reg, in, size, size); 471 472 for (i = 0; i < dw_size; i++) { 473 j = i * 4; 474 data_element = htonl(*(u32 *)&data[j]); 475 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4); 476 } 477 478 err = mlx5_core_access_reg(dev, in, in_size, out, 479 sizeof(out), MLX5_REG_MCDA, 0, 1); 480 kfree(in); 481 return err; 482 } 483 484 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev, 485 u16 component_index, bool read_pending, 486 u8 info_type, u16 data_size, void *mcqi_data) 487 { 488 u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_UN_SZ_DW(mcqi_reg_data)] = {}; 489 u32 in[MLX5_ST_SZ_DW(mcqi_reg)] = {}; 490 void *data; 491 int err; 492 493 MLX5_SET(mcqi_reg, in, component_index, component_index); 494 MLX5_SET(mcqi_reg, in, read_pending_component, read_pending); 495 MLX5_SET(mcqi_reg, in, info_type, info_type); 496 MLX5_SET(mcqi_reg, in, data_size, data_size); 497 498 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 499 MLX5_ST_SZ_BYTES(mcqi_reg) + data_size, 500 MLX5_REG_MCQI, 0, 0); 501 if (err) 502 return err; 503 504 data = MLX5_ADDR_OF(mcqi_reg, out, data); 505 memcpy(mcqi_data, data, data_size); 506 507 return 0; 508 } 509 510 static int mlx5_reg_mcqi_caps_query(struct mlx5_core_dev *dev, u16 component_index, 511 u32 *max_component_size, u8 *log_mcda_word_size, 512 u16 *mcda_max_write_size) 513 { 514 u32 mcqi_reg[MLX5_ST_SZ_DW(mcqi_cap)] = {}; 515 int err; 516 517 err = mlx5_reg_mcqi_query(dev, component_index, 0, 518 MCQI_INFO_TYPE_CAPABILITIES, 519 MLX5_ST_SZ_BYTES(mcqi_cap), mcqi_reg); 520 if (err) 521 return err; 522 523 *max_component_size = MLX5_GET(mcqi_cap, mcqi_reg, max_component_size); 524 *log_mcda_word_size = MLX5_GET(mcqi_cap, mcqi_reg, log_mcda_word_size); 525 *mcda_max_write_size = MLX5_GET(mcqi_cap, mcqi_reg, mcda_max_write_size); 526 527 return 0; 528 } 529 530 struct mlx5_mlxfw_dev { 531 struct mlxfw_dev mlxfw_dev; 532 struct mlx5_core_dev *mlx5_core_dev; 533 }; 534 535 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev, 536 u16 component_index, u32 *p_max_size, 537 u8 *p_align_bits, u16 *p_max_write_size) 538 { 539 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 540 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 541 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 542 543 if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi)) { 544 mlx5_core_warn(dev, "caps query isn't supported by running FW\n"); 545 return -EOPNOTSUPP; 546 } 547 548 return mlx5_reg_mcqi_caps_query(dev, component_index, p_max_size, 549 p_align_bits, p_max_write_size); 550 } 551 552 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 553 { 554 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 555 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 556 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 557 u8 control_state, error_code; 558 int err; 559 560 *fwhandle = 0; 561 err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state); 562 if (err) 563 return err; 564 565 if (control_state != MLXFW_FSM_STATE_IDLE) 566 return -EBUSY; 567 568 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 569 0, *fwhandle, 0); 570 } 571 572 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 573 u16 component_index, u32 component_size) 574 { 575 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 576 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 577 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 578 579 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 580 component_index, fwhandle, component_size); 581 } 582 583 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 584 u8 *data, u16 size, u32 offset) 585 { 586 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 587 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 588 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 589 590 return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data); 591 } 592 593 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 594 u16 component_index) 595 { 596 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 597 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 598 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 599 600 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 601 component_index, fwhandle, 0); 602 } 603 604 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 605 { 606 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 607 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 608 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 609 610 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0, 611 fwhandle, 0); 612 } 613 614 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 615 enum mlxfw_fsm_state *fsm_state, 616 enum mlxfw_fsm_state_err *fsm_state_err) 617 { 618 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 619 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 620 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 621 u8 control_state, error_code; 622 int err; 623 624 err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state); 625 if (err) 626 return err; 627 628 *fsm_state = control_state; 629 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, 630 MLXFW_FSM_STATE_ERR_MAX); 631 return 0; 632 } 633 634 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 635 { 636 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 637 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 638 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 639 640 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0); 641 } 642 643 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 644 { 645 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 646 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 647 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 648 649 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, 650 fwhandle, 0); 651 } 652 653 static int mlx5_fsm_reactivate(struct mlxfw_dev *mlxfw_dev, u8 *status) 654 { 655 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 656 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 657 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 658 u32 out[MLX5_ST_SZ_DW(mirc_reg)]; 659 u32 in[MLX5_ST_SZ_DW(mirc_reg)]; 660 unsigned long exp_time; 661 int err; 662 663 exp_time = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, FSM_REACTIVATE)); 664 665 if (!MLX5_CAP_MCAM_REG2(dev, mirc)) 666 return -EOPNOTSUPP; 667 668 memset(in, 0, sizeof(in)); 669 670 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 671 sizeof(out), MLX5_REG_MIRC, 0, 1); 672 if (err) 673 return err; 674 675 do { 676 memset(out, 0, sizeof(out)); 677 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 678 sizeof(out), MLX5_REG_MIRC, 0, 0); 679 if (err) 680 return err; 681 682 *status = MLX5_GET(mirc_reg, out, status_code); 683 if (*status != MLXFW_FSM_REACTIVATE_STATUS_BUSY) 684 return 0; 685 686 msleep(20); 687 } while (time_before(jiffies, exp_time)); 688 689 return 0; 690 } 691 692 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = { 693 .component_query = mlx5_component_query, 694 .fsm_lock = mlx5_fsm_lock, 695 .fsm_component_update = mlx5_fsm_component_update, 696 .fsm_block_download = mlx5_fsm_block_download, 697 .fsm_component_verify = mlx5_fsm_component_verify, 698 .fsm_activate = mlx5_fsm_activate, 699 .fsm_reactivate = mlx5_fsm_reactivate, 700 .fsm_query_state = mlx5_fsm_query_state, 701 .fsm_cancel = mlx5_fsm_cancel, 702 .fsm_release = mlx5_fsm_release 703 }; 704 705 int mlx5_firmware_flash(struct mlx5_core_dev *dev, 706 const struct firmware *firmware, 707 struct netlink_ext_ack *extack) 708 { 709 struct mlx5_mlxfw_dev mlx5_mlxfw_dev = { 710 .mlxfw_dev = { 711 .ops = &mlx5_mlxfw_dev_ops, 712 .psid = dev->board_id, 713 .psid_size = strlen(dev->board_id), 714 .devlink = priv_to_devlink(dev), 715 }, 716 .mlx5_core_dev = dev 717 }; 718 719 if (!MLX5_CAP_GEN(dev, mcam_reg) || 720 !MLX5_CAP_MCAM_REG(dev, mcqi) || 721 !MLX5_CAP_MCAM_REG(dev, mcc) || 722 !MLX5_CAP_MCAM_REG(dev, mcda)) { 723 pr_info("%s flashing isn't supported by the running FW\n", __func__); 724 return -EOPNOTSUPP; 725 } 726 727 return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev, 728 firmware, extack); 729 } 730 731 static int mlx5_reg_mcqi_version_query(struct mlx5_core_dev *dev, 732 u16 component_index, bool read_pending, 733 u32 *mcqi_version_out) 734 { 735 return mlx5_reg_mcqi_query(dev, component_index, read_pending, 736 MCQI_INFO_TYPE_VERSION, 737 MLX5_ST_SZ_BYTES(mcqi_version), 738 mcqi_version_out); 739 } 740 741 static int mlx5_reg_mcqs_query(struct mlx5_core_dev *dev, u32 *out, 742 u16 component_index) 743 { 744 u8 out_sz = MLX5_ST_SZ_BYTES(mcqs_reg); 745 u32 in[MLX5_ST_SZ_DW(mcqs_reg)] = {}; 746 int err; 747 748 memset(out, 0, out_sz); 749 750 MLX5_SET(mcqs_reg, in, component_index, component_index); 751 752 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 753 out_sz, MLX5_REG_MCQS, 0, 0); 754 return err; 755 } 756 757 /* scans component index sequentially, to find the boot img index */ 758 static int mlx5_get_boot_img_component_index(struct mlx5_core_dev *dev) 759 { 760 u32 out[MLX5_ST_SZ_DW(mcqs_reg)] = {}; 761 u16 identifier, component_idx = 0; 762 bool quit; 763 int err; 764 765 do { 766 err = mlx5_reg_mcqs_query(dev, out, component_idx); 767 if (err) 768 return err; 769 770 identifier = MLX5_GET(mcqs_reg, out, identifier); 771 quit = !!MLX5_GET(mcqs_reg, out, last_index_flag); 772 quit |= identifier == MCQS_IDENTIFIER_BOOT_IMG; 773 } while (!quit && ++component_idx); 774 775 if (identifier != MCQS_IDENTIFIER_BOOT_IMG) { 776 mlx5_core_warn(dev, "mcqs: can't find boot_img component ix, last scanned idx %d\n", 777 component_idx); 778 return -EOPNOTSUPP; 779 } 780 781 return component_idx; 782 } 783 784 static int 785 mlx5_fw_image_pending(struct mlx5_core_dev *dev, 786 int component_index, 787 bool *pending_version_exists) 788 { 789 u32 out[MLX5_ST_SZ_DW(mcqs_reg)]; 790 u8 component_update_state; 791 int err; 792 793 err = mlx5_reg_mcqs_query(dev, out, component_index); 794 if (err) 795 return err; 796 797 component_update_state = MLX5_GET(mcqs_reg, out, component_update_state); 798 799 if (component_update_state == MCQS_UPDATE_STATE_IDLE) { 800 *pending_version_exists = false; 801 } else if (component_update_state == MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET) { 802 *pending_version_exists = true; 803 } else { 804 mlx5_core_warn(dev, 805 "mcqs: can't read pending fw version while fw state is %d\n", 806 component_update_state); 807 return -ENODATA; 808 } 809 return 0; 810 } 811 812 int mlx5_fw_version_query(struct mlx5_core_dev *dev, 813 u32 *running_ver, u32 *pending_ver) 814 { 815 u32 reg_mcqi_version[MLX5_ST_SZ_DW(mcqi_version)] = {}; 816 bool pending_version_exists; 817 int component_index; 818 int err; 819 820 if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi) || 821 !MLX5_CAP_MCAM_REG(dev, mcqs)) { 822 mlx5_core_warn(dev, "fw query isn't supported by the FW\n"); 823 return -EOPNOTSUPP; 824 } 825 826 component_index = mlx5_get_boot_img_component_index(dev); 827 if (component_index < 0) 828 return component_index; 829 830 err = mlx5_reg_mcqi_version_query(dev, component_index, 831 MCQI_FW_RUNNING_VERSION, 832 reg_mcqi_version); 833 if (err) 834 return err; 835 836 *running_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version); 837 838 err = mlx5_fw_image_pending(dev, component_index, &pending_version_exists); 839 if (err) 840 return err; 841 842 if (!pending_version_exists) { 843 *pending_ver = 0; 844 return 0; 845 } 846 847 err = mlx5_reg_mcqi_version_query(dev, component_index, 848 MCQI_FW_STORED_VERSION, 849 reg_mcqi_version); 850 if (err) 851 return err; 852 853 *pending_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version); 854 855 return 0; 856 } 857