1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __MLX5_EN_H__ 33 #define __MLX5_EN_H__ 34 35 #include <linux/if_vlan.h> 36 #include <linux/etherdevice.h> 37 #include <linux/timecounter.h> 38 #include <linux/net_tstamp.h> 39 #include <linux/crash_dump.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/qp.h> 42 #include <linux/mlx5/cq.h> 43 #include <linux/mlx5/port.h> 44 #include <linux/mlx5/vport.h> 45 #include <linux/mlx5/transobj.h> 46 #include <linux/mlx5/fs.h> 47 #include <linux/rhashtable.h> 48 #include <net/udp_tunnel.h> 49 #include <net/switchdev.h> 50 #include <net/xdp.h> 51 #include <linux/dim.h> 52 #include <linux/bits.h> 53 #include "wq.h" 54 #include "mlx5_core.h" 55 #include "en_stats.h" 56 #include "en/dcbnl.h" 57 #include "en/fs.h" 58 #include "en/qos.h" 59 #include "lib/hv_vhca.h" 60 #include "lib/clock.h" 61 #include "en/rx_res.h" 62 #include "en/selq.h" 63 #include "lib/sd.h" 64 65 extern const struct net_device_ops mlx5e_netdev_ops; 66 struct page_pool; 67 68 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) 69 #define MLX5E_METADATA_ETHER_LEN 8 70 71 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 72 73 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) 74 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) 75 76 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE 77 78 #define MLX5_RX_HEADROOM NET_SKB_PAD 79 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ 80 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 81 82 #define MLX5E_RX_MAX_HEAD (256) 83 #define MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE (8) 84 #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9) 85 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE) 86 #define MLX5E_SHAMPO_LOG_WQ_HEADER_PER_PAGE (PAGE_SHIFT - MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE) 87 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64) 88 #define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024) 89 #define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096) 90 91 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ 92 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ 93 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ 94 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) 95 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \ 96 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD)) 97 98 /* Keep in sync with mlx5e_mpwrq_log_wqe_sz. 99 * These are theoretical maximums, which can be further restricted by 100 * capabilities. These values are used for static resource allocations and 101 * sanity checks. 102 * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE 103 * size actually used at runtime, but it's not a problem when calculating static 104 * array sizes. 105 */ 106 #define MLX5_UMR_MAX_FLEX_SPACE \ 107 (ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \ 108 MLX5_UMR_FLEX_ALIGNMENT)) 109 #define MLX5_MPWRQ_MAX_PAGES_PER_WQE \ 110 rounddown_pow_of_two(MLX5_UMR_MAX_FLEX_SPACE / sizeof(struct mlx5_mtt)) 111 112 #define MLX5E_MAX_RQ_NUM_MTTS \ 113 (ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */ 114 #define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */ 115 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) 116 117 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) 118 #define MLX5E_LOG_MAX_RX_WQE_BULK \ 119 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) 120 121 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 122 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 123 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd 124 125 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) 126 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 127 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd 128 129 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 130 131 #define MLX5E_DEFAULT_LRO_TIMEOUT 32 132 #define MLX5E_DEFAULT_SHAMPO_TIMEOUT 1024 133 134 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 135 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 136 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 137 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 138 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 139 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 140 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 141 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 142 143 #define MLX5E_MIN_NUM_CHANNELS 0x1 144 #define MLX5E_MAX_NUM_CHANNELS 256 145 #define MLX5E_TX_CQ_POLL_BUDGET 128 146 #define MLX5E_TX_XSK_POLL_BUDGET 64 147 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ 148 149 #define mlx5e_state_dereference(priv, p) \ 150 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock)) 151 152 enum mlx5e_devcom_events { 153 MPV_DEVCOM_MASTER_UP, 154 MPV_DEVCOM_MASTER_DOWN, 155 MPV_DEVCOM_IPSEC_MASTER_UP, 156 MPV_DEVCOM_IPSEC_MASTER_DOWN, 157 }; 158 159 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev) 160 { 161 if (mlx5_lag_is_lacp_owner(mdev)) 162 return 1; 163 164 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS); 165 } 166 167 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) 168 { 169 switch (wq_type) { 170 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 171 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, 172 wq_size / 2); 173 default: 174 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, 175 wq_size / 2); 176 } 177 } 178 179 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */ 180 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) 181 { 182 return is_kdump_kernel() ? 183 MLX5E_MIN_NUM_CHANNELS : 184 min3(mlx5_comp_vectors_max(mdev), (u32)MLX5E_MAX_NUM_CHANNELS, 185 (u32)(1 << MLX5_CAP_GEN(mdev, log_max_rqt_size))); 186 } 187 188 /* The maximum WQE size can be retrieved by max_wqe_sz_sq in 189 * bytes units. Driver hardens the limitation to 1KB (16 190 * WQEBBs), unless firmware capability is stricter. 191 */ 192 static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev) 193 { 194 BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX); 195 196 return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS, 197 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB); 198 } 199 200 static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev) 201 { 202 /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS. 203 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16, 204 * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64) 205 * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower 206 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be 207 * cache-aligned. 208 */ 209 u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev); 210 211 wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1); 212 #if L1_CACHE_BYTES >= 128 213 wqebbs = ALIGN_DOWN(wqebbs, 2); 214 #endif 215 return wqebbs; 216 } 217 218 struct mlx5e_tx_wqe { 219 struct mlx5_wqe_ctrl_seg ctrl; 220 struct mlx5_wqe_eth_seg eth; 221 struct mlx5_wqe_data_seg data[]; 222 }; 223 224 struct mlx5e_rx_wqe_ll { 225 struct mlx5_wqe_srq_next_seg next; 226 struct mlx5_wqe_data_seg data[]; 227 }; 228 229 struct mlx5e_rx_wqe_cyc { 230 DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data); 231 }; 232 233 struct mlx5e_umr_wqe_hdr { 234 struct mlx5_wqe_ctrl_seg ctrl; 235 struct mlx5_wqe_umr_ctrl_seg uctrl; 236 struct mlx5_mkey_seg mkc; 237 }; 238 239 struct mlx5e_umr_wqe { 240 struct mlx5e_umr_wqe_hdr hdr; 241 union { 242 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts); 243 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms); 244 DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms); 245 }; 246 }; 247 static_assert(offsetof(struct mlx5e_umr_wqe, inline_mtts) == sizeof(struct mlx5e_umr_wqe_hdr), 248 "struct members should be included in struct mlx5e_umr_wqe_hdr, not in struct mlx5e_umr_wqe"); 249 250 enum mlx5e_priv_flag { 251 MLX5E_PFLAG_RX_CQE_BASED_MODER, 252 MLX5E_PFLAG_TX_CQE_BASED_MODER, 253 MLX5E_PFLAG_RX_CQE_COMPRESS, 254 MLX5E_PFLAG_RX_STRIDING_RQ, 255 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, 256 MLX5E_PFLAG_XDP_TX_MPWQE, 257 MLX5E_PFLAG_SKB_TX_MPWQE, 258 MLX5E_PFLAG_TX_PORT_TS, 259 MLX5E_NUM_PFLAGS, /* Keep last */ 260 }; 261 262 #define MLX5E_SET_PFLAG(params, pflag, enable) \ 263 do { \ 264 if (enable) \ 265 (params)->pflags |= BIT(pflag); \ 266 else \ 267 (params)->pflags &= ~(BIT(pflag)); \ 268 } while (0) 269 270 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag)))) 271 272 enum packet_merge { 273 MLX5E_PACKET_MERGE_NONE, 274 MLX5E_PACKET_MERGE_LRO, 275 MLX5E_PACKET_MERGE_SHAMPO, 276 }; 277 278 struct mlx5e_packet_merge_param { 279 enum packet_merge type; 280 u32 timeout; 281 struct { 282 u8 match_criteria_type; 283 u8 alignment_granularity; 284 } shampo; 285 }; 286 287 struct mlx5e_params { 288 u8 log_sq_size; 289 u8 rq_wq_type; 290 u8 log_rq_mtu_frames; 291 u16 num_channels; 292 struct { 293 u16 mode; 294 u8 num_tc; 295 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE]; 296 struct { 297 u64 max_rate[TC_MAX_QUEUE]; 298 u32 hw_id[TC_MAX_QUEUE]; 299 } channel; 300 } mqprio; 301 bool rx_cqe_compress_def; 302 struct dim_cq_moder rx_cq_moderation; 303 struct dim_cq_moder tx_cq_moderation; 304 struct mlx5e_packet_merge_param packet_merge; 305 u8 tx_min_inline_mode; 306 bool vlan_strip_disable; 307 bool scatter_fcs_en; 308 bool rx_dim_enabled; 309 bool tx_dim_enabled; 310 bool rx_moder_use_cqe_mode; 311 bool tx_moder_use_cqe_mode; 312 u32 pflags; 313 struct bpf_prog *xdp_prog; 314 struct mlx5e_xsk *xsk; 315 unsigned int sw_mtu; 316 int hard_mtu; 317 bool ptp_rx; 318 __be32 terminate_lkey_be; 319 }; 320 321 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params) 322 { 323 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ? 324 params->mqprio.num_tc : 1; 325 } 326 327 /* Keep this enum consistent with the corresponding strings array 328 * declared in en/reporter_rx.c 329 */ 330 enum { 331 MLX5E_RQ_STATE_ENABLED = 0, 332 MLX5E_RQ_STATE_RECOVERING, 333 MLX5E_RQ_STATE_DIM, 334 MLX5E_RQ_STATE_NO_CSUM_COMPLETE, 335 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */ 336 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */ 337 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */ 338 MLX5E_RQ_STATE_MINI_CQE_ENHANCED, /* set when enhanced mini_cqe_cap is used */ 339 MLX5E_RQ_STATE_XSK, /* set to indicate an xsk rq */ 340 MLX5E_NUM_RQ_STATES, /* Must be kept last */ 341 }; 342 343 struct mlx5e_cq { 344 /* data path - accessed per cqe */ 345 struct mlx5_cqwq wq; 346 347 /* data path - accessed per napi poll */ 348 u16 event_ctr; 349 struct napi_struct *napi; 350 struct mlx5_core_cq mcq; 351 struct mlx5e_ch_stats *ch_stats; 352 353 /* control */ 354 struct net_device *netdev; 355 struct mlx5_core_dev *mdev; 356 struct workqueue_struct *workqueue; 357 struct mlx5_wq_ctrl wq_ctrl; 358 } ____cacheline_aligned_in_smp; 359 360 struct mlx5e_cq_decomp { 361 /* cqe decompression */ 362 struct mlx5_cqe64 title; 363 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; 364 u8 mini_arr_idx; 365 u16 left; 366 u16 wqe_counter; 367 bool last_cqe_title; 368 } ____cacheline_aligned_in_smp; 369 370 enum mlx5e_dma_map_type { 371 MLX5E_DMA_MAP_SINGLE, 372 MLX5E_DMA_MAP_PAGE 373 }; 374 375 struct mlx5e_sq_dma { 376 dma_addr_t addr; 377 u32 size; 378 enum mlx5e_dma_map_type type; 379 }; 380 381 /* Keep this enum consistent with with the corresponding strings array 382 * declared in en/reporter_tx.c 383 */ 384 enum { 385 MLX5E_SQ_STATE_ENABLED = 0, 386 MLX5E_SQ_STATE_MPWQE, 387 MLX5E_SQ_STATE_RECOVERING, 388 MLX5E_SQ_STATE_IPSEC, 389 MLX5E_SQ_STATE_DIM, 390 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, 391 MLX5E_SQ_STATE_PENDING_XSK_TX, 392 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, 393 MLX5E_NUM_SQ_STATES, /* Must be kept last */ 394 }; 395 396 struct mlx5e_tx_mpwqe { 397 /* Current MPWQE session */ 398 struct mlx5e_tx_wqe *wqe; 399 u32 bytes_count; 400 u8 ds_count; 401 u8 ds_count_max; 402 u8 pkt_count; 403 u8 inline_on; 404 }; 405 406 struct mlx5e_skb_fifo { 407 struct sk_buff **fifo; 408 u16 *pc; 409 u16 *cc; 410 u16 mask; 411 }; 412 413 struct mlx5e_ptpsq; 414 415 struct mlx5e_txqsq { 416 /* data path */ 417 418 /* dirtied @completion */ 419 u16 cc; 420 u16 skb_fifo_cc; 421 u32 dma_fifo_cc; 422 struct dim *dim; /* Adaptive Moderation */ 423 424 /* dirtied @xmit */ 425 u16 pc ____cacheline_aligned_in_smp; 426 u16 skb_fifo_pc; 427 u32 dma_fifo_pc; 428 struct mlx5e_tx_mpwqe mpwqe; 429 430 struct mlx5e_cq cq; 431 432 /* read only */ 433 struct mlx5_wq_cyc wq; 434 u32 dma_fifo_mask; 435 struct mlx5e_sq_stats *stats; 436 struct { 437 struct mlx5e_sq_dma *dma_fifo; 438 struct mlx5e_skb_fifo skb_fifo; 439 struct mlx5e_tx_wqe_info *wqe_info; 440 } db; 441 void __iomem *uar_map; 442 struct netdev_queue *txq; 443 u32 sqn; 444 u16 stop_room; 445 u8 max_sq_mpw_wqebbs; 446 u8 min_inline_mode; 447 struct device *pdev; 448 __be32 mkey_be; 449 unsigned long state; 450 unsigned int hw_mtu; 451 struct mlx5_clock *clock; 452 struct net_device *netdev; 453 struct mlx5_core_dev *mdev; 454 struct mlx5e_channel *channel; 455 struct mlx5e_priv *priv; 456 457 /* control path */ 458 struct mlx5_wq_ctrl wq_ctrl; 459 int ch_ix; 460 int txq_ix; 461 u32 rate_limit; 462 struct work_struct recover_work; 463 struct mlx5e_ptpsq *ptpsq; 464 cqe_ts_to_ns ptp_cyc2time; 465 } ____cacheline_aligned_in_smp; 466 467 struct mlx5e_xdp_info_fifo { 468 union mlx5e_xdp_info *xi; 469 u32 *cc; 470 u32 *pc; 471 u32 mask; 472 }; 473 474 struct mlx5e_xdpsq; 475 struct mlx5e_xmit_data; 476 struct xsk_tx_metadata; 477 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *); 478 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *, 479 struct mlx5e_xmit_data *, 480 int, 481 struct xsk_tx_metadata *); 482 483 struct mlx5e_xdpsq { 484 /* data path */ 485 486 /* dirtied @completion */ 487 u32 xdpi_fifo_cc; 488 u16 cc; 489 490 /* dirtied @xmit */ 491 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp; 492 u16 pc; 493 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 494 struct mlx5e_tx_mpwqe mpwqe; 495 496 struct mlx5e_cq cq; 497 498 /* read only */ 499 struct xsk_buff_pool *xsk_pool; 500 struct mlx5_wq_cyc wq; 501 struct mlx5e_xdpsq_stats *stats; 502 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check; 503 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame; 504 struct { 505 struct mlx5e_xdp_wqe_info *wqe_info; 506 struct mlx5e_xdp_info_fifo xdpi_fifo; 507 } db; 508 void __iomem *uar_map; 509 u32 sqn; 510 struct device *pdev; 511 __be32 mkey_be; 512 u16 stop_room; 513 u8 max_sq_mpw_wqebbs; 514 u8 min_inline_mode; 515 unsigned long state; 516 unsigned int hw_mtu; 517 518 /* control path */ 519 struct mlx5_wq_ctrl wq_ctrl; 520 struct mlx5e_channel *channel; 521 } ____cacheline_aligned_in_smp; 522 523 struct mlx5e_xdp_buff { 524 struct xdp_buff xdp; 525 struct mlx5_cqe64 *cqe; 526 struct mlx5e_rq *rq; 527 }; 528 529 struct mlx5e_ktls_resync_resp; 530 531 struct mlx5e_icosq { 532 /* data path */ 533 u16 cc; 534 u16 pc; 535 536 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 537 struct mlx5e_cq cq; 538 539 /* write@xmit, read@completion */ 540 struct { 541 struct mlx5e_icosq_wqe_info *wqe_info; 542 } db; 543 544 /* read only */ 545 struct mlx5_wq_cyc wq; 546 void __iomem *uar_map; 547 u32 sqn; 548 u16 reserved_room; 549 unsigned long state; 550 struct mlx5e_ktls_resync_resp *ktls_resync; 551 552 /* control path */ 553 struct mlx5_wq_ctrl wq_ctrl; 554 struct mlx5e_channel *channel; 555 556 struct work_struct recover_work; 557 } ____cacheline_aligned_in_smp; 558 559 struct mlx5e_frag_page { 560 struct page *page; 561 u16 frags; 562 }; 563 564 enum mlx5e_wqe_frag_flag { 565 MLX5E_WQE_FRAG_LAST_IN_PAGE, 566 MLX5E_WQE_FRAG_SKIP_RELEASE, 567 }; 568 569 struct mlx5e_wqe_frag_info { 570 union { 571 struct mlx5e_frag_page *frag_page; 572 struct xdp_buff **xskp; 573 }; 574 u32 offset; 575 u8 flags; 576 }; 577 578 union mlx5e_alloc_units { 579 DECLARE_FLEX_ARRAY(struct mlx5e_frag_page, frag_pages); 580 DECLARE_FLEX_ARRAY(struct page *, pages); 581 DECLARE_FLEX_ARRAY(struct xdp_buff *, xsk_buffs); 582 }; 583 584 struct mlx5e_mpw_info { 585 u16 consumed_strides; 586 DECLARE_BITMAP(skip_release_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE); 587 struct mlx5e_frag_page linear_page; 588 union mlx5e_alloc_units alloc_units; 589 }; 590 591 #define MLX5E_MAX_RX_FRAGS 4 592 593 struct mlx5e_rq; 594 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); 595 typedef struct sk_buff * 596 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 597 struct mlx5_cqe64 *cqe, u16 cqe_bcnt, 598 u32 head_offset, u32 page_idx); 599 typedef struct sk_buff * 600 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi, 601 struct mlx5_cqe64 *cqe, u32 cqe_bcnt); 602 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); 603 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); 604 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool); 605 606 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk); 607 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params); 608 609 enum mlx5e_rq_flag { 610 MLX5E_RQ_FLAG_XDP_XMIT, 611 MLX5E_RQ_FLAG_XDP_REDIRECT, 612 }; 613 614 struct mlx5e_rq_frag_info { 615 int frag_size; 616 int frag_stride; 617 }; 618 619 struct mlx5e_rq_frags_info { 620 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; 621 u8 num_frags; 622 u8 log_num_frags; 623 u16 wqe_bulk; 624 u16 refill_unit; 625 u8 wqe_index_mask; 626 }; 627 628 struct mlx5e_dma_info { 629 dma_addr_t addr; 630 union { 631 struct mlx5e_frag_page *frag_page; 632 struct page *page; 633 }; 634 }; 635 636 struct mlx5e_shampo_hd { 637 u32 mkey; 638 struct mlx5e_frag_page *pages; 639 u32 hd_per_wq; 640 u16 hd_per_wqe; 641 u16 pages_per_wq; 642 unsigned long *bitmap; 643 u16 pi; 644 u16 ci; 645 __be32 key; 646 }; 647 648 struct mlx5e_hw_gro_data { 649 struct sk_buff *skb; 650 struct flow_keys fk; 651 int second_ip_id; 652 }; 653 654 enum mlx5e_mpwrq_umr_mode { 655 MLX5E_MPWRQ_UMR_MODE_ALIGNED, 656 MLX5E_MPWRQ_UMR_MODE_UNALIGNED, 657 MLX5E_MPWRQ_UMR_MODE_OVERSIZED, 658 MLX5E_MPWRQ_UMR_MODE_TRIPLE, 659 }; 660 661 struct mlx5e_rq { 662 /* data path */ 663 union { 664 struct { 665 struct mlx5_wq_cyc wq; 666 struct mlx5e_wqe_frag_info *frags; 667 union mlx5e_alloc_units *alloc_units; 668 struct mlx5e_rq_frags_info info; 669 mlx5e_fp_skb_from_cqe skb_from_cqe; 670 } wqe; 671 struct { 672 struct mlx5_wq_ll wq; 673 struct mlx5e_umr_wqe_hdr umr_wqe; 674 struct mlx5e_mpw_info *info; 675 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; 676 __be32 umr_mkey_be; 677 u16 num_strides; 678 u16 actual_wq_head; 679 u8 log_stride_sz; 680 u8 umr_in_progress; 681 u8 umr_last_bulk; 682 u8 umr_completed; 683 u8 min_wqe_bulk; 684 u8 page_shift; 685 u8 pages_per_wqe; 686 u8 umr_wqebbs; 687 u8 mtts_per_wqe; 688 u8 umr_mode; 689 struct mlx5e_shampo_hd *shampo; 690 } mpwqe; 691 }; 692 struct { 693 u16 headroom; 694 u32 frame0_sz; 695 u8 map_dir; /* dma map direction */ 696 } buff; 697 698 struct device *pdev; 699 struct net_device *netdev; 700 struct mlx5e_rq_stats *stats; 701 struct mlx5e_cq cq; 702 struct mlx5e_cq_decomp cqd; 703 struct hwtstamp_config *tstamp; 704 struct mlx5_clock *clock; 705 struct mlx5e_icosq *icosq; 706 struct mlx5e_priv *priv; 707 708 struct mlx5e_hw_gro_data *hw_gro_data; 709 710 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 711 mlx5e_fp_post_rx_wqes post_wqes; 712 mlx5e_fp_dealloc_wqe dealloc_wqe; 713 714 unsigned long state; 715 int ix; 716 unsigned int hw_mtu; 717 718 struct dim *dim; /* Dynamic Interrupt Moderation */ 719 720 /* XDP */ 721 struct bpf_prog __rcu *xdp_prog; 722 struct mlx5e_xdpsq *xdpsq; 723 DECLARE_BITMAP(flags, 8); 724 struct page_pool *page_pool; 725 struct mlx5e_xdp_buff mxbuf; 726 727 /* AF_XDP zero-copy */ 728 struct xsk_buff_pool *xsk_pool; 729 730 struct work_struct recover_work; 731 struct work_struct rx_timeout_work; 732 733 /* control */ 734 struct mlx5_wq_ctrl wq_ctrl; 735 __be32 mkey_be; 736 u8 wq_type; 737 u32 rqn; 738 struct mlx5_core_dev *mdev; 739 struct mlx5e_channel *channel; 740 struct mlx5e_dma_info wqe_overflow; 741 742 /* XDP read-mostly */ 743 struct xdp_rxq_info xdp_rxq; 744 cqe_ts_to_ns ptp_cyc2time; 745 } ____cacheline_aligned_in_smp; 746 747 enum mlx5e_channel_state { 748 MLX5E_CHANNEL_STATE_XSK, 749 MLX5E_CHANNEL_NUM_STATES 750 }; 751 752 struct mlx5e_channel { 753 /* data path */ 754 struct mlx5e_rq rq; 755 struct mlx5e_xdpsq rq_xdpsq; 756 struct mlx5e_txqsq sq[MLX5_MAX_NUM_TC]; 757 struct mlx5e_icosq icosq; /* internal control operations */ 758 struct mlx5e_txqsq __rcu * __rcu *qos_sqs; 759 bool xdp; 760 struct napi_struct napi; 761 struct device *pdev; 762 struct net_device *netdev; 763 __be32 mkey_be; 764 u16 qos_sqs_size; 765 u8 num_tc; 766 u8 lag_port; 767 768 /* XDP_REDIRECT */ 769 struct mlx5e_xdpsq *xdpsq; 770 771 /* AF_XDP zero-copy */ 772 struct mlx5e_rq xskrq; 773 struct mlx5e_xdpsq xsksq; 774 775 /* Async ICOSQ */ 776 struct mlx5e_icosq async_icosq; 777 /* async_icosq can be accessed from any CPU - the spinlock protects it. */ 778 spinlock_t async_icosq_lock; 779 780 /* data path - accessed per napi poll */ 781 const struct cpumask *aff_mask; 782 struct mlx5e_ch_stats *stats; 783 784 /* control */ 785 struct mlx5e_priv *priv; 786 struct mlx5_core_dev *mdev; 787 struct hwtstamp_config *tstamp; 788 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES); 789 int ix; 790 int vec_ix; 791 int sd_ix; 792 int cpu; 793 /* Sync between icosq recovery and XSK enable/disable. */ 794 struct mutex icosq_recovery_lock; 795 796 /* coalescing configuration */ 797 struct dim_cq_moder rx_cq_moder; 798 struct dim_cq_moder tx_cq_moder; 799 }; 800 801 struct mlx5e_ptp; 802 803 struct mlx5e_channels { 804 struct mlx5e_channel **c; 805 struct mlx5e_ptp *ptp; 806 unsigned int num; 807 struct mlx5e_params params; 808 }; 809 810 struct mlx5e_channel_stats { 811 struct mlx5e_ch_stats ch; 812 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC]; 813 struct mlx5e_rq_stats rq; 814 struct mlx5e_rq_stats xskrq; 815 struct mlx5e_xdpsq_stats rq_xdpsq; 816 struct mlx5e_xdpsq_stats xdpsq; 817 struct mlx5e_xdpsq_stats xsksq; 818 } ____cacheline_aligned_in_smp; 819 820 struct mlx5e_ptp_stats { 821 struct mlx5e_ch_stats ch; 822 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC]; 823 struct mlx5e_ptp_cq_stats cq[MLX5_MAX_NUM_TC]; 824 struct mlx5e_rq_stats rq; 825 } ____cacheline_aligned_in_smp; 826 827 enum { 828 MLX5E_STATE_OPENED, 829 MLX5E_STATE_DESTROYING, 830 MLX5E_STATE_XDP_TX_ENABLED, 831 MLX5E_STATE_XDP_ACTIVE, 832 MLX5E_STATE_CHANNELS_ACTIVE, 833 }; 834 835 struct mlx5e_modify_sq_param { 836 int curr_state; 837 int next_state; 838 int rl_update; 839 int rl_index; 840 bool qos_update; 841 u16 qos_queue_group_id; 842 }; 843 844 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 845 struct mlx5e_hv_vhca_stats_agent { 846 struct mlx5_hv_vhca_agent *agent; 847 struct delayed_work work; 848 u16 delay; 849 void *buf; 850 }; 851 #endif 852 853 struct mlx5e_xsk { 854 /* XSK buffer pools are stored separately from channels, 855 * because we don't want to lose them when channels are 856 * recreated. The kernel also stores buffer pool, but it doesn't 857 * distinguish between zero-copy and non-zero-copy UMEMs, so 858 * rely on our mechanism. 859 */ 860 struct xsk_buff_pool **pools; 861 u16 refcnt; 862 bool ever_used; 863 }; 864 865 /* Temporary storage for variables that are allocated when struct mlx5e_priv is 866 * initialized, and used where we can't allocate them because that functions 867 * must not fail. Use with care and make sure the same variable is not used 868 * simultaneously by multiple users. 869 */ 870 struct mlx5e_scratchpad { 871 cpumask_var_t cpumask; 872 }; 873 874 struct mlx5e_trap; 875 struct mlx5e_htb; 876 877 struct mlx5e_priv { 878 /* priv data path fields - start */ 879 struct mlx5e_selq selq; 880 struct mlx5e_txqsq **txq2sq; 881 struct mlx5e_sq_stats **txq2sq_stats; 882 883 #ifdef CONFIG_MLX5_CORE_EN_DCB 884 struct mlx5e_dcbx_dp dcbx_dp; 885 #endif 886 /* priv data path fields - end */ 887 888 unsigned long state; 889 struct mutex state_lock; /* Protects Interface state */ 890 struct mlx5e_rq drop_rq; 891 892 struct mlx5e_channels channels; 893 struct mlx5e_rx_res *rx_res; 894 u32 *tx_rates; 895 896 struct mlx5e_flow_steering *fs; 897 898 struct workqueue_struct *wq; 899 struct work_struct update_carrier_work; 900 struct work_struct set_rx_mode_work; 901 struct work_struct tx_timeout_work; 902 struct work_struct update_stats_work; 903 struct work_struct monitor_counters_work; 904 struct mlx5_nb monitor_counters_nb; 905 906 struct mlx5_core_dev *mdev; 907 struct net_device *netdev; 908 struct mlx5e_trap *en_trap; 909 struct mlx5e_stats stats; 910 struct mlx5e_channel_stats **channel_stats; 911 struct mlx5e_channel_stats trap_stats; 912 struct mlx5e_ptp_stats ptp_stats; 913 struct mlx5e_sq_stats **htb_qos_sq_stats; 914 u16 htb_max_qos_sqs; 915 u16 stats_nch; 916 u16 max_nch; 917 u8 max_opened_tc; 918 bool tx_ptp_opened; 919 bool rx_ptp_opened; 920 struct hwtstamp_config tstamp; 921 u16 q_counter[MLX5_SD_MAX_GROUP_SZ]; 922 u16 drop_rq_q_counter; 923 struct notifier_block events_nb; 924 struct notifier_block blocking_events_nb; 925 926 struct udp_tunnel_nic_info nic_info; 927 #ifdef CONFIG_MLX5_CORE_EN_DCB 928 struct mlx5e_dcbx dcbx; 929 #endif 930 931 const struct mlx5e_profile *profile; 932 void *ppriv; 933 #ifdef CONFIG_MLX5_MACSEC 934 struct mlx5e_macsec *macsec; 935 #endif 936 #ifdef CONFIG_MLX5_EN_IPSEC 937 struct mlx5e_ipsec *ipsec; 938 #endif 939 #ifdef CONFIG_MLX5_EN_TLS 940 struct mlx5e_tls *tls; 941 #endif 942 struct devlink_health_reporter *tx_reporter; 943 struct devlink_health_reporter *rx_reporter; 944 struct mlx5e_xsk xsk; 945 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 946 struct mlx5e_hv_vhca_stats_agent stats_agent; 947 #endif 948 struct mlx5e_scratchpad scratchpad; 949 struct mlx5e_htb *htb; 950 struct mlx5e_mqprio_rl *mqprio_rl; 951 struct dentry *dfs_root; 952 struct mlx5_devcom_comp_dev *devcom; 953 }; 954 955 struct mlx5e_dev { 956 struct mlx5e_priv *priv; 957 struct devlink_port dl_port; 958 }; 959 960 struct mlx5e_rx_handlers { 961 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 962 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; 963 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo; 964 }; 965 966 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic; 967 968 enum mlx5e_profile_feature { 969 MLX5E_PROFILE_FEATURE_PTP_RX, 970 MLX5E_PROFILE_FEATURE_PTP_TX, 971 MLX5E_PROFILE_FEATURE_QOS_HTB, 972 MLX5E_PROFILE_FEATURE_FS_VLAN, 973 MLX5E_PROFILE_FEATURE_FS_TC, 974 }; 975 976 struct mlx5e_profile { 977 int (*init)(struct mlx5_core_dev *mdev, 978 struct net_device *netdev); 979 void (*cleanup)(struct mlx5e_priv *priv); 980 int (*init_rx)(struct mlx5e_priv *priv); 981 void (*cleanup_rx)(struct mlx5e_priv *priv); 982 int (*init_tx)(struct mlx5e_priv *priv); 983 void (*cleanup_tx)(struct mlx5e_priv *priv); 984 void (*enable)(struct mlx5e_priv *priv); 985 void (*disable)(struct mlx5e_priv *priv); 986 int (*update_rx)(struct mlx5e_priv *priv); 987 void (*update_stats)(struct mlx5e_priv *priv); 988 void (*update_carrier)(struct mlx5e_priv *priv); 989 int (*max_nch_limit)(struct mlx5_core_dev *mdev); 990 u32 (*get_tisn)(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv, 991 u8 lag_port, u8 tc); 992 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv); 993 mlx5e_stats_grp_t *stats_grps; 994 const struct mlx5e_rx_handlers *rx_handlers; 995 int max_tc; 996 u32 features; 997 }; 998 999 u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev, 1000 struct mlx5e_priv *priv, 1001 const struct mlx5e_profile *profile, 1002 u8 lag_port, u8 tc); 1003 1004 #define mlx5e_profile_feature_cap(profile, feature) \ 1005 ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature)) 1006 1007 void mlx5e_build_ptys2ethtool_map(void); 1008 1009 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift, 1010 enum mlx5e_mpwrq_umr_mode umr_mode); 1011 1012 void mlx5e_shampo_fill_umr(struct mlx5e_rq *rq, int len); 1013 void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq); 1014 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); 1015 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); 1016 1017 int mlx5e_self_test_num(struct mlx5e_priv *priv); 1018 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data); 1019 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, 1020 u64 *buf); 1021 void mlx5e_set_rx_mode_work(struct work_struct *work); 1022 1023 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); 1024 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); 1025 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter); 1026 1027 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, 1028 u16 vid); 1029 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, 1030 u16 vid); 1031 void mlx5e_timestamp_init(struct mlx5e_priv *priv); 1032 1033 struct mlx5e_xsk_param; 1034 1035 struct mlx5e_rq_param; 1036 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param, 1037 struct mlx5e_xsk_param *xsk, int node, u16 q_counter, 1038 struct mlx5e_rq *rq); 1039 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */ 1040 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time); 1041 void mlx5e_close_rq(struct mlx5e_rq *rq); 1042 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param, u16 q_counter); 1043 void mlx5e_destroy_rq(struct mlx5e_rq *rq); 1044 1045 bool mlx5e_reset_rx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode, 1046 bool dim_enabled); 1047 bool mlx5e_reset_rx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode, 1048 bool dim_enabled, bool keep_dim_state); 1049 1050 struct mlx5e_sq_param; 1051 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, 1052 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, 1053 struct mlx5e_xdpsq *sq, bool is_redirect); 1054 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq); 1055 1056 struct mlx5e_create_cq_param { 1057 struct net_device *netdev; 1058 struct workqueue_struct *wq; 1059 struct napi_struct *napi; 1060 struct mlx5e_ch_stats *ch_stats; 1061 int node; 1062 int ix; 1063 }; 1064 1065 struct mlx5e_cq_param; 1066 int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder, 1067 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, 1068 struct mlx5e_cq *cq); 1069 void mlx5e_close_cq(struct mlx5e_cq *cq); 1070 int mlx5e_modify_cq_period_mode(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, 1071 u8 cq_period_mode); 1072 int mlx5e_modify_cq_moderation(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, 1073 u16 cq_period, u16 cq_max_count, u8 cq_period_mode); 1074 1075 int mlx5e_open_locked(struct net_device *netdev); 1076 int mlx5e_close_locked(struct net_device *netdev); 1077 1078 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c); 1079 void mlx5e_trigger_napi_sched(struct napi_struct *napi); 1080 1081 int mlx5e_open_channels(struct mlx5e_priv *priv, 1082 struct mlx5e_channels *chs); 1083 void mlx5e_close_channels(struct mlx5e_channels *chs); 1084 1085 /* Function pointer to be used to modify HW or kernel settings while 1086 * switching channels 1087 */ 1088 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context); 1089 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \ 1090 int fn##_ctx(struct mlx5e_priv *priv, void *context) \ 1091 { \ 1092 return fn(priv); \ 1093 } 1094 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv); 1095 int mlx5e_safe_switch_params(struct mlx5e_priv *priv, 1096 struct mlx5e_params *new_params, 1097 mlx5e_fp_preactivate preactivate, 1098 void *context, bool reset); 1099 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv); 1100 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context); 1101 int mlx5e_update_tc_and_tx_queues_ctx(struct mlx5e_priv *priv, void *context); 1102 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); 1103 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); 1104 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx); 1105 1106 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state); 1107 void mlx5e_activate_rq(struct mlx5e_rq *rq); 1108 void mlx5e_deactivate_rq(struct mlx5e_rq *rq); 1109 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq); 1110 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq); 1111 1112 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, 1113 struct mlx5e_modify_sq_param *p); 1114 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, 1115 struct mlx5e_params *params, struct mlx5e_sq_param *param, 1116 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, 1117 struct mlx5e_sq_stats *sq_stats); 1118 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq); 1119 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq); 1120 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq); 1121 void mlx5e_tx_disable_queue(struct netdev_queue *txq); 1122 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa); 1123 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq); 1124 struct mlx5e_create_sq_param; 1125 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, 1126 struct mlx5e_sq_param *param, 1127 struct mlx5e_create_sq_param *csp, 1128 u16 qos_queue_group_id, 1129 u32 *sqn); 1130 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work); 1131 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq); 1132 1133 bool mlx5e_reset_tx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode, 1134 bool dim_enabled); 1135 bool mlx5e_reset_tx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode, 1136 bool dim_enabled, bool keep_dim_state); 1137 1138 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev) 1139 { 1140 return MLX5_CAP_ETH(mdev, swp) && 1141 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); 1142 } 1143 1144 extern const struct ethtool_ops mlx5e_ethtool_ops; 1145 1146 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey); 1147 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises); 1148 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); 1149 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb, 1150 bool enable_mc_lb); 1151 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc); 1152 1153 /* common netdev helpers */ 1154 void mlx5e_create_q_counters(struct mlx5e_priv *priv); 1155 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv); 1156 int mlx5e_open_drop_rq(struct mlx5e_priv *priv, 1157 struct mlx5e_rq *drop_rq); 1158 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); 1159 1160 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn); 1161 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); 1162 1163 void mlx5e_update_carrier(struct mlx5e_priv *priv); 1164 int mlx5e_close(struct net_device *netdev); 1165 int mlx5e_open(struct net_device *netdev); 1166 1167 void mlx5e_queue_update_stats(struct mlx5e_priv *priv); 1168 1169 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv); 1170 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context); 1171 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, 1172 mlx5e_fp_preactivate preactivate); 1173 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv); 1174 1175 /* ethtool helpers */ 1176 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, 1177 struct ethtool_drvinfo *drvinfo); 1178 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, 1179 u32 stringset, u8 *data); 1180 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); 1181 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, 1182 struct ethtool_stats *stats, u64 *data); 1183 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, 1184 struct ethtool_ringparam *param, 1185 struct kernel_ethtool_ringparam *kernel_param); 1186 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, 1187 struct ethtool_ringparam *param, 1188 struct netlink_ext_ack *extack); 1189 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, 1190 struct ethtool_channels *ch); 1191 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, 1192 struct ethtool_channels *ch); 1193 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, 1194 struct ethtool_coalesce *coal, 1195 struct kernel_ethtool_coalesce *kernel_coal, 1196 struct netlink_ext_ack *extack); 1197 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, 1198 struct ethtool_coalesce *coal, 1199 struct kernel_ethtool_coalesce *kernel_coal, 1200 struct netlink_ext_ack *extack); 1201 int mlx5e_get_per_queue_coalesce(struct net_device *dev, u32 queue, 1202 struct ethtool_coalesce *coal); 1203 int mlx5e_set_per_queue_coalesce(struct net_device *dev, u32 queue, 1204 struct ethtool_coalesce *coal); 1205 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv); 1206 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv); 1207 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, 1208 struct kernel_ethtool_ts_info *info); 1209 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, 1210 struct ethtool_flash *flash); 1211 1212 /* mlx5e generic netdev management API */ 1213 static inline bool 1214 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev) 1215 { 1216 return !is_kdump_kernel() && 1217 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe); 1218 } 1219 1220 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev); 1221 int mlx5e_priv_init(struct mlx5e_priv *priv, 1222 const struct mlx5e_profile *profile, 1223 struct net_device *netdev, 1224 struct mlx5_core_dev *mdev); 1225 void mlx5e_priv_cleanup(struct mlx5e_priv *priv); 1226 struct net_device * 1227 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile); 1228 int mlx5e_attach_netdev(struct mlx5e_priv *priv); 1229 void mlx5e_detach_netdev(struct mlx5e_priv *priv); 1230 void mlx5e_destroy_netdev(struct mlx5e_priv *priv); 1231 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv, 1232 const struct mlx5e_profile *new_profile, void *new_ppriv); 1233 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv); 1234 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv); 1235 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu); 1236 1237 void mlx5e_set_xdp_feature(struct net_device *netdev); 1238 netdev_features_t mlx5e_features_check(struct sk_buff *skb, 1239 struct net_device *netdev, 1240 netdev_features_t features); 1241 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features); 1242 #ifdef CONFIG_MLX5_ESWITCH 1243 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac); 1244 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate); 1245 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi); 1246 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats); 1247 #endif 1248 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey); 1249 #endif /* __MLX5_EN_H__ */ 1250