1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Virtual Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/etherdevice.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/net_tstamp.h> 12 13 #include "otx2_common.h" 14 #include "otx2_reg.h" 15 #include "otx2_ptp.h" 16 #include "cn10k.h" 17 #include "cn10k_ipsec.h" 18 19 #define DRV_NAME "rvu_nicvf" 20 #define DRV_STRING "Marvell RVU NIC Virtual Function Driver" 21 22 static const struct pci_device_id otx2_vf_id_table[] = { 23 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AFVF) }, 24 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF) }, 25 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_SDP_REP) }, 26 { } 27 }; 28 29 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 30 MODULE_DESCRIPTION(DRV_STRING); 31 MODULE_LICENSE("GPL v2"); 32 MODULE_DEVICE_TABLE(pci, otx2_vf_id_table); 33 34 /* RVU VF Interrupt Vector Enumeration */ 35 enum { 36 RVU_VF_INT_VEC_MBOX = 0x0, 37 }; 38 39 static void otx2vf_process_vfaf_mbox_msg(struct otx2_nic *vf, 40 struct mbox_msghdr *msg) 41 { 42 if (msg->id >= MBOX_MSG_MAX) { 43 dev_err(vf->dev, 44 "Mbox msg with unknown ID %d\n", msg->id); 45 return; 46 } 47 48 if (msg->sig != OTX2_MBOX_RSP_SIG) { 49 dev_err(vf->dev, 50 "Mbox msg with wrong signature %x, ID %d\n", 51 msg->sig, msg->id); 52 return; 53 } 54 55 if (msg->rc == MBOX_MSG_INVALID) { 56 dev_err(vf->dev, 57 "PF/AF says the sent msg(s) %d were invalid\n", 58 msg->id); 59 return; 60 } 61 62 switch (msg->id) { 63 case MBOX_MSG_READY: 64 vf->pcifunc = msg->pcifunc; 65 break; 66 case MBOX_MSG_MSIX_OFFSET: 67 mbox_handler_msix_offset(vf, (struct msix_offset_rsp *)msg); 68 break; 69 case MBOX_MSG_NPA_LF_ALLOC: 70 mbox_handler_npa_lf_alloc(vf, (struct npa_lf_alloc_rsp *)msg); 71 break; 72 case MBOX_MSG_NIX_LF_ALLOC: 73 mbox_handler_nix_lf_alloc(vf, (struct nix_lf_alloc_rsp *)msg); 74 break; 75 case MBOX_MSG_NIX_BP_ENABLE: 76 mbox_handler_nix_bp_enable(vf, (struct nix_bp_cfg_rsp *)msg); 77 break; 78 default: 79 if (msg->rc) 80 dev_err(vf->dev, 81 "Mbox msg response has err %d, ID %d\n", 82 msg->rc, msg->id); 83 } 84 } 85 86 static void otx2vf_vfaf_mbox_handler(struct work_struct *work) 87 { 88 struct otx2_mbox_dev *mdev; 89 struct mbox_hdr *rsp_hdr; 90 struct mbox_msghdr *msg; 91 struct otx2_mbox *mbox; 92 struct mbox *af_mbox; 93 int offset, id; 94 u16 num_msgs; 95 96 af_mbox = container_of(work, struct mbox, mbox_wrk); 97 mbox = &af_mbox->mbox; 98 mdev = &mbox->dev[0]; 99 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 100 num_msgs = rsp_hdr->num_msgs; 101 102 if (num_msgs == 0) 103 return; 104 105 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 106 107 for (id = 0; id < num_msgs; id++) { 108 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 109 otx2vf_process_vfaf_mbox_msg(af_mbox->pfvf, msg); 110 offset = mbox->rx_start + msg->next_msgoff; 111 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 112 __otx2_mbox_reset(mbox, 0); 113 mdev->msgs_acked++; 114 } 115 } 116 117 static int otx2vf_process_mbox_msg_up(struct otx2_nic *vf, 118 struct mbox_msghdr *req) 119 { 120 struct msg_rsp *rsp; 121 int err; 122 123 /* Check if valid, if not reply with a invalid msg */ 124 if (req->sig != OTX2_MBOX_REQ_SIG) { 125 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); 126 return -ENODEV; 127 } 128 129 switch (req->id) { 130 case MBOX_MSG_CGX_LINK_EVENT: 131 rsp = (struct msg_rsp *)otx2_mbox_alloc_msg( 132 &vf->mbox.mbox_up, 0, 133 sizeof(struct msg_rsp)); 134 if (!rsp) 135 return -ENOMEM; 136 137 rsp->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 138 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; 139 rsp->hdr.pcifunc = 0; 140 rsp->hdr.rc = 0; 141 err = otx2_mbox_up_handler_cgx_link_event( 142 vf, (struct cgx_link_info_msg *)req, rsp); 143 return err; 144 default: 145 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); 146 return -ENODEV; 147 } 148 return 0; 149 } 150 151 static void otx2vf_vfaf_mbox_up_handler(struct work_struct *work) 152 { 153 struct otx2_mbox_dev *mdev; 154 struct mbox_hdr *rsp_hdr; 155 struct mbox_msghdr *msg; 156 struct otx2_mbox *mbox; 157 struct mbox *vf_mbox; 158 struct otx2_nic *vf; 159 int offset, id; 160 u16 num_msgs; 161 162 vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 163 vf = vf_mbox->pfvf; 164 mbox = &vf_mbox->mbox_up; 165 mdev = &mbox->dev[0]; 166 167 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 168 num_msgs = rsp_hdr->num_msgs; 169 170 if (num_msgs == 0) 171 return; 172 173 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 174 175 for (id = 0; id < num_msgs; id++) { 176 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 177 otx2vf_process_mbox_msg_up(vf, msg); 178 offset = mbox->rx_start + msg->next_msgoff; 179 } 180 181 otx2_mbox_msg_send(mbox, 0); 182 } 183 184 static irqreturn_t otx2vf_vfaf_mbox_intr_handler(int irq, void *vf_irq) 185 { 186 struct otx2_nic *vf = (struct otx2_nic *)vf_irq; 187 struct otx2_mbox_dev *mdev; 188 struct otx2_mbox *mbox; 189 struct mbox_hdr *hdr; 190 u64 mbox_data; 191 192 /* Clear the IRQ */ 193 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); 194 195 mbox_data = otx2_read64(vf, RVU_VF_VFPF_MBOX0); 196 197 /* Read latest mbox data */ 198 smp_rmb(); 199 200 if (mbox_data & MBOX_DOWN_MSG) { 201 mbox_data &= ~MBOX_DOWN_MSG; 202 otx2_write64(vf, RVU_VF_VFPF_MBOX0, mbox_data); 203 204 /* Check for PF => VF response messages */ 205 mbox = &vf->mbox.mbox; 206 mdev = &mbox->dev[0]; 207 otx2_sync_mbox_bbuf(mbox, 0); 208 209 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 210 if (hdr->num_msgs) 211 queue_work(vf->mbox_wq, &vf->mbox.mbox_wrk); 212 213 trace_otx2_msg_interrupt(mbox->pdev, "DOWN reply from PF to VF", 214 BIT_ULL(0)); 215 } 216 217 if (mbox_data & MBOX_UP_MSG) { 218 mbox_data &= ~MBOX_UP_MSG; 219 otx2_write64(vf, RVU_VF_VFPF_MBOX0, mbox_data); 220 221 /* Check for PF => VF notification messages */ 222 mbox = &vf->mbox.mbox_up; 223 mdev = &mbox->dev[0]; 224 otx2_sync_mbox_bbuf(mbox, 0); 225 226 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 227 if (hdr->num_msgs) 228 queue_work(vf->mbox_wq, &vf->mbox.mbox_up_wrk); 229 230 trace_otx2_msg_interrupt(mbox->pdev, "UP message from PF to VF", 231 BIT_ULL(0)); 232 } 233 234 return IRQ_HANDLED; 235 } 236 237 static void otx2vf_disable_mbox_intr(struct otx2_nic *vf) 238 { 239 int vector = pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX); 240 241 /* Disable VF => PF mailbox IRQ */ 242 otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0)); 243 free_irq(vector, vf); 244 } 245 246 static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf) 247 { 248 struct otx2_hw *hw = &vf->hw; 249 struct msg_req *req; 250 char *irq_name; 251 int err; 252 253 /* Register mailbox interrupt handler */ 254 irq_name = &hw->irq_name[RVU_VF_INT_VEC_MBOX * NAME_SIZE]; 255 snprintf(irq_name, NAME_SIZE, "RVUVFAF Mbox"); 256 err = request_irq(pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX), 257 otx2vf_vfaf_mbox_intr_handler, 0, irq_name, vf); 258 if (err) { 259 dev_err(vf->dev, 260 "RVUPF: IRQ registration failed for VFAF mbox irq\n"); 261 return err; 262 } 263 264 /* Enable mailbox interrupt for msgs coming from PF. 265 * First clear to avoid spurious interrupts, if any. 266 */ 267 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); 268 otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0)); 269 270 if (!probe_pf) 271 return 0; 272 273 /* Check mailbox communication with PF */ 274 req = otx2_mbox_alloc_msg_ready(&vf->mbox); 275 if (!req) { 276 otx2vf_disable_mbox_intr(vf); 277 return -ENOMEM; 278 } 279 280 err = otx2_sync_mbox_msg(&vf->mbox); 281 if (err) { 282 dev_warn(vf->dev, 283 "AF not responding to mailbox, deferring probe\n"); 284 otx2vf_disable_mbox_intr(vf); 285 return -EPROBE_DEFER; 286 } 287 return 0; 288 } 289 290 static void otx2vf_vfaf_mbox_destroy(struct otx2_nic *vf) 291 { 292 struct mbox *mbox = &vf->mbox; 293 294 if (vf->mbox_wq) { 295 destroy_workqueue(vf->mbox_wq); 296 vf->mbox_wq = NULL; 297 } 298 299 if (mbox->mbox.hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag)) 300 iounmap((void __iomem *)mbox->mbox.hwbase); 301 302 otx2_mbox_destroy(&mbox->mbox); 303 otx2_mbox_destroy(&mbox->mbox_up); 304 } 305 306 static int otx2vf_vfaf_mbox_init(struct otx2_nic *vf) 307 { 308 struct mbox *mbox = &vf->mbox; 309 void __iomem *hwbase; 310 int err; 311 312 mbox->pfvf = vf; 313 vf->mbox_wq = alloc_ordered_workqueue("otx2_vfaf_mailbox", 314 WQ_HIGHPRI | WQ_MEM_RECLAIM); 315 if (!vf->mbox_wq) 316 return -ENOMEM; 317 318 if (test_bit(CN10K_MBOX, &vf->hw.cap_flag)) { 319 /* For cn10k platform, VF mailbox region is in its BAR2 320 * register space 321 */ 322 hwbase = vf->reg_base + RVU_VF_MBOX_REGION; 323 } else { 324 /* Mailbox is a reserved memory (in RAM) region shared between 325 * admin function (i.e PF0) and this VF, shouldn't be mapped as 326 * device memory to allow unaligned accesses. 327 */ 328 hwbase = ioremap_wc(pci_resource_start(vf->pdev, 329 PCI_MBOX_BAR_NUM), 330 pci_resource_len(vf->pdev, 331 PCI_MBOX_BAR_NUM)); 332 if (!hwbase) { 333 dev_err(vf->dev, "Unable to map VFAF mailbox region\n"); 334 err = -ENOMEM; 335 goto exit; 336 } 337 } 338 339 err = otx2_mbox_init(&mbox->mbox, hwbase, vf->pdev, vf->reg_base, 340 MBOX_DIR_VFPF, 1); 341 if (err) 342 goto exit; 343 344 err = otx2_mbox_init(&mbox->mbox_up, hwbase, vf->pdev, vf->reg_base, 345 MBOX_DIR_VFPF_UP, 1); 346 if (err) 347 goto exit; 348 349 err = otx2_mbox_bbuf_init(mbox, vf->pdev); 350 if (err) 351 goto exit; 352 353 INIT_WORK(&mbox->mbox_wrk, otx2vf_vfaf_mbox_handler); 354 INIT_WORK(&mbox->mbox_up_wrk, otx2vf_vfaf_mbox_up_handler); 355 mutex_init(&mbox->lock); 356 357 return 0; 358 exit: 359 if (hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag)) 360 iounmap(hwbase); 361 destroy_workqueue(vf->mbox_wq); 362 return err; 363 } 364 365 static int otx2vf_open(struct net_device *netdev) 366 { 367 struct otx2_nic *vf; 368 int err; 369 370 err = otx2_open(netdev); 371 if (err) 372 return err; 373 374 /* LBKs do not receive link events so tell everyone we are up here */ 375 vf = netdev_priv(netdev); 376 if (is_otx2_lbkvf(vf->pdev) || is_otx2_sdp_rep(vf->pdev)) { 377 pr_info("%s NIC Link is UP\n", netdev->name); 378 netif_carrier_on(netdev); 379 netif_tx_start_all_queues(netdev); 380 } 381 382 return 0; 383 } 384 385 static int otx2vf_stop(struct net_device *netdev) 386 { 387 return otx2_stop(netdev); 388 } 389 390 static netdev_tx_t otx2vf_xmit(struct sk_buff *skb, struct net_device *netdev) 391 { 392 struct otx2_nic *vf = netdev_priv(netdev); 393 int qidx = skb_get_queue_mapping(skb); 394 struct otx2_snd_queue *sq; 395 struct netdev_queue *txq; 396 397 sq = &vf->qset.sq[qidx]; 398 txq = netdev_get_tx_queue(netdev, qidx); 399 400 if (!otx2_sq_append_skb(vf, txq, sq, skb, qidx)) { 401 netif_tx_stop_queue(txq); 402 403 /* Check again, incase SQBs got freed up */ 404 smp_mb(); 405 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 406 > sq->sqe_thresh) 407 netif_tx_wake_queue(txq); 408 409 return NETDEV_TX_BUSY; 410 } 411 412 return NETDEV_TX_OK; 413 } 414 415 static void otx2vf_set_rx_mode(struct net_device *netdev) 416 { 417 struct otx2_nic *vf = netdev_priv(netdev); 418 419 queue_work(vf->otx2_wq, &vf->rx_mode_work); 420 } 421 422 static void otx2vf_do_set_rx_mode(struct work_struct *work) 423 { 424 struct otx2_nic *vf = container_of(work, struct otx2_nic, rx_mode_work); 425 struct net_device *netdev = vf->netdev; 426 unsigned int flags = netdev->flags; 427 struct nix_rx_mode *req; 428 429 mutex_lock(&vf->mbox.lock); 430 431 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&vf->mbox); 432 if (!req) { 433 mutex_unlock(&vf->mbox.lock); 434 return; 435 } 436 437 req->mode = NIX_RX_MODE_UCAST; 438 439 if (flags & IFF_PROMISC) 440 req->mode |= NIX_RX_MODE_PROMISC; 441 if (flags & (IFF_ALLMULTI | IFF_MULTICAST)) 442 req->mode |= NIX_RX_MODE_ALLMULTI; 443 444 req->mode |= NIX_RX_MODE_USE_MCE; 445 446 otx2_sync_mbox_msg(&vf->mbox); 447 448 mutex_unlock(&vf->mbox.lock); 449 } 450 451 static int otx2vf_change_mtu(struct net_device *netdev, int new_mtu) 452 { 453 bool if_up = netif_running(netdev); 454 int err = 0; 455 456 if (if_up) 457 otx2vf_stop(netdev); 458 459 netdev_info(netdev, "Changing MTU from %d to %d\n", 460 netdev->mtu, new_mtu); 461 WRITE_ONCE(netdev->mtu, new_mtu); 462 463 if (if_up) 464 err = otx2vf_open(netdev); 465 466 return err; 467 } 468 469 static void otx2vf_reset_task(struct work_struct *work) 470 { 471 struct otx2_nic *vf = container_of(work, struct otx2_nic, reset_task); 472 473 rtnl_lock(); 474 475 if (netif_running(vf->netdev)) { 476 otx2vf_stop(vf->netdev); 477 vf->reset_count++; 478 otx2vf_open(vf->netdev); 479 } 480 481 rtnl_unlock(); 482 } 483 484 static int otx2vf_set_features(struct net_device *netdev, 485 netdev_features_t features) 486 { 487 return otx2_handle_ntuple_tc_features(netdev, features); 488 } 489 490 static const struct net_device_ops otx2vf_netdev_ops = { 491 .ndo_open = otx2vf_open, 492 .ndo_stop = otx2vf_stop, 493 .ndo_start_xmit = otx2vf_xmit, 494 .ndo_select_queue = otx2_select_queue, 495 .ndo_set_rx_mode = otx2vf_set_rx_mode, 496 .ndo_set_mac_address = otx2_set_mac_address, 497 .ndo_change_mtu = otx2vf_change_mtu, 498 .ndo_set_features = otx2vf_set_features, 499 .ndo_get_stats64 = otx2_get_stats64, 500 .ndo_tx_timeout = otx2_tx_timeout, 501 .ndo_eth_ioctl = otx2_ioctl, 502 .ndo_setup_tc = otx2_setup_tc, 503 }; 504 505 static int otx2_vf_wq_init(struct otx2_nic *vf) 506 { 507 vf->otx2_wq = create_singlethread_workqueue("otx2vf_wq"); 508 if (!vf->otx2_wq) 509 return -ENOMEM; 510 511 INIT_WORK(&vf->rx_mode_work, otx2vf_do_set_rx_mode); 512 INIT_WORK(&vf->reset_task, otx2vf_reset_task); 513 return 0; 514 } 515 516 static int otx2vf_realloc_msix_vectors(struct otx2_nic *vf) 517 { 518 struct otx2_hw *hw = &vf->hw; 519 int num_vec, err; 520 521 num_vec = hw->nix_msixoff; 522 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 523 524 otx2vf_disable_mbox_intr(vf); 525 pci_free_irq_vectors(hw->pdev); 526 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 527 if (err < 0) { 528 dev_err(vf->dev, "%s: Failed to realloc %d IRQ vectors\n", 529 __func__, num_vec); 530 return err; 531 } 532 533 return otx2vf_register_mbox_intr(vf, false); 534 } 535 536 static int otx2vf_probe(struct pci_dev *pdev, const struct pci_device_id *id) 537 { 538 int num_vec = pci_msix_vec_count(pdev); 539 struct device *dev = &pdev->dev; 540 int err, qcount, qos_txqs; 541 struct net_device *netdev; 542 struct otx2_nic *vf; 543 struct otx2_hw *hw; 544 545 err = pcim_enable_device(pdev); 546 if (err) { 547 dev_err(dev, "Failed to enable PCI device\n"); 548 return err; 549 } 550 551 err = pci_request_regions(pdev, DRV_NAME); 552 if (err) { 553 dev_err(dev, "PCI request regions failed 0x%x\n", err); 554 return err; 555 } 556 557 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 558 if (err) { 559 dev_err(dev, "DMA mask config failed, abort\n"); 560 goto err_release_regions; 561 } 562 563 pci_set_master(pdev); 564 565 qcount = num_online_cpus(); 566 qos_txqs = min_t(int, qcount, OTX2_QOS_MAX_LEAF_NODES); 567 netdev = alloc_etherdev_mqs(sizeof(*vf), qcount + qos_txqs, qcount); 568 if (!netdev) { 569 err = -ENOMEM; 570 goto err_release_regions; 571 } 572 573 pci_set_drvdata(pdev, netdev); 574 SET_NETDEV_DEV(netdev, &pdev->dev); 575 vf = netdev_priv(netdev); 576 vf->netdev = netdev; 577 vf->pdev = pdev; 578 vf->dev = dev; 579 vf->iommu_domain = iommu_get_domain_for_dev(dev); 580 581 vf->flags |= OTX2_FLAG_INTF_DOWN; 582 hw = &vf->hw; 583 hw->pdev = vf->pdev; 584 hw->rx_queues = qcount; 585 hw->tx_queues = qcount; 586 hw->max_queues = qcount; 587 hw->non_qos_queues = qcount; 588 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 589 /* Use CQE of 128 byte descriptor size by default */ 590 hw->xqe_size = 128; 591 592 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 593 GFP_KERNEL); 594 if (!hw->irq_name) { 595 err = -ENOMEM; 596 goto err_free_netdev; 597 } 598 599 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 600 sizeof(cpumask_var_t), GFP_KERNEL); 601 if (!hw->affinity_mask) { 602 err = -ENOMEM; 603 goto err_free_netdev; 604 } 605 606 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 607 if (err < 0) { 608 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 609 __func__, num_vec); 610 goto err_free_netdev; 611 } 612 613 vf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 614 if (!vf->reg_base) { 615 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 616 err = -ENOMEM; 617 goto err_free_irq_vectors; 618 } 619 620 otx2_setup_dev_hw_settings(vf); 621 /* Init VF <=> PF mailbox stuff */ 622 err = otx2vf_vfaf_mbox_init(vf); 623 if (err) 624 goto err_free_irq_vectors; 625 626 /* Register mailbox interrupt */ 627 err = otx2vf_register_mbox_intr(vf, true); 628 if (err) 629 goto err_mbox_destroy; 630 631 /* Request AF to attach NPA and LIX LFs to this AF */ 632 err = otx2_attach_npa_nix(vf); 633 if (err) 634 goto err_disable_mbox_intr; 635 636 err = otx2vf_realloc_msix_vectors(vf); 637 if (err) 638 goto err_detach_rsrc; 639 640 err = otx2_set_real_num_queues(netdev, qcount, qcount); 641 if (err) 642 goto err_detach_rsrc; 643 644 err = cn10k_lmtst_init(vf); 645 if (err) 646 goto err_detach_rsrc; 647 648 /* Don't check for error. Proceed without ptp */ 649 otx2_ptp_init(vf); 650 651 /* Assign default mac address */ 652 otx2_get_mac_from_af(netdev); 653 654 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 655 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 656 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 657 NETIF_F_GSO_UDP_L4; 658 netdev->features = netdev->hw_features; 659 /* Support TSO on tag interface */ 660 netdev->vlan_features |= netdev->features; 661 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 662 NETIF_F_HW_VLAN_STAG_TX; 663 netdev->features |= netdev->hw_features; 664 665 netdev->hw_features |= NETIF_F_NTUPLE; 666 netdev->hw_features |= NETIF_F_RXALL; 667 netdev->hw_features |= NETIF_F_HW_TC; 668 669 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 670 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 671 672 netdev->netdev_ops = &otx2vf_netdev_ops; 673 674 netdev->min_mtu = OTX2_MIN_MTU; 675 netdev->max_mtu = otx2_get_max_mtu(vf); 676 hw->max_mtu = netdev->max_mtu; 677 678 /* To distinguish, for LBK VFs set netdev name explicitly */ 679 if (is_otx2_lbkvf(vf->pdev)) { 680 int n; 681 682 n = (vf->pcifunc >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK; 683 /* Need to subtract 1 to get proper VF number */ 684 n -= 1; 685 snprintf(netdev->name, sizeof(netdev->name), "lbk%d", n); 686 } 687 688 if (is_otx2_sdp_rep(vf->pdev)) { 689 int n; 690 691 n = vf->pcifunc & RVU_PFVF_FUNC_MASK; 692 n -= 1; 693 snprintf(netdev->name, sizeof(netdev->name), "sdp%d-%d", 694 pdev->bus->number, n); 695 } 696 697 err = cn10k_ipsec_init(netdev); 698 if (err) 699 goto err_ptp_destroy; 700 701 err = register_netdev(netdev); 702 if (err) { 703 dev_err(dev, "Failed to register netdevice\n"); 704 goto err_ipsec_clean; 705 } 706 707 err = otx2_vf_wq_init(vf); 708 if (err) 709 goto err_unreg_netdev; 710 711 otx2vf_set_ethtool_ops(netdev); 712 713 err = otx2vf_mcam_flow_init(vf); 714 if (err) 715 goto err_unreg_netdev; 716 717 err = otx2_init_tc(vf); 718 if (err) 719 goto err_unreg_netdev; 720 721 err = otx2_register_dl(vf); 722 if (err) 723 goto err_shutdown_tc; 724 725 #ifdef CONFIG_DCB 726 err = otx2_dcbnl_set_ops(netdev); 727 if (err) 728 goto err_shutdown_tc; 729 #endif 730 otx2_qos_init(vf, qos_txqs); 731 732 return 0; 733 734 err_shutdown_tc: 735 otx2_shutdown_tc(vf); 736 err_unreg_netdev: 737 unregister_netdev(netdev); 738 err_ipsec_clean: 739 cn10k_ipsec_clean(vf); 740 err_ptp_destroy: 741 otx2_ptp_destroy(vf); 742 err_detach_rsrc: 743 free_percpu(vf->hw.lmt_info); 744 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag)) 745 qmem_free(vf->dev, vf->dync_lmt); 746 otx2_detach_resources(&vf->mbox); 747 err_disable_mbox_intr: 748 otx2vf_disable_mbox_intr(vf); 749 err_mbox_destroy: 750 otx2vf_vfaf_mbox_destroy(vf); 751 err_free_irq_vectors: 752 pci_free_irq_vectors(hw->pdev); 753 err_free_netdev: 754 pci_set_drvdata(pdev, NULL); 755 free_netdev(netdev); 756 err_release_regions: 757 pci_release_regions(pdev); 758 return err; 759 } 760 761 static void otx2vf_remove(struct pci_dev *pdev) 762 { 763 struct net_device *netdev = pci_get_drvdata(pdev); 764 struct otx2_nic *vf; 765 766 if (!netdev) 767 return; 768 769 vf = netdev_priv(netdev); 770 771 /* Disable 802.3x pause frames */ 772 if (vf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 773 (vf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 774 vf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 775 vf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 776 otx2_config_pause_frm(vf); 777 } 778 779 #ifdef CONFIG_DCB 780 /* Disable PFC config */ 781 if (vf->pfc_en) { 782 vf->pfc_en = 0; 783 otx2_config_priority_flow_ctrl(vf); 784 } 785 #endif 786 787 cancel_work_sync(&vf->reset_task); 788 otx2_unregister_dl(vf); 789 unregister_netdev(netdev); 790 if (vf->otx2_wq) 791 destroy_workqueue(vf->otx2_wq); 792 cn10k_ipsec_clean(vf); 793 otx2_ptp_destroy(vf); 794 otx2_mcam_flow_del(vf); 795 otx2_shutdown_tc(vf); 796 otx2_shutdown_qos(vf); 797 otx2_detach_resources(&vf->mbox); 798 otx2vf_disable_mbox_intr(vf); 799 free_percpu(vf->hw.lmt_info); 800 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag)) 801 qmem_free(vf->dev, vf->dync_lmt); 802 otx2vf_vfaf_mbox_destroy(vf); 803 pci_free_irq_vectors(vf->pdev); 804 pci_set_drvdata(pdev, NULL); 805 free_netdev(netdev); 806 807 pci_release_regions(pdev); 808 } 809 810 static struct pci_driver otx2vf_driver = { 811 .name = DRV_NAME, 812 .id_table = otx2_vf_id_table, 813 .probe = otx2vf_probe, 814 .remove = otx2vf_remove, 815 .shutdown = otx2vf_remove, 816 }; 817 818 static int __init otx2vf_init_module(void) 819 { 820 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 821 822 return pci_register_driver(&otx2vf_driver); 823 } 824 825 static void __exit otx2vf_cleanup_module(void) 826 { 827 pci_unregister_driver(&otx2vf_driver); 828 } 829 830 module_init(otx2vf_init_module); 831 module_exit(otx2vf_cleanup_module); 832