1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef OTX2_COMMON_H 9 #define OTX2_COMMON_H 10 11 #include <linux/ethtool.h> 12 #include <linux/pci.h> 13 #include <linux/iommu.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/ptp_clock_kernel.h> 16 #include <linux/timecounter.h> 17 #include <linux/soc/marvell/octeontx2/asm.h> 18 #include <net/macsec.h> 19 #include <net/pkt_cls.h> 20 #include <net/devlink.h> 21 #include <linux/time64.h> 22 #include <linux/dim.h> 23 #include <uapi/linux/if_macsec.h> 24 25 #include <mbox.h> 26 #include <npc.h> 27 #include "otx2_reg.h" 28 #include "otx2_txrx.h" 29 #include "otx2_devlink.h" 30 #include <rvu_trace.h> 31 #include "qos.h" 32 #include "rep.h" 33 #include "cn10k_ipsec.h" 34 35 /* IPv4 flag more fragment bit */ 36 #define IPV4_FLAG_MORE 0x20 37 38 /* PCI device IDs */ 39 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 40 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 41 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8 42 43 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 44 #define PCI_SUBSYS_DEVID_CN10K_A_RVU_PFVF 0xB900 45 #define PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF 0xBD00 46 47 #define PCI_DEVID_OCTEONTX2_SDP_REP 0xA0F7 48 49 /* PCI BAR nos */ 50 #define PCI_CFG_REG_BAR_NUM 2 51 #define PCI_MBOX_BAR_NUM 4 52 53 #define NAME_SIZE 32 54 55 #ifdef CONFIG_DCB 56 /* Max priority supported for PFC */ 57 #define NIX_PF_PFC_PRIO_MAX 8 58 #endif 59 60 /* Number of segments per SG structure */ 61 #define MAX_SEGS_PER_SG 3 62 63 enum arua_mapped_qtypes { 64 AURA_NIX_RQ, 65 AURA_NIX_SQ, 66 }; 67 68 /* NIX LF interrupts range*/ 69 #define NIX_LF_QINT_VEC_START 0x00 70 #define NIX_LF_CINT_VEC_START 0x40 71 #define NIX_LF_GINT_VEC 0x80 72 #define NIX_LF_ERR_VEC 0x81 73 #define NIX_LF_POISON_VEC 0x82 74 75 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 76 #define SEND_CQ_SKID 2000 77 78 #define OTX2_GET_RX_STATS(reg) \ 79 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 80 #define OTX2_GET_TX_STATS(reg) \ 81 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 82 83 struct otx2_lmt_info { 84 u64 lmt_addr; 85 u16 lmt_id; 86 }; 87 /* RSS configuration */ 88 struct otx2_rss_ctx { 89 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 90 }; 91 92 struct otx2_rss_info { 93 u8 enable; 94 u32 flowkey_cfg; 95 u16 rss_size; 96 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 97 u8 key[RSS_HASH_KEY_SIZE]; 98 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS]; 99 }; 100 101 /* NIX (or NPC) RX errors */ 102 enum otx2_errlvl { 103 NPC_ERRLVL_RE, 104 NPC_ERRLVL_LID_LA, 105 NPC_ERRLVL_LID_LB, 106 NPC_ERRLVL_LID_LC, 107 NPC_ERRLVL_LID_LD, 108 NPC_ERRLVL_LID_LE, 109 NPC_ERRLVL_LID_LF, 110 NPC_ERRLVL_LID_LG, 111 NPC_ERRLVL_LID_LH, 112 NPC_ERRLVL_NIX = 0x0F, 113 }; 114 115 enum otx2_errcodes_re { 116 /* NPC_ERRLVL_RE errcodes */ 117 ERRCODE_FCS = 0x7, 118 ERRCODE_FCS_RCV = 0x8, 119 ERRCODE_UNDERSIZE = 0x10, 120 ERRCODE_OVERSIZE = 0x11, 121 ERRCODE_OL2_LEN_MISMATCH = 0x12, 122 /* NPC_ERRLVL_NIX errcodes */ 123 ERRCODE_OL3_LEN = 0x10, 124 ERRCODE_OL4_LEN = 0x11, 125 ERRCODE_OL4_CSUM = 0x12, 126 ERRCODE_IL3_LEN = 0x20, 127 ERRCODE_IL4_LEN = 0x21, 128 ERRCODE_IL4_CSUM = 0x22, 129 }; 130 131 struct otx2_dev_stats { 132 u64 rx_bytes; 133 u64 rx_frames; 134 u64 rx_ucast_frames; 135 u64 rx_bcast_frames; 136 u64 rx_mcast_frames; 137 u64 rx_drops; 138 139 u64 tx_bytes; 140 u64 tx_frames; 141 u64 tx_ucast_frames; 142 u64 tx_bcast_frames; 143 u64 tx_mcast_frames; 144 u64 tx_drops; 145 }; 146 147 /* Driver counted stats */ 148 struct otx2_drv_stats { 149 atomic_t rx_fcs_errs; 150 atomic_t rx_oversize_errs; 151 atomic_t rx_undersize_errs; 152 atomic_t rx_csum_errs; 153 atomic_t rx_len_errs; 154 atomic_t rx_other_errs; 155 }; 156 157 struct mbox { 158 struct otx2_mbox mbox; 159 struct work_struct mbox_wrk; 160 struct otx2_mbox mbox_up; 161 struct work_struct mbox_up_wrk; 162 struct otx2_nic *pfvf; 163 void *bbuf_base; /* Bounce buffer for mbox memory */ 164 struct mutex lock; /* serialize mailbox access */ 165 int num_msgs; /* mbox number of messages */ 166 int up_num_msgs; /* mbox_up number of messages */ 167 }; 168 169 /* Egress rate limiting definitions */ 170 #define MAX_BURST_EXPONENT 0x0FULL 171 #define MAX_BURST_MANTISSA 0xFFULL 172 #define MAX_BURST_SIZE 130816ULL 173 #define MAX_RATE_DIVIDER_EXPONENT 12ULL 174 #define MAX_RATE_EXPONENT 0x0FULL 175 #define MAX_RATE_MANTISSA 0xFFULL 176 177 /* Bitfields in NIX_TLX_PIR register */ 178 #define TLX_RATE_MANTISSA GENMASK_ULL(8, 1) 179 #define TLX_RATE_EXPONENT GENMASK_ULL(12, 9) 180 #define TLX_RATE_DIVIDER_EXPONENT GENMASK_ULL(16, 13) 181 #define TLX_BURST_MANTISSA GENMASK_ULL(36, 29) 182 #define TLX_BURST_EXPONENT GENMASK_ULL(40, 37) 183 184 struct otx2_hw { 185 struct pci_dev *pdev; 186 struct otx2_rss_info rss_info; 187 u16 rx_queues; 188 u16 tx_queues; 189 u16 xdp_queues; 190 u16 tc_tx_queues; 191 u16 non_qos_queues; /* tx queues plus xdp queues */ 192 u16 max_queues; 193 u16 pool_cnt; 194 u16 rqpool_cnt; 195 u16 sqpool_cnt; 196 197 #define OTX2_DEFAULT_RBUF_LEN 2048 198 u16 rbuf_len; 199 u32 xqe_size; 200 201 /* NPA */ 202 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 203 u32 stack_pg_bytes; /* Size of stack page */ 204 u16 sqb_size; 205 206 /* NIX */ 207 u8 txschq_link_cfg_lvl; 208 u8 txschq_cnt[NIX_TXSCH_LVL_CNT]; 209 u8 txschq_aggr_lvl_rr_prio; 210 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 211 u16 matchall_ipolicer; 212 u32 dwrr_mtu; 213 u32 max_mtu; 214 u8 smq_link_type; 215 216 /* HW settings, coalescing etc */ 217 u16 rx_chan_base; 218 u16 tx_chan_base; 219 u8 rx_chan_cnt; 220 u8 tx_chan_cnt; 221 u16 cq_qcount_wait; 222 u16 cq_ecount_wait; 223 u16 rq_skid; 224 u8 cq_time_wait; 225 226 /* Segmentation */ 227 u8 lso_tsov4_idx; 228 u8 lso_tsov6_idx; 229 u8 lso_udpv4_idx; 230 u8 lso_udpv6_idx; 231 232 /* RSS */ 233 u8 flowkey_alg_idx; 234 235 /* MSI-X */ 236 u8 cint_cnt; /* CQ interrupt count */ 237 u16 npa_msixoff; /* Offset of NPA vectors */ 238 u16 nix_msixoff; /* Offset of NIX vectors */ 239 char *irq_name; 240 cpumask_var_t *affinity_mask; 241 242 /* Stats */ 243 struct otx2_dev_stats dev_stats; 244 struct otx2_drv_stats drv_stats; 245 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 246 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 247 u64 cgx_fec_corr_blks; 248 u64 cgx_fec_uncorr_blks; 249 u8 cgx_links; /* No. of CGX links present in HW */ 250 u8 lbk_links; /* No. of LBK links present in HW */ 251 u8 tx_link; /* Transmit channel link number */ 252 #define HW_TSO 0 253 #define CN10K_MBOX 1 254 #define CN10K_LMTST 2 255 #define CN10K_RPM 3 256 #define CN10K_PTP_ONESTEP 4 257 #define CN10K_HW_MACSEC 5 258 #define QOS_CIR_PIR_SUPPORT 6 259 unsigned long cap_flag; 260 261 #define LMT_LINE_SIZE 128 262 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */ 263 u64 *lmt_base; 264 struct otx2_lmt_info __percpu *lmt_info; 265 }; 266 267 enum vfperm { 268 OTX2_RESET_VF_PERM, 269 OTX2_TRUSTED_VF, 270 }; 271 272 struct otx2_vf_config { 273 struct otx2_nic *pf; 274 struct delayed_work link_event_work; 275 bool intf_down; /* interface was either configured or not */ 276 u8 mac[ETH_ALEN]; 277 u16 vlan; 278 int tx_vtag_idx; 279 bool trusted; 280 }; 281 282 struct flr_work { 283 struct work_struct work; 284 struct otx2_nic *pf; 285 }; 286 287 struct refill_work { 288 struct delayed_work pool_refill_work; 289 struct otx2_nic *pf; 290 struct napi_struct *napi; 291 }; 292 293 /* PTPv2 originTimestamp structure */ 294 struct ptpv2_tstamp { 295 __be16 seconds_msb; /* 16 bits + */ 296 __be32 seconds_lsb; /* 32 bits = 48 bits*/ 297 __be32 nanoseconds; 298 } __packed; 299 300 struct otx2_ptp { 301 struct ptp_clock_info ptp_info; 302 struct ptp_clock *ptp_clock; 303 struct otx2_nic *nic; 304 305 struct cyclecounter cycle_counter; 306 struct timecounter time_counter; 307 308 struct delayed_work extts_work; 309 u64 last_extts; 310 u64 thresh; 311 312 struct ptp_pin_desc extts_config; 313 u64 (*convert_rx_ptp_tstmp)(u64 timestamp); 314 u64 (*convert_tx_ptp_tstmp)(u64 timestamp); 315 u64 (*ptp_tstamp2nsec)(const struct timecounter *time_counter, u64 timestamp); 316 struct delayed_work synctstamp_work; 317 u64 tstamp; 318 u32 base_ns; 319 }; 320 321 #define OTX2_HW_TIMESTAMP_LEN 8 322 323 struct otx2_mac_table { 324 u8 addr[ETH_ALEN]; 325 u16 mcam_entry; 326 bool inuse; 327 }; 328 329 struct otx2_flow_config { 330 u16 *flow_ent; 331 u16 *def_ent; 332 u16 nr_flows; 333 #define OTX2_DEFAULT_FLOWCOUNT 16 334 #define OTX2_DEFAULT_UNICAST_FLOWS 4 335 #define OTX2_MAX_VLAN_FLOWS 1 336 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT 337 u16 unicast_offset; 338 u16 rx_vlan_offset; 339 u16 vf_vlan_offset; 340 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */ 341 #define OTX2_VF_VLAN_RX_INDEX 0 342 #define OTX2_VF_VLAN_TX_INDEX 1 343 u32 *bmap_to_dmacindex; 344 unsigned long *dmacflt_bmap; 345 struct list_head flow_list; 346 u32 dmacflt_max_flows; 347 u16 max_flows; 348 refcount_t mark_flows; 349 struct list_head flow_list_tc; 350 u8 ucast_flt_cnt; 351 bool ntuple; 352 }; 353 354 struct dev_hw_ops { 355 int (*sq_aq_init)(void *dev, u16 qidx, u8 chan_offset, 356 u16 sqb_aura); 357 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, 358 int size, int qidx); 359 int (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); 360 void (*aura_freeptr)(void *dev, int aura, u64 buf); 361 }; 362 363 #define CN10K_MCS_SA_PER_SC 4 364 365 /* Stats which need to be accumulated in software because 366 * of shared counters in hardware. 367 */ 368 struct cn10k_txsc_stats { 369 u64 InPktsUntagged; 370 u64 InPktsNoTag; 371 u64 InPktsBadTag; 372 u64 InPktsUnknownSCI; 373 u64 InPktsNoSCI; 374 u64 InPktsOverrun; 375 }; 376 377 struct cn10k_rxsc_stats { 378 u64 InOctetsValidated; 379 u64 InOctetsDecrypted; 380 u64 InPktsUnchecked; 381 u64 InPktsDelayed; 382 u64 InPktsOK; 383 u64 InPktsInvalid; 384 u64 InPktsLate; 385 u64 InPktsNotValid; 386 u64 InPktsNotUsingSA; 387 u64 InPktsUnusedSA; 388 }; 389 390 struct cn10k_mcs_txsc { 391 struct macsec_secy *sw_secy; 392 struct cn10k_txsc_stats stats; 393 struct list_head entry; 394 enum macsec_validation_type last_validate_frames; 395 bool last_replay_protect; 396 u16 hw_secy_id_tx; 397 u16 hw_secy_id_rx; 398 u16 hw_flow_id; 399 u16 hw_sc_id; 400 u16 hw_sa_id[CN10K_MCS_SA_PER_SC]; 401 u8 sa_bmap; 402 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN]; 403 u8 encoding_sa; 404 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN]; 405 ssci_t ssci[CN10K_MCS_SA_PER_SC]; 406 bool vlan_dev; /* macsec running on VLAN ? */ 407 }; 408 409 struct cn10k_mcs_rxsc { 410 struct macsec_secy *sw_secy; 411 struct macsec_rx_sc *sw_rxsc; 412 struct cn10k_rxsc_stats stats; 413 struct list_head entry; 414 u16 hw_flow_id; 415 u16 hw_sc_id; 416 u16 hw_sa_id[CN10K_MCS_SA_PER_SC]; 417 u8 sa_bmap; 418 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN]; 419 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN]; 420 ssci_t ssci[CN10K_MCS_SA_PER_SC]; 421 }; 422 423 struct cn10k_mcs_cfg { 424 struct list_head txsc_list; 425 struct list_head rxsc_list; 426 }; 427 428 struct otx2_nic { 429 void __iomem *reg_base; 430 struct net_device *netdev; 431 struct dev_hw_ops *hw_ops; 432 void *iommu_domain; 433 u16 tx_max_pktlen; 434 u16 rbsize; /* Receive buffer size */ 435 436 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0) 437 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1) 438 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 439 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3) 440 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4) 441 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5) 442 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6) 443 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7) 444 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8) 445 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) 446 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) 447 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11) 448 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12) 449 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13) 450 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14) 451 #define OTX2_FLAG_PTP_ONESTEP_SYNC BIT_ULL(15) 452 #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16) 453 #define OTX2_FLAG_TC_MARK_ENABLED BIT_ULL(17) 454 #define OTX2_FLAG_REP_MODE_ENABLED BIT_ULL(18) 455 #define OTX2_FLAG_PORT_UP BIT_ULL(19) 456 #define OTX2_FLAG_IPSEC_OFFLOAD_ENABLED BIT_ULL(20) 457 u64 flags; 458 u64 *cq_op_addr; 459 460 struct bpf_prog *xdp_prog; 461 struct otx2_qset qset; 462 struct otx2_hw hw; 463 struct pci_dev *pdev; 464 struct device *dev; 465 466 /* Mbox */ 467 struct mbox mbox; 468 struct mbox *mbox_pfvf; 469 struct workqueue_struct *mbox_wq; 470 struct workqueue_struct *mbox_pfvf_wq; 471 472 u8 total_vfs; 473 u16 pcifunc; /* RVU PF_FUNC */ 474 u16 bpid[NIX_MAX_BPID_CHAN]; 475 struct otx2_vf_config *vf_configs; 476 struct cgx_link_user_info linfo; 477 478 /* NPC MCAM */ 479 struct otx2_flow_config *flow_cfg; 480 struct otx2_mac_table *mac_table; 481 482 u64 reset_count; 483 struct work_struct reset_task; 484 struct workqueue_struct *flr_wq; 485 struct flr_work *flr_wrk; 486 struct refill_work *refill_wrk; 487 struct workqueue_struct *otx2_wq; 488 struct work_struct rx_mode_work; 489 490 /* Ethtool stuff */ 491 u32 msg_enable; 492 493 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 494 int nix_blkaddr; 495 /* LMTST Lines info */ 496 struct qmem *dync_lmt; 497 u16 tot_lmt_lines; 498 u16 npa_lmt_lines; 499 u32 nix_lmt_size; 500 501 struct otx2_ptp *ptp; 502 struct hwtstamp_config tstamp; 503 504 unsigned long rq_bmap; 505 506 /* Devlink */ 507 struct otx2_devlink *dl; 508 /* PFC */ 509 u8 pfc_en; 510 #ifdef CONFIG_DCB 511 u8 *queue_to_pfc_map; 512 u16 pfc_schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 513 bool pfc_alloc_status[NIX_PF_PFC_PRIO_MAX]; 514 #endif 515 /* qos */ 516 struct otx2_qos qos; 517 518 /* napi event count. It is needed for adaptive irq coalescing. */ 519 u32 napi_events; 520 521 #if IS_ENABLED(CONFIG_MACSEC) 522 struct cn10k_mcs_cfg *macsec_cfg; 523 #endif 524 525 #if IS_ENABLED(CONFIG_RVU_ESWITCH) 526 struct rep_dev **reps; 527 int rep_cnt; 528 u16 rep_pf_map[RVU_MAX_REP]; 529 u16 esw_mode; 530 #endif 531 532 /* Inline ipsec */ 533 struct cn10k_ipsec ipsec; 534 }; 535 536 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) 537 { 538 return (pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF) || 539 (pdev->device == PCI_DEVID_RVU_REP); 540 } 541 542 static inline bool is_96xx_A0(struct pci_dev *pdev) 543 { 544 return (pdev->revision == 0x00) && 545 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 546 } 547 548 static inline bool is_96xx_B0(struct pci_dev *pdev) 549 { 550 return (pdev->revision == 0x01) && 551 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 552 } 553 554 static inline bool is_otx2_sdp_rep(struct pci_dev *pdev) 555 { 556 return pdev->device == PCI_DEVID_OCTEONTX2_SDP_REP; 557 } 558 559 /* REVID for PCIe devices. 560 * Bits 0..1: minor pass, bit 3..2: major pass 561 * bits 7..4: midr id 562 */ 563 #define PCI_REVISION_ID_96XX 0x00 564 #define PCI_REVISION_ID_95XX 0x10 565 #define PCI_REVISION_ID_95XXN 0x20 566 #define PCI_REVISION_ID_98XX 0x30 567 #define PCI_REVISION_ID_95XXMM 0x40 568 #define PCI_REVISION_ID_95XXO 0xE0 569 570 static inline bool is_dev_otx2(struct pci_dev *pdev) 571 { 572 u8 midr = pdev->revision & 0xF0; 573 574 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 575 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 576 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 577 } 578 579 static inline bool is_dev_cn10kb(struct pci_dev *pdev) 580 { 581 return pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF; 582 } 583 584 static inline bool is_dev_cn10ka_b0(struct pci_dev *pdev) 585 { 586 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A_RVU_PFVF && 587 (pdev->revision & 0xFF) == 0x54) 588 return true; 589 590 return false; 591 } 592 593 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 594 { 595 struct otx2_hw *hw = &pfvf->hw; 596 597 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 598 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 599 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 600 601 __set_bit(HW_TSO, &hw->cap_flag); 602 603 if (is_96xx_A0(pfvf->pdev)) { 604 __clear_bit(HW_TSO, &hw->cap_flag); 605 606 /* Time based irq coalescing is not supported */ 607 pfvf->hw.cq_qcount_wait = 0x0; 608 609 /* Due to HW issue previous silicons required minimum 610 * 600 unused CQE to avoid CQ overflow. 611 */ 612 pfvf->hw.rq_skid = 600; 613 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 614 } 615 if (is_96xx_B0(pfvf->pdev)) 616 __clear_bit(HW_TSO, &hw->cap_flag); 617 618 if (!is_dev_otx2(pfvf->pdev)) { 619 __set_bit(CN10K_MBOX, &hw->cap_flag); 620 __set_bit(CN10K_LMTST, &hw->cap_flag); 621 __set_bit(CN10K_RPM, &hw->cap_flag); 622 __set_bit(CN10K_PTP_ONESTEP, &hw->cap_flag); 623 __set_bit(QOS_CIR_PIR_SUPPORT, &hw->cap_flag); 624 } 625 626 if (is_dev_cn10kb(pfvf->pdev)) 627 __set_bit(CN10K_HW_MACSEC, &hw->cap_flag); 628 } 629 630 /* Register read/write APIs */ 631 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 632 { 633 u64 blkaddr; 634 635 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 636 case BLKTYPE_NIX: 637 blkaddr = nic->nix_blkaddr; 638 break; 639 case BLKTYPE_NPA: 640 blkaddr = BLKADDR_NPA; 641 break; 642 case BLKTYPE_CPT: 643 blkaddr = BLKADDR_CPT0; 644 break; 645 default: 646 blkaddr = BLKADDR_RVUM; 647 break; 648 } 649 650 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 651 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 652 653 return nic->reg_base + offset; 654 } 655 656 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 657 { 658 void __iomem *addr = otx2_get_regaddr(nic, offset); 659 660 writeq(val, addr); 661 } 662 663 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 664 { 665 void __iomem *addr = otx2_get_regaddr(nic, offset); 666 667 return readq(addr); 668 } 669 670 /* Mbox bounce buffer APIs */ 671 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 672 { 673 struct otx2_mbox *otx2_mbox; 674 struct otx2_mbox_dev *mdev; 675 676 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 677 if (!mbox->bbuf_base) 678 return -ENOMEM; 679 680 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 681 * prepare all mbox messages in bounce buffer instead of directly 682 * in hw mbox memory. 683 */ 684 otx2_mbox = &mbox->mbox; 685 mdev = &otx2_mbox->dev[0]; 686 mdev->mbase = mbox->bbuf_base; 687 688 otx2_mbox = &mbox->mbox_up; 689 mdev = &otx2_mbox->dev[0]; 690 mdev->mbase = mbox->bbuf_base; 691 return 0; 692 } 693 694 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 695 { 696 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 697 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 698 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 699 struct mbox_hdr *hdr; 700 u64 msg_size; 701 702 if (mdev->mbase == hw_mbase) 703 return; 704 705 hdr = hw_mbase + mbox->rx_start; 706 msg_size = hdr->msg_size; 707 708 if (msg_size > mbox->rx_size - msgs_offset) 709 msg_size = mbox->rx_size - msgs_offset; 710 711 /* Copy mbox messages from mbox memory to bounce buffer */ 712 memcpy(mdev->mbase + mbox->rx_start, 713 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 714 } 715 716 /* With the absence of API for 128-bit IO memory access for arm64, 717 * implement required operations at place. 718 */ 719 #if defined(CONFIG_ARM64) 720 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 721 { 722 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 723 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 724 } 725 726 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr) 727 { 728 u64 result; 729 730 __asm__ volatile(".cpu generic+lse\n" 731 "ldadd %x[i], %x[r], [%[b]]" 732 : [r]"=r"(result), "+m"(*ptr) 733 : [i]"r"(incr), [b]"r"(ptr) 734 : "memory"); 735 return result; 736 } 737 738 #else 739 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr) 740 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; }) 741 #endif 742 743 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, 744 u64 *ptrs, u64 num_ptrs) 745 { 746 struct otx2_lmt_info *lmt_info; 747 u64 size = 0, count_eot = 0; 748 u64 tar_addr, val = 0; 749 750 lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id()); 751 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0); 752 /* LMTID is same as AURA Id */ 753 val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63); 754 /* Set if [127:64] of last 128bit word has a valid pointer */ 755 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL; 756 /* Set AURA ID to free pointer */ 757 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF); 758 /* Target address for LMTST flush tells HW how many 128bit 759 * words are valid from NPA_LF_AURA_BATCH_FREE0. 760 * 761 * tar_addr[6:4] is LMTST size-1 in units of 128b. 762 */ 763 if (num_ptrs > 2) { 764 size = (sizeof(u64) * num_ptrs) / 16; 765 if (!count_eot) 766 size++; 767 tar_addr |= ((size - 1) & 0x7) << 4; 768 } 769 dma_wmb(); 770 memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs); 771 /* Perform LMTST flush */ 772 cn10k_lmt_flush(val, tar_addr); 773 } 774 775 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) 776 { 777 struct otx2_nic *pfvf = dev; 778 u64 ptrs[2]; 779 780 ptrs[1] = buf; 781 get_cpu(); 782 /* Free only one buffer at time during init and teardown */ 783 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2); 784 put_cpu(); 785 } 786 787 /* Alloc pointer from pool/aura */ 788 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 789 { 790 u64 *ptr = (__force u64 *)otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_ALLOCX(0)); 791 u64 incr = (u64)aura | BIT_ULL(63); 792 793 return otx2_atomic64_add(incr, ptr); 794 } 795 796 /* Free pointer to a pool/aura */ 797 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) 798 { 799 struct otx2_nic *pfvf = dev; 800 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0); 801 802 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr); 803 } 804 805 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 806 { 807 if (type == AURA_NIX_SQ) 808 return pfvf->hw.rqpool_cnt + idx; 809 810 /* AURA_NIX_RQ */ 811 return idx; 812 } 813 814 /* Mbox APIs */ 815 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 816 { 817 int err; 818 819 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 820 return 0; 821 otx2_mbox_msg_send(&mbox->mbox, 0); 822 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 823 if (err) 824 return err; 825 826 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 827 } 828 829 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 830 { 831 int err; 832 833 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 834 return 0; 835 otx2_mbox_msg_send_up(&mbox->mbox_up, devid); 836 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 837 if (err) 838 return err; 839 840 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 841 } 842 843 /* Use this API to send mbox msgs in atomic context 844 * where sleeping is not allowed 845 */ 846 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 847 { 848 int err; 849 850 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 851 return 0; 852 otx2_mbox_msg_send(&mbox->mbox, 0); 853 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 854 if (err) 855 return err; 856 857 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 858 } 859 860 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 861 static struct _req_type __maybe_unused \ 862 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 863 { \ 864 struct _req_type *req; \ 865 \ 866 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 867 &mbox->mbox, 0, sizeof(struct _req_type), \ 868 sizeof(struct _rsp_type)); \ 869 if (!req) \ 870 return NULL; \ 871 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 872 req->hdr.id = _id; \ 873 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \ 874 return req; \ 875 } 876 877 MBOX_MESSAGES 878 #undef M 879 880 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 881 int \ 882 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 883 struct _req_type *req, \ 884 struct _rsp_type *rsp); \ 885 886 MBOX_UP_CGX_MESSAGES 887 MBOX_UP_MCS_MESSAGES 888 #undef M 889 890 /* Time to wait before watchdog kicks off */ 891 #define OTX2_TX_TIMEOUT (100 * HZ) 892 893 #define RVU_PFVF_PF_SHIFT 10 894 #define RVU_PFVF_PF_MASK 0x3F 895 #define RVU_PFVF_FUNC_SHIFT 0 896 #define RVU_PFVF_FUNC_MASK 0x3FF 897 898 static inline bool is_otx2_vf(u16 pcifunc) 899 { 900 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 901 } 902 903 static inline int rvu_get_pf(u16 pcifunc) 904 { 905 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 906 } 907 908 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 909 struct page *page, 910 size_t offset, size_t size, 911 enum dma_data_direction dir) 912 { 913 dma_addr_t iova; 914 915 iova = dma_map_page_attrs(pfvf->dev, page, 916 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 917 if (unlikely(dma_mapping_error(pfvf->dev, iova))) 918 return (dma_addr_t)NULL; 919 return iova; 920 } 921 922 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 923 dma_addr_t addr, size_t size, 924 enum dma_data_direction dir) 925 { 926 dma_unmap_page_attrs(pfvf->dev, addr, size, 927 dir, DMA_ATTR_SKIP_CPU_SYNC); 928 } 929 930 static inline u16 otx2_get_smq_idx(struct otx2_nic *pfvf, u16 qidx) 931 { 932 u16 smq; 933 int idx; 934 935 #ifdef CONFIG_DCB 936 if (qidx < NIX_PF_PFC_PRIO_MAX && pfvf->pfc_alloc_status[qidx]) 937 return pfvf->pfc_schq_list[NIX_TXSCH_LVL_SMQ][qidx]; 938 #endif 939 /* check if qidx falls under QOS queues */ 940 if (qidx >= pfvf->hw.non_qos_queues) { 941 smq = pfvf->qos.qid_to_sqmap[qidx - pfvf->hw.non_qos_queues]; 942 } else { 943 idx = qidx % pfvf->hw.txschq_cnt[NIX_TXSCH_LVL_SMQ]; 944 smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][idx]; 945 } 946 947 return smq; 948 } 949 950 static inline u16 otx2_get_total_tx_queues(struct otx2_nic *pfvf) 951 { 952 return pfvf->hw.non_qos_queues + pfvf->hw.tc_tx_queues; 953 } 954 955 static inline u64 otx2_convert_rate(u64 rate) 956 { 957 u64 converted_rate; 958 959 /* Convert bytes per second to Mbps */ 960 converted_rate = rate * 8; 961 converted_rate = max_t(u64, converted_rate / 1000000, 1); 962 963 return converted_rate; 964 } 965 966 static inline int otx2_tc_flower_rule_cnt(struct otx2_nic *pfvf) 967 { 968 /* return here if MCAM entries not allocated */ 969 if (!pfvf->flow_cfg) 970 return 0; 971 972 return pfvf->flow_cfg->nr_flows; 973 } 974 975 /* MSI-X APIs */ 976 void otx2_free_cints(struct otx2_nic *pfvf, int n); 977 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 978 int otx2_set_mac_address(struct net_device *netdev, void *p); 979 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 980 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 981 void otx2_get_mac_from_af(struct net_device *netdev); 982 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 983 int otx2_config_pause_frm(struct otx2_nic *pfvf); 984 void otx2_setup_segmentation(struct otx2_nic *pfvf); 985 int otx2_reset_mac_stats(struct otx2_nic *pfvf); 986 987 /* RVU block related APIs */ 988 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 989 int otx2_detach_resources(struct mbox *mbox); 990 int otx2_config_npa(struct otx2_nic *pfvf); 991 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 992 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 993 void otx2_aura_pool_free(struct otx2_nic *pfvf); 994 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 995 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 996 int otx2_config_nix(struct otx2_nic *pfvf); 997 int otx2_config_nix_queues(struct otx2_nic *pfvf); 998 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool pfc_en); 999 int otx2_txsch_alloc(struct otx2_nic *pfvf); 1000 void otx2_txschq_stop(struct otx2_nic *pfvf); 1001 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq); 1002 void otx2_free_pending_sqe(struct otx2_nic *pfvf); 1003 void otx2_sqb_flush(struct otx2_nic *pfvf); 1004 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 1005 dma_addr_t *dma); 1006 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 1007 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 1008 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); 1009 int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable); 1010 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, int qidx); 1011 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 1012 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura); 1013 int otx2_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura); 1014 int cn10k_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura); 1015 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 1016 dma_addr_t *dma); 1017 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1018 int stack_pages, int numptrs, int buf_size, int type); 1019 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1020 int pool_id, int numptrs); 1021 int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf); 1022 void otx2_free_queue_mem(struct otx2_qset *qset); 1023 int otx2_alloc_queue_mem(struct otx2_nic *pf); 1024 int otx2_init_hw_resources(struct otx2_nic *pfvf); 1025 void otx2_free_hw_resources(struct otx2_nic *pf); 1026 int otx2_wq_init(struct otx2_nic *pf); 1027 int otx2_check_pf_usable(struct otx2_nic *pf); 1028 int otx2_pfaf_mbox_init(struct otx2_nic *pf); 1029 int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af); 1030 int otx2_realloc_msix_vectors(struct otx2_nic *pf); 1031 void otx2_pfaf_mbox_destroy(struct otx2_nic *pf); 1032 void otx2_disable_mbox_intr(struct otx2_nic *pf); 1033 void otx2_disable_napi(struct otx2_nic *pf); 1034 irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq); 1035 1036 /* RSS configuration APIs*/ 1037 int otx2_rss_init(struct otx2_nic *pfvf); 1038 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 1039 void otx2_set_rss_key(struct otx2_nic *pfvf); 1040 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id); 1041 1042 /* Mbox handlers */ 1043 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1044 struct msix_offset_rsp *rsp); 1045 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1046 struct npa_lf_alloc_rsp *rsp); 1047 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1048 struct nix_lf_alloc_rsp *rsp); 1049 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1050 struct nix_txsch_alloc_rsp *rsp); 1051 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1052 struct cgx_stats_rsp *rsp); 1053 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1054 struct cgx_fec_stats_rsp *rsp); 1055 void otx2_set_fec_stats_count(struct otx2_nic *pfvf); 1056 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1057 struct nix_bp_cfg_rsp *rsp); 1058 1059 /* Device stats APIs */ 1060 void otx2_get_dev_stats(struct otx2_nic *pfvf); 1061 void otx2_get_stats64(struct net_device *netdev, 1062 struct rtnl_link_stats64 *stats); 1063 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 1064 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf); 1065 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 1066 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 1067 void otx2_set_ethtool_ops(struct net_device *netdev); 1068 void otx2vf_set_ethtool_ops(struct net_device *netdev); 1069 1070 int otx2_open(struct net_device *netdev); 1071 int otx2_stop(struct net_device *netdev); 1072 int otx2_set_real_num_queues(struct net_device *netdev, 1073 int tx_queues, int rx_queues); 1074 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd); 1075 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr); 1076 1077 /* MCAM filter related APIs */ 1078 int otx2_mcam_flow_init(struct otx2_nic *pf); 1079 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf); 1080 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count); 1081 void otx2_mcam_flow_del(struct otx2_nic *pf); 1082 int otx2_destroy_ntuple_flows(struct otx2_nic *pf); 1083 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf); 1084 int otx2_get_flow(struct otx2_nic *pfvf, 1085 struct ethtool_rxnfc *nfc, u32 location); 1086 int otx2_get_all_flows(struct otx2_nic *pfvf, 1087 struct ethtool_rxnfc *nfc, u32 *rule_locs); 1088 int otx2_add_flow(struct otx2_nic *pfvf, 1089 struct ethtool_rxnfc *nfc); 1090 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location); 1091 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg); 1092 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id); 1093 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac); 1094 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac); 1095 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable); 1096 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf); 1097 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx); 1098 u16 otx2_get_max_mtu(struct otx2_nic *pfvf); 1099 int otx2_handle_ntuple_tc_features(struct net_device *netdev, 1100 netdev_features_t features); 1101 int otx2_smq_flush(struct otx2_nic *pfvf, int smq); 1102 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool, 1103 u64 iova, int size); 1104 int otx2_mcam_entry_init(struct otx2_nic *pfvf); 1105 1106 /* tc support */ 1107 int otx2_init_tc(struct otx2_nic *nic); 1108 void otx2_shutdown_tc(struct otx2_nic *nic); 1109 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type, 1110 void *type_data); 1111 void otx2_tc_apply_ingress_police_rules(struct otx2_nic *nic); 1112 1113 /* CGX/RPM DMAC filters support */ 1114 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf); 1115 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 1116 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 1117 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u32 bit_pos); 1118 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf); 1119 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf); 1120 1121 #ifdef CONFIG_DCB 1122 /* DCB support*/ 1123 void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx, bool pfc_enable); 1124 int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf); 1125 int otx2_dcbnl_set_ops(struct net_device *dev); 1126 /* PFC support */ 1127 int otx2_pfc_txschq_config(struct otx2_nic *pfvf); 1128 int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf); 1129 int otx2_pfc_txschq_update(struct otx2_nic *pfvf); 1130 int otx2_pfc_txschq_stop(struct otx2_nic *pfvf); 1131 #endif 1132 1133 #if IS_ENABLED(CONFIG_MACSEC) 1134 /* MACSEC offload support */ 1135 int cn10k_mcs_init(struct otx2_nic *pfvf); 1136 void cn10k_mcs_free(struct otx2_nic *pfvf); 1137 void cn10k_handle_mcs_event(struct otx2_nic *pfvf, struct mcs_intr_info *event); 1138 #else 1139 static inline int cn10k_mcs_init(struct otx2_nic *pfvf) { return 0; } 1140 static inline void cn10k_mcs_free(struct otx2_nic *pfvf) {} 1141 static inline void cn10k_handle_mcs_event(struct otx2_nic *pfvf, 1142 struct mcs_intr_info *event) 1143 {} 1144 #endif /* CONFIG_MACSEC */ 1145 1146 /* qos support */ 1147 static inline void otx2_qos_init(struct otx2_nic *pfvf, int qos_txqs) 1148 { 1149 struct otx2_hw *hw = &pfvf->hw; 1150 1151 hw->tc_tx_queues = qos_txqs; 1152 INIT_LIST_HEAD(&pfvf->qos.qos_tree); 1153 mutex_init(&pfvf->qos.qos_lock); 1154 } 1155 1156 static inline void otx2_shutdown_qos(struct otx2_nic *pfvf) 1157 { 1158 mutex_destroy(&pfvf->qos.qos_lock); 1159 } 1160 1161 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 1162 struct net_device *sb_dev); 1163 int otx2_get_txq_by_classid(struct otx2_nic *pfvf, u16 classid); 1164 void otx2_qos_config_txschq(struct otx2_nic *pfvf); 1165 void otx2_clean_qos_queues(struct otx2_nic *pfvf); 1166 int rvu_event_up_notify(struct otx2_nic *pf, struct rep_event *info); 1167 int otx2_setup_tc_cls_flower(struct otx2_nic *nic, 1168 struct flow_cls_offload *cls_flower); 1169 1170 static inline int mcam_entry_cmp(const void *a, const void *b) 1171 { 1172 return *(u16 *)a - *(u16 *)b; 1173 } 1174 1175 dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf, 1176 struct sk_buff *skb, int seg, int *len); 1177 void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg); 1178 #endif /* OTX2_COMMON_H */ 1179