1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef RVU_H 9 #define RVU_H 10 11 #include <linux/pci.h> 12 #include <net/devlink.h> 13 #include <linux/soc/marvell/silicons.h> 14 15 #include "rvu_struct.h" 16 #include "rvu_devlink.h" 17 #include "common.h" 18 #include "mbox.h" 19 #include "npc.h" 20 #include "rvu_reg.h" 21 #include "ptp.h" 22 23 /* PCI device IDs */ 24 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 25 #define PCI_DEVID_OCTEONTX2_LBK 0xA061 26 27 /* Subsystem Device ID */ 28 #define PCI_SUBSYS_DEVID_98XX 0xB100 29 #define PCI_SUBSYS_DEVID_96XX 0xB200 30 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900 31 #define PCI_SUBSYS_DEVID_CNF10K_A 0xBA00 32 #define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00 33 #define PCI_SUBSYS_DEVID_CN10K_B 0xBD00 34 #define PCI_SUBSYS_DEVID_CN20KA 0xC220 35 #define PCI_SUBSYS_DEVID_CNF20KA 0xC320 36 37 /* PCI BAR nos */ 38 #define PCI_AF_REG_BAR_NUM 0 39 #define PCI_PF_REG_BAR_NUM 2 40 #define PCI_MBOX_BAR_NUM 4 41 42 #define NAME_SIZE 32 43 #define MAX_NIX_BLKS 2 44 #define MAX_CPT_BLKS 2 45 46 /* PF_FUNC */ 47 #define RVU_OTX2_PFVF_PF_SHIFT 10 48 #define RVU_OTX2_PFVF_PF_MASK 0x3F 49 #define RVU_PFVF_FUNC_SHIFT 0 50 #define RVU_PFVF_FUNC_MASK 0x3FF 51 #define RVU_CN20K_PFVF_PF_SHIFT 9 52 #define RVU_CN20K_PFVF_PF_MASK 0x7F 53 54 static inline u16 rvu_make_pcifunc(struct pci_dev *pdev, int pf, int func) 55 { 56 if (is_cn20k(pdev)) 57 return ((pf & RVU_CN20K_PFVF_PF_MASK) << 58 RVU_CN20K_PFVF_PF_SHIFT) | 59 ((func & RVU_PFVF_FUNC_MASK) << 60 RVU_PFVF_FUNC_SHIFT); 61 else 62 return ((pf & RVU_OTX2_PFVF_PF_MASK) << 63 RVU_OTX2_PFVF_PF_SHIFT) | 64 ((func & RVU_PFVF_FUNC_MASK) << 65 RVU_PFVF_FUNC_SHIFT); 66 } 67 68 static inline int rvu_pcifunc_pf_mask(struct pci_dev *pdev) 69 { 70 if (is_cn20k(pdev)) 71 return ~(RVU_CN20K_PFVF_PF_MASK << RVU_CN20K_PFVF_PF_SHIFT); 72 else 73 return ~(RVU_OTX2_PFVF_PF_MASK << RVU_OTX2_PFVF_PF_SHIFT); 74 } 75 76 #ifdef CONFIG_DEBUG_FS 77 struct dump_ctx { 78 int lf; 79 int id; 80 bool all; 81 }; 82 83 struct cpt_ctx { 84 int blkaddr; 85 struct rvu *rvu; 86 }; 87 88 struct rvu_debugfs { 89 struct dentry *root; 90 struct dentry *cgx_root; 91 struct dentry *cgx; 92 struct dentry *lmac; 93 struct dentry *npa; 94 struct dentry *nix; 95 struct dentry *npc; 96 struct dentry *cpt; 97 struct dentry *mcs_root; 98 struct dentry *mcs; 99 struct dentry *mcs_rx; 100 struct dentry *mcs_tx; 101 struct dump_ctx npa_aura_ctx; 102 struct dump_ctx npa_pool_ctx; 103 struct dump_ctx nix_cq_ctx; 104 struct dump_ctx nix_rq_ctx; 105 struct dump_ctx nix_sq_ctx; 106 struct dump_ctx nix_tm_ctx; 107 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS]; 108 int npa_qsize_id; 109 int nix_qsize_id; 110 }; 111 #endif 112 113 struct rvu_work { 114 struct work_struct work; 115 struct rvu *rvu; 116 int num_msgs; 117 int up_num_msgs; 118 }; 119 120 struct rsrc_bmap { 121 unsigned long *bmap; /* Pointer to resource bitmap */ 122 u16 max; /* Max resource id or count */ 123 }; 124 125 struct rvu_block { 126 struct rsrc_bmap lf; 127 struct admin_queue *aq; /* NIX/NPA AQ */ 128 u16 *fn_map; /* LF to pcifunc mapping */ 129 bool multislot; 130 bool implemented; 131 u8 addr; /* RVU_BLOCK_ADDR_E */ 132 u8 type; /* RVU_BLOCK_TYPE_E */ 133 u8 lfshift; 134 u64 lookup_reg; 135 u64 pf_lfcnt_reg; 136 u64 vf_lfcnt_reg; 137 u64 lfcfg_reg; 138 u64 msixcfg_reg; 139 u64 lfreset_reg; 140 unsigned char name[NAME_SIZE]; 141 struct rvu *rvu; 142 u64 cpt_flt_eng_map[3]; 143 u64 cpt_rcvrd_eng_map[3]; 144 }; 145 146 struct nix_mcast { 147 struct qmem *mce_ctx; 148 struct qmem *mcast_buf; 149 int replay_pkind; 150 struct rsrc_bmap mce_counter[2]; 151 /* Counters for both ingress and egress mcast lists */ 152 struct mutex mce_lock; /* Serialize MCE updates */ 153 }; 154 155 struct nix_mce_list { 156 struct hlist_head head; 157 int count; 158 int max; 159 }; 160 161 struct nix_mcast_grp_elem { 162 struct nix_mce_list mcast_mce_list; 163 u32 mcast_grp_idx; 164 u32 pcifunc; 165 int mcam_index; 166 int mce_start_index; 167 struct list_head list; 168 u8 dir; 169 }; 170 171 struct nix_mcast_grp { 172 struct list_head mcast_grp_head; 173 int count; 174 int next_grp_index; 175 struct mutex mcast_grp_lock; /* Serialize MCE updates */ 176 }; 177 178 /* layer metadata to uniquely identify a packet header field */ 179 struct npc_layer_mdata { 180 u8 lid; 181 u8 ltype; 182 u8 hdr; 183 u8 key; 184 u8 len; 185 }; 186 187 /* Structure to represent a field present in the 188 * generated key. A key field may present anywhere and can 189 * be of any size in the generated key. Once this structure 190 * is populated for fields of interest then field's presence 191 * and location (if present) can be known. 192 */ 193 struct npc_key_field { 194 /* Masks where all set bits indicate position 195 * of a field in the key 196 */ 197 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 198 /* Number of words in the key a field spans. If a field is 199 * of 16 bytes and key offset is 4 then the field will use 200 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and 201 * nr_kws will be 3(KW0, KW1 and KW2). 202 */ 203 int nr_kws; 204 /* used by packet header fields */ 205 struct npc_layer_mdata layer_mdata; 206 }; 207 208 struct npc_mcam { 209 struct rsrc_bmap counters; 210 struct mutex lock; /* MCAM entries and counters update lock */ 211 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 212 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 213 u16 bmap_entries; /* Number of unreserved MCAM entries */ 214 u16 bmap_fcnt; /* MCAM entries free count */ 215 u16 *entry2pfvf_map; 216 u16 *entry2cntr_map; 217 u16 *cntr2pfvf_map; 218 u16 *cntr_refcnt; 219 u16 *entry2target_pffunc; 220 u8 keysize; /* MCAM keysize 112/224/448 bits */ 221 u8 banks; /* Number of MCAM banks */ 222 u8 banks_per_entry;/* Number of keywords in key */ 223 u16 banksize; /* Number of MCAM entries in each bank */ 224 u16 total_entries; /* Total number of MCAM entries */ 225 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 226 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 227 u16 lprio_count; 228 u16 lprio_start; 229 u16 hprio_count; 230 u16 hprio_end; 231 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 232 /* fields present in the generated key */ 233 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX]; 234 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX]; 235 u64 tx_features; 236 u64 rx_features; 237 struct list_head mcam_rules; 238 }; 239 240 /* Structure for per RVU func info ie PF/VF */ 241 struct rvu_pfvf { 242 bool npalf; /* Only one NPALF per RVU_FUNC */ 243 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 244 u16 sso; 245 u16 ssow; 246 u16 cptlfs; 247 u16 timlfs; 248 u16 cpt1_lfs; 249 u8 cgx_lmac; 250 251 /* Block LF's MSIX vector info */ 252 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 253 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 254 u16 *msix_lfmap; /* Vector to block LF mapping */ 255 256 /* NPA contexts */ 257 struct qmem *aura_ctx; 258 struct qmem *pool_ctx; 259 struct qmem *npa_qints_ctx; 260 unsigned long *aura_bmap; 261 unsigned long *pool_bmap; 262 263 /* NIX contexts */ 264 struct qmem *rq_ctx; 265 struct qmem *sq_ctx; 266 struct qmem *cq_ctx; 267 struct qmem *rss_ctx; 268 struct qmem *cq_ints_ctx; 269 struct qmem *nix_qints_ctx; 270 unsigned long *sq_bmap; 271 unsigned long *rq_bmap; 272 unsigned long *cq_bmap; 273 274 u16 rx_chan_base; 275 u16 tx_chan_base; 276 u8 rx_chan_cnt; /* total number of RX channels */ 277 u8 tx_chan_cnt; /* total number of TX channels */ 278 u16 maxlen; 279 u16 minlen; 280 281 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */ 282 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 283 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ 284 285 /* Broadcast/Multicast/Promisc pkt replication info */ 286 u16 bcast_mce_idx; 287 u16 mcast_mce_idx; 288 u16 promisc_mce_idx; 289 struct nix_mce_list bcast_mce_list; 290 struct nix_mce_list mcast_mce_list; 291 struct nix_mce_list promisc_mce_list; 292 bool use_mce_list; 293 294 struct rvu_npc_mcam_rule *def_ucast_rule; 295 296 bool cgx_in_use; /* this PF/VF using CGX? */ 297 int cgx_users; /* number of cgx users - used only by PFs */ 298 299 int intf_mode; 300 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 301 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */ 302 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ 303 u8 lbkid; /* NIX0/1 lbk link ID */ 304 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/ 305 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/ 306 unsigned long flags; 307 struct sdp_node_info *sdp_info; 308 }; 309 310 enum rvu_pfvf_flags { 311 NIXLF_INITIALIZED = 0, 312 PF_SET_VF_MAC, 313 PF_SET_VF_CFG, 314 PF_SET_VF_TRUSTED, 315 }; 316 317 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC) 318 319 struct nix_bp { 320 struct rsrc_bmap bpids; /* free bpids bitmap */ 321 u16 cgx_bpid_cnt; 322 u16 sdp_bpid_cnt; 323 u16 free_pool_base; 324 u16 *fn_map; /* pcifunc mapping */ 325 u8 *intf_map; /* interface type map */ 326 u8 *ref_cnt; 327 }; 328 329 struct nix_txsch { 330 struct rsrc_bmap schq; 331 u8 lvl; 332 #define NIX_TXSCHQ_FREE BIT_ULL(1) 333 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 334 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 335 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 336 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 337 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 338 u32 *pfvf_map; 339 }; 340 341 struct nix_mark_format { 342 u8 total; 343 u8 in_use; 344 u32 *cfg; 345 }; 346 347 /* smq(flush) to tl1 cir/pir info */ 348 struct nix_smq_tree_ctx { 349 u16 schq; 350 u64 cir_off; 351 u64 cir_val; 352 u64 pir_off; 353 u64 pir_val; 354 }; 355 356 /* smq flush context */ 357 struct nix_smq_flush_ctx { 358 int smq; 359 struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT]; 360 }; 361 362 struct npc_pkind { 363 struct rsrc_bmap rsrc; 364 u32 *pfchan_map; 365 }; 366 367 struct nix_flowkey { 368 #define NIX_FLOW_KEY_ALG_MAX 32 369 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 370 int in_use; 371 }; 372 373 struct nix_lso { 374 u8 total; 375 u8 in_use; 376 }; 377 378 struct nix_txvlan { 379 #define NIX_TX_VTAG_DEF_MAX 0x400 380 struct rsrc_bmap rsrc; 381 u16 *entry2pfvf_map; 382 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 383 }; 384 385 struct nix_ipolicer { 386 struct rsrc_bmap band_prof; 387 u16 *pfvf_map; 388 u16 *match_id; 389 u16 *ref_count; 390 }; 391 392 struct nix_hw { 393 int blkaddr; 394 struct rvu *rvu; 395 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 396 struct nix_mcast mcast; 397 struct nix_mcast_grp mcast_grp; 398 struct nix_flowkey flowkey; 399 struct nix_mark_format mark_format; 400 struct nix_lso lso; 401 struct nix_txvlan txvlan; 402 struct nix_ipolicer *ipolicer; 403 struct nix_bp bp; 404 u64 *tx_credits; 405 u8 cc_mcs_cnt; 406 }; 407 408 /* RVU block's capabilities or functionality, 409 * which vary by silicon version/skew. 410 */ 411 struct hw_cap { 412 /* Transmit side supported functionality */ 413 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 414 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 415 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 416 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 417 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 418 bool nix_shaping; /* Is shaping and coloring supported */ 419 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */ 420 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 421 bool nix_rx_multicast; /* Rx packet replication support */ 422 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */ 423 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */ 424 bool programmable_chans; /* Channels programmable ? */ 425 bool ipolicer; 426 bool nix_multiple_dwrr_mtu; /* Multiple DWRR_MTU to choose from */ 427 bool npc_hash_extract; /* Hash extract enabled ? */ 428 bool npc_exact_match_enabled; /* Exact match supported ? */ 429 bool cpt_rxc; /* Is CPT-RXC supported */ 430 }; 431 432 struct rvu_hwinfo { 433 u8 total_pfs; /* MAX RVU PFs HW supports */ 434 u16 total_vfs; /* Max RVU VFs HW supports */ 435 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 436 u8 cgx; 437 u8 lmac_per_cgx; 438 u16 cgx_chan_base; /* CGX base channel number */ 439 u16 lbk_chan_base; /* LBK base channel number */ 440 u16 sdp_chan_base; /* SDP base channel number */ 441 u16 cpt_chan_base; /* CPT base channel number */ 442 u8 cgx_links; 443 u8 lbk_links; 444 u8 sdp_links; 445 u8 cpt_links; /* Number of CPT links */ 446 u8 npc_kpus; /* No of parser units */ 447 u8 npc_pkinds; /* No of port kinds */ 448 u8 npc_intfs; /* No of interfaces */ 449 u8 npc_kpu_entries; /* No of KPU entries */ 450 u16 npc_counters; /* No of match stats counters */ 451 u32 lbk_bufsize; /* FIFO size supported by LBK */ 452 bool npc_ext_set; /* Extended register set */ 453 u64 npc_stat_ena; /* Match stats enable bit */ 454 455 struct hw_cap cap; 456 struct rvu_block block[BLK_COUNT]; /* Block info */ 457 struct nix_hw *nix; 458 struct rvu *rvu; 459 struct npc_pkind pkind; 460 struct npc_mcam mcam; 461 struct npc_exact_table *table; 462 }; 463 464 struct mbox_wq_info { 465 struct otx2_mbox mbox; 466 struct rvu_work *mbox_wrk; 467 468 struct otx2_mbox mbox_up; 469 struct rvu_work *mbox_wrk_up; 470 471 struct workqueue_struct *mbox_wq; 472 }; 473 474 struct channel_fwdata { 475 struct sdp_node_info info; 476 u8 valid; 477 #define RVU_CHANL_INFO_RESERVED 379 478 u8 reserved[RVU_CHANL_INFO_RESERVED]; 479 }; 480 481 struct rvu_fwdata { 482 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 483 #define RVU_FWDATA_VERSION 0x0001 484 u32 header_magic; 485 u32 version; /* version id */ 486 487 /* MAC address */ 488 #define PF_MACNUM_MAX 32 489 #define VF_MACNUM_MAX 256 490 u64 pf_macs[PF_MACNUM_MAX]; 491 u64 vf_macs[VF_MACNUM_MAX]; 492 u64 sclk; 493 u64 rclk; 494 u64 mcam_addr; 495 u64 mcam_sz; 496 u64 msixtr_base; 497 u32 ptp_ext_clk_rate; 498 u32 ptp_ext_tstamp; 499 struct channel_fwdata channel_data; 500 #define FWDATA_RESERVED_MEM 958 501 u64 reserved[FWDATA_RESERVED_MEM]; 502 #define CGX_MAX 9 503 #define CGX_LMACS_MAX 4 504 #define CGX_LMACS_USX 8 505 #define FWDATA_CGX_LMAC_OFFSET 10536 506 union { 507 struct cgx_lmac_fwdata_s 508 cgx_fw_data[CGX_MAX][CGX_LMACS_MAX]; 509 struct cgx_lmac_fwdata_s 510 cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX]; 511 }; 512 /* Do not add new fields below this line */ 513 }; 514 515 struct ptp; 516 517 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 518 * source where it came from. 519 */ 520 struct npc_kpu_profile_adapter { 521 const char *name; 522 u64 version; 523 const struct npc_lt_def_cfg *lt_def; 524 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 525 const struct npc_kpu_profile *kpu; /* array[kpus] */ 526 struct npc_mcam_kex *mkex; 527 struct npc_mcam_kex_hash *mkex_hash; 528 bool custom; 529 size_t pkinds; 530 size_t kpus; 531 }; 532 533 #define RVU_SWITCH_LBK_CHAN 63 534 535 struct rvu_switch { 536 struct mutex switch_lock; /* Serialize flow installation */ 537 u32 used_entries; 538 u16 *entry2pcifunc; 539 u16 mode; 540 u16 start_entry; 541 }; 542 543 struct rep_evtq_ent { 544 struct list_head node; 545 struct rep_event event; 546 }; 547 548 struct rvu { 549 void __iomem *afreg_base; 550 void __iomem *pfreg_base; 551 struct pci_dev *pdev; 552 struct device *dev; 553 struct rvu_hwinfo *hw; 554 struct rvu_pfvf *pf; 555 struct rvu_pfvf *hwvf; 556 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 557 struct mutex alias_lock; /* Serialize bar2 alias access */ 558 int vfs; /* Number of VFs attached to RVU */ 559 u16 vf_devid; /* VF devices id */ 560 bool def_rule_cntr_en; 561 int nix_blkaddr[MAX_NIX_BLKS]; 562 563 /* Mbox */ 564 struct mbox_wq_info afpf_wq_info; 565 struct mbox_wq_info afvf_wq_info; 566 567 /* PF FLR */ 568 struct rvu_work *flr_wrk; 569 struct workqueue_struct *flr_wq; 570 struct mutex flr_lock; /* Serialize FLRs */ 571 572 /* MSI-X */ 573 u16 num_vec; 574 char *irq_name; 575 bool *irq_allocated; 576 dma_addr_t msix_base_iova; 577 u64 msixtr_base_phy; /* Register reset value */ 578 579 /* CGX */ 580 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 581 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */ 582 u8 cgx_mapped_pfs; 583 u8 cgx_cnt_max; /* CGX port count max */ 584 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 585 u64 *cgxlmac2pf_map; /* bitmap of mapped pfs for 586 * every cgx lmac port 587 */ 588 unsigned long pf_notify_bmap; /* Flags for PF notification */ 589 void **cgx_idmap; /* cgx id to cgx data map table */ 590 struct work_struct cgx_evh_work; 591 struct workqueue_struct *cgx_evh_wq; 592 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 593 struct list_head cgx_evq_head; /* cgx event queue head */ 594 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 595 596 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 597 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */ 598 599 /* Firmware data */ 600 struct rvu_fwdata *fwdata; 601 void *kpu_fwdata; 602 size_t kpu_fwdata_sz; 603 void __iomem *kpu_prfl_addr; 604 605 /* NPC KPU data */ 606 struct npc_kpu_profile_adapter kpu; 607 608 struct ptp *ptp; 609 610 int mcs_blk_cnt; 611 int cpt_pf_num; 612 613 #ifdef CONFIG_DEBUG_FS 614 struct rvu_debugfs rvu_dbg; 615 #endif 616 struct rvu_devlink *rvu_dl; 617 618 /* RVU switch implementation over NPC with DMAC rules */ 619 struct rvu_switch rswitch; 620 621 struct work_struct mcs_intr_work; 622 struct workqueue_struct *mcs_intr_wq; 623 struct list_head mcs_intrq_head; 624 /* mcs interrupt queue lock */ 625 spinlock_t mcs_intrq_lock; 626 /* CPT interrupt lock */ 627 spinlock_t cpt_intr_lock; 628 629 struct mutex mbox_lock; /* Serialize mbox up and down msgs */ 630 u16 rep_pcifunc; 631 int rep_cnt; 632 u16 *rep2pfvf_map; 633 u8 rep_mode; 634 struct work_struct rep_evt_work; 635 struct workqueue_struct *rep_evt_wq; 636 struct list_head rep_evtq_head; 637 /* Representor event lock */ 638 spinlock_t rep_evtq_lock; 639 }; 640 641 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 642 { 643 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 644 } 645 646 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 647 { 648 return readq(rvu->afreg_base + ((block << 28) | offset)); 649 } 650 651 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 652 { 653 writeq(val, rvu->pfreg_base + offset); 654 } 655 656 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 657 { 658 return readq(rvu->pfreg_base + offset); 659 } 660 661 static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 662 { 663 /* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of 664 * write operation. 665 */ 666 rvu_write64(rvu, block, offset, val); 667 rvu_read64(rvu, block, offset); 668 /* Barrier to ensure read completes before accessing LF registers */ 669 mb(); 670 } 671 672 /* Silicon revisions */ 673 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu) 674 { 675 struct pci_dev *pdev = rvu->pdev; 676 /* 96XX A0/B0, 95XX A0/A1/B0 chips */ 677 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) || 678 (pdev->revision == 0x10) || (pdev->revision == 0x11) || 679 (pdev->revision == 0x14)); 680 } 681 682 static inline bool is_rvu_96xx_A0(struct rvu *rvu) 683 { 684 struct pci_dev *pdev = rvu->pdev; 685 686 return (pdev->revision == 0x00); 687 } 688 689 static inline bool is_rvu_96xx_B0(struct rvu *rvu) 690 { 691 struct pci_dev *pdev = rvu->pdev; 692 693 return (pdev->revision == 0x00) || (pdev->revision == 0x01); 694 } 695 696 static inline bool is_rvu_95xx_A0(struct rvu *rvu) 697 { 698 struct pci_dev *pdev = rvu->pdev; 699 700 return (pdev->revision == 0x10) || (pdev->revision == 0x11); 701 } 702 703 /* REVID for PCIe devices. 704 * Bits 0..1: minor pass, bit 3..2: major pass 705 * bits 7..4: midr id 706 */ 707 #define PCI_REVISION_ID_96XX 0x00 708 #define PCI_REVISION_ID_95XX 0x10 709 #define PCI_REVISION_ID_95XXN 0x20 710 #define PCI_REVISION_ID_98XX 0x30 711 #define PCI_REVISION_ID_95XXMM 0x40 712 #define PCI_REVISION_ID_95XXO 0xE0 713 714 static inline bool is_rvu_otx2(struct rvu *rvu) 715 { 716 struct pci_dev *pdev = rvu->pdev; 717 718 u8 midr = pdev->revision & 0xF0; 719 720 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 721 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 722 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 723 } 724 725 static inline bool is_cnf10ka_a0(struct rvu *rvu) 726 { 727 struct pci_dev *pdev = rvu->pdev; 728 729 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A && 730 (pdev->revision & 0x0F) == 0x0) 731 return true; 732 return false; 733 } 734 735 static inline bool is_cn10ka_a0(struct rvu *rvu) 736 { 737 struct pci_dev *pdev = rvu->pdev; 738 739 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A && 740 (pdev->revision & 0x0F) == 0x0) 741 return true; 742 return false; 743 } 744 745 static inline bool is_cn10ka_a1(struct rvu *rvu) 746 { 747 struct pci_dev *pdev = rvu->pdev; 748 749 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A && 750 (pdev->revision & 0x0F) == 0x1) 751 return true; 752 return false; 753 } 754 755 static inline bool is_cn10kb(struct rvu *rvu) 756 { 757 struct pci_dev *pdev = rvu->pdev; 758 759 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B) 760 return true; 761 return false; 762 } 763 764 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu) 765 { 766 u64 npc_const3; 767 768 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3); 769 if (!(npc_const3 & BIT_ULL(62))) 770 return false; 771 772 return true; 773 } 774 775 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid, 776 u8 lmacid, u8 chan) 777 { 778 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 779 u16 cgx_chans = nix_const & 0xFFULL; 780 struct rvu_hwinfo *hw = rvu->hw; 781 782 if (!hw->cap.programmable_chans) 783 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan); 784 785 return rvu->hw->cgx_chan_base + 786 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan; 787 } 788 789 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid, 790 u8 chan) 791 { 792 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 793 u16 lbk_chans = (nix_const >> 16) & 0xFFULL; 794 struct rvu_hwinfo *hw = rvu->hw; 795 796 if (!hw->cap.programmable_chans) 797 return NIX_CHAN_LBK_CHX(lbkid, chan); 798 799 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan; 800 } 801 802 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan) 803 { 804 struct rvu_hwinfo *hw = rvu->hw; 805 806 if (!hw->cap.programmable_chans) 807 return NIX_CHAN_SDP_CHX(chan); 808 809 return hw->sdp_chan_base + chan; 810 } 811 812 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan) 813 { 814 return rvu->hw->cpt_chan_base + chan; 815 } 816 817 static inline bool is_rvu_supports_nix1(struct rvu *rvu) 818 { 819 struct pci_dev *pdev = rvu->pdev; 820 821 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX) 822 return true; 823 824 return false; 825 } 826 827 /* Function Prototypes 828 * RVU 829 */ 830 #define RVU_LBK_VF_DEVID 0xA0F8 831 static inline bool is_lbk_vf(struct rvu *rvu, u16 pcifunc) 832 { 833 return (!(pcifunc & ~RVU_PFVF_FUNC_MASK) && 834 (rvu->vf_devid == RVU_LBK_VF_DEVID)); 835 } 836 837 static inline bool is_vf(u16 pcifunc) 838 { 839 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 840 } 841 842 /* check if PF_FUNC is AF */ 843 static inline bool is_pffunc_af(u16 pcifunc) 844 { 845 return !pcifunc; 846 } 847 848 static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 849 { 850 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 851 (rvu->fwdata->version == RVU_FWDATA_VERSION); 852 } 853 854 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 855 void rvu_free_bitmap(struct rsrc_bmap *rsrc); 856 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 857 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 858 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id); 859 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 860 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 861 void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start); 862 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 863 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 864 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 865 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 866 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 867 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 868 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 869 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 870 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 871 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 872 int rvu_get_num_lbk_chans(void); 873 int rvu_ndc_sync(struct rvu *rvu, int lfblkid, int lfidx, u64 lfoffset); 874 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 875 u16 global_slot, u16 *slot_in_block); 876 877 /* RVU HW reg validation */ 878 enum regmap_block { 879 TXSCHQ_HWREGMAP = 0, 880 MAX_HWREGMAP, 881 }; 882 883 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 884 885 /* NPA/NIX AQ APIs */ 886 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 887 int qsize, int inst_size, int res_size); 888 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 889 890 /* SDP APIs */ 891 int rvu_sdp_init(struct rvu *rvu); 892 bool is_sdp_pfvf(struct rvu *rvu, u16 pcifunc); 893 bool is_sdp_pf(struct rvu *rvu, u16 pcifunc); 894 bool is_sdp_vf(struct rvu *rvu, u16 pcifunc); 895 896 static inline bool is_rep_dev(struct rvu *rvu, u16 pcifunc) 897 { 898 if (rvu->rep_pcifunc && rvu->rep_pcifunc == pcifunc) 899 return true; 900 901 return false; 902 } 903 904 static inline int rvu_get_pf(struct pci_dev *pdev, u16 pcifunc) 905 { 906 if (is_cn20k(pdev)) 907 return (pcifunc >> RVU_CN20K_PFVF_PF_SHIFT) & 908 RVU_CN20K_PFVF_PF_MASK; 909 else 910 return (pcifunc >> RVU_OTX2_PFVF_PF_SHIFT) & 911 RVU_OTX2_PFVF_PF_MASK; 912 } 913 914 /* CGX APIs */ 915 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 916 { 917 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) && 918 !is_sdp_pf(rvu, rvu_make_pcifunc(rvu->pdev, pf, 0)); 919 } 920 921 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 922 { 923 *cgx_id = (map >> 4) & 0xF; 924 *lmac_id = (map & 0xF); 925 } 926 927 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc) 928 { 929 return ((pcifunc & RVU_PFVF_FUNC_MASK) && 930 is_pf_cgxmapped(rvu, rvu_get_pf(rvu->pdev, pcifunc))); 931 } 932 933 #define M(_name, _id, fn_name, req, rsp) \ 934 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 935 MBOX_MESSAGES 936 #undef M 937 938 int rvu_cgx_init(struct rvu *rvu); 939 int rvu_cgx_exit(struct rvu *rvu); 940 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 941 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 942 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 943 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 944 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 945 int rxtxflag, u64 *stat); 946 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc); 947 948 /* NPA APIs */ 949 int rvu_npa_init(struct rvu *rvu); 950 void rvu_npa_freemem(struct rvu *rvu); 951 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 952 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 953 struct npa_aq_enq_rsp *rsp); 954 955 /* NIX APIs */ 956 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 957 int rvu_nix_init(struct rvu *rvu); 958 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 959 int blkaddr, u32 cfg); 960 void rvu_nix_freemem(struct rvu *rvu); 961 int rvu_get_nixlf_count(struct rvu *rvu); 962 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 963 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 964 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 965 struct nix_mce_list *mce_list, 966 int mce_idx, int mcam_index, bool add); 967 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 968 struct nix_mce_list **mce_list, int *mce_idx); 969 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); 970 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 971 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); 972 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 973 struct nix_hw **nix_hw, int *blkaddr); 974 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 975 u16 rq_idx, u16 match_id); 976 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 977 struct nix_cn10k_aq_enq_req *aq_req, 978 struct nix_cn10k_aq_enq_rsp *aq_rsp, 979 u16 pcifunc, u8 ctype, u32 qidx); 980 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc); 981 int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type); 982 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu); 983 u32 convert_bytes_to_dwrr_mtu(u32 bytes); 984 void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc, 985 struct nix_txsch *txsch, bool enable); 986 void rvu_nix_mcast_flr_free_entries(struct rvu *rvu, u16 pcifunc); 987 int rvu_nix_mcast_get_mce_index(struct rvu *rvu, u16 pcifunc, 988 u32 mcast_grp_idx); 989 int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc, 990 u32 mcast_grp_idx, u16 mcam_index); 991 void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc); 992 993 /* NPC APIs */ 994 void rvu_npc_freemem(struct rvu *rvu); 995 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 996 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 997 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 998 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 999 int nixlf, u64 chan, u8 *mac_addr); 1000 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 1001 int nixlf, u64 chan, u8 chan_cnt); 1002 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 1003 bool enable); 1004 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 1005 int nixlf, u64 chan); 1006 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 1007 u64 chan); 1008 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 1009 bool enable); 1010 1011 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, 1012 int nixlf, int type, bool enable); 1013 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 1014 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable); 1015 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 1016 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 1017 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 1018 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 1019 int group, int alg_idx, int mcam_index); 1020 void __rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc, 1021 struct rvu_npc_mcam_rule *rule); 1022 void __rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc, 1023 struct rvu_npc_mcam_rule *rule, 1024 struct npc_install_flow_rsp *rsp); 1025 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 1026 int blkaddr, int *alloc_cnt, 1027 int *enable_cnt); 1028 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 1029 int blkaddr, int *alloc_cnt, 1030 int *enable_cnt); 1031 void rvu_npc_clear_ucast_entry(struct rvu *rvu, int pcifunc, int nixlf); 1032 1033 bool is_npc_intf_tx(u8 intf); 1034 bool is_npc_intf_rx(u8 intf); 1035 bool is_npc_interface_valid(struct rvu *rvu, u8 intf); 1036 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); 1037 int npc_flow_steering_init(struct rvu *rvu, int blkaddr); 1038 const char *npc_get_field_name(u8 hdr); 1039 int npc_get_bank(struct npc_mcam *mcam, int index); 1040 void npc_mcam_enable_flows(struct rvu *rvu, u16 target); 1041 void npc_mcam_disable_flows(struct rvu *rvu, u16 target); 1042 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 1043 int blkaddr, int index, bool enable); 1044 u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 1045 int blkaddr, int index); 1046 void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 1047 int blkaddr, int index, u64 cfg); 1048 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 1049 int blkaddr, u16 src, struct mcam_entry *entry, 1050 u8 *intf, u8 *ena); 1051 int npc_config_cntr_default_entries(struct rvu *rvu, bool enable); 1052 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc); 1053 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); 1054 u32 rvu_cgx_get_fifolen(struct rvu *rvu); 1055 void *rvu_first_cgx_pdata(struct rvu *rvu); 1056 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id); 1057 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable); 1058 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable); 1059 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause, 1060 u16 pfc_en); 1061 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause); 1062 void rvu_mac_reset(struct rvu *rvu, u16 pcifunc); 1063 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac); 1064 void cgx_start_linkup(struct rvu *rvu); 1065 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf, 1066 int type); 1067 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, 1068 int index); 1069 int rvu_npc_init(struct rvu *rvu); 1070 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx, 1071 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask, 1072 u64 bcast_mcast_val, u64 bcast_mcast_mask); 1073 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx); 1074 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf); 1075 int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr); 1076 void npc_mcam_rsrcs_deinit(struct rvu *rvu); 1077 1078 /* CPT APIs */ 1079 int rvu_cpt_register_interrupts(struct rvu *rvu); 1080 void rvu_cpt_unregister_interrupts(struct rvu *rvu); 1081 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf, 1082 int slot); 1083 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc); 1084 int rvu_cpt_init(struct rvu *rvu); 1085 1086 #define NDC_AF_BANK_MASK GENMASK_ULL(7, 0) 1087 #define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16) 1088 1089 /* CN10K RVU */ 1090 int rvu_set_channels_base(struct rvu *rvu); 1091 void rvu_program_channels(struct rvu *rvu); 1092 1093 /* CN10K NIX */ 1094 void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw); 1095 1096 /* CN10K RVU - LMT*/ 1097 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc); 1098 void rvu_apr_block_cn10k_init(struct rvu *rvu); 1099 1100 #ifdef CONFIG_DEBUG_FS 1101 void rvu_dbg_init(struct rvu *rvu); 1102 void rvu_dbg_exit(struct rvu *rvu); 1103 #else 1104 static inline void rvu_dbg_init(struct rvu *rvu) {} 1105 static inline void rvu_dbg_exit(struct rvu *rvu) {} 1106 #endif 1107 1108 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr); 1109 1110 /* RVU Switch */ 1111 void rvu_switch_enable(struct rvu *rvu); 1112 void rvu_switch_disable(struct rvu *rvu); 1113 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc, bool ena); 1114 void rvu_switch_enable_lbk_link(struct rvu *rvu, u16 pcifunc, bool ena); 1115 1116 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, 1117 u64 pkind, u8 var_len_off, u8 var_len_off_mask, 1118 u8 shift_dir); 1119 int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 1120 1121 /* CN10K MCS */ 1122 int rvu_mcs_init(struct rvu *rvu); 1123 int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc); 1124 void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena); 1125 void rvu_mcs_exit(struct rvu *rvu); 1126 1127 /* Representor APIs */ 1128 int rvu_rep_pf_init(struct rvu *rvu); 1129 int rvu_rep_install_mcam_rules(struct rvu *rvu); 1130 void rvu_rep_update_rules(struct rvu *rvu, u16 pcifunc, bool ena); 1131 int rvu_rep_notify_pfvf_state(struct rvu *rvu, u16 pcifunc, bool enable); 1132 #endif /* RVU_H */ 1133