1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef RVU_H 9 #define RVU_H 10 11 #include <linux/pci.h> 12 #include <net/devlink.h> 13 14 #include "rvu_struct.h" 15 #include "rvu_devlink.h" 16 #include "common.h" 17 #include "mbox.h" 18 #include "npc.h" 19 #include "rvu_reg.h" 20 #include "ptp.h" 21 22 /* PCI device IDs */ 23 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 24 #define PCI_DEVID_OCTEONTX2_LBK 0xA061 25 26 /* Subsystem Device ID */ 27 #define PCI_SUBSYS_DEVID_98XX 0xB100 28 #define PCI_SUBSYS_DEVID_96XX 0xB200 29 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900 30 #define PCI_SUBSYS_DEVID_CNF10K_A 0xBA00 31 #define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00 32 #define PCI_SUBSYS_DEVID_CN10K_B 0xBD00 33 #define PCI_SUBSYS_DEVID_CN20KA 0xC220 34 #define PCI_SUBSYS_DEVID_CNF20KA 0xC320 35 36 /* PCI BAR nos */ 37 #define PCI_AF_REG_BAR_NUM 0 38 #define PCI_PF_REG_BAR_NUM 2 39 #define PCI_MBOX_BAR_NUM 4 40 41 #define NAME_SIZE 32 42 #define MAX_NIX_BLKS 2 43 #define MAX_CPT_BLKS 2 44 45 /* PF_FUNC */ 46 #define RVU_PFVF_PF_SHIFT 10 47 #define RVU_PFVF_PF_MASK 0x3F 48 #define RVU_PFVF_FUNC_SHIFT 0 49 #define RVU_PFVF_FUNC_MASK 0x3FF 50 51 #ifdef CONFIG_DEBUG_FS 52 struct dump_ctx { 53 int lf; 54 int id; 55 bool all; 56 }; 57 58 struct cpt_ctx { 59 int blkaddr; 60 struct rvu *rvu; 61 }; 62 63 struct rvu_debugfs { 64 struct dentry *root; 65 struct dentry *cgx_root; 66 struct dentry *cgx; 67 struct dentry *lmac; 68 struct dentry *npa; 69 struct dentry *nix; 70 struct dentry *npc; 71 struct dentry *cpt; 72 struct dentry *mcs_root; 73 struct dentry *mcs; 74 struct dentry *mcs_rx; 75 struct dentry *mcs_tx; 76 struct dump_ctx npa_aura_ctx; 77 struct dump_ctx npa_pool_ctx; 78 struct dump_ctx nix_cq_ctx; 79 struct dump_ctx nix_rq_ctx; 80 struct dump_ctx nix_sq_ctx; 81 struct dump_ctx nix_tm_ctx; 82 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS]; 83 int npa_qsize_id; 84 int nix_qsize_id; 85 }; 86 #endif 87 88 struct rvu_work { 89 struct work_struct work; 90 struct rvu *rvu; 91 int num_msgs; 92 int up_num_msgs; 93 }; 94 95 struct rsrc_bmap { 96 unsigned long *bmap; /* Pointer to resource bitmap */ 97 u16 max; /* Max resource id or count */ 98 }; 99 100 struct rvu_block { 101 struct rsrc_bmap lf; 102 struct admin_queue *aq; /* NIX/NPA AQ */ 103 u16 *fn_map; /* LF to pcifunc mapping */ 104 bool multislot; 105 bool implemented; 106 u8 addr; /* RVU_BLOCK_ADDR_E */ 107 u8 type; /* RVU_BLOCK_TYPE_E */ 108 u8 lfshift; 109 u64 lookup_reg; 110 u64 pf_lfcnt_reg; 111 u64 vf_lfcnt_reg; 112 u64 lfcfg_reg; 113 u64 msixcfg_reg; 114 u64 lfreset_reg; 115 unsigned char name[NAME_SIZE]; 116 struct rvu *rvu; 117 u64 cpt_flt_eng_map[3]; 118 u64 cpt_rcvrd_eng_map[3]; 119 }; 120 121 struct nix_mcast { 122 struct qmem *mce_ctx; 123 struct qmem *mcast_buf; 124 int replay_pkind; 125 struct rsrc_bmap mce_counter[2]; 126 /* Counters for both ingress and egress mcast lists */ 127 struct mutex mce_lock; /* Serialize MCE updates */ 128 }; 129 130 struct nix_mce_list { 131 struct hlist_head head; 132 int count; 133 int max; 134 }; 135 136 struct nix_mcast_grp_elem { 137 struct nix_mce_list mcast_mce_list; 138 u32 mcast_grp_idx; 139 u32 pcifunc; 140 int mcam_index; 141 int mce_start_index; 142 struct list_head list; 143 u8 dir; 144 }; 145 146 struct nix_mcast_grp { 147 struct list_head mcast_grp_head; 148 int count; 149 int next_grp_index; 150 struct mutex mcast_grp_lock; /* Serialize MCE updates */ 151 }; 152 153 /* layer metadata to uniquely identify a packet header field */ 154 struct npc_layer_mdata { 155 u8 lid; 156 u8 ltype; 157 u8 hdr; 158 u8 key; 159 u8 len; 160 }; 161 162 /* Structure to represent a field present in the 163 * generated key. A key field may present anywhere and can 164 * be of any size in the generated key. Once this structure 165 * is populated for fields of interest then field's presence 166 * and location (if present) can be known. 167 */ 168 struct npc_key_field { 169 /* Masks where all set bits indicate position 170 * of a field in the key 171 */ 172 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 173 /* Number of words in the key a field spans. If a field is 174 * of 16 bytes and key offset is 4 then the field will use 175 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and 176 * nr_kws will be 3(KW0, KW1 and KW2). 177 */ 178 int nr_kws; 179 /* used by packet header fields */ 180 struct npc_layer_mdata layer_mdata; 181 }; 182 183 struct npc_mcam { 184 struct rsrc_bmap counters; 185 struct mutex lock; /* MCAM entries and counters update lock */ 186 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 187 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 188 u16 bmap_entries; /* Number of unreserved MCAM entries */ 189 u16 bmap_fcnt; /* MCAM entries free count */ 190 u16 *entry2pfvf_map; 191 u16 *entry2cntr_map; 192 u16 *cntr2pfvf_map; 193 u16 *cntr_refcnt; 194 u16 *entry2target_pffunc; 195 u8 keysize; /* MCAM keysize 112/224/448 bits */ 196 u8 banks; /* Number of MCAM banks */ 197 u8 banks_per_entry;/* Number of keywords in key */ 198 u16 banksize; /* Number of MCAM entries in each bank */ 199 u16 total_entries; /* Total number of MCAM entries */ 200 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 201 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 202 u16 lprio_count; 203 u16 lprio_start; 204 u16 hprio_count; 205 u16 hprio_end; 206 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 207 /* fields present in the generated key */ 208 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX]; 209 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX]; 210 u64 tx_features; 211 u64 rx_features; 212 struct list_head mcam_rules; 213 }; 214 215 /* Structure for per RVU func info ie PF/VF */ 216 struct rvu_pfvf { 217 bool npalf; /* Only one NPALF per RVU_FUNC */ 218 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 219 u16 sso; 220 u16 ssow; 221 u16 cptlfs; 222 u16 timlfs; 223 u16 cpt1_lfs; 224 u8 cgx_lmac; 225 226 /* Block LF's MSIX vector info */ 227 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 228 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 229 u16 *msix_lfmap; /* Vector to block LF mapping */ 230 231 /* NPA contexts */ 232 struct qmem *aura_ctx; 233 struct qmem *pool_ctx; 234 struct qmem *npa_qints_ctx; 235 unsigned long *aura_bmap; 236 unsigned long *pool_bmap; 237 238 /* NIX contexts */ 239 struct qmem *rq_ctx; 240 struct qmem *sq_ctx; 241 struct qmem *cq_ctx; 242 struct qmem *rss_ctx; 243 struct qmem *cq_ints_ctx; 244 struct qmem *nix_qints_ctx; 245 unsigned long *sq_bmap; 246 unsigned long *rq_bmap; 247 unsigned long *cq_bmap; 248 249 u16 rx_chan_base; 250 u16 tx_chan_base; 251 u8 rx_chan_cnt; /* total number of RX channels */ 252 u8 tx_chan_cnt; /* total number of TX channels */ 253 u16 maxlen; 254 u16 minlen; 255 256 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */ 257 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 258 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ 259 260 /* Broadcast/Multicast/Promisc pkt replication info */ 261 u16 bcast_mce_idx; 262 u16 mcast_mce_idx; 263 u16 promisc_mce_idx; 264 struct nix_mce_list bcast_mce_list; 265 struct nix_mce_list mcast_mce_list; 266 struct nix_mce_list promisc_mce_list; 267 bool use_mce_list; 268 269 struct rvu_npc_mcam_rule *def_ucast_rule; 270 271 bool cgx_in_use; /* this PF/VF using CGX? */ 272 int cgx_users; /* number of cgx users - used only by PFs */ 273 274 int intf_mode; 275 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 276 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */ 277 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ 278 u8 lbkid; /* NIX0/1 lbk link ID */ 279 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/ 280 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/ 281 unsigned long flags; 282 struct sdp_node_info *sdp_info; 283 }; 284 285 enum rvu_pfvf_flags { 286 NIXLF_INITIALIZED = 0, 287 PF_SET_VF_MAC, 288 PF_SET_VF_CFG, 289 PF_SET_VF_TRUSTED, 290 }; 291 292 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC) 293 294 struct nix_bp { 295 struct rsrc_bmap bpids; /* free bpids bitmap */ 296 u16 cgx_bpid_cnt; 297 u16 sdp_bpid_cnt; 298 u16 free_pool_base; 299 u16 *fn_map; /* pcifunc mapping */ 300 u8 *intf_map; /* interface type map */ 301 u8 *ref_cnt; 302 }; 303 304 struct nix_txsch { 305 struct rsrc_bmap schq; 306 u8 lvl; 307 #define NIX_TXSCHQ_FREE BIT_ULL(1) 308 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 309 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 310 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 311 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 312 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 313 u32 *pfvf_map; 314 }; 315 316 struct nix_mark_format { 317 u8 total; 318 u8 in_use; 319 u32 *cfg; 320 }; 321 322 /* smq(flush) to tl1 cir/pir info */ 323 struct nix_smq_tree_ctx { 324 u16 schq; 325 u64 cir_off; 326 u64 cir_val; 327 u64 pir_off; 328 u64 pir_val; 329 }; 330 331 /* smq flush context */ 332 struct nix_smq_flush_ctx { 333 int smq; 334 struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT]; 335 }; 336 337 struct npc_pkind { 338 struct rsrc_bmap rsrc; 339 u32 *pfchan_map; 340 }; 341 342 struct nix_flowkey { 343 #define NIX_FLOW_KEY_ALG_MAX 32 344 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 345 int in_use; 346 }; 347 348 struct nix_lso { 349 u8 total; 350 u8 in_use; 351 }; 352 353 struct nix_txvlan { 354 #define NIX_TX_VTAG_DEF_MAX 0x400 355 struct rsrc_bmap rsrc; 356 u16 *entry2pfvf_map; 357 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 358 }; 359 360 struct nix_ipolicer { 361 struct rsrc_bmap band_prof; 362 u16 *pfvf_map; 363 u16 *match_id; 364 u16 *ref_count; 365 }; 366 367 struct nix_hw { 368 int blkaddr; 369 struct rvu *rvu; 370 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 371 struct nix_mcast mcast; 372 struct nix_mcast_grp mcast_grp; 373 struct nix_flowkey flowkey; 374 struct nix_mark_format mark_format; 375 struct nix_lso lso; 376 struct nix_txvlan txvlan; 377 struct nix_ipolicer *ipolicer; 378 struct nix_bp bp; 379 u64 *tx_credits; 380 u8 cc_mcs_cnt; 381 }; 382 383 /* RVU block's capabilities or functionality, 384 * which vary by silicon version/skew. 385 */ 386 struct hw_cap { 387 /* Transmit side supported functionality */ 388 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 389 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 390 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 391 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 392 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 393 bool nix_shaping; /* Is shaping and coloring supported */ 394 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */ 395 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 396 bool nix_rx_multicast; /* Rx packet replication support */ 397 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */ 398 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */ 399 bool programmable_chans; /* Channels programmable ? */ 400 bool ipolicer; 401 bool nix_multiple_dwrr_mtu; /* Multiple DWRR_MTU to choose from */ 402 bool npc_hash_extract; /* Hash extract enabled ? */ 403 bool npc_exact_match_enabled; /* Exact match supported ? */ 404 bool cpt_rxc; /* Is CPT-RXC supported */ 405 }; 406 407 struct rvu_hwinfo { 408 u8 total_pfs; /* MAX RVU PFs HW supports */ 409 u16 total_vfs; /* Max RVU VFs HW supports */ 410 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 411 u8 cgx; 412 u8 lmac_per_cgx; 413 u16 cgx_chan_base; /* CGX base channel number */ 414 u16 lbk_chan_base; /* LBK base channel number */ 415 u16 sdp_chan_base; /* SDP base channel number */ 416 u16 cpt_chan_base; /* CPT base channel number */ 417 u8 cgx_links; 418 u8 lbk_links; 419 u8 sdp_links; 420 u8 cpt_links; /* Number of CPT links */ 421 u8 npc_kpus; /* No of parser units */ 422 u8 npc_pkinds; /* No of port kinds */ 423 u8 npc_intfs; /* No of interfaces */ 424 u8 npc_kpu_entries; /* No of KPU entries */ 425 u16 npc_counters; /* No of match stats counters */ 426 u32 lbk_bufsize; /* FIFO size supported by LBK */ 427 bool npc_ext_set; /* Extended register set */ 428 u64 npc_stat_ena; /* Match stats enable bit */ 429 430 struct hw_cap cap; 431 struct rvu_block block[BLK_COUNT]; /* Block info */ 432 struct nix_hw *nix; 433 struct rvu *rvu; 434 struct npc_pkind pkind; 435 struct npc_mcam mcam; 436 struct npc_exact_table *table; 437 }; 438 439 struct mbox_wq_info { 440 struct otx2_mbox mbox; 441 struct rvu_work *mbox_wrk; 442 443 struct otx2_mbox mbox_up; 444 struct rvu_work *mbox_wrk_up; 445 446 struct workqueue_struct *mbox_wq; 447 }; 448 449 struct channel_fwdata { 450 struct sdp_node_info info; 451 u8 valid; 452 #define RVU_CHANL_INFO_RESERVED 379 453 u8 reserved[RVU_CHANL_INFO_RESERVED]; 454 }; 455 456 struct rvu_fwdata { 457 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 458 #define RVU_FWDATA_VERSION 0x0001 459 u32 header_magic; 460 u32 version; /* version id */ 461 462 /* MAC address */ 463 #define PF_MACNUM_MAX 32 464 #define VF_MACNUM_MAX 256 465 u64 pf_macs[PF_MACNUM_MAX]; 466 u64 vf_macs[VF_MACNUM_MAX]; 467 u64 sclk; 468 u64 rclk; 469 u64 mcam_addr; 470 u64 mcam_sz; 471 u64 msixtr_base; 472 u32 ptp_ext_clk_rate; 473 u32 ptp_ext_tstamp; 474 struct channel_fwdata channel_data; 475 #define FWDATA_RESERVED_MEM 958 476 u64 reserved[FWDATA_RESERVED_MEM]; 477 #define CGX_MAX 9 478 #define CGX_LMACS_MAX 4 479 #define CGX_LMACS_USX 8 480 #define FWDATA_CGX_LMAC_OFFSET 10536 481 union { 482 struct cgx_lmac_fwdata_s 483 cgx_fw_data[CGX_MAX][CGX_LMACS_MAX]; 484 struct cgx_lmac_fwdata_s 485 cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX]; 486 }; 487 /* Do not add new fields below this line */ 488 }; 489 490 struct ptp; 491 492 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 493 * source where it came from. 494 */ 495 struct npc_kpu_profile_adapter { 496 const char *name; 497 u64 version; 498 const struct npc_lt_def_cfg *lt_def; 499 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 500 const struct npc_kpu_profile *kpu; /* array[kpus] */ 501 struct npc_mcam_kex *mkex; 502 struct npc_mcam_kex_hash *mkex_hash; 503 bool custom; 504 size_t pkinds; 505 size_t kpus; 506 }; 507 508 #define RVU_SWITCH_LBK_CHAN 63 509 510 struct rvu_switch { 511 struct mutex switch_lock; /* Serialize flow installation */ 512 u32 used_entries; 513 u16 *entry2pcifunc; 514 u16 mode; 515 u16 start_entry; 516 }; 517 518 struct rep_evtq_ent { 519 struct list_head node; 520 struct rep_event event; 521 }; 522 523 struct rvu { 524 void __iomem *afreg_base; 525 void __iomem *pfreg_base; 526 struct pci_dev *pdev; 527 struct device *dev; 528 struct rvu_hwinfo *hw; 529 struct rvu_pfvf *pf; 530 struct rvu_pfvf *hwvf; 531 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 532 struct mutex alias_lock; /* Serialize bar2 alias access */ 533 int vfs; /* Number of VFs attached to RVU */ 534 u16 vf_devid; /* VF devices id */ 535 bool def_rule_cntr_en; 536 int nix_blkaddr[MAX_NIX_BLKS]; 537 538 /* Mbox */ 539 struct mbox_wq_info afpf_wq_info; 540 struct mbox_wq_info afvf_wq_info; 541 542 /* PF FLR */ 543 struct rvu_work *flr_wrk; 544 struct workqueue_struct *flr_wq; 545 struct mutex flr_lock; /* Serialize FLRs */ 546 547 /* MSI-X */ 548 u16 num_vec; 549 char *irq_name; 550 bool *irq_allocated; 551 dma_addr_t msix_base_iova; 552 u64 msixtr_base_phy; /* Register reset value */ 553 554 /* CGX */ 555 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 556 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */ 557 u8 cgx_mapped_pfs; 558 u8 cgx_cnt_max; /* CGX port count max */ 559 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 560 u64 *cgxlmac2pf_map; /* bitmap of mapped pfs for 561 * every cgx lmac port 562 */ 563 unsigned long pf_notify_bmap; /* Flags for PF notification */ 564 void **cgx_idmap; /* cgx id to cgx data map table */ 565 struct work_struct cgx_evh_work; 566 struct workqueue_struct *cgx_evh_wq; 567 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 568 struct list_head cgx_evq_head; /* cgx event queue head */ 569 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 570 571 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 572 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */ 573 574 /* Firmware data */ 575 struct rvu_fwdata *fwdata; 576 void *kpu_fwdata; 577 size_t kpu_fwdata_sz; 578 void __iomem *kpu_prfl_addr; 579 580 /* NPC KPU data */ 581 struct npc_kpu_profile_adapter kpu; 582 583 struct ptp *ptp; 584 585 int mcs_blk_cnt; 586 int cpt_pf_num; 587 588 #ifdef CONFIG_DEBUG_FS 589 struct rvu_debugfs rvu_dbg; 590 #endif 591 struct rvu_devlink *rvu_dl; 592 593 /* RVU switch implementation over NPC with DMAC rules */ 594 struct rvu_switch rswitch; 595 596 struct work_struct mcs_intr_work; 597 struct workqueue_struct *mcs_intr_wq; 598 struct list_head mcs_intrq_head; 599 /* mcs interrupt queue lock */ 600 spinlock_t mcs_intrq_lock; 601 /* CPT interrupt lock */ 602 spinlock_t cpt_intr_lock; 603 604 struct mutex mbox_lock; /* Serialize mbox up and down msgs */ 605 u16 rep_pcifunc; 606 int rep_cnt; 607 u16 *rep2pfvf_map; 608 u8 rep_mode; 609 struct work_struct rep_evt_work; 610 struct workqueue_struct *rep_evt_wq; 611 struct list_head rep_evtq_head; 612 /* Representor event lock */ 613 spinlock_t rep_evtq_lock; 614 }; 615 616 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 617 { 618 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 619 } 620 621 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 622 { 623 return readq(rvu->afreg_base + ((block << 28) | offset)); 624 } 625 626 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 627 { 628 writeq(val, rvu->pfreg_base + offset); 629 } 630 631 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 632 { 633 return readq(rvu->pfreg_base + offset); 634 } 635 636 static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 637 { 638 /* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of 639 * write operation. 640 */ 641 rvu_write64(rvu, block, offset, val); 642 rvu_read64(rvu, block, offset); 643 /* Barrier to ensure read completes before accessing LF registers */ 644 mb(); 645 } 646 647 /* Silicon revisions */ 648 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu) 649 { 650 struct pci_dev *pdev = rvu->pdev; 651 /* 96XX A0/B0, 95XX A0/A1/B0 chips */ 652 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) || 653 (pdev->revision == 0x10) || (pdev->revision == 0x11) || 654 (pdev->revision == 0x14)); 655 } 656 657 static inline bool is_rvu_96xx_A0(struct rvu *rvu) 658 { 659 struct pci_dev *pdev = rvu->pdev; 660 661 return (pdev->revision == 0x00); 662 } 663 664 static inline bool is_rvu_96xx_B0(struct rvu *rvu) 665 { 666 struct pci_dev *pdev = rvu->pdev; 667 668 return (pdev->revision == 0x00) || (pdev->revision == 0x01); 669 } 670 671 static inline bool is_rvu_95xx_A0(struct rvu *rvu) 672 { 673 struct pci_dev *pdev = rvu->pdev; 674 675 return (pdev->revision == 0x10) || (pdev->revision == 0x11); 676 } 677 678 /* REVID for PCIe devices. 679 * Bits 0..1: minor pass, bit 3..2: major pass 680 * bits 7..4: midr id 681 */ 682 #define PCI_REVISION_ID_96XX 0x00 683 #define PCI_REVISION_ID_95XX 0x10 684 #define PCI_REVISION_ID_95XXN 0x20 685 #define PCI_REVISION_ID_98XX 0x30 686 #define PCI_REVISION_ID_95XXMM 0x40 687 #define PCI_REVISION_ID_95XXO 0xE0 688 689 static inline bool is_rvu_otx2(struct rvu *rvu) 690 { 691 struct pci_dev *pdev = rvu->pdev; 692 693 u8 midr = pdev->revision & 0xF0; 694 695 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 696 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 697 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 698 } 699 700 static inline bool is_cnf10ka_a0(struct rvu *rvu) 701 { 702 struct pci_dev *pdev = rvu->pdev; 703 704 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A && 705 (pdev->revision & 0x0F) == 0x0) 706 return true; 707 return false; 708 } 709 710 static inline bool is_cn10ka_a0(struct rvu *rvu) 711 { 712 struct pci_dev *pdev = rvu->pdev; 713 714 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A && 715 (pdev->revision & 0x0F) == 0x0) 716 return true; 717 return false; 718 } 719 720 static inline bool is_cn10ka_a1(struct rvu *rvu) 721 { 722 struct pci_dev *pdev = rvu->pdev; 723 724 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A && 725 (pdev->revision & 0x0F) == 0x1) 726 return true; 727 return false; 728 } 729 730 static inline bool is_cn10kb(struct rvu *rvu) 731 { 732 struct pci_dev *pdev = rvu->pdev; 733 734 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B) 735 return true; 736 return false; 737 } 738 739 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu) 740 { 741 u64 npc_const3; 742 743 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3); 744 if (!(npc_const3 & BIT_ULL(62))) 745 return false; 746 747 return true; 748 } 749 750 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid, 751 u8 lmacid, u8 chan) 752 { 753 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 754 u16 cgx_chans = nix_const & 0xFFULL; 755 struct rvu_hwinfo *hw = rvu->hw; 756 757 if (!hw->cap.programmable_chans) 758 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan); 759 760 return rvu->hw->cgx_chan_base + 761 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan; 762 } 763 764 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid, 765 u8 chan) 766 { 767 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 768 u16 lbk_chans = (nix_const >> 16) & 0xFFULL; 769 struct rvu_hwinfo *hw = rvu->hw; 770 771 if (!hw->cap.programmable_chans) 772 return NIX_CHAN_LBK_CHX(lbkid, chan); 773 774 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan; 775 } 776 777 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan) 778 { 779 struct rvu_hwinfo *hw = rvu->hw; 780 781 if (!hw->cap.programmable_chans) 782 return NIX_CHAN_SDP_CHX(chan); 783 784 return hw->sdp_chan_base + chan; 785 } 786 787 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan) 788 { 789 return rvu->hw->cpt_chan_base + chan; 790 } 791 792 static inline bool is_rvu_supports_nix1(struct rvu *rvu) 793 { 794 struct pci_dev *pdev = rvu->pdev; 795 796 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX) 797 return true; 798 799 return false; 800 } 801 802 /* Function Prototypes 803 * RVU 804 */ 805 #define RVU_LBK_VF_DEVID 0xA0F8 806 static inline bool is_lbk_vf(struct rvu *rvu, u16 pcifunc) 807 { 808 return (!(pcifunc & ~RVU_PFVF_FUNC_MASK) && 809 (rvu->vf_devid == RVU_LBK_VF_DEVID)); 810 } 811 812 static inline bool is_vf(u16 pcifunc) 813 { 814 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 815 } 816 817 /* check if PF_FUNC is AF */ 818 static inline bool is_pffunc_af(u16 pcifunc) 819 { 820 return !pcifunc; 821 } 822 823 static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 824 { 825 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 826 (rvu->fwdata->version == RVU_FWDATA_VERSION); 827 } 828 829 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 830 void rvu_free_bitmap(struct rsrc_bmap *rsrc); 831 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 832 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 833 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id); 834 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 835 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 836 void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start); 837 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 838 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 839 int rvu_get_pf(u16 pcifunc); 840 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 841 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 842 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 843 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 844 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 845 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 846 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 847 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 848 int rvu_get_num_lbk_chans(void); 849 int rvu_ndc_sync(struct rvu *rvu, int lfblkid, int lfidx, u64 lfoffset); 850 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 851 u16 global_slot, u16 *slot_in_block); 852 853 /* RVU HW reg validation */ 854 enum regmap_block { 855 TXSCHQ_HWREGMAP = 0, 856 MAX_HWREGMAP, 857 }; 858 859 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 860 861 /* NPA/NIX AQ APIs */ 862 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 863 int qsize, int inst_size, int res_size); 864 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 865 866 /* SDP APIs */ 867 int rvu_sdp_init(struct rvu *rvu); 868 bool is_sdp_pfvf(u16 pcifunc); 869 bool is_sdp_pf(u16 pcifunc); 870 bool is_sdp_vf(struct rvu *rvu, u16 pcifunc); 871 872 static inline bool is_rep_dev(struct rvu *rvu, u16 pcifunc) 873 { 874 if (rvu->rep_pcifunc && rvu->rep_pcifunc == pcifunc) 875 return true; 876 877 return false; 878 } 879 880 /* CGX APIs */ 881 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 882 { 883 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) && 884 !is_sdp_pf(pf << RVU_PFVF_PF_SHIFT); 885 } 886 887 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 888 { 889 *cgx_id = (map >> 4) & 0xF; 890 *lmac_id = (map & 0xF); 891 } 892 893 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc) 894 { 895 return ((pcifunc & RVU_PFVF_FUNC_MASK) && 896 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))); 897 } 898 899 #define M(_name, _id, fn_name, req, rsp) \ 900 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 901 MBOX_MESSAGES 902 #undef M 903 904 int rvu_cgx_init(struct rvu *rvu); 905 int rvu_cgx_exit(struct rvu *rvu); 906 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 907 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 908 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 909 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 910 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 911 int rxtxflag, u64 *stat); 912 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc); 913 914 /* NPA APIs */ 915 int rvu_npa_init(struct rvu *rvu); 916 void rvu_npa_freemem(struct rvu *rvu); 917 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 918 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 919 struct npa_aq_enq_rsp *rsp); 920 921 /* NIX APIs */ 922 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 923 int rvu_nix_init(struct rvu *rvu); 924 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 925 int blkaddr, u32 cfg); 926 void rvu_nix_freemem(struct rvu *rvu); 927 int rvu_get_nixlf_count(struct rvu *rvu); 928 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 929 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 930 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 931 struct nix_mce_list *mce_list, 932 int mce_idx, int mcam_index, bool add); 933 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 934 struct nix_mce_list **mce_list, int *mce_idx); 935 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); 936 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 937 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); 938 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 939 struct nix_hw **nix_hw, int *blkaddr); 940 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 941 u16 rq_idx, u16 match_id); 942 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 943 struct nix_cn10k_aq_enq_req *aq_req, 944 struct nix_cn10k_aq_enq_rsp *aq_rsp, 945 u16 pcifunc, u8 ctype, u32 qidx); 946 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc); 947 int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type); 948 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu); 949 u32 convert_bytes_to_dwrr_mtu(u32 bytes); 950 void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc, 951 struct nix_txsch *txsch, bool enable); 952 void rvu_nix_mcast_flr_free_entries(struct rvu *rvu, u16 pcifunc); 953 int rvu_nix_mcast_get_mce_index(struct rvu *rvu, u16 pcifunc, 954 u32 mcast_grp_idx); 955 int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc, 956 u32 mcast_grp_idx, u16 mcam_index); 957 void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc); 958 959 /* NPC APIs */ 960 void rvu_npc_freemem(struct rvu *rvu); 961 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 962 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 963 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 964 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 965 int nixlf, u64 chan, u8 *mac_addr); 966 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 967 int nixlf, u64 chan, u8 chan_cnt); 968 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 969 bool enable); 970 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 971 int nixlf, u64 chan); 972 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 973 bool enable); 974 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 975 u64 chan); 976 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 977 bool enable); 978 979 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, 980 int nixlf, int type, bool enable); 981 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 982 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable); 983 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 984 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 985 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 986 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 987 int group, int alg_idx, int mcam_index); 988 void __rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc, 989 struct rvu_npc_mcam_rule *rule); 990 void __rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc, 991 struct rvu_npc_mcam_rule *rule, 992 struct npc_install_flow_rsp *rsp); 993 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 994 int blkaddr, int *alloc_cnt, 995 int *enable_cnt); 996 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 997 int blkaddr, int *alloc_cnt, 998 int *enable_cnt); 999 bool is_npc_intf_tx(u8 intf); 1000 bool is_npc_intf_rx(u8 intf); 1001 bool is_npc_interface_valid(struct rvu *rvu, u8 intf); 1002 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); 1003 int npc_flow_steering_init(struct rvu *rvu, int blkaddr); 1004 const char *npc_get_field_name(u8 hdr); 1005 int npc_get_bank(struct npc_mcam *mcam, int index); 1006 void npc_mcam_enable_flows(struct rvu *rvu, u16 target); 1007 void npc_mcam_disable_flows(struct rvu *rvu, u16 target); 1008 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 1009 int blkaddr, int index, bool enable); 1010 u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 1011 int blkaddr, int index); 1012 void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 1013 int blkaddr, int index, u64 cfg); 1014 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 1015 int blkaddr, u16 src, struct mcam_entry *entry, 1016 u8 *intf, u8 *ena); 1017 int npc_config_cntr_default_entries(struct rvu *rvu, bool enable); 1018 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc); 1019 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); 1020 u32 rvu_cgx_get_fifolen(struct rvu *rvu); 1021 void *rvu_first_cgx_pdata(struct rvu *rvu); 1022 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id); 1023 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable); 1024 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable); 1025 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause, 1026 u16 pfc_en); 1027 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause); 1028 void rvu_mac_reset(struct rvu *rvu, u16 pcifunc); 1029 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac); 1030 void cgx_start_linkup(struct rvu *rvu); 1031 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf, 1032 int type); 1033 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, 1034 int index); 1035 int rvu_npc_init(struct rvu *rvu); 1036 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx, 1037 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask, 1038 u64 bcast_mcast_val, u64 bcast_mcast_mask); 1039 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx); 1040 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf); 1041 int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr); 1042 void npc_mcam_rsrcs_deinit(struct rvu *rvu); 1043 1044 /* CPT APIs */ 1045 int rvu_cpt_register_interrupts(struct rvu *rvu); 1046 void rvu_cpt_unregister_interrupts(struct rvu *rvu); 1047 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf, 1048 int slot); 1049 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc); 1050 int rvu_cpt_init(struct rvu *rvu); 1051 1052 #define NDC_AF_BANK_MASK GENMASK_ULL(7, 0) 1053 #define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16) 1054 1055 /* CN10K RVU */ 1056 int rvu_set_channels_base(struct rvu *rvu); 1057 void rvu_program_channels(struct rvu *rvu); 1058 1059 /* CN10K NIX */ 1060 void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw); 1061 1062 /* CN10K RVU - LMT*/ 1063 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc); 1064 void rvu_apr_block_cn10k_init(struct rvu *rvu); 1065 1066 #ifdef CONFIG_DEBUG_FS 1067 void rvu_dbg_init(struct rvu *rvu); 1068 void rvu_dbg_exit(struct rvu *rvu); 1069 #else 1070 static inline void rvu_dbg_init(struct rvu *rvu) {} 1071 static inline void rvu_dbg_exit(struct rvu *rvu) {} 1072 #endif 1073 1074 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr); 1075 1076 /* RVU Switch */ 1077 void rvu_switch_enable(struct rvu *rvu); 1078 void rvu_switch_disable(struct rvu *rvu); 1079 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc, bool ena); 1080 void rvu_switch_enable_lbk_link(struct rvu *rvu, u16 pcifunc, bool ena); 1081 1082 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, 1083 u64 pkind, u8 var_len_off, u8 var_len_off_mask, 1084 u8 shift_dir); 1085 int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 1086 1087 /* CN10K MCS */ 1088 int rvu_mcs_init(struct rvu *rvu); 1089 int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc); 1090 void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena); 1091 void rvu_mcs_exit(struct rvu *rvu); 1092 1093 /* Representor APIs */ 1094 int rvu_rep_pf_init(struct rvu *rvu); 1095 int rvu_rep_install_mcam_rules(struct rvu *rvu); 1096 void rvu_rep_update_rules(struct rvu *rvu, u16 pcifunc, bool ena); 1097 int rvu_rep_notify_pfvf_state(struct rvu *rvu, u16 pcifunc, bool enable); 1098 #endif /* RVU_H */ 1099