xref: /linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h (revision aec35aecc3ccc822b358e2594ff70ff54245261e)
12ef17216SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0+ */
2d71d8381SJian Shen // Copyright (c) 2016-2017 Hisilicon Limited.
346a3df9fSSalil 
446a3df9fSSalil #ifndef __HCLGE_MAIN_H
546a3df9fSSalil #define __HCLGE_MAIN_H
646a3df9fSSalil #include <linux/fs.h>
746a3df9fSSalil #include <linux/types.h>
846a3df9fSSalil #include <linux/phy.h>
9dc8131d8SYunsheng Lin #include <linux/if_vlan.h>
10a6345787SWeihang Li #include <linux/kfifo.h>
11b741269bSYufeng Mo #include <net/devlink.h>
12dc8131d8SYunsheng Lin 
1346a3df9fSSalil #include "hclge_cmd.h"
140bf5eb78SHuazhong Tan #include "hclge_ptp.h"
1546a3df9fSSalil #include "hnae3.h"
1646a3df9fSSalil 
173c7624d8SXi Wang #define HCLGE_MOD_VERSION "1.0"
1846a3df9fSSalil #define HCLGE_DRIVER_NAME "hclge"
1946a3df9fSSalil 
2039932473SJian Shen #define HCLGE_MAX_PF_NUM		8
2139932473SJian Shen 
22693e4415SGuoJia Liao #define HCLGE_VF_VPORT_START_NUM	1
23693e4415SGuoJia Liao 
24d174ea75Sliuzhongzhu #define HCLGE_RD_FIRST_STATS_NUM        2
25d174ea75Sliuzhongzhu #define HCLGE_RD_OTHER_STATS_NUM        4
26d174ea75Sliuzhongzhu 
2746a3df9fSSalil #define HCLGE_INVALID_VPORT 0xffff
2846a3df9fSSalil 
2946a3df9fSSalil #define HCLGE_PF_CFG_BLOCK_SIZE		32
3046a3df9fSSalil #define HCLGE_PF_CFG_DESC_NUM \
3146a3df9fSSalil 	(HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
3246a3df9fSSalil 
3346a3df9fSSalil #define HCLGE_VECTOR_REG_BASE		0x20000
343a6863e4SYufeng Mo #define HCLGE_VECTOR_EXT_REG_BASE	0x30000
35466b0c00SLipeng #define HCLGE_MISC_VECTOR_REG_BASE	0x20400
3646a3df9fSSalil 
3746a3df9fSSalil #define HCLGE_VECTOR_REG_OFFSET		0x4
383a6863e4SYufeng Mo #define HCLGE_VECTOR_REG_OFFSET_H	0x1000
3946a3df9fSSalil #define HCLGE_VECTOR_VF_OFFSET		0x100000
4046a3df9fSSalil 
415a24b1fdSPeng Li #define HCLGE_NIC_CSQ_BASEADDR_L_REG	0x27000
425a24b1fdSPeng Li #define HCLGE_NIC_CSQ_BASEADDR_H_REG	0x27004
435a24b1fdSPeng Li #define HCLGE_NIC_CSQ_DEPTH_REG		0x27008
445a24b1fdSPeng Li #define HCLGE_NIC_CSQ_TAIL_REG		0x27010
455a24b1fdSPeng Li #define HCLGE_NIC_CSQ_HEAD_REG		0x27014
465a24b1fdSPeng Li #define HCLGE_NIC_CRQ_BASEADDR_L_REG	0x27018
475a24b1fdSPeng Li #define HCLGE_NIC_CRQ_BASEADDR_H_REG	0x2701C
485a24b1fdSPeng Li #define HCLGE_NIC_CRQ_DEPTH_REG		0x27020
495a24b1fdSPeng Li #define HCLGE_NIC_CRQ_TAIL_REG		0x27024
505a24b1fdSPeng Li #define HCLGE_NIC_CRQ_HEAD_REG		0x27028
515a24b1fdSPeng Li 
52ea4750caSJian Shen #define HCLGE_CMDQ_INTR_STS_REG		0x27104
53ea4750caSJian Shen #define HCLGE_CMDQ_INTR_EN_REG		0x27108
54ea4750caSJian Shen #define HCLGE_CMDQ_INTR_GEN_REG		0x2710C
55ea4750caSJian Shen 
56ea4750caSJian Shen /* bar registers for common func */
57ea4750caSJian Shen #define HCLGE_GRO_EN_REG		0x28000
5879664077SHuazhong Tan #define HCLGE_RXD_ADV_LAYOUT_EN_REG	0x28008
59ea4750caSJian Shen 
60ea4750caSJian Shen /* bar registers for rcb */
61ea4750caSJian Shen #define HCLGE_RING_RX_ADDR_L_REG	0x80000
62ea4750caSJian Shen #define HCLGE_RING_RX_ADDR_H_REG	0x80004
63ea4750caSJian Shen #define HCLGE_RING_RX_BD_NUM_REG	0x80008
64ea4750caSJian Shen #define HCLGE_RING_RX_BD_LENGTH_REG	0x8000C
65ea4750caSJian Shen #define HCLGE_RING_RX_MERGE_EN_REG	0x80014
66ea4750caSJian Shen #define HCLGE_RING_RX_TAIL_REG		0x80018
67ea4750caSJian Shen #define HCLGE_RING_RX_HEAD_REG		0x8001C
68ea4750caSJian Shen #define HCLGE_RING_RX_FBD_NUM_REG	0x80020
69ea4750caSJian Shen #define HCLGE_RING_RX_OFFSET_REG	0x80024
70ea4750caSJian Shen #define HCLGE_RING_RX_FBD_OFFSET_REG	0x80028
71ea4750caSJian Shen #define HCLGE_RING_RX_STASH_REG		0x80030
72ea4750caSJian Shen #define HCLGE_RING_RX_BD_ERR_REG	0x80034
73ea4750caSJian Shen #define HCLGE_RING_TX_ADDR_L_REG	0x80040
74ea4750caSJian Shen #define HCLGE_RING_TX_ADDR_H_REG	0x80044
75ea4750caSJian Shen #define HCLGE_RING_TX_BD_NUM_REG	0x80048
76ea4750caSJian Shen #define HCLGE_RING_TX_PRIORITY_REG	0x8004C
77ea4750caSJian Shen #define HCLGE_RING_TX_TC_REG		0x80050
78ea4750caSJian Shen #define HCLGE_RING_TX_MERGE_EN_REG	0x80054
79ea4750caSJian Shen #define HCLGE_RING_TX_TAIL_REG		0x80058
80ea4750caSJian Shen #define HCLGE_RING_TX_HEAD_REG		0x8005C
81ea4750caSJian Shen #define HCLGE_RING_TX_FBD_NUM_REG	0x80060
82ea4750caSJian Shen #define HCLGE_RING_TX_OFFSET_REG	0x80064
83ea4750caSJian Shen #define HCLGE_RING_TX_EBD_NUM_REG	0x80068
84ea4750caSJian Shen #define HCLGE_RING_TX_EBD_OFFSET_REG	0x80070
85ea4750caSJian Shen #define HCLGE_RING_TX_BD_ERR_REG	0x80074
86ea4750caSJian Shen #define HCLGE_RING_EN_REG		0x80090
87ea4750caSJian Shen 
88ea4750caSJian Shen /* bar registers for tqp interrupt */
89ea4750caSJian Shen #define HCLGE_TQP_INTR_CTRL_REG		0x20000
90ea4750caSJian Shen #define HCLGE_TQP_INTR_GL0_REG		0x20100
91ea4750caSJian Shen #define HCLGE_TQP_INTR_GL1_REG		0x20200
92ea4750caSJian Shen #define HCLGE_TQP_INTR_GL2_REG		0x20300
93ea4750caSJian Shen #define HCLGE_TQP_INTR_RL_REG		0x20900
94ea4750caSJian Shen 
9546a3df9fSSalil #define HCLGE_RSS_IND_TBL_SIZE		512
965392902dSYunsheng Lin #define HCLGE_RSS_SET_BITMAP_MSK	GENMASK(15, 0)
9746a3df9fSSalil #define HCLGE_RSS_KEY_SIZE		40
9846a3df9fSSalil #define HCLGE_RSS_HASH_ALGO_TOEPLITZ	0
9946a3df9fSSalil #define HCLGE_RSS_HASH_ALGO_SIMPLE	1
10046a3df9fSSalil #define HCLGE_RSS_HASH_ALGO_SYMMETRIC	2
101c79301d8SJian Shen #define HCLGE_RSS_HASH_ALGO_MASK	GENMASK(3, 0)
10246a3df9fSSalil 
103f7db940aSLipeng #define HCLGE_RSS_INPUT_TUPLE_OTHER	GENMASK(3, 0)
104f7db940aSLipeng #define HCLGE_RSS_INPUT_TUPLE_SCTP	GENMASK(4, 0)
105f7db940aSLipeng #define HCLGE_D_PORT_BIT		BIT(0)
106f7db940aSLipeng #define HCLGE_S_PORT_BIT		BIT(1)
107f7db940aSLipeng #define HCLGE_D_IP_BIT			BIT(2)
108f7db940aSLipeng #define HCLGE_S_IP_BIT			BIT(3)
109f7db940aSLipeng #define HCLGE_V_TAG_BIT			BIT(4)
110ab6e32d2SJian Shen #define HCLGE_RSS_INPUT_TUPLE_SCTP_NO_PORT	\
111ab6e32d2SJian Shen 		(HCLGE_D_IP_BIT | HCLGE_S_IP_BIT | HCLGE_V_TAG_BIT)
112f7db940aSLipeng 
11346a3df9fSSalil #define HCLGE_RSS_TC_SIZE_0		1
11446a3df9fSSalil #define HCLGE_RSS_TC_SIZE_1		2
11546a3df9fSSalil #define HCLGE_RSS_TC_SIZE_2		4
11646a3df9fSSalil #define HCLGE_RSS_TC_SIZE_3		8
11746a3df9fSSalil #define HCLGE_RSS_TC_SIZE_4		16
11846a3df9fSSalil #define HCLGE_RSS_TC_SIZE_5		32
11946a3df9fSSalil #define HCLGE_RSS_TC_SIZE_6		64
12046a3df9fSSalil #define HCLGE_RSS_TC_SIZE_7		128
12146a3df9fSSalil 
12239932473SJian Shen #define HCLGE_UMV_TBL_SIZE		3072
12339932473SJian Shen #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \
12439932473SJian Shen 	(HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM)
12539932473SJian Shen 
126e8df45c2SZhongzhu Liu #define HCLGE_TQP_RESET_TRY_TIMES	200
12746a3df9fSSalil 
12846a3df9fSSalil #define HCLGE_PHY_PAGE_MDIX		0
12946a3df9fSSalil #define HCLGE_PHY_PAGE_COPPER		0
13046a3df9fSSalil 
13146a3df9fSSalil /* Page Selection Reg. */
13246a3df9fSSalil #define HCLGE_PHY_PAGE_REG		22
13346a3df9fSSalil 
13446a3df9fSSalil /* Copper Specific Control Register */
13546a3df9fSSalil #define HCLGE_PHY_CSC_REG		16
13646a3df9fSSalil 
13746a3df9fSSalil /* Copper Specific Status Register */
13846a3df9fSSalil #define HCLGE_PHY_CSS_REG		17
13946a3df9fSSalil 
140a10829c4SJian Shen #define HCLGE_PHY_MDIX_CTRL_S		5
1415392902dSYunsheng Lin #define HCLGE_PHY_MDIX_CTRL_M		GENMASK(6, 5)
14246a3df9fSSalil 
143a10829c4SJian Shen #define HCLGE_PHY_MDIX_STATUS_B		6
144a10829c4SJian Shen #define HCLGE_PHY_SPEED_DUP_RESOLVE_B	11
14546a3df9fSSalil 
1469027d043SGuojia Liao #define HCLGE_GET_DFX_REG_TYPE_CNT	4
1479027d043SGuojia Liao 
1485f6ea83fSPeng Li /* Factor used to calculate offset and bitmap of VF num */
1495f6ea83fSPeng Li #define HCLGE_VF_NUM_PER_CMD           64
1505f6ea83fSPeng Li 
1513f094bd1SGuangbin Huang #define HCLGE_MAX_QSET_NUM		1024
1523f094bd1SGuangbin Huang 
1531a7ff828SJiaran Zhang #define HCLGE_DBG_RESET_INFO_LEN	1024
1541a7ff828SJiaran Zhang 
15511732868SJian Shen enum HLCGE_PORT_TYPE {
15611732868SJian Shen 	HOST_PORT,
15711732868SJian Shen 	NETWORK_PORT
15811732868SJian Shen };
15911732868SJian Shen 
160dd2956eaSYufeng Mo #define PF_VPORT_ID			0
161dd2956eaSYufeng Mo 
16211732868SJian Shen #define HCLGE_PF_ID_S			0
16311732868SJian Shen #define HCLGE_PF_ID_M			GENMASK(2, 0)
16411732868SJian Shen #define HCLGE_VF_ID_S			3
16511732868SJian Shen #define HCLGE_VF_ID_M			GENMASK(10, 3)
16611732868SJian Shen #define HCLGE_PORT_TYPE_B		11
16711732868SJian Shen #define HCLGE_NETWORK_PORT_ID_S		0
16811732868SJian Shen #define HCLGE_NETWORK_PORT_ID_M		GENMASK(3, 0)
16911732868SJian Shen 
1704ed340abSLipeng /* Reset related Registers */
1716dd22bbcSHuazhong Tan #define HCLGE_PF_OTHER_INT_REG		0x20600
1724ed340abSLipeng #define HCLGE_MISC_RESET_STS_REG	0x20700
1739ca8d1a7SHuazhong Tan #define HCLGE_MISC_VECTOR_INT_STS	0x20800
1744ed340abSLipeng #define HCLGE_GLOBAL_RESET_REG		0x20A00
175f8a91784SJian Shen #define HCLGE_GLOBAL_RESET_BIT		0
176f8a91784SJian Shen #define HCLGE_CORE_RESET_BIT		1
17765e41e7eSHuazhong Tan #define HCLGE_IMP_RESET_BIT		2
17874e78d6bSHuazhong Tan #define HCLGE_RESET_INT_M		GENMASK(7, 5)
1794ed340abSLipeng #define HCLGE_FUN_RST_ING		0x20C00
1804ed340abSLipeng #define HCLGE_FUN_RST_ING_B		0
1814ed340abSLipeng 
1824ed340abSLipeng /* Vector0 register bits define */
1830bf5eb78SHuazhong Tan #define HCLGE_VECTOR0_REG_PTP_INT_B	0
1844ed340abSLipeng #define HCLGE_VECTOR0_GLOBALRESET_INT_B	5
1854ed340abSLipeng #define HCLGE_VECTOR0_CORERESET_INT_B	6
1864ed340abSLipeng #define HCLGE_VECTOR0_IMPRESET_INT_B	7
1874ed340abSLipeng 
188c1a81619SSalil Mehta /* Vector0 interrupt CMDQ event source register(RW) */
189c1a81619SSalil Mehta #define HCLGE_VECTOR0_CMDQ_SRC_REG	0x27100
190c1a81619SSalil Mehta /* CMDQ register bits for RX event(=MBX event) */
191c1a81619SSalil Mehta #define HCLGE_VECTOR0_RX_CMDQ_INT_B	1
192c1a81619SSalil Mehta 
1936dd22bbcSHuazhong Tan #define HCLGE_VECTOR0_IMP_RESET_INT_B	1
194a83d2961SWeihang Li #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B	4U
195a83d2961SWeihang Li #define HCLGE_VECTOR0_IMP_RD_POISON_B	5U
19617f59244SYufeng Mo #define HCLGE_VECTOR0_ALL_MSIX_ERR_B	6U
197ddccc5e3SYufeng Mo #define HCLGE_TRIGGER_IMP_RESET_B	7U
1986dd22bbcSHuazhong Tan 
1992866ccb2SFuyun Liang #define HCLGE_MAC_DEFAULT_FRAME \
200a0b43717SYunsheng Lin 	(ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
2012866ccb2SFuyun Liang #define HCLGE_MAC_MIN_FRAME		64
2022866ccb2SFuyun Liang #define HCLGE_MAC_MAX_FRAME		9728
2032866ccb2SFuyun Liang 
2040979aa0bSFuyun Liang #define HCLGE_SUPPORT_1G_BIT		BIT(0)
2050979aa0bSFuyun Liang #define HCLGE_SUPPORT_10G_BIT		BIT(1)
2060979aa0bSFuyun Liang #define HCLGE_SUPPORT_25G_BIT		BIT(2)
2070979aa0bSFuyun Liang #define HCLGE_SUPPORT_50G_BIT		BIT(3)
2080979aa0bSFuyun Liang #define HCLGE_SUPPORT_100G_BIT		BIT(4)
20988d10bd6SJian Shen /* to be compatible with exsit board */
21088d10bd6SJian Shen #define HCLGE_SUPPORT_40G_BIT		BIT(5)
211f18635d5SJian Shen #define HCLGE_SUPPORT_100M_BIT		BIT(6)
212f18635d5SJian Shen #define HCLGE_SUPPORT_10M_BIT		BIT(7)
213ae6f010cSGuangbin Huang #define HCLGE_SUPPORT_200G_BIT		BIT(8)
214f18635d5SJian Shen #define HCLGE_SUPPORT_GE \
215f18635d5SJian Shen 	(HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)
2160979aa0bSFuyun Liang 
21746a3df9fSSalil enum HCLGE_DEV_STATE {
21846a3df9fSSalil 	HCLGE_STATE_REINITING,
21946a3df9fSSalil 	HCLGE_STATE_DOWN,
22046a3df9fSSalil 	HCLGE_STATE_DISABLED,
22146a3df9fSSalil 	HCLGE_STATE_REMOVING,
222bd9109c9SHuazhong Tan 	HCLGE_STATE_NIC_REGISTERED,
2232a0bfc36SHuazhong Tan 	HCLGE_STATE_ROCE_REGISTERED,
22446a3df9fSSalil 	HCLGE_STATE_SERVICE_INITED,
225cb1b9f77SSalil Mehta 	HCLGE_STATE_RST_SERVICE_SCHED,
226cb1b9f77SSalil Mehta 	HCLGE_STATE_RST_HANDLING,
227c1a81619SSalil Mehta 	HCLGE_STATE_MBX_SERVICE_SCHED,
22846a3df9fSSalil 	HCLGE_STATE_MBX_HANDLING,
229d991452dSJiaran Zhang 	HCLGE_STATE_ERR_SERVICE_SCHED,
230c5f65480SJian Shen 	HCLGE_STATE_STATISTICS_UPDATING,
2318d40854fSHuazhong Tan 	HCLGE_STATE_CMD_DISABLE,
2321c6dfe6fSYunsheng Lin 	HCLGE_STATE_LINK_UPDATING,
233d5432455SGuojia Liao 	HCLGE_STATE_RST_FAIL,
234fc4243b8SJian Shen 	HCLGE_STATE_FD_TBL_CHANGED,
235fc4243b8SJian Shen 	HCLGE_STATE_FD_CLEAR_ALL,
23667b0e142SJian Shen 	HCLGE_STATE_FD_USER_DEF_CHANGED,
2370bf5eb78SHuazhong Tan 	HCLGE_STATE_PTP_EN,
2380bf5eb78SHuazhong Tan 	HCLGE_STATE_PTP_TX_HANDLING,
23946a3df9fSSalil 	HCLGE_STATE_MAX
24046a3df9fSSalil };
24146a3df9fSSalil 
242ca1d7669SSalil Mehta enum hclge_evt_cause {
243ca1d7669SSalil Mehta 	HCLGE_VECTOR0_EVENT_RST,
244ca1d7669SSalil Mehta 	HCLGE_VECTOR0_EVENT_MBX,
245f6162d44SSalil Mehta 	HCLGE_VECTOR0_EVENT_ERR,
2460bf5eb78SHuazhong Tan 	HCLGE_VECTOR0_EVENT_PTP,
247ca1d7669SSalil Mehta 	HCLGE_VECTOR0_EVENT_OTHER,
248ca1d7669SSalil Mehta };
249ca1d7669SSalil Mehta 
25046a3df9fSSalil enum HCLGE_MAC_SPEED {
2515d497936SPeng Li 	HCLGE_MAC_SPEED_UNKNOWN = 0,		/* unknown */
25246a3df9fSSalil 	HCLGE_MAC_SPEED_10M	= 10,		/* 10 Mbps */
25346a3df9fSSalil 	HCLGE_MAC_SPEED_100M	= 100,		/* 100 Mbps */
25446a3df9fSSalil 	HCLGE_MAC_SPEED_1G	= 1000,		/* 1000 Mbps   = 1 Gbps */
25546a3df9fSSalil 	HCLGE_MAC_SPEED_10G	= 10000,	/* 10000 Mbps  = 10 Gbps */
25646a3df9fSSalil 	HCLGE_MAC_SPEED_25G	= 25000,	/* 25000 Mbps  = 25 Gbps */
25746a3df9fSSalil 	HCLGE_MAC_SPEED_40G	= 40000,	/* 40000 Mbps  = 40 Gbps */
25846a3df9fSSalil 	HCLGE_MAC_SPEED_50G	= 50000,	/* 50000 Mbps  = 50 Gbps */
259ae6f010cSGuangbin Huang 	HCLGE_MAC_SPEED_100G	= 100000,	/* 100000 Mbps = 100 Gbps */
260ae6f010cSGuangbin Huang 	HCLGE_MAC_SPEED_200G	= 200000	/* 200000 Mbps = 200 Gbps */
26146a3df9fSSalil };
26246a3df9fSSalil 
26346a3df9fSSalil enum HCLGE_MAC_DUPLEX {
26446a3df9fSSalil 	HCLGE_MAC_HALF,
26546a3df9fSSalil 	HCLGE_MAC_FULL
26646a3df9fSSalil };
26746a3df9fSSalil 
26888d10bd6SJian Shen #define QUERY_SFP_SPEED		0
26988d10bd6SJian Shen #define QUERY_ACTIVE_SPEED	1
27088d10bd6SJian Shen 
27146a3df9fSSalil struct hclge_mac {
272ded45d40SYufeng Mo 	u8 mac_id;
27346a3df9fSSalil 	u8 phy_addr;
27446a3df9fSSalil 	u8 flag;
27588d10bd6SJian Shen 	u8 media_type;	/* port media type, e.g. fibre/copper/backplane */
27646a3df9fSSalil 	u8 mac_addr[ETH_ALEN];
27746a3df9fSSalil 	u8 autoneg;
27846a3df9fSSalil 	u8 duplex;
27988d10bd6SJian Shen 	u8 support_autoneg;
28088d10bd6SJian Shen 	u8 speed_type;	/* 0: sfp speed, 1: active speed */
28146a3df9fSSalil 	u32 speed;
282ee9e4424SYonglong Liu 	u32 max_speed;
28388d10bd6SJian Shen 	u32 speed_ability; /* speed ability supported by current media */
28488d10bd6SJian Shen 	u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */
2857e6ec914SJian Shen 	u32 fec_mode; /* active fec mode */
2867e6ec914SJian Shen 	u32 user_fec_mode;
2877e6ec914SJian Shen 	u32 fec_ability;
288a3a0ff01SGuangbin Huang 	int link;	/* store the link status of mac & phy (if phy exists) */
28946a3df9fSSalil 	struct phy_device *phydev;
29046a3df9fSSalil 	struct mii_bus *mdio_bus;
29146a3df9fSSalil 	phy_interface_t phy_if;
2920979aa0bSFuyun Liang 	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
2930979aa0bSFuyun Liang 	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
29446a3df9fSSalil };
29546a3df9fSSalil 
29646a3df9fSSalil struct hclge_hw {
29746a3df9fSSalil 	void __iomem *io_base;
29830ae7f8aSHuazhong Tan 	void __iomem *mem_base;
29946a3df9fSSalil 	struct hclge_mac mac;
30046a3df9fSSalil 	int num_vec;
30146a3df9fSSalil 	struct hclge_cmq cmq;
30246a3df9fSSalil };
30346a3df9fSSalil 
30446a3df9fSSalil /* TQP stats */
30546a3df9fSSalil struct hlcge_tqp_stats {
30646a3df9fSSalil 	/* query_tqp_tx_queue_statistics ,opcode id:  0x0B03 */
30746a3df9fSSalil 	u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
30846a3df9fSSalil 	/* query_tqp_rx_queue_statistics ,opcode id:  0x0B13 */
30946a3df9fSSalil 	u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
31046a3df9fSSalil };
31146a3df9fSSalil 
31246a3df9fSSalil struct hclge_tqp {
313fdace1bcSJian Shen 	/* copy of device pointer from pci_dev,
314fdace1bcSJian Shen 	 * used when perform DMA mapping
315fdace1bcSJian Shen 	 */
316fdace1bcSJian Shen 	struct device *dev;
31746a3df9fSSalil 	struct hnae3_queue q;
31846a3df9fSSalil 	struct hlcge_tqp_stats tqp_stats;
31946a3df9fSSalil 	u16 index;	/* Global index in a NIC controller */
32046a3df9fSSalil 
32146a3df9fSSalil 	bool alloced;
32246a3df9fSSalil };
32346a3df9fSSalil 
32446a3df9fSSalil enum hclge_fc_mode {
32546a3df9fSSalil 	HCLGE_FC_NONE,
32646a3df9fSSalil 	HCLGE_FC_RX_PAUSE,
32746a3df9fSSalil 	HCLGE_FC_TX_PAUSE,
32846a3df9fSSalil 	HCLGE_FC_FULL,
32946a3df9fSSalil 	HCLGE_FC_PFC,
33046a3df9fSSalil 	HCLGE_FC_DEFAULT
33146a3df9fSSalil };
33246a3df9fSSalil 
3330ca821daSJian Shen #define HCLGE_FILTER_TYPE_VF		0
3340ca821daSJian Shen #define HCLGE_FILTER_TYPE_PORT		1
3350ca821daSJian Shen #define HCLGE_FILTER_FE_EGRESS_V1_B	BIT(0)
3360ca821daSJian Shen #define HCLGE_FILTER_FE_NIC_INGRESS_B	BIT(0)
3370ca821daSJian Shen #define HCLGE_FILTER_FE_NIC_EGRESS_B	BIT(1)
3380ca821daSJian Shen #define HCLGE_FILTER_FE_ROCE_INGRESS_B	BIT(2)
3390ca821daSJian Shen #define HCLGE_FILTER_FE_ROCE_EGRESS_B	BIT(3)
3400ca821daSJian Shen #define HCLGE_FILTER_FE_EGRESS		(HCLGE_FILTER_FE_NIC_EGRESS_B \
3410ca821daSJian Shen 					| HCLGE_FILTER_FE_ROCE_EGRESS_B)
3420ca821daSJian Shen #define HCLGE_FILTER_FE_INGRESS		(HCLGE_FILTER_FE_NIC_INGRESS_B \
3430ca821daSJian Shen 					| HCLGE_FILTER_FE_ROCE_INGRESS_B)
3440ca821daSJian Shen 
3452ba30662SJian Shen enum hclge_vlan_fltr_cap {
3462ba30662SJian Shen 	HCLGE_VLAN_FLTR_DEF,
3472ba30662SJian Shen 	HCLGE_VLAN_FLTR_CAN_MDF,
3482ba30662SJian Shen };
349ed8fb4b2SJian Shen enum hclge_link_fail_code {
350ed8fb4b2SJian Shen 	HCLGE_LF_NORMAL,
351ed8fb4b2SJian Shen 	HCLGE_LF_REF_CLOCK_LOST,
352ed8fb4b2SJian Shen 	HCLGE_LF_XSFP_TX_DISABLE,
353ed8fb4b2SJian Shen 	HCLGE_LF_XSFP_ABSENT,
354ed8fb4b2SJian Shen };
355ed8fb4b2SJian Shen 
356fac24df7SJian Shen #define HCLGE_LINK_STATUS_DOWN 0
357fac24df7SJian Shen #define HCLGE_LINK_STATUS_UP   1
358fac24df7SJian Shen 
35946a3df9fSSalil #define HCLGE_PG_NUM		4
36046a3df9fSSalil #define HCLGE_SCH_MODE_SP	0
36146a3df9fSSalil #define HCLGE_SCH_MODE_DWRR	1
36246a3df9fSSalil struct hclge_pg_info {
36346a3df9fSSalil 	u8 pg_id;
36446a3df9fSSalil 	u8 pg_sch_mode;		/* 0: sp; 1: dwrr */
36546a3df9fSSalil 	u8 tc_bit_map;
36646a3df9fSSalil 	u32 bw_limit;
36746a3df9fSSalil 	u8 tc_dwrr[HNAE3_MAX_TC];
36846a3df9fSSalil };
36946a3df9fSSalil 
37046a3df9fSSalil struct hclge_tc_info {
37146a3df9fSSalil 	u8 tc_id;
37246a3df9fSSalil 	u8 tc_sch_mode;		/* 0: sp; 1: dwrr */
37346a3df9fSSalil 	u8 pgid;
37446a3df9fSSalil 	u32 bw_limit;
37546a3df9fSSalil };
37646a3df9fSSalil 
37746a3df9fSSalil struct hclge_cfg {
37846a3df9fSSalil 	u8 tc_num;
3792ba30662SJian Shen 	u8 vlan_fliter_cap;
38046a3df9fSSalil 	u16 tqp_desc_num;
38146a3df9fSSalil 	u16 rx_buf_len;
382f1c2e66dSGuojia Liao 	u16 vf_rss_size_max;
383f1c2e66dSGuojia Liao 	u16 pf_rss_size_max;
38446a3df9fSSalil 	u8 phy_addr;
38546a3df9fSSalil 	u8 media_type;
38646a3df9fSSalil 	u8 mac_addr[ETH_ALEN];
38746a3df9fSSalil 	u8 default_speed;
38846a3df9fSSalil 	u32 numa_node_map;
3891a00197bSHuazhong Tan 	u32 tx_spare_buf_size;
390ae6f010cSGuangbin Huang 	u16 speed_ability;
39139932473SJian Shen 	u16 umv_space;
39246a3df9fSSalil };
39346a3df9fSSalil 
39446a3df9fSSalil struct hclge_tm_info {
39546a3df9fSSalil 	u8 num_tc;
39646a3df9fSSalil 	u8 num_pg;      /* It must be 1 if vNET-Base schd */
39746a3df9fSSalil 	u8 pg_dwrr[HCLGE_PG_NUM];
398c5795c53SYunsheng Lin 	u8 prio_tc[HNAE3_MAX_USER_PRIO];
39946a3df9fSSalil 	struct hclge_pg_info pg_info[HCLGE_PG_NUM];
40046a3df9fSSalil 	struct hclge_tc_info tc_info[HNAE3_MAX_TC];
40146a3df9fSSalil 	enum hclge_fc_mode fc_mode;
40246a3df9fSSalil 	u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
403d3ad430aSYunsheng Lin 	u8 pfc_en;	/* PFC enabled or not for user priority */
40446a3df9fSSalil };
40546a3df9fSSalil 
40646a3df9fSSalil struct hclge_comm_stats_str {
40746a3df9fSSalil 	char desc[ETH_GSTRING_LEN];
40846a3df9fSSalil 	unsigned long offset;
40946a3df9fSSalil };
41046a3df9fSSalil 
41146a3df9fSSalil /* mac stats ,opcode id: 0x0032 */
41246a3df9fSSalil struct hclge_mac_stats {
41346a3df9fSSalil 	u64 mac_tx_mac_pause_num;
41446a3df9fSSalil 	u64 mac_rx_mac_pause_num;
41546a3df9fSSalil 	u64 mac_tx_pfc_pri0_pkt_num;
41646a3df9fSSalil 	u64 mac_tx_pfc_pri1_pkt_num;
41746a3df9fSSalil 	u64 mac_tx_pfc_pri2_pkt_num;
41846a3df9fSSalil 	u64 mac_tx_pfc_pri3_pkt_num;
41946a3df9fSSalil 	u64 mac_tx_pfc_pri4_pkt_num;
42046a3df9fSSalil 	u64 mac_tx_pfc_pri5_pkt_num;
42146a3df9fSSalil 	u64 mac_tx_pfc_pri6_pkt_num;
42246a3df9fSSalil 	u64 mac_tx_pfc_pri7_pkt_num;
42346a3df9fSSalil 	u64 mac_rx_pfc_pri0_pkt_num;
42446a3df9fSSalil 	u64 mac_rx_pfc_pri1_pkt_num;
42546a3df9fSSalil 	u64 mac_rx_pfc_pri2_pkt_num;
42646a3df9fSSalil 	u64 mac_rx_pfc_pri3_pkt_num;
42746a3df9fSSalil 	u64 mac_rx_pfc_pri4_pkt_num;
42846a3df9fSSalil 	u64 mac_rx_pfc_pri5_pkt_num;
42946a3df9fSSalil 	u64 mac_rx_pfc_pri6_pkt_num;
43046a3df9fSSalil 	u64 mac_rx_pfc_pri7_pkt_num;
43146a3df9fSSalil 	u64 mac_tx_total_pkt_num;
43246a3df9fSSalil 	u64 mac_tx_total_oct_num;
43346a3df9fSSalil 	u64 mac_tx_good_pkt_num;
43446a3df9fSSalil 	u64 mac_tx_bad_pkt_num;
43546a3df9fSSalil 	u64 mac_tx_good_oct_num;
43646a3df9fSSalil 	u64 mac_tx_bad_oct_num;
43746a3df9fSSalil 	u64 mac_tx_uni_pkt_num;
43846a3df9fSSalil 	u64 mac_tx_multi_pkt_num;
43946a3df9fSSalil 	u64 mac_tx_broad_pkt_num;
44046a3df9fSSalil 	u64 mac_tx_undersize_pkt_num;
441200a88c6SJian Shen 	u64 mac_tx_oversize_pkt_num;
44246a3df9fSSalil 	u64 mac_tx_64_oct_pkt_num;
44346a3df9fSSalil 	u64 mac_tx_65_127_oct_pkt_num;
44446a3df9fSSalil 	u64 mac_tx_128_255_oct_pkt_num;
44546a3df9fSSalil 	u64 mac_tx_256_511_oct_pkt_num;
44646a3df9fSSalil 	u64 mac_tx_512_1023_oct_pkt_num;
44746a3df9fSSalil 	u64 mac_tx_1024_1518_oct_pkt_num;
44891f384f6SJian Shen 	u64 mac_tx_1519_2047_oct_pkt_num;
44991f384f6SJian Shen 	u64 mac_tx_2048_4095_oct_pkt_num;
45091f384f6SJian Shen 	u64 mac_tx_4096_8191_oct_pkt_num;
451dbecc779SXi Wang 	u64 rsv0;
452dbecc779SXi Wang 	u64 mac_tx_8192_9216_oct_pkt_num;
453dbecc779SXi Wang 	u64 mac_tx_9217_12287_oct_pkt_num;
45491f384f6SJian Shen 	u64 mac_tx_12288_16383_oct_pkt_num;
45591f384f6SJian Shen 	u64 mac_tx_1519_max_good_oct_pkt_num;
45691f384f6SJian Shen 	u64 mac_tx_1519_max_bad_oct_pkt_num;
45791f384f6SJian Shen 
45846a3df9fSSalil 	u64 mac_rx_total_pkt_num;
45946a3df9fSSalil 	u64 mac_rx_total_oct_num;
46046a3df9fSSalil 	u64 mac_rx_good_pkt_num;
46146a3df9fSSalil 	u64 mac_rx_bad_pkt_num;
46246a3df9fSSalil 	u64 mac_rx_good_oct_num;
46346a3df9fSSalil 	u64 mac_rx_bad_oct_num;
46446a3df9fSSalil 	u64 mac_rx_uni_pkt_num;
46546a3df9fSSalil 	u64 mac_rx_multi_pkt_num;
46646a3df9fSSalil 	u64 mac_rx_broad_pkt_num;
46746a3df9fSSalil 	u64 mac_rx_undersize_pkt_num;
468200a88c6SJian Shen 	u64 mac_rx_oversize_pkt_num;
46946a3df9fSSalil 	u64 mac_rx_64_oct_pkt_num;
47046a3df9fSSalil 	u64 mac_rx_65_127_oct_pkt_num;
47146a3df9fSSalil 	u64 mac_rx_128_255_oct_pkt_num;
47246a3df9fSSalil 	u64 mac_rx_256_511_oct_pkt_num;
47346a3df9fSSalil 	u64 mac_rx_512_1023_oct_pkt_num;
47446a3df9fSSalil 	u64 mac_rx_1024_1518_oct_pkt_num;
47591f384f6SJian Shen 	u64 mac_rx_1519_2047_oct_pkt_num;
47691f384f6SJian Shen 	u64 mac_rx_2048_4095_oct_pkt_num;
47791f384f6SJian Shen 	u64 mac_rx_4096_8191_oct_pkt_num;
478dbecc779SXi Wang 	u64 rsv1;
479dbecc779SXi Wang 	u64 mac_rx_8192_9216_oct_pkt_num;
480dbecc779SXi Wang 	u64 mac_rx_9217_12287_oct_pkt_num;
48191f384f6SJian Shen 	u64 mac_rx_12288_16383_oct_pkt_num;
48291f384f6SJian Shen 	u64 mac_rx_1519_max_good_oct_pkt_num;
48391f384f6SJian Shen 	u64 mac_rx_1519_max_bad_oct_pkt_num;
48446a3df9fSSalil 
485a6c51c26SJian Shen 	u64 mac_tx_fragment_pkt_num;
486a6c51c26SJian Shen 	u64 mac_tx_undermin_pkt_num;
487a6c51c26SJian Shen 	u64 mac_tx_jabber_pkt_num;
488a6c51c26SJian Shen 	u64 mac_tx_err_all_pkt_num;
489a6c51c26SJian Shen 	u64 mac_tx_from_app_good_pkt_num;
490a6c51c26SJian Shen 	u64 mac_tx_from_app_bad_pkt_num;
491a6c51c26SJian Shen 	u64 mac_rx_fragment_pkt_num;
492a6c51c26SJian Shen 	u64 mac_rx_undermin_pkt_num;
493a6c51c26SJian Shen 	u64 mac_rx_jabber_pkt_num;
494a6c51c26SJian Shen 	u64 mac_rx_fcs_err_pkt_num;
495a6c51c26SJian Shen 	u64 mac_rx_send_app_good_pkt_num;
496a6c51c26SJian Shen 	u64 mac_rx_send_app_bad_pkt_num;
497d174ea75Sliuzhongzhu 	u64 mac_tx_pfc_pause_pkt_num;
498d174ea75Sliuzhongzhu 	u64 mac_rx_pfc_pause_pkt_num;
499d174ea75Sliuzhongzhu 	u64 mac_tx_ctrl_pkt_num;
500d174ea75Sliuzhongzhu 	u64 mac_rx_ctrl_pkt_num;
50146a3df9fSSalil };
50246a3df9fSSalil 
5031c6dfe6fSYunsheng Lin #define HCLGE_STATS_TIMER_INTERVAL	300UL
50446a3df9fSSalil 
5055f6ea83fSPeng Li struct hclge_vlan_type_cfg {
5065f6ea83fSPeng Li 	u16 rx_ot_fst_vlan_type;
5075f6ea83fSPeng Li 	u16 rx_ot_sec_vlan_type;
5085f6ea83fSPeng Li 	u16 rx_in_fst_vlan_type;
5095f6ea83fSPeng Li 	u16 rx_in_sec_vlan_type;
5105f6ea83fSPeng Li 	u16 tx_ot_vlan_type;
5115f6ea83fSPeng Li 	u16 tx_in_vlan_type;
5125f6ea83fSPeng Li };
5135f6ea83fSPeng Li 
514d695964dSJian Shen enum HCLGE_FD_MODE {
515d695964dSJian Shen 	HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1,
516d695964dSJian Shen 	HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2,
517d695964dSJian Shen 	HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1,
518d695964dSJian Shen 	HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2,
519d695964dSJian Shen };
520d695964dSJian Shen 
521d695964dSJian Shen enum HCLGE_FD_KEY_TYPE {
522d695964dSJian Shen 	HCLGE_FD_KEY_BASE_ON_PTYPE,
523d695964dSJian Shen 	HCLGE_FD_KEY_BASE_ON_TUPLE,
524d695964dSJian Shen };
525d695964dSJian Shen 
526d695964dSJian Shen enum HCLGE_FD_STAGE {
527d695964dSJian Shen 	HCLGE_FD_STAGE_1,
528d695964dSJian Shen 	HCLGE_FD_STAGE_2,
529e91e388cSJian Shen 	MAX_STAGE_NUM,
530d695964dSJian Shen };
531d695964dSJian Shen 
532d695964dSJian Shen /* OUTER_XXX indicates tuples in tunnel header of tunnel packet
533d695964dSJian Shen  * INNER_XXX indicate tuples in tunneled header of tunnel packet or
534d695964dSJian Shen  *           tuples of non-tunnel packet
535d695964dSJian Shen  */
536d695964dSJian Shen enum HCLGE_FD_TUPLE {
537d695964dSJian Shen 	OUTER_DST_MAC,
538d695964dSJian Shen 	OUTER_SRC_MAC,
539d695964dSJian Shen 	OUTER_VLAN_TAG_FST,
540d695964dSJian Shen 	OUTER_VLAN_TAG_SEC,
541d695964dSJian Shen 	OUTER_ETH_TYPE,
542d695964dSJian Shen 	OUTER_L2_RSV,
543d695964dSJian Shen 	OUTER_IP_TOS,
544d695964dSJian Shen 	OUTER_IP_PROTO,
545d695964dSJian Shen 	OUTER_SRC_IP,
546d695964dSJian Shen 	OUTER_DST_IP,
547d695964dSJian Shen 	OUTER_L3_RSV,
548d695964dSJian Shen 	OUTER_SRC_PORT,
549d695964dSJian Shen 	OUTER_DST_PORT,
550d695964dSJian Shen 	OUTER_L4_RSV,
551d695964dSJian Shen 	OUTER_TUN_VNI,
552d695964dSJian Shen 	OUTER_TUN_FLOW_ID,
553d695964dSJian Shen 	INNER_DST_MAC,
554d695964dSJian Shen 	INNER_SRC_MAC,
555d695964dSJian Shen 	INNER_VLAN_TAG_FST,
556d695964dSJian Shen 	INNER_VLAN_TAG_SEC,
557d695964dSJian Shen 	INNER_ETH_TYPE,
558d695964dSJian Shen 	INNER_L2_RSV,
559d695964dSJian Shen 	INNER_IP_TOS,
560d695964dSJian Shen 	INNER_IP_PROTO,
561d695964dSJian Shen 	INNER_SRC_IP,
562d695964dSJian Shen 	INNER_DST_IP,
563d695964dSJian Shen 	INNER_L3_RSV,
564d695964dSJian Shen 	INNER_SRC_PORT,
565d695964dSJian Shen 	INNER_DST_PORT,
566d695964dSJian Shen 	INNER_L4_RSV,
567d695964dSJian Shen 	MAX_TUPLE,
568d695964dSJian Shen };
569d695964dSJian Shen 
57067b0e142SJian Shen #define HCLGE_FD_TUPLE_USER_DEF_TUPLES \
57167b0e142SJian Shen 	(BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV))
57267b0e142SJian Shen 
573d695964dSJian Shen enum HCLGE_FD_META_DATA {
574d695964dSJian Shen 	PACKET_TYPE_ID,
575d695964dSJian Shen 	IP_FRAGEMENT,
576d695964dSJian Shen 	ROCE_TYPE,
577d695964dSJian Shen 	NEXT_KEY,
578d695964dSJian Shen 	VLAN_NUMBER,
579d695964dSJian Shen 	SRC_VPORT,
580d695964dSJian Shen 	DST_VPORT,
581d695964dSJian Shen 	TUNNEL_PACKET,
582d695964dSJian Shen 	MAX_META_DATA,
583d695964dSJian Shen };
584d695964dSJian Shen 
585fb72699dSJian Shen enum HCLGE_FD_KEY_OPT {
586fb72699dSJian Shen 	KEY_OPT_U8,
587fb72699dSJian Shen 	KEY_OPT_LE16,
588fb72699dSJian Shen 	KEY_OPT_LE32,
589fb72699dSJian Shen 	KEY_OPT_MAC,
590fb72699dSJian Shen 	KEY_OPT_IP,
591fb72699dSJian Shen 	KEY_OPT_VNI,
592fb72699dSJian Shen };
593fb72699dSJian Shen 
594d695964dSJian Shen struct key_info {
595d695964dSJian Shen 	u8 key_type;
596e91e388cSJian Shen 	u8 key_length; /* use bit as unit */
597fb72699dSJian Shen 	enum HCLGE_FD_KEY_OPT key_opt;
598fb72699dSJian Shen 	int offset;
599fb72699dSJian Shen 	int moffset;
600d695964dSJian Shen };
601d695964dSJian Shen 
602d695964dSJian Shen #define MAX_KEY_LENGTH	400
603d695964dSJian Shen #define MAX_KEY_DWORDS	DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4)
604d695964dSJian Shen #define MAX_KEY_BYTES	(MAX_KEY_DWORDS * 4)
605d695964dSJian Shen #define MAX_META_DATA_LENGTH	32
606d695964dSJian Shen 
60767b0e142SJian Shen #define HCLGE_FD_MAX_USER_DEF_OFFSET	9000
60867b0e142SJian Shen #define HCLGE_FD_USER_DEF_DATA		GENMASK(15, 0)
60967b0e142SJian Shen #define HCLGE_FD_USER_DEF_OFFSET	GENMASK(15, 0)
61067b0e142SJian Shen #define HCLGE_FD_USER_DEF_OFFSET_UNMASK	GENMASK(15, 0)
61167b0e142SJian Shen 
61244122887SJian Shen /* assigned by firmware, the real filter number for each pf may be less */
61344122887SJian Shen #define MAX_FD_FILTER_NUM	4096
6141c6dfe6fSYunsheng Lin #define HCLGE_ARFS_EXPIRE_INTERVAL	5UL
61544122887SJian Shen 
61644122887SJian Shen enum HCLGE_FD_ACTIVE_RULE_TYPE {
61744122887SJian Shen 	HCLGE_FD_RULE_NONE,
61844122887SJian Shen 	HCLGE_FD_ARFS_ACTIVE,
61944122887SJian Shen 	HCLGE_FD_EP_ACTIVE,
6200205ec04SJian Shen 	HCLGE_FD_TC_FLOWER_ACTIVE,
62144122887SJian Shen };
62244122887SJian Shen 
623d695964dSJian Shen enum HCLGE_FD_PACKET_TYPE {
624d695964dSJian Shen 	NIC_PACKET,
625d695964dSJian Shen 	ROCE_PACKET,
626d695964dSJian Shen };
627d695964dSJian Shen 
62811732868SJian Shen enum HCLGE_FD_ACTION {
6290f993fe2SJian Shen 	HCLGE_FD_ACTION_SELECT_QUEUE,
63011732868SJian Shen 	HCLGE_FD_ACTION_DROP_PACKET,
6310f993fe2SJian Shen 	HCLGE_FD_ACTION_SELECT_TC,
63211732868SJian Shen };
63311732868SJian Shen 
634fc4243b8SJian Shen enum HCLGE_FD_NODE_STATE {
635fc4243b8SJian Shen 	HCLGE_FD_TO_ADD,
636fc4243b8SJian Shen 	HCLGE_FD_TO_DEL,
637fc4243b8SJian Shen 	HCLGE_FD_ACTIVE,
638fc4243b8SJian Shen 	HCLGE_FD_DELETED,
639fc4243b8SJian Shen };
640fc4243b8SJian Shen 
64167b0e142SJian Shen enum HCLGE_FD_USER_DEF_LAYER {
64267b0e142SJian Shen 	HCLGE_FD_USER_DEF_NONE,
64367b0e142SJian Shen 	HCLGE_FD_USER_DEF_L2,
64467b0e142SJian Shen 	HCLGE_FD_USER_DEF_L3,
64567b0e142SJian Shen 	HCLGE_FD_USER_DEF_L4,
64667b0e142SJian Shen };
64767b0e142SJian Shen 
64867b0e142SJian Shen #define HCLGE_FD_USER_DEF_LAYER_NUM 3
64967b0e142SJian Shen struct hclge_fd_user_def_cfg {
65067b0e142SJian Shen 	u16 ref_cnt;
65167b0e142SJian Shen 	u16 offset;
65267b0e142SJian Shen };
65367b0e142SJian Shen 
65467b0e142SJian Shen struct hclge_fd_user_def_info {
65567b0e142SJian Shen 	enum HCLGE_FD_USER_DEF_LAYER layer;
65667b0e142SJian Shen 	u16 data;
65767b0e142SJian Shen 	u16 data_mask;
65867b0e142SJian Shen 	u16 offset;
65967b0e142SJian Shen };
66067b0e142SJian Shen 
661d695964dSJian Shen struct hclge_fd_key_cfg {
662d695964dSJian Shen 	u8 key_sel;
663d695964dSJian Shen 	u8 inner_sipv6_word_en;
664d695964dSJian Shen 	u8 inner_dipv6_word_en;
665d695964dSJian Shen 	u8 outer_sipv6_word_en;
666d695964dSJian Shen 	u8 outer_dipv6_word_en;
667d695964dSJian Shen 	u32 tuple_active;
668d695964dSJian Shen 	u32 meta_data_active;
669d695964dSJian Shen };
670d695964dSJian Shen 
671d695964dSJian Shen struct hclge_fd_cfg {
672d695964dSJian Shen 	u8 fd_mode;
673e91e388cSJian Shen 	u16 max_key_length; /* use bit as unit */
674e91e388cSJian Shen 	u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */
675e91e388cSJian Shen 	u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */
676e91e388cSJian Shen 	struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM];
67767b0e142SJian Shen 	struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM];
678d695964dSJian Shen };
679d695964dSJian Shen 
680e91e388cSJian Shen #define IPV4_INDEX	3
681e91e388cSJian Shen #define IPV6_SIZE	4
68211732868SJian Shen struct hclge_fd_rule_tuples {
683e91e388cSJian Shen 	u8 src_mac[ETH_ALEN];
684e91e388cSJian Shen 	u8 dst_mac[ETH_ALEN];
685e91e388cSJian Shen 	/* Be compatible for ip address of both ipv4 and ipv6.
686e91e388cSJian Shen 	 * For ipv4 address, we store it in src/dst_ip[3].
687e91e388cSJian Shen 	 */
688e91e388cSJian Shen 	u32 src_ip[IPV6_SIZE];
689e91e388cSJian Shen 	u32 dst_ip[IPV6_SIZE];
69011732868SJian Shen 	u16 src_port;
69111732868SJian Shen 	u16 dst_port;
69211732868SJian Shen 	u16 vlan_tag1;
69311732868SJian Shen 	u16 ether_proto;
69467b0e142SJian Shen 	u16 l2_user_def;
69567b0e142SJian Shen 	u16 l3_user_def;
69667b0e142SJian Shen 	u32 l4_user_def;
69711732868SJian Shen 	u8 ip_tos;
69811732868SJian Shen 	u8 ip_proto;
69911732868SJian Shen };
70011732868SJian Shen 
70111732868SJian Shen struct hclge_fd_rule {
70211732868SJian Shen 	struct hlist_node rule_node;
70311732868SJian Shen 	struct hclge_fd_rule_tuples tuples;
70411732868SJian Shen 	struct hclge_fd_rule_tuples tuples_mask;
70511732868SJian Shen 	u32 unused_tuple;
70611732868SJian Shen 	u32 flow_type;
7070205ec04SJian Shen 	union {
7080205ec04SJian Shen 		struct {
7090205ec04SJian Shen 			unsigned long cookie;
7100f993fe2SJian Shen 			u8 tc;
7110205ec04SJian Shen 		} cls_flower;
7120205ec04SJian Shen 		struct {
713d93ed94fSJian Shen 			u16 flow_id; /* only used for arfs */
7140205ec04SJian Shen 		} arfs;
71567b0e142SJian Shen 		struct {
71667b0e142SJian Shen 			struct hclge_fd_user_def_info user_def;
71767b0e142SJian Shen 		} ep;
7180205ec04SJian Shen 	};
7190205ec04SJian Shen 	u16 queue_id;
7200205ec04SJian Shen 	u16 vf_id;
7210205ec04SJian Shen 	u16 location;
72244122887SJian Shen 	enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type;
723fc4243b8SJian Shen 	enum HCLGE_FD_NODE_STATE state;
7240205ec04SJian Shen 	u8 action;
72511732868SJian Shen };
72611732868SJian Shen 
72711732868SJian Shen struct hclge_fd_ad_data {
72811732868SJian Shen 	u16 ad_id;
72911732868SJian Shen 	u8 drop_packet;
73011732868SJian Shen 	u8 forward_to_direct_queue;
73111732868SJian Shen 	u16 queue_id;
73211732868SJian Shen 	u8 use_counter;
73311732868SJian Shen 	u8 counter_id;
73411732868SJian Shen 	u8 use_next_stage;
73511732868SJian Shen 	u8 write_rule_id_to_bd;
73611732868SJian Shen 	u8 next_input_key;
73711732868SJian Shen 	u16 rule_id;
7380f993fe2SJian Shen 	u16 tc_size;
7390f993fe2SJian Shen 	u8 override_tc;
74011732868SJian Shen };
74111732868SJian Shen 
742ee4bcd3bSJian Shen enum HCLGE_MAC_NODE_STATE {
743ee4bcd3bSJian Shen 	HCLGE_MAC_TO_ADD,
744ee4bcd3bSJian Shen 	HCLGE_MAC_TO_DEL,
745ee4bcd3bSJian Shen 	HCLGE_MAC_ACTIVE
746ee4bcd3bSJian Shen };
747ee4bcd3bSJian Shen 
748ee4bcd3bSJian Shen struct hclge_mac_node {
7496dd86902Sliuzhongzhu 	struct list_head node;
750ee4bcd3bSJian Shen 	enum HCLGE_MAC_NODE_STATE state;
7516dd86902Sliuzhongzhu 	u8 mac_addr[ETH_ALEN];
7526dd86902Sliuzhongzhu };
7536dd86902Sliuzhongzhu 
7546dd86902Sliuzhongzhu enum HCLGE_MAC_ADDR_TYPE {
7556dd86902Sliuzhongzhu 	HCLGE_MAC_ADDR_UC,
7566dd86902Sliuzhongzhu 	HCLGE_MAC_ADDR_MC
7576dd86902Sliuzhongzhu };
7586dd86902Sliuzhongzhu 
759c6075b19Sliuzhongzhu struct hclge_vport_vlan_cfg {
760c6075b19Sliuzhongzhu 	struct list_head node;
761c6075b19Sliuzhongzhu 	int hd_tbl_status;
762c6075b19Sliuzhongzhu 	u16 vlan_id;
763c6075b19Sliuzhongzhu };
764c6075b19Sliuzhongzhu 
765f02eb82dSHuazhong Tan struct hclge_rst_stats {
766f02eb82dSHuazhong Tan 	u32 reset_done_cnt;	/* the number of reset has completed */
767f02eb82dSHuazhong Tan 	u32 hw_reset_done_cnt;	/* the number of HW reset has completed */
768f02eb82dSHuazhong Tan 	u32 pf_rst_cnt;		/* the number of PF reset */
769f02eb82dSHuazhong Tan 	u32 flr_rst_cnt;	/* the number of FLR */
770f02eb82dSHuazhong Tan 	u32 global_rst_cnt;	/* the number of GLOBAL */
771f02eb82dSHuazhong Tan 	u32 imp_rst_cnt;	/* the number of IMP reset */
772f02eb82dSHuazhong Tan 	u32 reset_cnt;		/* the number of reset */
7730ecf1f7bSHuazhong Tan 	u32 reset_fail_cnt;	/* the number of reset fail */
774f02eb82dSHuazhong Tan };
775f02eb82dSHuazhong Tan 
776a6345787SWeihang Li /* time and register status when mac tunnel interruption occur */
777a6345787SWeihang Li struct hclge_mac_tnl_stats {
778a6345787SWeihang Li 	u64 time;
779a6345787SWeihang Li 	u32 status;
780a6345787SWeihang Li };
781a6345787SWeihang Li 
782b37ce587SYufeng Mo #define HCLGE_RESET_INTERVAL	(10 * HZ)
7837cf9c069SHuazhong Tan #define HCLGE_WAIT_RESET_DONE	100
784b37ce587SYufeng Mo 
785ebaf1908SWeihang Li #pragma pack(1)
786ebaf1908SWeihang Li struct hclge_vf_vlan_cfg {
787ebaf1908SWeihang Li 	u8 mbx_cmd;
788ebaf1908SWeihang Li 	u8 subcode;
789060e9accSJian Shen 	union {
790060e9accSJian Shen 		struct {
791ebaf1908SWeihang Li 			u8 is_kill;
792ebaf1908SWeihang Li 			u16 vlan;
793ebaf1908SWeihang Li 			u16 proto;
794ebaf1908SWeihang Li 		};
795060e9accSJian Shen 		u8 enable;
796060e9accSJian Shen 	};
797060e9accSJian Shen };
798ebaf1908SWeihang Li 
799ebaf1908SWeihang Li #pragma pack()
800ebaf1908SWeihang Li 
80111732868SJian Shen /* For each bit of TCAM entry, it uses a pair of 'x' and
80211732868SJian Shen  * 'y' to indicate which value to match, like below:
80311732868SJian Shen  * ----------------------------------
80411732868SJian Shen  * | bit x | bit y |  search value  |
80511732868SJian Shen  * ----------------------------------
80611732868SJian Shen  * |   0   |   0   |   always hit   |
80711732868SJian Shen  * ----------------------------------
80811732868SJian Shen  * |   1   |   0   |   match '0'    |
80911732868SJian Shen  * ----------------------------------
81011732868SJian Shen  * |   0   |   1   |   match '1'    |
81111732868SJian Shen  * ----------------------------------
81211732868SJian Shen  * |   1   |   1   |   invalid      |
81311732868SJian Shen  * ----------------------------------
81411732868SJian Shen  * Then for input key(k) and mask(v), we can calculate the value by
81511732868SJian Shen  * the formulae:
81611732868SJian Shen  *	x = (~k) & v
81711732868SJian Shen  *	y = (k ^ ~v) & k
81811732868SJian Shen  */
8199393eb50SYufeng Mo #define calc_x(x, k, v) (x = ~(k) & (v))
82011732868SJian Shen #define calc_y(y, k, v) \
82111732868SJian Shen 	do { \
82211732868SJian Shen 		const typeof(k) _k_ = (k); \
82311732868SJian Shen 		const typeof(v) _v_ = (v); \
82411732868SJian Shen 		(y) = (_k_ ^ ~_v_) & (_k_); \
82511732868SJian Shen 	} while (0)
82611732868SJian Shen 
827a6345787SWeihang Li #define HCLGE_MAC_TNL_LOG_SIZE	8
828dc8131d8SYunsheng Lin #define HCLGE_VPORT_NUM 256
82946a3df9fSSalil struct hclge_dev {
83046a3df9fSSalil 	struct pci_dev *pdev;
83146a3df9fSSalil 	struct hnae3_ae_dev *ae_dev;
83246a3df9fSSalil 	struct hclge_hw hw;
833466b0c00SLipeng 	struct hclge_misc_vector misc_vector;
8341c6dfe6fSYunsheng Lin 	struct hclge_mac_stats mac_stats;
83546a3df9fSSalil 	unsigned long state;
8366b9a97eeSHuazhong Tan 	unsigned long flr_state;
8370742ed7cSHuazhong Tan 	unsigned long last_reset_time;
83846a3df9fSSalil 
8394ed340abSLipeng 	enum hnae3_reset_type reset_type;
8400742ed7cSHuazhong Tan 	enum hnae3_reset_type reset_level;
841720bd583SHuazhong Tan 	unsigned long default_reset_request;
842cb1b9f77SSalil Mehta 	unsigned long reset_request;	/* reset has been requested */
843ca1d7669SSalil Mehta 	unsigned long reset_pending;	/* client rst is pending to be served */
844f02eb82dSHuazhong Tan 	struct hclge_rst_stats rst_stats;
8458627bdedSHuazhong Tan 	struct semaphore reset_sem;	/* protect reset process */
84646a3df9fSSalil 	u32 fw_version;
84746a3df9fSSalil 	u16 num_tqps;			/* Num task queue pairs of this PF */
84846a3df9fSSalil 	u16 num_req_vfs;		/* Num VFs requested for this PF */
84946a3df9fSSalil 
850fdace1bcSJian Shen 	u16 base_tqp_pid;	/* Base task tqp physical id of this PF */
85146a3df9fSSalil 	u16 alloc_rss_size;		/* Allocated RSS task queue */
852f1c2e66dSGuojia Liao 	u16 vf_rss_size_max;		/* HW defined VF max RSS task queue */
853f1c2e66dSGuojia Liao 	u16 pf_rss_size_max;		/* HW defined PF max RSS task queue */
8541a00197bSHuazhong Tan 	u32 tx_spare_buf_size;		/* HW defined TX spare buffer size */
85546a3df9fSSalil 
856fdace1bcSJian Shen 	u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */
85746a3df9fSSalil 	u16 num_alloc_vport;		/* Num vports this driver supports */
85846a3df9fSSalil 	u32 numa_node_mask;
85946a3df9fSSalil 	u16 rx_buf_len;
860c0425944SPeng Li 	u16 num_tx_desc;		/* desc num of per tx queue */
861c0425944SPeng Li 	u16 num_rx_desc;		/* desc num of per rx queue */
86246a3df9fSSalil 	u8 hw_tc_map;
86346a3df9fSSalil 	enum hclge_fc_mode fc_mode_last_time;
8645d497936SPeng Li 	u8 support_sfp_query;
86546a3df9fSSalil 
86646a3df9fSSalil #define HCLGE_FLAG_TC_BASE_SCH_MODE		1
86746a3df9fSSalil #define HCLGE_FLAG_VNET_BASE_SCH_MODE		2
86846a3df9fSSalil 	u8 tx_sch_mode;
869cacde272SYunsheng Lin 	u8 tc_max;
870cacde272SYunsheng Lin 	u8 pfc_max;
87146a3df9fSSalil 
87246a3df9fSSalil 	u8 default_up;
873cacde272SYunsheng Lin 	u8 dcbx_cap;
87446a3df9fSSalil 	struct hclge_tm_info tm_info;
87546a3df9fSSalil 
87646a3df9fSSalil 	u16 num_msi;
87746a3df9fSSalil 	u16 num_msi_left;
87846a3df9fSSalil 	u16 num_msi_used;
87946a3df9fSSalil 	u32 base_msi_vector;
88046a3df9fSSalil 	u16 *vector_status;
881887c3820SSalil Mehta 	int *vector_irq;
882580a05f9SYonglong Liu 	u16 num_nic_msi;	/* Num of nic vectors for this PF */
883887c3820SSalil Mehta 	u16 num_roce_msi;	/* Num of roce vectors for this PF */
884887c3820SSalil Mehta 	int roce_base_vector;
88546a3df9fSSalil 
88646a3df9fSSalil 	unsigned long service_timer_period;
88746a3df9fSSalil 	unsigned long service_timer_previous;
88865e41e7eSHuazhong Tan 	struct timer_list reset_timer;
8897be1b9f3SYunsheng Lin 	struct delayed_work service_task;
89046a3df9fSSalil 
89146a3df9fSSalil 	bool cur_promisc;
89246a3df9fSSalil 	int num_alloc_vfs;	/* Actual number of VFs allocated */
89346a3df9fSSalil 
89446a3df9fSSalil 	struct hclge_tqp *htqp;
89546a3df9fSSalil 	struct hclge_vport *vport;
89646a3df9fSSalil 
89746a3df9fSSalil 	struct dentry *hclge_dbgfs;
89846a3df9fSSalil 
89946a3df9fSSalil 	struct hnae3_client *nic_client;
90046a3df9fSSalil 	struct hnae3_client *roce_client;
90146a3df9fSSalil 
902887c3820SSalil Mehta #define HCLGE_FLAG_MAIN			BIT(0)
903887c3820SSalil Mehta #define HCLGE_FLAG_DCB_CAPABLE		BIT(1)
904887c3820SSalil Mehta #define HCLGE_FLAG_DCB_ENABLE		BIT(2)
905887c3820SSalil Mehta #define HCLGE_FLAG_MQPRIO_ENABLE	BIT(3)
90646a3df9fSSalil 	u32 flag;
90746a3df9fSSalil 
90846a3df9fSSalil 	u32 pkt_buf_size; /* Total pf buf size for tx/rx */
909368686beSYunsheng Lin 	u32 tx_buf_size; /* Tx buffer size for each TC */
910368686beSYunsheng Lin 	u32 dv_buf_size; /* Dv buffer size for each TC */
911368686beSYunsheng Lin 
91246a3df9fSSalil 	u32 mps; /* Max packet size */
913818f1675SYunsheng Lin 	/* vport_lock protect resource shared by vports */
914818f1675SYunsheng Lin 	struct mutex vport_lock;
91546a3df9fSSalil 
9165f6ea83fSPeng Li 	struct hclge_vlan_type_cfg vlan_type_cfg;
917716aaac1SJian Shen 
918dc8131d8SYunsheng Lin 	unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)];
91981a9255eSJian Shen 	unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
920d695964dSJian Shen 
921ee4bcd3bSJian Shen 	unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
922ee4bcd3bSJian Shen 
923d695964dSJian Shen 	struct hclge_fd_cfg fd_cfg;
924dd74f815SJian Shen 	struct hlist_head fd_rule_list;
92544122887SJian Shen 	spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */
926dd74f815SJian Shen 	u16 hclge_fd_rule_num;
9271c6dfe6fSYunsheng Lin 	unsigned long serv_processed_cnt;
9281c6dfe6fSYunsheng Lin 	unsigned long last_serv_processed;
92944122887SJian Shen 	unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)];
93044122887SJian Shen 	enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type;
9319abeb7d8SJian Shen 	u8 fd_en;
9323462207dSYufeng Mo 	bool gro_en;
93339932473SJian Shen 
93439932473SJian Shen 	u16 wanted_umv_size;
93539932473SJian Shen 	/* max available unicast mac vlan space */
93639932473SJian Shen 	u16 max_umv_size;
93739932473SJian Shen 	/* private unicast mac vlan space, it's same for PF and its VFs */
93839932473SJian Shen 	u16 priv_umv_size;
93939932473SJian Shen 	/* unicast mac vlan space shared by PF and its VFs */
94039932473SJian Shen 	u16 share_umv_size;
9416dd86902Sliuzhongzhu 
942a6345787SWeihang Li 	DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats,
943a6345787SWeihang Li 		      HCLGE_MAC_TNL_LOG_SIZE);
94408125454SYunsheng Lin 
94508125454SYunsheng Lin 	/* affinity mask and notify for misc interrupt */
94608125454SYunsheng Lin 	cpumask_t affinity_mask;
94708125454SYunsheng Lin 	struct irq_affinity_notify affinity_notify;
9480bf5eb78SHuazhong Tan 	struct hclge_ptp *ptp;
949b741269bSYufeng Mo 	struct devlink *devlink;
9505f6ea83fSPeng Li };
9515f6ea83fSPeng Li 
9525f6ea83fSPeng Li /* VPort level vlan tag configuration for TX direction */
9535f6ea83fSPeng Li struct hclge_tx_vtag_cfg {
954dcb35cceSPeng Li 	bool accept_tag1;	/* Whether accept tag1 packet from host */
955dcb35cceSPeng Li 	bool accept_untag1;	/* Whether accept untag1 packet from host */
956dcb35cceSPeng Li 	bool accept_tag2;
957dcb35cceSPeng Li 	bool accept_untag2;
9585f6ea83fSPeng Li 	bool insert_tag1_en;	/* Whether insert inner vlan tag */
9595f6ea83fSPeng Li 	bool insert_tag2_en;	/* Whether insert outer vlan tag */
9605f6ea83fSPeng Li 	u16  default_tag1;	/* The default inner vlan tag to insert */
9615f6ea83fSPeng Li 	u16  default_tag2;	/* The default outer vlan tag to insert */
962592b0179SGuojia Liao 	bool tag_shift_mode_en;
9635f6ea83fSPeng Li };
9645f6ea83fSPeng Li 
9655f6ea83fSPeng Li /* VPort level vlan tag configuration for RX direction */
9665f6ea83fSPeng Li struct hclge_rx_vtag_cfg {
967592b0179SGuojia Liao 	bool rx_vlan_offload_en; /* Whether enable rx vlan offload */
968592b0179SGuojia Liao 	bool strip_tag1_en;	 /* Whether strip inner vlan tag */
969592b0179SGuojia Liao 	bool strip_tag2_en;	 /* Whether strip outer vlan tag */
970592b0179SGuojia Liao 	bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */
971592b0179SGuojia Liao 	bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */
972592b0179SGuojia Liao 	bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */
973592b0179SGuojia Liao 	bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */
97446a3df9fSSalil };
97546a3df9fSSalil 
9766f2af429SYunsheng Lin struct hclge_rss_tuple_cfg {
9776f2af429SYunsheng Lin 	u8 ipv4_tcp_en;
9786f2af429SYunsheng Lin 	u8 ipv4_udp_en;
9796f2af429SYunsheng Lin 	u8 ipv4_sctp_en;
9806f2af429SYunsheng Lin 	u8 ipv4_fragment_en;
9816f2af429SYunsheng Lin 	u8 ipv6_tcp_en;
9826f2af429SYunsheng Lin 	u8 ipv6_udp_en;
9836f2af429SYunsheng Lin 	u8 ipv6_sctp_en;
9846f2af429SYunsheng Lin 	u8 ipv6_fragment_en;
9856f2af429SYunsheng Lin };
9866f2af429SYunsheng Lin 
987a6d818e3SYunsheng Lin enum HCLGE_VPORT_STATE {
988a6d818e3SYunsheng Lin 	HCLGE_VPORT_STATE_ALIVE,
989ee4bcd3bSJian Shen 	HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
9901e6e7610SJian Shen 	HCLGE_VPORT_STATE_PROMISC_CHANGE,
9912ba30662SJian Shen 	HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
992a6d818e3SYunsheng Lin 	HCLGE_VPORT_STATE_MAX
993a6d818e3SYunsheng Lin };
994a6d818e3SYunsheng Lin 
995741fca16SJian Shen struct hclge_vlan_info {
996741fca16SJian Shen 	u16 vlan_proto; /* so far support 802.1Q only */
997741fca16SJian Shen 	u16 qos;
998741fca16SJian Shen 	u16 vlan_tag;
999741fca16SJian Shen };
1000741fca16SJian Shen 
1001741fca16SJian Shen struct hclge_port_base_vlan_config {
1002741fca16SJian Shen 	u16 state;
1003741fca16SJian Shen 	struct hclge_vlan_info vlan_info;
1004741fca16SJian Shen };
1005741fca16SJian Shen 
10066430f744SYufeng Mo struct hclge_vf_info {
10076430f744SYufeng Mo 	int link_state;
10086430f744SYufeng Mo 	u8 mac[ETH_ALEN];
100922044f95SJian Shen 	u32 spoofchk;
1010ee9e4424SYonglong Liu 	u32 max_tx_rate;
1011e196ec75SJian Shen 	u32 trusted;
10121e6e7610SJian Shen 	u8 request_uc_en;
10131e6e7610SJian Shen 	u8 request_mc_en;
10141e6e7610SJian Shen 	u8 request_bc_en;
10156430f744SYufeng Mo };
10166430f744SYufeng Mo 
101746a3df9fSSalil struct hclge_vport {
101846a3df9fSSalil 	u16 alloc_tqps;	/* Allocated Tx/Rx queues */
101946a3df9fSSalil 
102046a3df9fSSalil 	u8  rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
102146a3df9fSSalil 	/* User configured lookup table entries */
102287ce161eSGuangbin Huang 	u16 *rss_indirection_tbl;
102389523cfaSYunsheng Lin 	int rss_algo;		/* User configured hash algorithm */
10246f2af429SYunsheng Lin 	/* User configured rss tuple sets */
10256f2af429SYunsheng Lin 	struct hclge_rss_tuple_cfg rss_tuple_sets;
102689523cfaSYunsheng Lin 
102768ece54eSYunsheng Lin 	u16 alloc_rss_size;
102846a3df9fSSalil 
102946a3df9fSSalil 	u16 qs_offset;
10302566f106SYunsheng Lin 	u32 bw_limit;		/* VSI BW Limit (0 = disabled) */
103146a3df9fSSalil 	u8  dwrr;
103246a3df9fSSalil 
10332ba30662SJian Shen 	bool req_vlan_fltr_en;
10342ba30662SJian Shen 	bool cur_vlan_fltr_en;
1035fe4144d4SJian Shen 	unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
1036741fca16SJian Shen 	struct hclge_port_base_vlan_config port_base_vlan_cfg;
10375f6ea83fSPeng Li 	struct hclge_tx_vtag_cfg  txvlan_cfg;
10385f6ea83fSPeng Li 	struct hclge_rx_vtag_cfg  rxvlan_cfg;
10395f6ea83fSPeng Li 
104039932473SJian Shen 	u16 used_umv_num;
104139932473SJian Shen 
1042ebaf1908SWeihang Li 	u16 vport_id;
104346a3df9fSSalil 	struct hclge_dev *back;  /* Back reference to associated dev */
104446a3df9fSSalil 	struct hnae3_handle nic;
104546a3df9fSSalil 	struct hnae3_handle roce;
1046a6d818e3SYunsheng Lin 
1047a6d818e3SYunsheng Lin 	unsigned long state;
1048a6d818e3SYunsheng Lin 	unsigned long last_active_jiffies;
1049818f1675SYunsheng Lin 	u32 mps; /* Max packet size */
10506430f744SYufeng Mo 	struct hclge_vf_info vf_info;
10516dd86902Sliuzhongzhu 
1052c631c696SJian Shen 	u8 overflow_promisc_flags;
1053c631c696SJian Shen 	u8 last_promisc_flags;
1054c631c696SJian Shen 
1055ee4bcd3bSJian Shen 	spinlock_t mac_list_lock; /* protect mac address need to add/detele */
10566dd86902Sliuzhongzhu 	struct list_head uc_mac_list;   /* Store VF unicast table */
10576dd86902Sliuzhongzhu 	struct list_head mc_mac_list;   /* Store VF multicast table */
1058c6075b19Sliuzhongzhu 	struct list_head vlan_list;     /* Store VF vlan table */
105946a3df9fSSalil };
106046a3df9fSSalil 
1061aec35aecSGuangbin Huang struct hclge_speed_bit_map {
1062aec35aecSGuangbin Huang 	u32 speed;
1063aec35aecSGuangbin Huang 	u32 speed_bit;
1064aec35aecSGuangbin Huang };
1065aec35aecSGuangbin Huang 
1066e196ec75SJian Shen int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
1067e196ec75SJian Shen 				 bool en_mc_pmc, bool en_bc_pmc);
106846a3df9fSSalil int hclge_add_uc_addr_common(struct hclge_vport *vport,
106946a3df9fSSalil 			     const unsigned char *addr);
107046a3df9fSSalil int hclge_rm_uc_addr_common(struct hclge_vport *vport,
107146a3df9fSSalil 			    const unsigned char *addr);
107246a3df9fSSalil int hclge_add_mc_addr_common(struct hclge_vport *vport,
107346a3df9fSSalil 			     const unsigned char *addr);
107446a3df9fSSalil int hclge_rm_mc_addr_common(struct hclge_vport *vport,
107546a3df9fSSalil 			    const unsigned char *addr);
107646a3df9fSSalil 
107746a3df9fSSalil struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
107884e095d6SSalil Mehta int hclge_bind_ring_with_vector(struct hclge_vport *vport,
107984e095d6SSalil Mehta 				int vector_id, bool en,
108046a3df9fSSalil 				struct hnae3_ring_chain_node *ring_chain);
108184e095d6SSalil Mehta 
108246a3df9fSSalil static inline int hclge_get_queue_id(struct hnae3_queue *queue)
108346a3df9fSSalil {
108446a3df9fSSalil 	struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);
108546a3df9fSSalil 
108646a3df9fSSalil 	return tqp->index;
108746a3df9fSSalil }
108846a3df9fSSalil 
10896dd22bbcSHuazhong Tan static inline bool hclge_is_reset_pending(struct hclge_dev *hdev)
10906dd22bbcSHuazhong Tan {
10916dd22bbcSHuazhong Tan 	return !!hdev->reset_pending;
10926dd22bbcSHuazhong Tan }
10936dd22bbcSHuazhong Tan 
1094dea846e8SHuazhong Tan int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport);
109546a3df9fSSalil int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
1096dc8131d8SYunsheng Lin int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
1097dc8131d8SYunsheng Lin 			  u16 vlan_id, bool is_kill);
1098b2641e2aSYunsheng Lin int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable);
109977f255c1SYunsheng Lin 
110077f255c1SYunsheng Lin int hclge_buffer_alloc(struct hclge_dev *hdev);
110177f255c1SYunsheng Lin int hclge_rss_init_hw(struct hclge_dev *hdev);
1102268f5dfaSYunsheng Lin void hclge_rss_indir_init_cfg(struct hclge_dev *hdev);
1103dde1a86eSSalil Mehta 
1104dde1a86eSSalil Mehta void hclge_mbx_handler(struct hclge_dev *hdev);
11058fa86551SYufeng Mo int hclge_reset_tqp(struct hnae3_handle *handle);
11061770a7a3SPeng Li int hclge_cfg_flowctrl(struct hclge_dev *hdev);
11072bfbd35dSSalil Mehta int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id);
1108a6d818e3SYunsheng Lin int hclge_vport_start(struct hclge_vport *vport);
1109a6d818e3SYunsheng Lin void hclge_vport_stop(struct hclge_vport *vport);
1110818f1675SYunsheng Lin int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu);
11115e69ea7eSYufeng Mo int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,
111204987ca1SGuangbin Huang 		       char *buf, int len);
11130c29d191Sliuzhongzhu u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id);
1114af013903SHuazhong Tan int hclge_notify_client(struct hclge_dev *hdev,
1115af013903SHuazhong Tan 			enum hnae3_reset_notify_type type);
1116ee4bcd3bSJian Shen int hclge_update_mac_list(struct hclge_vport *vport,
1117ee4bcd3bSJian Shen 			  enum HCLGE_MAC_NODE_STATE state,
1118ee4bcd3bSJian Shen 			  enum HCLGE_MAC_ADDR_TYPE mac_type,
1119ee4bcd3bSJian Shen 			  const unsigned char *addr);
1120ee4bcd3bSJian Shen int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport,
1121ee4bcd3bSJian Shen 				       const u8 *old_addr, const u8 *new_addr);
11226dd86902Sliuzhongzhu void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,
11236dd86902Sliuzhongzhu 				  enum HCLGE_MAC_ADDR_TYPE mac_type);
1124c6075b19Sliuzhongzhu void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list);
1125c6075b19Sliuzhongzhu void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev);
1126ee4bcd3bSJian Shen void hclge_restore_mac_table_common(struct hclge_vport *vport);
1127039ba863SJian Shen void hclge_restore_vport_vlan_table(struct hclge_vport *vport);
112821e043cdSJian Shen int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
112921e043cdSJian Shen 				    struct hclge_vlan_info *vlan_info);
113092f11ea1SJian Shen int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid,
1131f2dbf0edSJian Shen 				      u16 state,
1132f2dbf0edSJian Shen 				      struct hclge_vlan_info *vlan_info);
1133ed8fb4b2SJian Shen void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time);
1134ddb54554SGuangbin Huang int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev,
1135ddb54554SGuangbin Huang 				struct hclge_desc *desc);
1136a83d2961SWeihang Li void hclge_report_hw_error(struct hclge_dev *hdev,
1137a83d2961SWeihang Li 			   enum hnae3_hw_error_type type);
1138e196ec75SJian Shen void hclge_inform_vf_promisc_info(struct hclge_vport *vport);
11391a7ff828SJiaran Zhang int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len);
114018b6e31fSGuangbin Huang int hclge_push_vf_link_status(struct hclge_vport *vport);
1141fa6a262aSJian Shen int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en);
114246a3df9fSSalil #endif
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