xref: /linux/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h (revision c04259442395a6d9648e8dd105e9058726b2451a)
1b11a0bb2SSalil Mehta /* SPDX-License-Identifier: GPL-2.0+ */
2b11a0bb2SSalil Mehta /* Copyright (c) 2016-2017 Hisilicon Limited. */
3b11a0bb2SSalil Mehta 
4b11a0bb2SSalil Mehta #ifndef __HCLGE_MBX_H
5b11a0bb2SSalil Mehta #define __HCLGE_MBX_H
6b11a0bb2SSalil Mehta #include <linux/init.h>
7b11a0bb2SSalil Mehta #include <linux/mutex.h>
8b11a0bb2SSalil Mehta #include <linux/types.h>
9b11a0bb2SSalil Mehta 
10b11a0bb2SSalil Mehta #define HCLGE_MBX_VF_MSG_DATA_NUM	16
11b11a0bb2SSalil Mehta 
12b11a0bb2SSalil Mehta enum HCLGE_MBX_OPCODE {
13b11a0bb2SSalil Mehta 	HCLGE_MBX_RESET = 0x01,		/* (VF -> PF) assert reset */
14a15fa7d4SSalil Mehta 	HCLGE_MBX_ASSERTING_RESET,	/* (PF -> VF) PF is asserting reset*/
15b11a0bb2SSalil Mehta 	HCLGE_MBX_SET_UNICAST,		/* (VF -> PF) set UC addr */
16b11a0bb2SSalil Mehta 	HCLGE_MBX_SET_MULTICAST,	/* (VF -> PF) set MC addr */
17b11a0bb2SSalil Mehta 	HCLGE_MBX_SET_VLAN,		/* (VF -> PF) set VLAN */
18b11a0bb2SSalil Mehta 	HCLGE_MBX_MAP_RING_TO_VECTOR,	/* (VF -> PF) map ring-to-vector */
19b11a0bb2SSalil Mehta 	HCLGE_MBX_UNMAP_RING_TO_VECTOR,	/* (VF -> PF) unamp ring-to-vector */
20b11a0bb2SSalil Mehta 	HCLGE_MBX_SET_PROMISC_MODE,	/* (VF -> PF) set promiscuous mode */
21b11a0bb2SSalil Mehta 	HCLGE_MBX_SET_MACVLAN,		/* (VF -> PF) set unicast filter */
22b11a0bb2SSalil Mehta 	HCLGE_MBX_API_NEGOTIATE,	/* (VF -> PF) negotiate API version */
23b11a0bb2SSalil Mehta 	HCLGE_MBX_GET_QINFO,		/* (VF -> PF) get queue config */
24*c0425944SPeng Li 	HCLGE_MBX_GET_QDEPTH,		/* (VF -> PF) get queue depth */
25b11a0bb2SSalil Mehta 	HCLGE_MBX_GET_TCINFO,		/* (VF -> PF) get TC config */
26b11a0bb2SSalil Mehta 	HCLGE_MBX_GET_RETA,		/* (VF -> PF) get RETA */
27b11a0bb2SSalil Mehta 	HCLGE_MBX_GET_RSS_KEY,		/* (VF -> PF) get RSS key */
28b11a0bb2SSalil Mehta 	HCLGE_MBX_GET_MAC_ADDR,		/* (VF -> PF) get MAC addr */
29b11a0bb2SSalil Mehta 	HCLGE_MBX_PF_VF_RESP,		/* (PF -> VF) generate respone to VF */
30b11a0bb2SSalil Mehta 	HCLGE_MBX_GET_BDNUM,		/* (VF -> PF) get BD num */
31b11a0bb2SSalil Mehta 	HCLGE_MBX_GET_BUFSIZE,		/* (VF -> PF) get buffer size */
32b11a0bb2SSalil Mehta 	HCLGE_MBX_GET_STREAMID,		/* (VF -> PF) get stream id */
33b11a0bb2SSalil Mehta 	HCLGE_MBX_SET_AESTART,		/* (VF -> PF) start ae */
34b11a0bb2SSalil Mehta 	HCLGE_MBX_SET_TSOSTATS,		/* (VF -> PF) get tso stats */
35b11a0bb2SSalil Mehta 	HCLGE_MBX_LINK_STAT_CHANGE,	/* (PF -> VF) link status has changed */
36b11a0bb2SSalil Mehta 	HCLGE_MBX_GET_BASE_CONFIG,	/* (VF -> PF) get config */
37b11a0bb2SSalil Mehta 	HCLGE_MBX_BIND_FUNC_QUEUE,	/* (VF -> PF) bind function and queue */
38b11a0bb2SSalil Mehta 	HCLGE_MBX_GET_LINK_STATUS,	/* (VF -> PF) get link status */
39b11a0bb2SSalil Mehta 	HCLGE_MBX_QUEUE_RESET,		/* (VF -> PF) reset queue */
40a6d818e3SYunsheng Lin 	HCLGE_MBX_KEEP_ALIVE,		/* (VF -> PF) send keep alive cmd */
41a6d818e3SYunsheng Lin 	HCLGE_MBX_SET_ALIVE,		/* (VF -> PF) set alive state */
42818f1675SYunsheng Lin 	HCLGE_MBX_SET_MTU,		/* (VF -> PF) set mtu */
430c29d191Sliuzhongzhu 	HCLGE_MBX_GET_QID_IN_PF,	/* (VF -> PF) get queue id in pf */
449194d18bSliuzhongzhu 	HCLGE_MBX_LINK_STAT_MODE,	/* (PF -> VF) link mode has changed */
459194d18bSliuzhongzhu 	HCLGE_MBX_GET_LINK_MODE,	/* (VF -> PF) get the link mode of pf */
466dd86902Sliuzhongzhu 
476dd86902Sliuzhongzhu 	HCLGE_MBX_GET_VF_FLR_STATUS = 200, /* (M7 -> PF) get vf reset status */
48b11a0bb2SSalil Mehta };
49b11a0bb2SSalil Mehta 
50b11a0bb2SSalil Mehta /* below are per-VF mac-vlan subcodes */
51b11a0bb2SSalil Mehta enum hclge_mbx_mac_vlan_subcode {
52b11a0bb2SSalil Mehta 	HCLGE_MBX_MAC_VLAN_UC_MODIFY = 0,	/* modify UC mac addr */
53b11a0bb2SSalil Mehta 	HCLGE_MBX_MAC_VLAN_UC_ADD,		/* add a new UC mac addr */
54b11a0bb2SSalil Mehta 	HCLGE_MBX_MAC_VLAN_UC_REMOVE,		/* remove a new UC mac addr */
55b11a0bb2SSalil Mehta 	HCLGE_MBX_MAC_VLAN_MC_MODIFY,		/* modify MC mac addr */
56b11a0bb2SSalil Mehta 	HCLGE_MBX_MAC_VLAN_MC_ADD,		/* add new MC mac addr */
57b11a0bb2SSalil Mehta 	HCLGE_MBX_MAC_VLAN_MC_REMOVE,		/* remove MC mac addr */
58b11a0bb2SSalil Mehta };
59b11a0bb2SSalil Mehta 
60b11a0bb2SSalil Mehta /* below are per-VF vlan cfg subcodes */
61b11a0bb2SSalil Mehta enum hclge_mbx_vlan_cfg_subcode {
62b11a0bb2SSalil Mehta 	HCLGE_MBX_VLAN_FILTER = 0,	/* set vlan filter */
63b11a0bb2SSalil Mehta 	HCLGE_MBX_VLAN_TX_OFF_CFG,	/* set tx side vlan offload */
64b11a0bb2SSalil Mehta 	HCLGE_MBX_VLAN_RX_OFF_CFG,	/* set rx side vlan offload */
65b11a0bb2SSalil Mehta };
66b11a0bb2SSalil Mehta 
67b11a0bb2SSalil Mehta #define HCLGE_MBX_MAX_MSG_SIZE	16
689194d18bSliuzhongzhu #define HCLGE_MBX_MAX_RESP_DATA_SIZE	16
695d02a58dSYunsheng Lin #define HCLGE_MBX_RING_MAP_BASIC_MSG_NUM	3
705d02a58dSYunsheng Lin #define HCLGE_MBX_RING_NODE_VARIABLE_NUM	3
71b11a0bb2SSalil Mehta 
72b11a0bb2SSalil Mehta struct hclgevf_mbx_resp_status {
73b11a0bb2SSalil Mehta 	struct mutex mbx_mutex; /* protects against contending sync cmd resp */
74b11a0bb2SSalil Mehta 	u32 origin_mbx_msg;
75b11a0bb2SSalil Mehta 	bool received_resp;
76b11a0bb2SSalil Mehta 	int resp_status;
77b11a0bb2SSalil Mehta 	u8 additional_info[HCLGE_MBX_MAX_RESP_DATA_SIZE];
78b11a0bb2SSalil Mehta };
79b11a0bb2SSalil Mehta 
80b11a0bb2SSalil Mehta struct hclge_mbx_vf_to_pf_cmd {
81b11a0bb2SSalil Mehta 	u8 rsv;
82b11a0bb2SSalil Mehta 	u8 mbx_src_vfid; /* Auto filled by IMP */
83b11a0bb2SSalil Mehta 	u8 rsv1[2];
84b11a0bb2SSalil Mehta 	u8 msg_len;
85b11a0bb2SSalil Mehta 	u8 rsv2[3];
86b11a0bb2SSalil Mehta 	u8 msg[HCLGE_MBX_MAX_MSG_SIZE];
87b11a0bb2SSalil Mehta };
88b11a0bb2SSalil Mehta 
89b11a0bb2SSalil Mehta struct hclge_mbx_pf_to_vf_cmd {
90b11a0bb2SSalil Mehta 	u8 dest_vfid;
91b11a0bb2SSalil Mehta 	u8 rsv[3];
92b11a0bb2SSalil Mehta 	u8 msg_len;
93b11a0bb2SSalil Mehta 	u8 rsv1[3];
94b11a0bb2SSalil Mehta 	u16 msg[8];
95b11a0bb2SSalil Mehta };
96b11a0bb2SSalil Mehta 
97aa5c4f17SHuazhong Tan struct hclge_vf_rst_cmd {
98aa5c4f17SHuazhong Tan 	u8 dest_vfid;
99aa5c4f17SHuazhong Tan 	u8 vf_rst;
100aa5c4f17SHuazhong Tan 	u8 rsv[22];
101aa5c4f17SHuazhong Tan };
102aa5c4f17SHuazhong Tan 
10307a0556aSSalil Mehta /* used by VF to store the received Async responses from PF */
10407a0556aSSalil Mehta struct hclgevf_mbx_arq_ring {
10507a0556aSSalil Mehta #define HCLGE_MBX_MAX_ARQ_MSG_SIZE	8
10607a0556aSSalil Mehta #define HCLGE_MBX_MAX_ARQ_MSG_NUM	1024
10707a0556aSSalil Mehta 	struct hclgevf_dev *hdev;
10807a0556aSSalil Mehta 	u32 head;
10907a0556aSSalil Mehta 	u32 tail;
11007a0556aSSalil Mehta 	u32 count;
11107a0556aSSalil Mehta 	u16 msg_q[HCLGE_MBX_MAX_ARQ_MSG_NUM][HCLGE_MBX_MAX_ARQ_MSG_SIZE];
11207a0556aSSalil Mehta };
11307a0556aSSalil Mehta 
114b11a0bb2SSalil Mehta #define hclge_mbx_ring_ptr_move_crq(crq) \
115b11a0bb2SSalil Mehta 	(crq->next_to_use = (crq->next_to_use + 1) % crq->desc_num)
11607a0556aSSalil Mehta #define hclge_mbx_tail_ptr_move_arq(arq) \
11707a0556aSSalil Mehta 	(arq.tail = (arq.tail + 1) % HCLGE_MBX_MAX_ARQ_MSG_SIZE)
11807a0556aSSalil Mehta #define hclge_mbx_head_ptr_move_arq(arq) \
11907a0556aSSalil Mehta 		(arq.head = (arq.head + 1) % HCLGE_MBX_MAX_ARQ_MSG_SIZE)
120b11a0bb2SSalil Mehta #endif
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