1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2017-2019 NXP */ 3 4 #include <linux/bitops.h> 5 6 #define ENETC_MM_VERIFY_SLEEP_US USEC_PER_MSEC 7 #define ENETC_MM_VERIFY_RETRIES 3 8 9 #define ENETC_NUM_TC 8 10 11 /* ENETC device IDs */ 12 #define ENETC_DEV_ID_PF 0xe100 13 #define ENETC_DEV_ID_VF 0xef00 14 #define ENETC_DEV_ID_PTP 0xee02 15 16 /* ENETC register block BAR */ 17 #define ENETC_BAR_REGS 0 18 19 /** SI regs, offset: 0h */ 20 #define ENETC_SIMR 0 21 #define ENETC_SIMR_EN BIT(31) 22 #define ENETC_SIMR_RSSE BIT(0) 23 #define ENETC_SICTR0 0x18 24 #define ENETC_SICTR1 0x1c 25 #define ENETC_SIPCAPR0 0x20 26 #define ENETC_SIPCAPR0_RSS BIT(8) 27 #define ENETC_SIPCAPR0_RFS BIT(2) 28 #define ENETC_SIPCAPR0_LSO BIT(1) 29 #define ENETC_SIPCAPR1 0x24 30 #define ENETC_SITGTGR 0x30 31 #define ENETC_SIRBGCR 0x38 32 /* cache attribute registers for transactions initiated by ENETC */ 33 #define ENETC_SICAR0 0x40 34 #define ENETC_SICAR1 0x44 35 #define ENETC_SICAR2 0x48 36 /* rd snoop, no alloc 37 * wr snoop, no alloc, partial cache line update for BDs and full cache line 38 * update for data 39 */ 40 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000 41 #define ENETC_SICAR_WR_COHERENT 0x00006727 42 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */ 43 44 #define ENETC_SIPMAR0 0x80 45 #define ENETC_SIPMAR1 0x84 46 #define ENETC_SICVLANR1 0x90 47 #define ENETC_SICVLANR2 0x94 48 #define SICVLANR_ETYPE GENMASK(15, 0) 49 50 /* VF-PF Message passing */ 51 #define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */ 52 /* msg size encoding: default and max msg value of 1024B encoded as 0 */ 53 static inline u32 enetc_vsi_set_msize(u32 size) 54 { 55 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0; 56 } 57 58 #define ENETC_PSIMSGRR 0x204 59 #define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1) 60 #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */ 61 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */ 62 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8) 63 64 #define ENETC_VSIMSGSR 0x204 /* RO */ 65 #define ENETC_VSIMSGSR_MB BIT(0) 66 #define ENETC_VSIMSGSR_MS BIT(1) 67 #define ENETC_VSIMSGSNDAR0 0x210 68 #define ENETC_VSIMSGSNDAR1 0x214 69 70 #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16) 71 #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16) 72 73 /* SI statistics */ 74 #define ENETC_SIROCT 0x300 75 #define ENETC_SIRFRM 0x308 76 #define ENETC_SIRUCA 0x310 77 #define ENETC_SIRMCA 0x318 78 #define ENETC_SITOCT 0x320 79 #define ENETC_SITFRM 0x328 80 #define ENETC_SITUCA 0x330 81 #define ENETC_SITMCA 0x338 82 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200) 83 84 /* Control BDR regs */ 85 #define ENETC_SICBDRMR 0x800 86 #define ENETC_SICBDRSR 0x804 /* RO */ 87 #define ENETC_SICBDRBAR0 0x810 88 #define ENETC_SICBDRBAR1 0x814 89 #define ENETC_SICBDRPIR 0x818 90 #define ENETC_SICBDRCIR 0x81c 91 #define ENETC_SICBDRLENR 0x820 92 93 #define ENETC_SICAPR0 0x900 94 #define ENETC_SICAPR1 0x904 95 96 #define ENETC_PSIIER 0xa00 97 #define ENETC_PSIIER_MR_MASK GENMASK(2, 1) 98 #define ENETC_PSIIDR 0xa08 99 #define ENETC_SITXIDR 0xa18 100 #define ENETC_SIRXIDR 0xa28 101 #define ENETC_SIMSIVR 0xa30 102 103 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4) 104 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4) 105 106 #define ENETC_SIUEFDCR 0xe28 107 108 #define ENETC_SIRFSCAPR 0x1200 109 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f) 110 #define ENETC_SIRSSCAPR 0x1600 111 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 112 113 /** SI BDR sub-blocks, n = 0..7 */ 114 enum enetc_bdr_type {TX, RX}; 115 #define ENETC_BDR_OFF(i) ((i) * 0x200) 116 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r)) 117 /* RX BDR reg offsets */ 118 #define ENETC_RBMR 0 119 #define ENETC_RBMR_BDS BIT(2) 120 #define ENETC_RBMR_CM BIT(4) 121 #define ENETC_RBMR_VTE BIT(5) 122 #define ENETC_RBMR_EN BIT(31) 123 #define ENETC_RBSR 0x4 124 #define ENETC_RBBSR 0x8 125 #define ENETC_RBCIR 0xc 126 #define ENETC_RBBAR0 0x10 127 #define ENETC_RBBAR1 0x14 128 #define ENETC_RBPIR 0x18 129 #define ENETC_RBLENR 0x20 130 #define ENETC_RBIER 0xa0 131 #define ENETC_RBIER_RXTIE BIT(0) 132 #define ENETC_RBIDR 0xa4 133 #define ENETC_RBICR0 0xa8 134 #define ENETC_RBICR0_ICEN BIT(31) 135 #define ENETC_RBICR0_ICPT_MASK 0x1ff 136 #define ENETC_RBICR0_SET_ICPT(n) ((n) & ENETC_RBICR0_ICPT_MASK) 137 #define ENETC_RBICR1 0xac 138 139 /* TX BDR reg offsets */ 140 #define ENETC_TBMR 0 141 #define ENETC_TBSR_BUSY BIT(0) 142 #define ENETC_TBMR_VIH BIT(9) 143 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0) 144 #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK) 145 #define ENETC_TBMR_EN BIT(31) 146 #define ENETC_TBSR 0x4 147 #define ENETC_TBBAR0 0x10 148 #define ENETC_TBBAR1 0x14 149 #define ENETC_TBPIR 0x18 150 #define ENETC_TBCIR 0x1c 151 #define ENETC_TBCIR_IDX_MASK 0xffff 152 #define ENETC_TBLENR 0x20 153 #define ENETC_TBIER 0xa0 154 #define ENETC_TBIER_TXTIE BIT(0) 155 #define ENETC_TBIDR 0xa4 156 #define ENETC_TBICR0 0xa8 157 #define ENETC_TBICR0_ICEN BIT(31) 158 #define ENETC_TBICR0_ICPT_MASK 0xf 159 #define ENETC_TBICR0_SET_ICPT(n) ((ilog2(n) + 1) & ENETC_TBICR0_ICPT_MASK) 160 #define ENETC_TBICR1 0xac 161 162 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7) 163 164 /* Port regs, offset: 1_0000h */ 165 #define ENETC_PORT_BASE 0x10000 166 #define ENETC_PMR 0x0000 167 #define ENETC_PMR_EN GENMASK(18, 16) 168 #define ENETC_PMR_PSPEED_MASK GENMASK(11, 8) 169 #define ENETC_PMR_PSPEED_10M 0 170 #define ENETC_PMR_PSPEED_100M BIT(8) 171 #define ENETC_PMR_PSPEED_1000M BIT(9) 172 #define ENETC_PMR_PSPEED_2500M BIT(10) 173 #define ENETC_PSR 0x0004 /* RO */ 174 #define ENETC_PSIPMR 0x0018 175 #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */ 176 #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16) 177 #define ENETC_PSIPVMR 0x001c 178 #define ENETC_VLAN_PROMISC_MAP_ALL 0x7 179 #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7) 180 #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16) 181 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */ 182 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8) 183 #define ENETC_PVCLCTR 0x0208 184 #define ENETC_PCVLANR1 0x0210 185 #define ENETC_PCVLANR2 0x0214 186 #define ENETC_VLAN_TYPE_C BIT(0) 187 #define ENETC_VLAN_TYPE_S BIT(1) 188 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */ 189 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */ 190 #define ENETC_PSIVLAN_EN BIT(31) 191 #define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12) 192 #define ENETC_PPAUONTR 0x0410 193 #define ENETC_PPAUOFFTR 0x0414 194 #define ENETC_PTXMBAR 0x0608 195 #define ENETC_PCAPR0 0x0900 196 #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24) 197 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff) 198 #define ENETC_PCAPR0_PSFP BIT(9) 199 #define ENETC_PCAPR0_QBV BIT(4) 200 #define ENETC_PCAPR0_QBU BIT(3) 201 #define ENETC_PCAPR1 0x0904 202 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */ 203 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff) 204 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16) 205 #define ENETC_PSICFGR0_VTE BIT(12) 206 #define ENETC_PSICFGR0_SIVIE BIT(14) 207 #define ENETC_PSICFGR0_ASE BIT(15) 208 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */ 209 210 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/ 211 #define ENETC_CBSE BIT(31) 212 #define ENETC_CBS_BW_MASK GENMASK(6, 0) 213 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/ 214 #define ENETC_RSSHASH_KEY_SIZE 40 215 #define ENETC_PRSSCAPR 0x1404 216 #define ENETC_PRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) 217 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */ 218 #define ENETC_PSIVLANFMR 0x1700 219 #define ENETC_PSIVLANFMR_VS BIT(0) 220 #define ENETC_PRFSMR 0x1800 221 #define ENETC_PRFSMR_RFSE BIT(31) 222 #define ENETC_PRFSCAPR 0x1804 223 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16) 224 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */ 225 #define ENETC_PFPMR 0x1900 226 #define ENETC_PFPMR_PMACE BIT(1) 227 #define ENETC_EMDIO_BASE 0x1c00 228 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10) 229 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10) 230 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10) 231 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10) 232 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */ 233 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */ 234 #define ENETC_MMCSR 0x1f00 235 #define ENETC_MMCSR_LINK_FAIL BIT(31) 236 #define ENETC_MMCSR_VT_MASK GENMASK(29, 23) /* Verify Time */ 237 #define ENETC_MMCSR_VT(x) (((x) << 23) & ENETC_MMCSR_VT_MASK) 238 #define ENETC_MMCSR_GET_VT(x) (((x) & ENETC_MMCSR_VT_MASK) >> 23) 239 #define ENETC_MMCSR_TXSTS_MASK GENMASK(22, 21) /* Merge Status */ 240 #define ENETC_MMCSR_GET_TXSTS(x) (((x) & ENETC_MMCSR_TXSTS_MASK) >> 21) 241 #define ENETC_MMCSR_VSTS_MASK GENMASK(20, 18) /* Verify Status */ 242 #define ENETC_MMCSR_GET_VSTS(x) (((x) & ENETC_MMCSR_VSTS_MASK) >> 18) 243 #define ENETC_MMCSR_VDIS BIT(17) /* Verify Disabled */ 244 #define ENETC_MMCSR_ME BIT(16) /* Merge Enabled */ 245 #define ENETC_MMCSR_RAFS_MASK GENMASK(9, 8) /* Remote Additional Fragment Size */ 246 #define ENETC_MMCSR_RAFS(x) (((x) << 8) & ENETC_MMCSR_RAFS_MASK) 247 #define ENETC_MMCSR_GET_RAFS(x) (((x) & ENETC_MMCSR_RAFS_MASK) >> 8) 248 #define ENETC_MMCSR_LAFS_MASK GENMASK(4, 3) /* Local Additional Fragment Size */ 249 #define ENETC_MMCSR_GET_LAFS(x) (((x) & ENETC_MMCSR_LAFS_MASK) >> 3) 250 #define ENETC_MMCSR_LPA BIT(2) /* Local Preemption Active */ 251 #define ENETC_MMCSR_LPE BIT(1) /* Local Preemption Enabled */ 252 #define ENETC_MMCSR_LPS BIT(0) /* Local Preemption Supported */ 253 #define ENETC_MMFAECR 0x1f08 254 #define ENETC_MMFSECR 0x1f0c 255 #define ENETC_MMFAOCR 0x1f10 256 #define ENETC_MMFCRXR 0x1f14 257 #define ENETC_MMFCTXR 0x1f18 258 #define ENETC_MMHCR 0x1f1c 259 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */ 260 261 #define ENETC_PMAC_OFFSET 0x1000 262 263 #define ENETC_PM0_CMD_CFG 0x8008 264 #define ENETC_PM0_TX_EN BIT(0) 265 #define ENETC_PM0_RX_EN BIT(1) 266 #define ENETC_PM0_PROMISC BIT(4) 267 #define ENETC_PM0_PAUSE_IGN BIT(8) 268 #define ENETC_PM0_CMD_XGLP BIT(10) 269 #define ENETC_PM0_CMD_TXP BIT(11) 270 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15) 271 #define ENETC_PM0_CMD_SFD BIT(21) 272 #define ENETC_PM0_MAXFRM 0x8014 273 #define ENETC_SET_TX_MTU(val) ((val) << 16) 274 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff) 275 #define ENETC_PM0_RX_FIFO 0x801c 276 #define ENETC_PM0_RX_FIFO_VAL 1 277 278 #define ENETC_PM_IMDIO_BASE 0x8030 279 280 #define ENETC_PM0_PAUSE_QUANTA 0x8054 281 #define ENETC_PM0_PAUSE_THRESH 0x8064 282 283 #define ENETC_PM0_SINGLE_STEP 0x80c0 284 #define ENETC_PM0_SINGLE_STEP_CH BIT(7) 285 #define ENETC_PM0_SINGLE_STEP_EN BIT(31) 286 #define ENETC_SET_SINGLE_STEP_OFFSET(v) (((v) & 0xff) << 8) 287 288 #define ENETC_PM0_IF_MODE 0x8300 289 #define ENETC_PM0_IFM_RG BIT(2) 290 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11)) 291 #define ENETC_PM0_IFM_EN_AUTO BIT(15) 292 #define ENETC_PM0_IFM_SSP_MASK GENMASK(14, 13) 293 #define ENETC_PM0_IFM_SSP_1000 (2 << 13) 294 #define ENETC_PM0_IFM_SSP_100 (0 << 13) 295 #define ENETC_PM0_IFM_SSP_10 (1 << 13) 296 #define ENETC_PM0_IFM_FULL_DPX BIT(12) 297 #define ENETC_PM0_IFM_IFMODE_MASK GENMASK(1, 0) 298 #define ENETC_PM0_IFM_IFMODE_XGMII 0 299 #define ENETC_PM0_IFM_IFMODE_GMII 2 300 #define ENETC_PSIDCAPR 0x1b08 301 #define ENETC_PSIDCAPR_MSK GENMASK(15, 0) 302 #define ENETC_PSFCAPR 0x1b18 303 #define ENETC_PSFCAPR_MSK GENMASK(15, 0) 304 #define ENETC_PSGCAPR 0x1b28 305 #define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16) 306 #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0) 307 #define ENETC_PFMCAPR 0x1b38 308 #define ENETC_PFMCAPR_MSK GENMASK(15, 0) 309 310 /* Port MAC counters: Port MAC 0 corresponds to the eMAC and 311 * Port MAC 1 to the pMAC. 312 */ 313 #define ENETC_PM_REOCT(mac) (0x8100 + ENETC_PMAC_OFFSET * (mac)) 314 #define ENETC_PM_RALN(mac) (0x8110 + ENETC_PMAC_OFFSET * (mac)) 315 #define ENETC_PM_RXPF(mac) (0x8118 + ENETC_PMAC_OFFSET * (mac)) 316 #define ENETC_PM_RFRM(mac) (0x8120 + ENETC_PMAC_OFFSET * (mac)) 317 #define ENETC_PM_RFCS(mac) (0x8128 + ENETC_PMAC_OFFSET * (mac)) 318 #define ENETC_PM_RVLAN(mac) (0x8130 + ENETC_PMAC_OFFSET * (mac)) 319 #define ENETC_PM_RERR(mac) (0x8138 + ENETC_PMAC_OFFSET * (mac)) 320 #define ENETC_PM_RUCA(mac) (0x8140 + ENETC_PMAC_OFFSET * (mac)) 321 #define ENETC_PM_RMCA(mac) (0x8148 + ENETC_PMAC_OFFSET * (mac)) 322 #define ENETC_PM_RBCA(mac) (0x8150 + ENETC_PMAC_OFFSET * (mac)) 323 #define ENETC_PM_RDRP(mac) (0x8158 + ENETC_PMAC_OFFSET * (mac)) 324 #define ENETC_PM_RPKT(mac) (0x8160 + ENETC_PMAC_OFFSET * (mac)) 325 #define ENETC_PM_RUND(mac) (0x8168 + ENETC_PMAC_OFFSET * (mac)) 326 #define ENETC_PM_R64(mac) (0x8170 + ENETC_PMAC_OFFSET * (mac)) 327 #define ENETC_PM_R127(mac) (0x8178 + ENETC_PMAC_OFFSET * (mac)) 328 #define ENETC_PM_R255(mac) (0x8180 + ENETC_PMAC_OFFSET * (mac)) 329 #define ENETC_PM_R511(mac) (0x8188 + ENETC_PMAC_OFFSET * (mac)) 330 #define ENETC_PM_R1023(mac) (0x8190 + ENETC_PMAC_OFFSET * (mac)) 331 #define ENETC_PM_R1522(mac) (0x8198 + ENETC_PMAC_OFFSET * (mac)) 332 #define ENETC_PM_R1523X(mac) (0x81A0 + ENETC_PMAC_OFFSET * (mac)) 333 #define ENETC_PM_ROVR(mac) (0x81A8 + ENETC_PMAC_OFFSET * (mac)) 334 #define ENETC_PM_RJBR(mac) (0x81B0 + ENETC_PMAC_OFFSET * (mac)) 335 #define ENETC_PM_RFRG(mac) (0x81B8 + ENETC_PMAC_OFFSET * (mac)) 336 #define ENETC_PM_RCNP(mac) (0x81C0 + ENETC_PMAC_OFFSET * (mac)) 337 #define ENETC_PM_RDRNTP(mac) (0x81C8 + ENETC_PMAC_OFFSET * (mac)) 338 #define ENETC_PM_TEOCT(mac) (0x8200 + ENETC_PMAC_OFFSET * (mac)) 339 #define ENETC_PM_TOCT(mac) (0x8208 + ENETC_PMAC_OFFSET * (mac)) 340 #define ENETC_PM_TCRSE(mac) (0x8210 + ENETC_PMAC_OFFSET * (mac)) 341 #define ENETC_PM_TXPF(mac) (0x8218 + ENETC_PMAC_OFFSET * (mac)) 342 #define ENETC_PM_TFRM(mac) (0x8220 + ENETC_PMAC_OFFSET * (mac)) 343 #define ENETC_PM_TFCS(mac) (0x8228 + ENETC_PMAC_OFFSET * (mac)) 344 #define ENETC_PM_TVLAN(mac) (0x8230 + ENETC_PMAC_OFFSET * (mac)) 345 #define ENETC_PM_TERR(mac) (0x8238 + ENETC_PMAC_OFFSET * (mac)) 346 #define ENETC_PM_TUCA(mac) (0x8240 + ENETC_PMAC_OFFSET * (mac)) 347 #define ENETC_PM_TMCA(mac) (0x8248 + ENETC_PMAC_OFFSET * (mac)) 348 #define ENETC_PM_TBCA(mac) (0x8250 + ENETC_PMAC_OFFSET * (mac)) 349 #define ENETC_PM_TPKT(mac) (0x8260 + ENETC_PMAC_OFFSET * (mac)) 350 #define ENETC_PM_TUND(mac) (0x8268 + ENETC_PMAC_OFFSET * (mac)) 351 #define ENETC_PM_T64(mac) (0x8270 + ENETC_PMAC_OFFSET * (mac)) 352 #define ENETC_PM_T127(mac) (0x8278 + ENETC_PMAC_OFFSET * (mac)) 353 #define ENETC_PM_T255(mac) (0x8280 + ENETC_PMAC_OFFSET * (mac)) 354 #define ENETC_PM_T511(mac) (0x8288 + ENETC_PMAC_OFFSET * (mac)) 355 #define ENETC_PM_T1023(mac) (0x8290 + ENETC_PMAC_OFFSET * (mac)) 356 #define ENETC_PM_T1522(mac) (0x8298 + ENETC_PMAC_OFFSET * (mac)) 357 #define ENETC_PM_T1523X(mac) (0x82A0 + ENETC_PMAC_OFFSET * (mac)) 358 #define ENETC_PM_TCNP(mac) (0x82C0 + ENETC_PMAC_OFFSET * (mac)) 359 #define ENETC_PM_TDFR(mac) (0x82D0 + ENETC_PMAC_OFFSET * (mac)) 360 #define ENETC_PM_TMCOL(mac) (0x82D8 + ENETC_PMAC_OFFSET * (mac)) 361 #define ENETC_PM_TSCOL(mac) (0x82E0 + ENETC_PMAC_OFFSET * (mac)) 362 #define ENETC_PM_TLCOL(mac) (0x82E8 + ENETC_PMAC_OFFSET * (mac)) 363 #define ENETC_PM_TECOL(mac) (0x82F0 + ENETC_PMAC_OFFSET * (mac)) 364 365 /* Port counters */ 366 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */ 367 #define ENETC_PBFDSIR 0x0810 368 #define ENETC_PFDMSAPR 0x0814 369 #define ENETC_UFDMF 0x1680 370 #define ENETC_MFDMF 0x1684 371 #define ENETC_PUFDVFR 0x1780 372 #define ENETC_PMFDVFR 0x1784 373 #define ENETC_PBFDVFR 0x1788 374 375 /** Global regs, offset: 2_0000h */ 376 #define ENETC_GLOBAL_BASE 0x20000 377 #define ENETC_G_EIPBRR0 0x0bf8 378 #define EIPBRR0_REVISION GENMASK(15, 0) 379 #define ENETC_REV_1_0 0x0100 380 #define ENETC_REV_4_1 0X0401 381 382 #define ENETC_G_EIPBRR1 0x0bfc 383 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n)) 384 #define ENETC_G_EPFBLPR1_XGMII 0x80000000 385 386 /* PCI device info */ 387 struct enetc_hw { 388 /* SI registers, used by all PCI functions */ 389 void __iomem *reg; 390 /* Port registers, PF only */ 391 void __iomem *port; 392 /* IP global registers, PF only */ 393 void __iomem *global; 394 }; 395 396 /* ENETC register accessors */ 397 398 /* MDIO issue workaround (on LS1028A) - 399 * Due to a hardware issue, an access to MDIO registers 400 * that is concurrent with other ENETC register accesses 401 * may lead to the MDIO access being dropped or corrupted. 402 * To protect the MDIO accesses a readers-writers locking 403 * scheme is used, where the MDIO register accesses are 404 * protected by write locks to insure exclusivity, while 405 * the remaining ENETC registers are accessed under read 406 * locks since they only compete with MDIO accesses. 407 */ 408 extern rwlock_t enetc_mdio_lock; 409 410 DECLARE_STATIC_KEY_FALSE(enetc_has_err050089); 411 412 /* use this locking primitive only on the fast datapath to 413 * group together multiple non-MDIO register accesses to 414 * minimize the overhead of the lock 415 */ 416 static inline void enetc_lock_mdio(void) 417 { 418 if (static_branch_unlikely(&enetc_has_err050089)) 419 read_lock(&enetc_mdio_lock); 420 } 421 422 static inline void enetc_unlock_mdio(void) 423 { 424 if (static_branch_unlikely(&enetc_has_err050089)) 425 read_unlock(&enetc_mdio_lock); 426 } 427 428 /* use these accessors only on the fast datapath under 429 * the enetc_lock_mdio() locking primitive to minimize 430 * the overhead of the lock 431 */ 432 static inline u32 enetc_rd_reg_hot(void __iomem *reg) 433 { 434 if (static_branch_unlikely(&enetc_has_err050089)) 435 lockdep_assert_held(&enetc_mdio_lock); 436 437 return ioread32(reg); 438 } 439 440 static inline void enetc_wr_reg_hot(void __iomem *reg, u32 val) 441 { 442 if (static_branch_unlikely(&enetc_has_err050089)) 443 lockdep_assert_held(&enetc_mdio_lock); 444 445 iowrite32(val, reg); 446 } 447 448 /* internal helpers for the MDIO w/a */ 449 static inline u32 _enetc_rd_reg_wa(void __iomem *reg) 450 { 451 u32 val; 452 453 enetc_lock_mdio(); 454 val = ioread32(reg); 455 enetc_unlock_mdio(); 456 457 return val; 458 } 459 460 static inline void _enetc_wr_reg_wa(void __iomem *reg, u32 val) 461 { 462 enetc_lock_mdio(); 463 iowrite32(val, reg); 464 enetc_unlock_mdio(); 465 } 466 467 static inline u32 _enetc_rd_mdio_reg_wa(void __iomem *reg) 468 { 469 unsigned long flags; 470 u32 val; 471 472 if (static_branch_unlikely(&enetc_has_err050089)) { 473 write_lock_irqsave(&enetc_mdio_lock, flags); 474 val = ioread32(reg); 475 write_unlock_irqrestore(&enetc_mdio_lock, flags); 476 } else { 477 val = ioread32(reg); 478 } 479 480 return val; 481 } 482 483 static inline void _enetc_wr_mdio_reg_wa(void __iomem *reg, u32 val) 484 { 485 unsigned long flags; 486 487 if (static_branch_unlikely(&enetc_has_err050089)) { 488 write_lock_irqsave(&enetc_mdio_lock, flags); 489 iowrite32(val, reg); 490 write_unlock_irqrestore(&enetc_mdio_lock, flags); 491 } else { 492 iowrite32(val, reg); 493 } 494 } 495 496 #ifdef ioread64 497 static inline u64 _enetc_rd_reg64(void __iomem *reg) 498 { 499 return ioread64(reg); 500 } 501 #else 502 /* using this to read out stats on 32b systems */ 503 static inline u64 _enetc_rd_reg64(void __iomem *reg) 504 { 505 u32 low, high, tmp; 506 507 do { 508 high = ioread32(reg + 4); 509 low = ioread32(reg); 510 tmp = ioread32(reg + 4); 511 } while (high != tmp); 512 513 return (u64)high << 32 | low; 514 } 515 #endif 516 517 static inline u64 _enetc_rd_reg64_wa(void __iomem *reg) 518 { 519 u64 val; 520 521 enetc_lock_mdio(); 522 val = _enetc_rd_reg64(reg); 523 enetc_unlock_mdio(); 524 525 return val; 526 } 527 528 /* general register accessors */ 529 #define enetc_rd_reg(reg) _enetc_rd_reg_wa((reg)) 530 #define enetc_wr_reg(reg, val) _enetc_wr_reg_wa((reg), (val)) 531 #define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off)) 532 #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val) 533 #define enetc_rd_hot(hw, off) enetc_rd_reg_hot((hw)->reg + (off)) 534 #define enetc_wr_hot(hw, off, val) enetc_wr_reg_hot((hw)->reg + (off), val) 535 #define enetc_rd64(hw, off) _enetc_rd_reg64_wa((hw)->reg + (off)) 536 /* port register accessors - PF only */ 537 #define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off)) 538 #define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val) 539 #define enetc_port_rd64(hw, off) _enetc_rd_reg64_wa((hw)->port + (off)) 540 #define enetc_port_rd_mdio(hw, off) _enetc_rd_mdio_reg_wa((hw)->port + (off)) 541 #define enetc_port_wr_mdio(hw, off, val) _enetc_wr_mdio_reg_wa(\ 542 (hw)->port + (off), val) 543 /* global register accessors - PF only */ 544 #define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off)) 545 #define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val) 546 /* BDR register accessors, see ENETC_BDR() */ 547 #define enetc_bdr_rd(hw, t, n, off) \ 548 enetc_rd(hw, ENETC_BDR(t, n, off)) 549 #define enetc_bdr_wr(hw, t, n, off, val) \ 550 enetc_wr(hw, ENETC_BDR(t, n, off), val) 551 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off) 552 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off) 553 #define enetc_txbdr_wr(hw, n, off, val) \ 554 enetc_bdr_wr(hw, TX, n, off, val) 555 #define enetc_rxbdr_wr(hw, n, off, val) \ 556 enetc_bdr_wr(hw, RX, n, off, val) 557 558 /* Buffer Descriptors (BD) */ 559 union enetc_tx_bd { 560 struct { 561 __le64 addr; 562 union { 563 __le16 buf_len; 564 __le16 hdr_len; /* For LSO, ENETC 4.1 and later */ 565 }; 566 __le16 frm_len; 567 union { 568 struct { 569 u8 l3_aux0; 570 #define ENETC_TX_BD_L3_START GENMASK(6, 0) 571 #define ENETC_TX_BD_IPCS BIT(7) 572 u8 l3_aux1; 573 #define ENETC_TX_BD_L3_HDR_LEN GENMASK(6, 0) 574 #define ENETC_TX_BD_L3T BIT(7) 575 u8 l4_aux; 576 #define ENETC_TX_BD_L4T GENMASK(7, 5) 577 #define ENETC_TXBD_L4T_UDP 1 578 #define ENETC_TXBD_L4T_TCP 2 579 u8 flags; 580 }; /* default layout */ 581 __le32 txstart; 582 __le32 lstatus; 583 }; 584 }; 585 struct { 586 __le32 tstamp; 587 __le16 tpid; 588 __le16 vid; 589 __le16 lso_sg_size; /* For ENETC 4.1 and later */ 590 __le16 frm_len_ext; /* For ENETC 4.1 and later */ 591 u8 reserved[2]; 592 u8 e_flags; 593 u8 flags; 594 } ext; /* Tx BD extension */ 595 struct { 596 __le32 tstamp; 597 u8 reserved[8]; 598 __le16 lso_err_count; /* For ENETC 4.1 and later */ 599 u8 status; 600 u8 flags; 601 } wb; /* writeback descriptor */ 602 }; 603 604 enum enetc_txbd_flags { 605 ENETC_TXBD_FLAGS_L4CS = BIT(0), /* For ENETC 4.1 and later */ 606 ENETC_TXBD_FLAGS_TSE = BIT(1), 607 ENETC_TXBD_FLAGS_LSO = BIT(1), /* For ENETC 4.1 and later */ 608 ENETC_TXBD_FLAGS_W = BIT(2), 609 ENETC_TXBD_FLAGS_CSUM_LSO = BIT(3), /* For ENETC 4.1 and later */ 610 ENETC_TXBD_FLAGS_TXSTART = BIT(4), 611 ENETC_TXBD_FLAGS_EX = BIT(6), 612 ENETC_TXBD_FLAGS_F = BIT(7) 613 }; 614 #define ENETC_TXBD_STATS_WIN BIT(7) 615 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0) 616 #define ENETC_TXBD_FLAGS_OFFSET 24 617 618 static inline __le32 enetc_txbd_set_tx_start(u64 tx_start, u8 flags) 619 { 620 u32 temp; 621 622 temp = (tx_start >> 5 & ENETC_TXBD_TXSTART_MASK) | 623 (flags << ENETC_TXBD_FLAGS_OFFSET); 624 625 return cpu_to_le32(temp); 626 } 627 628 static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd) 629 { 630 memset(txbd, 0, sizeof(*txbd)); 631 } 632 633 /* Extension flags */ 634 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0) 635 #define ENETC_TXBD_E_FLAGS_ONE_STEP_PTP BIT(1) 636 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2) 637 638 union enetc_rx_bd { 639 struct { 640 __le64 addr; 641 u8 reserved[8]; 642 } w; 643 struct { 644 __le16 inet_csum; 645 __le16 parse_summary; 646 __le32 rss_hash; 647 __le16 buf_len; 648 __le16 vlan_opt; 649 union { 650 struct { 651 __le16 flags; 652 __le16 error; 653 }; 654 __le32 lstatus; 655 }; 656 } r; 657 struct { 658 __le32 tstamp; 659 u8 reserved[12]; 660 } ext; 661 }; 662 663 #define ENETC_RXBD_LSTATUS_R BIT(30) 664 #define ENETC_RXBD_LSTATUS_F BIT(31) 665 #define ENETC_RXBD_ERR_MASK 0xff 666 #define ENETC_RXBD_LSTATUS(flags) ((flags) << 16) 667 #define ENETC_RXBD_FLAG_VLAN BIT(9) 668 #define ENETC_RXBD_FLAG_TSTMP BIT(10) 669 #define ENETC_RXBD_FLAG_TPID GENMASK(1, 0) 670 671 #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */ 672 #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */ 673 #define ENETC_MAX_NUM_VFS 2 674 675 #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */ 676 #define ENETC_CBD_STATUS_MASK 0xf 677 678 #define ENETC_TPID_8021Q 0 679 680 struct enetc_cmd_rfse { 681 u8 smac_h[6]; 682 u8 smac_m[6]; 683 u8 dmac_h[6]; 684 u8 dmac_m[6]; 685 __be32 sip_h[4]; 686 __be32 sip_m[4]; 687 __be32 dip_h[4]; 688 __be32 dip_m[4]; 689 u16 ethtype_h; 690 u16 ethtype_m; 691 u16 ethtype4_h; 692 u16 ethtype4_m; 693 u16 sport_h; 694 u16 sport_m; 695 u16 dport_h; 696 u16 dport_m; 697 u16 vlan_h; 698 u16 vlan_m; 699 u8 proto_h; 700 u8 proto_m; 701 u16 flags; 702 u16 result; 703 u16 mode; 704 }; 705 706 #define ENETC_RFSE_EN BIT(15) 707 #define ENETC_RFSE_MODE_BD 2 708 709 static inline void enetc_load_primary_mac_addr(struct enetc_hw *hw, 710 struct net_device *ndev) 711 { 712 u8 addr[ETH_ALEN] __aligned(4); 713 714 *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0); 715 *(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1); 716 eth_hw_addr_set(ndev, addr); 717 } 718 719 #define ENETC_SI_INT_IDX 0 720 /* base index for Rx/Tx interrupts */ 721 #define ENETC_BDR_INT_BASE_IDX 1 722 723 /* Messaging */ 724 725 /* Command completion status */ 726 enum enetc_msg_cmd_status { 727 ENETC_MSG_CMD_STATUS_OK, 728 ENETC_MSG_CMD_STATUS_FAIL 729 }; 730 731 /* VSI-PSI command message types */ 732 enum enetc_msg_cmd_type { 733 ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */ 734 ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */ 735 ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */ 736 }; 737 738 /* VSI-PSI command action types */ 739 enum enetc_msg_cmd_action_type { 740 ENETC_MSG_CMD_MNG_ADD = 1, 741 ENETC_MSG_CMD_MNG_REMOVE 742 }; 743 744 /* PSI-VSI command header format */ 745 struct enetc_msg_cmd_header { 746 u16 type; /* command class type */ 747 u16 id; /* denotes the specific required action */ 748 }; 749 750 /* Common H/W utility functions */ 751 752 static inline void enetc_bdr_enable_rxvlan(struct enetc_hw *hw, int idx, 753 bool en) 754 { 755 u32 val = enetc_rxbdr_rd(hw, idx, ENETC_RBMR); 756 757 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0); 758 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, val); 759 } 760 761 static inline void enetc_bdr_enable_txvlan(struct enetc_hw *hw, int idx, 762 bool en) 763 { 764 u32 val = enetc_txbdr_rd(hw, idx, ENETC_TBMR); 765 766 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0); 767 enetc_txbdr_wr(hw, idx, ENETC_TBMR, val); 768 } 769 770 static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx, 771 int prio) 772 { 773 u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR); 774 775 val &= ~ENETC_TBMR_PRIO_MASK; 776 val |= ENETC_TBMR_SET_PRIO(prio); 777 enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val); 778 } 779 780 enum bdcr_cmd_class { 781 BDCR_CMD_UNSPEC = 0, 782 BDCR_CMD_MAC_FILTER, 783 BDCR_CMD_VLAN_FILTER, 784 BDCR_CMD_RSS, 785 BDCR_CMD_RFS, 786 BDCR_CMD_PORT_GCL, 787 BDCR_CMD_RECV_CLASSIFIER, 788 BDCR_CMD_STREAM_IDENTIFY, 789 BDCR_CMD_STREAM_FILTER, 790 BDCR_CMD_STREAM_GCL, 791 BDCR_CMD_FLOW_METER, 792 __BDCR_CMD_MAX_LEN, 793 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1, 794 }; 795 796 /* class 5, command 0 */ 797 struct tgs_gcl_conf { 798 u8 atc; /* init gate value */ 799 u8 res[7]; 800 struct { 801 u8 res1[4]; 802 __le16 acl_len; 803 u8 res2[2]; 804 }; 805 }; 806 807 /* gate control list entry */ 808 struct gce { 809 __le32 period; 810 u8 gate; 811 u8 res[3]; 812 }; 813 814 /* tgs_gcl_conf address point to this data space */ 815 struct tgs_gcl_data { 816 __le32 btl; 817 __le32 bth; 818 __le32 ct; 819 __le32 cte; 820 struct gce entry[]; 821 }; 822 823 /* class 7, command 0, Stream Identity Entry Configuration */ 824 struct streamid_conf { 825 __le32 stream_handle; /* init gate value */ 826 __le32 iports; 827 u8 id_type; 828 u8 oui[3]; 829 u8 res[3]; 830 u8 en; 831 }; 832 833 #define ENETC_CBDR_SID_VID_MASK 0xfff 834 #define ENETC_CBDR_SID_VIDM BIT(12) 835 #define ENETC_CBDR_SID_TG_MASK 0xc000 836 /* streamid_conf address point to this data space */ 837 struct streamid_data { 838 union { 839 u8 dmac[6]; 840 u8 smac[6]; 841 }; 842 u16 vid_vidm_tg; 843 }; 844 845 #define ENETC_CBDR_SFI_PRI_MASK 0x7 846 #define ENETC_CBDR_SFI_PRIM BIT(3) 847 #define ENETC_CBDR_SFI_BLOV BIT(4) 848 #define ENETC_CBDR_SFI_BLEN BIT(5) 849 #define ENETC_CBDR_SFI_MSDUEN BIT(6) 850 #define ENETC_CBDR_SFI_FMITEN BIT(7) 851 #define ENETC_CBDR_SFI_ENABLE BIT(7) 852 /* class 8, command 0, Stream Filter Instance, Short Format */ 853 struct sfi_conf { 854 __le32 stream_handle; 855 u8 multi; 856 u8 res[2]; 857 u8 sthm; 858 /* Max Service Data Unit or Flow Meter Instance Table index. 859 * Depending on the value of FLT this represents either Max 860 * Service Data Unit (max frame size) allowed by the filter 861 * entry or is an index into the Flow Meter Instance table 862 * index identifying the policer which will be used to police 863 * it. 864 */ 865 __le16 fm_inst_table_index; 866 __le16 msdu; 867 __le16 sg_inst_table_index; 868 u8 res1[2]; 869 __le32 input_ports; 870 u8 res2[3]; 871 u8 en; 872 }; 873 874 /* class 8, command 2 stream Filter Instance status query short format 875 * command no need structure define 876 * Stream Filter Instance Query Statistics Response data 877 */ 878 struct sfi_counter_data { 879 u32 matchl; 880 u32 matchh; 881 u32 msdu_dropl; 882 u32 msdu_droph; 883 u32 stream_gate_dropl; 884 u32 stream_gate_droph; 885 u32 flow_meter_dropl; 886 u32 flow_meter_droph; 887 }; 888 889 #define ENETC_CBDR_SGI_OIPV_MASK 0x7 890 #define ENETC_CBDR_SGI_OIPV_EN BIT(3) 891 #define ENETC_CBDR_SGI_CGTST BIT(6) 892 #define ENETC_CBDR_SGI_OGTST BIT(7) 893 #define ENETC_CBDR_SGI_CFG_CHG BIT(1) 894 #define ENETC_CBDR_SGI_CFG_PND BIT(2) 895 #define ENETC_CBDR_SGI_OEX BIT(4) 896 #define ENETC_CBDR_SGI_OEXEN BIT(5) 897 #define ENETC_CBDR_SGI_IRX BIT(6) 898 #define ENETC_CBDR_SGI_IRXEN BIT(7) 899 #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3 900 #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc 901 #define ENETC_CBDR_SGI_EN BIT(7) 902 /* class 9, command 0, Stream Gate Instance Table, Short Format 903 * class 9, command 2, Stream Gate Instance Table entry query write back 904 * Short Format 905 */ 906 struct sgi_table { 907 u8 res[8]; 908 u8 oipv; 909 u8 res0[2]; 910 u8 ocgtst; 911 u8 res1[7]; 912 u8 gset; 913 u8 oacl_len; 914 u8 res2[2]; 915 u8 en; 916 }; 917 918 #define ENETC_CBDR_SGI_AIPV_MASK 0x7 919 #define ENETC_CBDR_SGI_AIPV_EN BIT(3) 920 #define ENETC_CBDR_SGI_AGTST BIT(7) 921 922 /* class 9, command 1, Stream Gate Control List, Long Format */ 923 struct sgcl_conf { 924 u8 aipv; 925 u8 res[2]; 926 u8 agtst; 927 u8 res1[4]; 928 union { 929 struct { 930 u8 res2[4]; 931 u8 acl_len; 932 u8 res3[3]; 933 }; 934 u8 cct[8]; /* Config change time */ 935 }; 936 }; 937 938 #define ENETC_CBDR_SGL_IOMEN BIT(0) 939 #define ENETC_CBDR_SGL_IPVEN BIT(3) 940 #define ENETC_CBDR_SGL_GTST BIT(4) 941 #define ENETC_CBDR_SGL_IPV_MASK 0xe 942 /* Stream Gate Control List Entry */ 943 struct sgce { 944 u32 interval; 945 u8 msdu[3]; 946 u8 multi; 947 }; 948 949 /* stream control list class 9 , cmd 1 data buffer */ 950 struct sgcl_data { 951 u32 btl; 952 u32 bth; 953 u32 ct; 954 u32 cte; 955 struct sgce sgcl[]; 956 }; 957 958 #define ENETC_CBDR_FMI_MR BIT(0) 959 #define ENETC_CBDR_FMI_MREN BIT(1) 960 #define ENETC_CBDR_FMI_DOY BIT(2) 961 #define ENETC_CBDR_FMI_CM BIT(3) 962 #define ENETC_CBDR_FMI_CF BIT(4) 963 #define ENETC_CBDR_FMI_NDOR BIT(5) 964 #define ENETC_CBDR_FMI_OALEN BIT(6) 965 #define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0) 966 967 /* class 10: command 0/1, Flow Meter Instance Set, short Format */ 968 struct fmi_conf { 969 __le32 cir; 970 __le32 cbs; 971 __le32 eir; 972 __le32 ebs; 973 u8 conf; 974 u8 res1; 975 u8 ir_fpp; 976 u8 res2[4]; 977 u8 en; 978 }; 979 980 struct enetc_cbd { 981 union{ 982 struct sfi_conf sfi_conf; 983 struct sgi_table sgi_table; 984 struct fmi_conf fmi_conf; 985 struct { 986 __le32 addr[2]; 987 union { 988 __le32 opt[4]; 989 struct tgs_gcl_conf gcl_conf; 990 struct streamid_conf sid_set; 991 struct sgcl_conf sgcl_conf; 992 }; 993 }; /* Long format */ 994 __le32 data[6]; 995 }; 996 __le16 index; 997 __le16 length; 998 u8 cmd; 999 u8 cls; 1000 u8 _res; 1001 u8 status_flags; 1002 }; 1003 1004 #define ENETC_CLK_400M 400000000ULL 1005 #define ENETC_CLK_333M 333000000ULL 1006 1007 static inline u32 enetc_cycles_to_usecs(u32 cycles, u64 clk_freq) 1008 { 1009 return (u32)div_u64(cycles * 1000000ULL, clk_freq); 1010 } 1011 1012 static inline u32 enetc_usecs_to_cycles(u32 usecs, u64 clk_freq) 1013 { 1014 return (u32)div_u64(usecs * clk_freq, 1000000ULL); 1015 } 1016 1017 /* Port traffic class frame preemption register */ 1018 #define ENETC_PTCFPR(n) (0x1910 + (n) * 4) /* n = [0 ..7] */ 1019 #define ENETC_PTCFPR_FPE BIT(31) 1020 1021 /* port time gating control register */ 1022 #define ENETC_PTGCR 0x11a00 1023 #define ENETC_PTGCR_TGE BIT(31) 1024 #define ENETC_PTGCR_TGPE BIT(30) 1025 1026 /* Port time gating capability register */ 1027 #define ENETC_PTGCAPR 0x11a08 1028 #define ENETC_PTGCAPR_MAX_GCL_LEN_MASK GENMASK(15, 0) 1029 1030 /* Port time specific departure */ 1031 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n)) 1032 #define ENETC_TSDE BIT(31) 1033 1034 /* PSFP setting */ 1035 #define ENETC_PPSFPMR 0x11b00 1036 #define ENETC_PPSFPMR_PSFPEN BIT(0) 1037 #define ENETC_PPSFPMR_VS BIT(1) 1038 #define ENETC_PPSFPMR_PVC BIT(2) 1039 #define ENETC_PPSFPMR_PVZC BIT(3) 1040