1d4fd0404SClaudiu Manoil /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2d4fd0404SClaudiu Manoil /* Copyright 2017-2019 NXP */ 3d4fd0404SClaudiu Manoil 4d4fd0404SClaudiu Manoil #include <linux/timer.h> 5d4fd0404SClaudiu Manoil #include <linux/pci.h> 6d4fd0404SClaudiu Manoil #include <linux/netdevice.h> 7d4fd0404SClaudiu Manoil #include <linux/etherdevice.h> 8d4fd0404SClaudiu Manoil #include <linux/dma-mapping.h> 9d4fd0404SClaudiu Manoil #include <linux/skbuff.h> 10d4fd0404SClaudiu Manoil #include <linux/ethtool.h> 11d4fd0404SClaudiu Manoil #include <linux/if_vlan.h> 1271b77a7aSClaudiu Manoil #include <linux/phylink.h> 13ae0e6a5dSClaudiu Manoil #include <linux/dim.h> 14d4fd0404SClaudiu Manoil 15d4fd0404SClaudiu Manoil #include "enetc_hw.h" 16d4fd0404SClaudiu Manoil 17d4fd0404SClaudiu Manoil #define ENETC_MAC_MAXFRM_SIZE 9600 18d4fd0404SClaudiu Manoil #define ENETC_MAX_MTU (ENETC_MAC_MAXFRM_SIZE - \ 19d4fd0404SClaudiu Manoil (ETH_FCS_LEN + ETH_HLEN + VLAN_HLEN)) 20d4fd0404SClaudiu Manoil 210cc11cdbSPo Liu #define ENETC_CBD_DATA_MEM_ALIGN 64 220cc11cdbSPo Liu 23d4fd0404SClaudiu Manoil struct enetc_tx_swbd { 249d2b68ccSVladimir Oltean union { 25d4fd0404SClaudiu Manoil struct sk_buff *skb; 269d2b68ccSVladimir Oltean struct xdp_frame *xdp_frame; 279d2b68ccSVladimir Oltean }; 28d4fd0404SClaudiu Manoil dma_addr_t dma; 297ed2bc80SVladimir Oltean struct page *page; /* valid only if is_xdp_tx */ 307ed2bc80SVladimir Oltean u16 page_offset; /* valid only if is_xdp_tx */ 31d4fd0404SClaudiu Manoil u16 len; 327ed2bc80SVladimir Oltean enum dma_data_direction dir; 33d3982312SY.b. Lu u8 is_dma_page:1; 34d3982312SY.b. Lu u8 check_wb:1; 357294380cSYangbo Lu u8 do_twostep_tstamp:1; 36d504498dSVladimir Oltean u8 is_eof:1; 377ed2bc80SVladimir Oltean u8 is_xdp_tx:1; 389d2b68ccSVladimir Oltean u8 is_xdp_redirect:1; 39285e8dedSPo Liu u8 qbv_en:1; 40d4fd0404SClaudiu Manoil }; 41d4fd0404SClaudiu Manoil 42d4fd0404SClaudiu Manoil #define ENETC_RX_MAXFRM_SIZE ENETC_MAC_MAXFRM_SIZE 43d4fd0404SClaudiu Manoil #define ENETC_RXB_TRUESIZE 2048 /* PAGE_SIZE >> 1 */ 44d4fd0404SClaudiu Manoil #define ENETC_RXB_PAD NET_SKB_PAD /* add extra space if needed */ 45d4fd0404SClaudiu Manoil #define ENETC_RXB_DMA_SIZE \ 46d4fd0404SClaudiu Manoil (SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - ENETC_RXB_PAD) 47d1b15102SVladimir Oltean #define ENETC_RXB_DMA_SIZE_XDP \ 48d1b15102SVladimir Oltean (SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - XDP_PACKET_HEADROOM) 49d4fd0404SClaudiu Manoil 50d4fd0404SClaudiu Manoil struct enetc_rx_swbd { 51d4fd0404SClaudiu Manoil dma_addr_t dma; 52d4fd0404SClaudiu Manoil struct page *page; 53d4fd0404SClaudiu Manoil u16 page_offset; 547ed2bc80SVladimir Oltean enum dma_data_direction dir; 557ed2bc80SVladimir Oltean u16 len; 56d4fd0404SClaudiu Manoil }; 57d4fd0404SClaudiu Manoil 587ed2bc80SVladimir Oltean /* ENETC overhead: optional extension BD + 1 BD gap */ 597ed2bc80SVladimir Oltean #define ENETC_TXBDS_NEEDED(val) ((val) + 2) 607ed2bc80SVladimir Oltean /* max # of chained Tx BDs is 15, including head and extension BD */ 617ed2bc80SVladimir Oltean #define ENETC_MAX_SKB_FRAGS 13 627ed2bc80SVladimir Oltean #define ENETC_TXBDS_MAX_NEEDED ENETC_TXBDS_NEEDED(ENETC_MAX_SKB_FRAGS + 1) 637ed2bc80SVladimir Oltean 64d4fd0404SClaudiu Manoil struct enetc_ring_stats { 65d4fd0404SClaudiu Manoil unsigned int packets; 66d4fd0404SClaudiu Manoil unsigned int bytes; 67d4fd0404SClaudiu Manoil unsigned int rx_alloc_errs; 68d1b15102SVladimir Oltean unsigned int xdp_drops; 697ed2bc80SVladimir Oltean unsigned int xdp_tx; 707ed2bc80SVladimir Oltean unsigned int xdp_tx_drops; 719d2b68ccSVladimir Oltean unsigned int xdp_redirect; 729d2b68ccSVladimir Oltean unsigned int xdp_redirect_failures; 737ed2bc80SVladimir Oltean unsigned int recycles; 747ed2bc80SVladimir Oltean unsigned int recycle_failures; 75285e8dedSPo Liu unsigned int win_drop; 76d1b15102SVladimir Oltean }; 77d1b15102SVladimir Oltean 78d1b15102SVladimir Oltean struct enetc_xdp_data { 79d1b15102SVladimir Oltean struct xdp_rxq_info rxq; 80d1b15102SVladimir Oltean struct bpf_prog *prog; 817ed2bc80SVladimir Oltean int xdp_tx_in_flight; 82d4fd0404SClaudiu Manoil }; 83d4fd0404SClaudiu Manoil 84d6a2829eSVladimir Oltean #define ENETC_RX_RING_DEFAULT_SIZE 2048 85ee3e875fSVladimir Oltean #define ENETC_TX_RING_DEFAULT_SIZE 2048 8602293dd4SClaudiu Manoil #define ENETC_DEFAULT_TX_WORK (ENETC_TX_RING_DEFAULT_SIZE / 2) 87d4fd0404SClaudiu Manoil 88f3ce29e1SVladimir Oltean struct enetc_bdr_resource { 89f3ce29e1SVladimir Oltean /* Input arguments saved for teardown */ 90f3ce29e1SVladimir Oltean struct device *dev; /* for DMA mapping */ 91f3ce29e1SVladimir Oltean size_t bd_count; 92f3ce29e1SVladimir Oltean size_t bd_size; 93f3ce29e1SVladimir Oltean 94f3ce29e1SVladimir Oltean /* Resource proper */ 95f3ce29e1SVladimir Oltean void *bd_base; /* points to Rx or Tx BD ring */ 96f3ce29e1SVladimir Oltean dma_addr_t bd_dma_base; 97f3ce29e1SVladimir Oltean union { 98f3ce29e1SVladimir Oltean struct enetc_tx_swbd *tx_swbd; 99f3ce29e1SVladimir Oltean struct enetc_rx_swbd *rx_swbd; 100f3ce29e1SVladimir Oltean }; 101f3ce29e1SVladimir Oltean char *tso_headers; 102f3ce29e1SVladimir Oltean dma_addr_t tso_headers_dma; 103f3ce29e1SVladimir Oltean }; 104f3ce29e1SVladimir Oltean 105d4fd0404SClaudiu Manoil struct enetc_bdr { 106d4fd0404SClaudiu Manoil struct device *dev; /* for DMA mapping */ 107d4fd0404SClaudiu Manoil struct net_device *ndev; 108d4fd0404SClaudiu Manoil void *bd_base; /* points to Rx or Tx BD ring */ 109d4fd0404SClaudiu Manoil union { 110d4fd0404SClaudiu Manoil void __iomem *tpir; 111d4fd0404SClaudiu Manoil void __iomem *rcir; 112d4fd0404SClaudiu Manoil }; 113d4fd0404SClaudiu Manoil u16 index; 114290b5fe0SVladimir Oltean u16 prio; 115d4fd0404SClaudiu Manoil int bd_count; /* # of BDs */ 116d4fd0404SClaudiu Manoil int next_to_use; 117d4fd0404SClaudiu Manoil int next_to_clean; 118d4fd0404SClaudiu Manoil union { 119d4fd0404SClaudiu Manoil struct enetc_tx_swbd *tx_swbd; 120d4fd0404SClaudiu Manoil struct enetc_rx_swbd *rx_swbd; 121d4fd0404SClaudiu Manoil }; 122d4fd0404SClaudiu Manoil union { 123d4fd0404SClaudiu Manoil void __iomem *tcir; /* Tx */ 124d4fd0404SClaudiu Manoil int next_to_alloc; /* Rx */ 125d4fd0404SClaudiu Manoil }; 126d4fd0404SClaudiu Manoil void __iomem *idr; /* Interrupt Detect Register pointer */ 127d4fd0404SClaudiu Manoil 128d1b15102SVladimir Oltean int buffer_offset; 129d1b15102SVladimir Oltean struct enetc_xdp_data xdp; 130d1b15102SVladimir Oltean 131d4fd0404SClaudiu Manoil struct enetc_ring_stats stats; 132d4fd0404SClaudiu Manoil 133d4fd0404SClaudiu Manoil dma_addr_t bd_dma_base; 1340d08c9ecSPo Liu u8 tsd_enable; /* Time specific departure */ 135434cebabSClaudiu Manoil bool ext_en; /* enable h/w descriptor extensions */ 136fb8629e2SIoana Ciornei 137fb8629e2SIoana Ciornei /* DMA buffer for TSO headers */ 138fb8629e2SIoana Ciornei char *tso_headers; 139fb8629e2SIoana Ciornei dma_addr_t tso_headers_dma; 140d4fd0404SClaudiu Manoil } ____cacheline_aligned_in_smp; 141d4fd0404SClaudiu Manoil 142d4fd0404SClaudiu Manoil static inline void enetc_bdr_idx_inc(struct enetc_bdr *bdr, int *i) 143d4fd0404SClaudiu Manoil { 144d4fd0404SClaudiu Manoil if (unlikely(++*i == bdr->bd_count)) 145d4fd0404SClaudiu Manoil *i = 0; 146d4fd0404SClaudiu Manoil } 147d4fd0404SClaudiu Manoil 148d4fd0404SClaudiu Manoil static inline int enetc_bd_unused(struct enetc_bdr *bdr) 149d4fd0404SClaudiu Manoil { 150d4fd0404SClaudiu Manoil if (bdr->next_to_clean > bdr->next_to_use) 151d4fd0404SClaudiu Manoil return bdr->next_to_clean - bdr->next_to_use - 1; 152d4fd0404SClaudiu Manoil 153d4fd0404SClaudiu Manoil return bdr->bd_count + bdr->next_to_clean - bdr->next_to_use - 1; 154d4fd0404SClaudiu Manoil } 155d4fd0404SClaudiu Manoil 1567ed2bc80SVladimir Oltean static inline int enetc_swbd_unused(struct enetc_bdr *bdr) 1577ed2bc80SVladimir Oltean { 1587ed2bc80SVladimir Oltean if (bdr->next_to_clean > bdr->next_to_alloc) 1597ed2bc80SVladimir Oltean return bdr->next_to_clean - bdr->next_to_alloc - 1; 1607ed2bc80SVladimir Oltean 1617ed2bc80SVladimir Oltean return bdr->bd_count + bdr->next_to_clean - bdr->next_to_alloc - 1; 1627ed2bc80SVladimir Oltean } 1637ed2bc80SVladimir Oltean 164d4fd0404SClaudiu Manoil /* Control BD ring */ 165d4fd0404SClaudiu Manoil #define ENETC_CBDR_DEFAULT_SIZE 64 166d4fd0404SClaudiu Manoil struct enetc_cbdr { 167d4fd0404SClaudiu Manoil void *bd_base; /* points to Rx or Tx BD ring */ 168d4fd0404SClaudiu Manoil void __iomem *pir; 169d4fd0404SClaudiu Manoil void __iomem *cir; 17027f9025dSVladimir Oltean void __iomem *mr; /* mode register */ 171d4fd0404SClaudiu Manoil 172d4fd0404SClaudiu Manoil int bd_count; /* # of BDs */ 173d4fd0404SClaudiu Manoil int next_to_use; 174d4fd0404SClaudiu Manoil int next_to_clean; 175d4fd0404SClaudiu Manoil 176d4fd0404SClaudiu Manoil dma_addr_t bd_dma_base; 17701121ab7SVladimir Oltean struct device *dma_dev; 178d4fd0404SClaudiu Manoil }; 179d4fd0404SClaudiu Manoil 180d4fd0404SClaudiu Manoil #define ENETC_TXBD(BDR, i) (&(((union enetc_tx_bd *)((BDR).bd_base))[i])) 181714239acSClaudiu Manoil 182714239acSClaudiu Manoil static inline union enetc_rx_bd *enetc_rxbd(struct enetc_bdr *rx_ring, int i) 183714239acSClaudiu Manoil { 184434cebabSClaudiu Manoil int hw_idx = i; 185434cebabSClaudiu Manoil 186434cebabSClaudiu Manoil #ifdef CONFIG_FSL_ENETC_PTP_CLOCK 187434cebabSClaudiu Manoil if (rx_ring->ext_en) 188434cebabSClaudiu Manoil hw_idx = 2 * i; 189434cebabSClaudiu Manoil #endif 190434cebabSClaudiu Manoil return &(((union enetc_rx_bd *)rx_ring->bd_base)[hw_idx]); 191714239acSClaudiu Manoil } 192714239acSClaudiu Manoil 193c027aa92SVladimir Oltean static inline void enetc_rxbd_next(struct enetc_bdr *rx_ring, 194c027aa92SVladimir Oltean union enetc_rx_bd **old_rxbd, int *old_index) 195714239acSClaudiu Manoil { 196c027aa92SVladimir Oltean union enetc_rx_bd *new_rxbd = *old_rxbd; 197c027aa92SVladimir Oltean int new_index = *old_index; 198c027aa92SVladimir Oltean 199c027aa92SVladimir Oltean new_rxbd++; 200c027aa92SVladimir Oltean 201434cebabSClaudiu Manoil #ifdef CONFIG_FSL_ENETC_PTP_CLOCK 202434cebabSClaudiu Manoil if (rx_ring->ext_en) 203c027aa92SVladimir Oltean new_rxbd++; 204434cebabSClaudiu Manoil #endif 205714239acSClaudiu Manoil 206c027aa92SVladimir Oltean if (unlikely(++new_index == rx_ring->bd_count)) { 207c027aa92SVladimir Oltean new_rxbd = rx_ring->bd_base; 208c027aa92SVladimir Oltean new_index = 0; 209c027aa92SVladimir Oltean } 210c027aa92SVladimir Oltean 211c027aa92SVladimir Oltean *old_rxbd = new_rxbd; 212c027aa92SVladimir Oltean *old_index = new_index; 213714239acSClaudiu Manoil } 214d4fd0404SClaudiu Manoil 215434cebabSClaudiu Manoil static inline union enetc_rx_bd *enetc_rxbd_ext(union enetc_rx_bd *rxbd) 216434cebabSClaudiu Manoil { 217434cebabSClaudiu Manoil return ++rxbd; 218434cebabSClaudiu Manoil } 219434cebabSClaudiu Manoil 220beb74ac8SClaudiu Manoil struct enetc_msg_swbd { 221beb74ac8SClaudiu Manoil void *vaddr; 222beb74ac8SClaudiu Manoil dma_addr_t dma; 223beb74ac8SClaudiu Manoil int size; 224beb74ac8SClaudiu Manoil }; 225beb74ac8SClaudiu Manoil 226d4fd0404SClaudiu Manoil #define ENETC_REV1 0x1 227d4fd0404SClaudiu Manoil enum enetc_errata { 22882728b91SClaudiu Manoil ENETC_ERR_VLAN_ISOL = BIT(0), 22982728b91SClaudiu Manoil ENETC_ERR_UCMCSWP = BIT(1), 230d4fd0404SClaudiu Manoil }; 231d4fd0404SClaudiu Manoil 23294557a9aSVladimir Oltean #define ENETC_SI_F_PSFP BIT(0) 23394557a9aSVladimir Oltean #define ENETC_SI_F_QBV BIT(1) 23494557a9aSVladimir Oltean #define ENETC_SI_F_QBU BIT(2) 2352e47cb41SPo Liu 236d4fd0404SClaudiu Manoil /* PCI IEP device data */ 237d4fd0404SClaudiu Manoil struct enetc_si { 238d4fd0404SClaudiu Manoil struct pci_dev *pdev; 239d4fd0404SClaudiu Manoil struct enetc_hw hw; 240d4fd0404SClaudiu Manoil enum enetc_errata errata; 241d4fd0404SClaudiu Manoil 242d4fd0404SClaudiu Manoil struct net_device *ndev; /* back ref. */ 243d4fd0404SClaudiu Manoil 244d4fd0404SClaudiu Manoil struct enetc_cbdr cbd_ring; 245d4fd0404SClaudiu Manoil 246d4fd0404SClaudiu Manoil int num_rx_rings; /* how many rings are available in the SI */ 247d4fd0404SClaudiu Manoil int num_tx_rings; 248d382563fSClaudiu Manoil int num_fs_entries; 249d382563fSClaudiu Manoil int num_rss; /* number of RSS buckets */ 250d4fd0404SClaudiu Manoil unsigned short pad; 2512e47cb41SPo Liu int hw_features; 252d4fd0404SClaudiu Manoil }; 253d4fd0404SClaudiu Manoil 254d4fd0404SClaudiu Manoil #define ENETC_SI_ALIGN 32 255d4fd0404SClaudiu Manoil 256d4fd0404SClaudiu Manoil static inline void *enetc_si_priv(const struct enetc_si *si) 257d4fd0404SClaudiu Manoil { 258d4fd0404SClaudiu Manoil return (char *)si + ALIGN(sizeof(struct enetc_si), ENETC_SI_ALIGN); 259d4fd0404SClaudiu Manoil } 260d4fd0404SClaudiu Manoil 261d4fd0404SClaudiu Manoil static inline bool enetc_si_is_pf(struct enetc_si *si) 262d4fd0404SClaudiu Manoil { 263d4fd0404SClaudiu Manoil return !!(si->hw.port); 264d4fd0404SClaudiu Manoil } 265d4fd0404SClaudiu Manoil 26687614b93SVladimir Oltean static inline int enetc_pf_to_port(struct pci_dev *pf_pdev) 26787614b93SVladimir Oltean { 26887614b93SVladimir Oltean switch (pf_pdev->devfn) { 26987614b93SVladimir Oltean case 0: 27087614b93SVladimir Oltean return 0; 27187614b93SVladimir Oltean case 1: 27287614b93SVladimir Oltean return 1; 27387614b93SVladimir Oltean case 2: 27487614b93SVladimir Oltean return 2; 27587614b93SVladimir Oltean case 6: 27687614b93SVladimir Oltean return 3; 27787614b93SVladimir Oltean default: 27887614b93SVladimir Oltean return -1; 27987614b93SVladimir Oltean } 28087614b93SVladimir Oltean } 28187614b93SVladimir Oltean 282d4fd0404SClaudiu Manoil #define ENETC_MAX_NUM_TXQS 8 283d4fd0404SClaudiu Manoil #define ENETC_INT_NAME_MAX (IFNAMSIZ + 8) 284d4fd0404SClaudiu Manoil 285d4fd0404SClaudiu Manoil struct enetc_int_vector { 286d4fd0404SClaudiu Manoil void __iomem *rbier; 287d4fd0404SClaudiu Manoil void __iomem *tbier_base; 28891571081SClaudiu Manoil void __iomem *ricr1; 289d4fd0404SClaudiu Manoil unsigned long tx_rings_map; 290d4fd0404SClaudiu Manoil int count_tx_rings; 29191571081SClaudiu Manoil u32 rx_ictt; 292ae0e6a5dSClaudiu Manoil u16 comp_cnt; 293ae0e6a5dSClaudiu Manoil bool rx_dim_en, rx_napi_work; 294ae0e6a5dSClaudiu Manoil struct napi_struct napi ____cacheline_aligned_in_smp; 295ae0e6a5dSClaudiu Manoil struct dim rx_dim ____cacheline_aligned_in_smp; 296d4fd0404SClaudiu Manoil char name[ENETC_INT_NAME_MAX]; 297d4fd0404SClaudiu Manoil 298058d9cfaSClaudiu Manoil struct enetc_bdr rx_ring; 299cc5b48b5SGustavo A. R. Silva struct enetc_bdr tx_ring[]; 300ae0e6a5dSClaudiu Manoil } ____cacheline_aligned_in_smp; 301d4fd0404SClaudiu Manoil 302d382563fSClaudiu Manoil struct enetc_cls_rule { 303d382563fSClaudiu Manoil struct ethtool_rx_flow_spec fs; 304d382563fSClaudiu Manoil int used; 305d382563fSClaudiu Manoil }; 306d382563fSClaudiu Manoil 307d4fd0404SClaudiu Manoil #define ENETC_MAX_BDR_INT 2 /* fixed to max # of available cpus */ 30879e49982SPo Liu struct psfp_cap { 30979e49982SPo Liu u32 max_streamid; 31079e49982SPo Liu u32 max_psfp_filter; 31179e49982SPo Liu u32 max_psfp_gate; 31279e49982SPo Liu u32 max_psfp_gatelist; 31379e49982SPo Liu u32 max_psfp_meter; 31479e49982SPo Liu }; 315d4fd0404SClaudiu Manoil 316f768e751SYangbo Lu #define ENETC_F_TX_TSTAMP_MASK 0xff 317d3982312SY.b. Lu enum enetc_active_offloads { 318f768e751SYangbo Lu /* 8 bits reserved for TX timestamp types (hwtstamp_tx_types) */ 319f768e751SYangbo Lu ENETC_F_TX_TSTAMP = BIT(0), 3207294380cSYangbo Lu ENETC_F_TX_ONESTEP_SYNC_TSTAMP = BIT(1), 321f768e751SYangbo Lu 322f768e751SYangbo Lu ENETC_F_RX_TSTAMP = BIT(8), 323f768e751SYangbo Lu ENETC_F_QBV = BIT(9), 324f768e751SYangbo Lu ENETC_F_QCI = BIT(10), 325*c7b9e808SVladimir Oltean ENETC_F_QBU = BIT(11), 326d3982312SY.b. Lu }; 327d3982312SY.b. Lu 3287294380cSYangbo Lu enum enetc_flags_bit { 3297294380cSYangbo Lu ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS = 0, 3307294380cSYangbo Lu }; 3317294380cSYangbo Lu 33291571081SClaudiu Manoil /* interrupt coalescing modes */ 33391571081SClaudiu Manoil enum enetc_ic_mode { 33491571081SClaudiu Manoil /* one interrupt per frame */ 33591571081SClaudiu Manoil ENETC_IC_NONE = 0, 33691571081SClaudiu Manoil /* activated when int coalescing time is set to a non-0 value */ 33791571081SClaudiu Manoil ENETC_IC_RX_MANUAL = BIT(0), 33891571081SClaudiu Manoil ENETC_IC_TX_MANUAL = BIT(1), 339ae0e6a5dSClaudiu Manoil /* use dynamic interrupt moderation */ 340ae0e6a5dSClaudiu Manoil ENETC_IC_RX_ADAPTIVE = BIT(2), 34191571081SClaudiu Manoil }; 34291571081SClaudiu Manoil 34391571081SClaudiu Manoil #define ENETC_RXIC_PKTTHR min_t(u32, 256, ENETC_RX_RING_DEFAULT_SIZE / 2) 34491571081SClaudiu Manoil #define ENETC_TXIC_PKTTHR min_t(u32, 128, ENETC_TX_RING_DEFAULT_SIZE / 2) 345ae0e6a5dSClaudiu Manoil #define ENETC_TXIC_TIMETHR enetc_usecs_to_cycles(600) 34691571081SClaudiu Manoil 347d4fd0404SClaudiu Manoil struct enetc_ndev_priv { 348d4fd0404SClaudiu Manoil struct net_device *ndev; 349d4fd0404SClaudiu Manoil struct device *dev; /* dma-mapping device */ 350d4fd0404SClaudiu Manoil struct enetc_si *si; 351d4fd0404SClaudiu Manoil 352d4fd0404SClaudiu Manoil int bdr_int_num; /* number of Rx/Tx ring interrupts */ 353d4fd0404SClaudiu Manoil struct enetc_int_vector *int_vector[ENETC_MAX_BDR_INT]; 354d4fd0404SClaudiu Manoil u16 num_rx_rings, num_tx_rings; 355d4fd0404SClaudiu Manoil u16 rx_bd_count, tx_bd_count; 356d4fd0404SClaudiu Manoil 357d4fd0404SClaudiu Manoil u16 msg_enable; 3587f071a45SVladimir Oltean enum enetc_active_offloads active_offloads; 359d4fd0404SClaudiu Manoil 3602e47cb41SPo Liu u32 speed; /* store speed for compare update pspeed */ 3612e47cb41SPo Liu 3627eab503bSVladimir Oltean struct enetc_bdr **xdp_tx_ring; 363d4fd0404SClaudiu Manoil struct enetc_bdr *tx_ring[16]; 364d4fd0404SClaudiu Manoil struct enetc_bdr *rx_ring[16]; 365f3ce29e1SVladimir Oltean const struct enetc_bdr_resource *tx_res; 366f3ce29e1SVladimir Oltean const struct enetc_bdr_resource *rx_res; 367d4fd0404SClaudiu Manoil 368d382563fSClaudiu Manoil struct enetc_cls_rule *cls_rules; 369d382563fSClaudiu Manoil 37079e49982SPo Liu struct psfp_cap psfp_cap; 37179e49982SPo Liu 372800db2d1SVladimir Oltean /* Minimum number of TX queues required by the network stack */ 373800db2d1SVladimir Oltean unsigned int min_num_stack_tx_queues; 374800db2d1SVladimir Oltean 37571b77a7aSClaudiu Manoil struct phylink *phylink; 37691571081SClaudiu Manoil int ic_mode; 37791571081SClaudiu Manoil u32 tx_ictt; 378d1b15102SVladimir Oltean 379d1b15102SVladimir Oltean struct bpf_prog *xdp_prog; 3807294380cSYangbo Lu 3817294380cSYangbo Lu unsigned long flags; 3827294380cSYangbo Lu 3837294380cSYangbo Lu struct work_struct tx_onestep_tstamp; 3847294380cSYangbo Lu struct sk_buff_head tx_skbs; 385*c7b9e808SVladimir Oltean 386*c7b9e808SVladimir Oltean /* Serialize access to MAC Merge state between ethtool requests 387*c7b9e808SVladimir Oltean * and link state updates 388*c7b9e808SVladimir Oltean */ 389*c7b9e808SVladimir Oltean struct mutex mm_lock; 390d4fd0404SClaudiu Manoil }; 391d4fd0404SClaudiu Manoil 392beb74ac8SClaudiu Manoil /* Messaging */ 393beb74ac8SClaudiu Manoil 394beb74ac8SClaudiu Manoil /* VF-PF set primary MAC address message format */ 395beb74ac8SClaudiu Manoil struct enetc_msg_cmd_set_primary_mac { 396beb74ac8SClaudiu Manoil struct enetc_msg_cmd_header header; 397beb74ac8SClaudiu Manoil struct sockaddr mac; 398beb74ac8SClaudiu Manoil }; 399beb74ac8SClaudiu Manoil 400d4fd0404SClaudiu Manoil #define ENETC_CBD(R, i) (&(((struct enetc_cbd *)((R).bd_base))[i])) 401d4fd0404SClaudiu Manoil 402d4fd0404SClaudiu Manoil #define ENETC_CBDR_TIMEOUT 1000 /* usecs */ 403d4fd0404SClaudiu Manoil 40441514737SY.b. Lu /* PTP driver exports */ 40541514737SY.b. Lu extern int enetc_phc_index; 40641514737SY.b. Lu 407d4fd0404SClaudiu Manoil /* SI common */ 40812717decSVladimir Oltean u32 enetc_port_mac_rd(struct enetc_si *si, u32 reg); 40912717decSVladimir Oltean void enetc_port_mac_wr(struct enetc_si *si, u32 reg, u32 val); 410d4fd0404SClaudiu Manoil int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv); 411d4fd0404SClaudiu Manoil void enetc_pci_remove(struct pci_dev *pdev); 412d4fd0404SClaudiu Manoil int enetc_alloc_msix(struct enetc_ndev_priv *priv); 413d4fd0404SClaudiu Manoil void enetc_free_msix(struct enetc_ndev_priv *priv); 414d4fd0404SClaudiu Manoil void enetc_get_si_caps(struct enetc_si *si); 415d4fd0404SClaudiu Manoil void enetc_init_si_rings_params(struct enetc_ndev_priv *priv); 416d4fd0404SClaudiu Manoil int enetc_alloc_si_resources(struct enetc_ndev_priv *priv); 417d4fd0404SClaudiu Manoil void enetc_free_si_resources(struct enetc_ndev_priv *priv); 418c646d10dSVladimir Oltean int enetc_configure_si(struct enetc_ndev_priv *priv); 419d4fd0404SClaudiu Manoil 420d4fd0404SClaudiu Manoil int enetc_open(struct net_device *ndev); 421d4fd0404SClaudiu Manoil int enetc_close(struct net_device *ndev); 42291571081SClaudiu Manoil void enetc_start(struct net_device *ndev); 42391571081SClaudiu Manoil void enetc_stop(struct net_device *ndev); 424d4fd0404SClaudiu Manoil netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev); 425d4fd0404SClaudiu Manoil struct net_device_stats *enetc_get_stats(struct net_device *ndev); 426fed38e64SVladimir Oltean void enetc_set_features(struct net_device *ndev, netdev_features_t features); 427d3982312SY.b. Lu int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd); 4285641c751SVladimir Oltean int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data); 429766338c7SVladimir Oltean int enetc_setup_bpf(struct net_device *ndev, struct netdev_bpf *bpf); 4309d2b68ccSVladimir Oltean int enetc_xdp_xmit(struct net_device *ndev, int num_frames, 4319d2b68ccSVladimir Oltean struct xdp_frame **frames, u32 flags); 432cbe9e835SCamelia Groza 433d4fd0404SClaudiu Manoil /* ethtool */ 434d4fd0404SClaudiu Manoil void enetc_set_ethtool_ops(struct net_device *ndev); 435*c7b9e808SVladimir Oltean void enetc_mm_link_state_update(struct enetc_ndev_priv *priv, bool link); 436d4fd0404SClaudiu Manoil 437d4fd0404SClaudiu Manoil /* control buffer descriptor ring (CBDR) */ 4385b4daa7fSVladimir Oltean int enetc_setup_cbdr(struct device *dev, struct enetc_hw *hw, int bd_count, 43924be14e3SVladimir Oltean struct enetc_cbdr *cbdr); 4400bfde022SVladimir Oltean void enetc_teardown_cbdr(struct enetc_cbdr *cbdr); 441d4fd0404SClaudiu Manoil int enetc_set_mac_flt_entry(struct enetc_si *si, int index, 442d4fd0404SClaudiu Manoil char *mac_addr, int si_map); 443d4fd0404SClaudiu Manoil int enetc_clear_mac_flt_entry(struct enetc_si *si, int index); 444d382563fSClaudiu Manoil int enetc_set_fs_entry(struct enetc_si *si, struct enetc_cmd_rfse *rfse, 445d382563fSClaudiu Manoil int index); 446d382563fSClaudiu Manoil void enetc_set_rss_key(struct enetc_hw *hw, const u8 *bytes); 447d382563fSClaudiu Manoil int enetc_get_rss_table(struct enetc_si *si, u32 *table, int count); 448d382563fSClaudiu Manoil int enetc_set_rss_table(struct enetc_si *si, const u32 *table, int count); 44934c6adf1SPo Liu int enetc_send_cmd(struct enetc_si *si, struct enetc_cbd *cbd); 45034c6adf1SPo Liu 4510cc11cdbSPo Liu static inline void *enetc_cbd_alloc_data_mem(struct enetc_si *si, 4520cc11cdbSPo Liu struct enetc_cbd *cbd, 4530cc11cdbSPo Liu int size, dma_addr_t *dma, 4540cc11cdbSPo Liu void **data_align) 4550cc11cdbSPo Liu { 4560cc11cdbSPo Liu struct enetc_cbdr *ring = &si->cbd_ring; 4570cc11cdbSPo Liu dma_addr_t dma_align; 4580cc11cdbSPo Liu void *data; 4590cc11cdbSPo Liu 4600cc11cdbSPo Liu data = dma_alloc_coherent(ring->dma_dev, 4610cc11cdbSPo Liu size + ENETC_CBD_DATA_MEM_ALIGN, 4620cc11cdbSPo Liu dma, GFP_KERNEL); 4630cc11cdbSPo Liu if (!data) { 4640cc11cdbSPo Liu dev_err(ring->dma_dev, "CBD alloc data memory failed!\n"); 4650cc11cdbSPo Liu return NULL; 4660cc11cdbSPo Liu } 4670cc11cdbSPo Liu 4680cc11cdbSPo Liu dma_align = ALIGN(*dma, ENETC_CBD_DATA_MEM_ALIGN); 4690cc11cdbSPo Liu *data_align = PTR_ALIGN(data, ENETC_CBD_DATA_MEM_ALIGN); 4700cc11cdbSPo Liu 4710cc11cdbSPo Liu cbd->addr[0] = cpu_to_le32(lower_32_bits(dma_align)); 4720cc11cdbSPo Liu cbd->addr[1] = cpu_to_le32(upper_32_bits(dma_align)); 4730cc11cdbSPo Liu cbd->length = cpu_to_le16(size); 4740cc11cdbSPo Liu 4750cc11cdbSPo Liu return data; 4760cc11cdbSPo Liu } 4770cc11cdbSPo Liu 4780cc11cdbSPo Liu static inline void enetc_cbd_free_data_mem(struct enetc_si *si, int size, 4790cc11cdbSPo Liu void *data, dma_addr_t *dma) 4800cc11cdbSPo Liu { 4810cc11cdbSPo Liu struct enetc_cbdr *ring = &si->cbd_ring; 4820cc11cdbSPo Liu 4830cc11cdbSPo Liu dma_free_coherent(ring->dma_dev, size + ENETC_CBD_DATA_MEM_ALIGN, 4840cc11cdbSPo Liu data, *dma); 4850cc11cdbSPo Liu } 4860cc11cdbSPo Liu 487dfc7175dSVladimir Oltean void enetc_reset_ptcmsdur(struct enetc_hw *hw); 488dfc7175dSVladimir Oltean void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *queue_max_sdu); 489dfc7175dSVladimir Oltean 49034c6adf1SPo Liu #ifdef CONFIG_FSL_ENETC_QOS 491dfc7175dSVladimir Oltean int enetc_qos_query_caps(struct net_device *ndev, void *type_data); 49234c6adf1SPo Liu int enetc_setup_tc_taprio(struct net_device *ndev, void *type_data); 49371b77a7aSClaudiu Manoil void enetc_sched_speed_set(struct enetc_ndev_priv *priv, int speed); 494c431047cSPo Liu int enetc_setup_tc_cbs(struct net_device *ndev, void *type_data); 4950d08c9ecSPo Liu int enetc_setup_tc_txtime(struct net_device *ndev, void *type_data); 496888ae5a3SPo Liu int enetc_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 497888ae5a3SPo Liu void *cb_priv); 498888ae5a3SPo Liu int enetc_setup_tc_psfp(struct net_device *ndev, void *type_data); 499888ae5a3SPo Liu int enetc_psfp_init(struct enetc_ndev_priv *priv); 500888ae5a3SPo Liu int enetc_psfp_clean(struct enetc_ndev_priv *priv); 501fed38e64SVladimir Oltean int enetc_set_psfp(struct net_device *ndev, bool en); 50279e49982SPo Liu 50379e49982SPo Liu static inline void enetc_get_max_cap(struct enetc_ndev_priv *priv) 50479e49982SPo Liu { 505715bf261SVladimir Oltean struct enetc_hw *hw = &priv->si->hw; 50679e49982SPo Liu u32 reg; 50779e49982SPo Liu 508715bf261SVladimir Oltean reg = enetc_port_rd(hw, ENETC_PSIDCAPR); 50979e49982SPo Liu priv->psfp_cap.max_streamid = reg & ENETC_PSIDCAPR_MSK; 51079e49982SPo Liu /* Port stream filter capability */ 511715bf261SVladimir Oltean reg = enetc_port_rd(hw, ENETC_PSFCAPR); 51279e49982SPo Liu priv->psfp_cap.max_psfp_filter = reg & ENETC_PSFCAPR_MSK; 51379e49982SPo Liu /* Port stream gate capability */ 514715bf261SVladimir Oltean reg = enetc_port_rd(hw, ENETC_PSGCAPR); 51579e49982SPo Liu priv->psfp_cap.max_psfp_gate = (reg & ENETC_PSGCAPR_SGIT_MSK); 51679e49982SPo Liu priv->psfp_cap.max_psfp_gatelist = (reg & ENETC_PSGCAPR_GCL_MSK) >> 16; 51779e49982SPo Liu /* Port flow meter capability */ 518715bf261SVladimir Oltean reg = enetc_port_rd(hw, ENETC_PFMCAPR); 51979e49982SPo Liu priv->psfp_cap.max_psfp_meter = reg & ENETC_PFMCAPR_MSK; 52079e49982SPo Liu } 52179e49982SPo Liu 522888ae5a3SPo Liu static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv) 52379e49982SPo Liu { 524888ae5a3SPo Liu struct enetc_hw *hw = &priv->si->hw; 525888ae5a3SPo Liu int err; 526888ae5a3SPo Liu 527888ae5a3SPo Liu enetc_get_max_cap(priv); 528888ae5a3SPo Liu 529888ae5a3SPo Liu err = enetc_psfp_init(priv); 530888ae5a3SPo Liu if (err) 531888ae5a3SPo Liu return err; 532888ae5a3SPo Liu 53379e49982SPo Liu enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) | 53479e49982SPo Liu ENETC_PPSFPMR_PSFPEN | ENETC_PPSFPMR_VS | 53579e49982SPo Liu ENETC_PPSFPMR_PVC | ENETC_PPSFPMR_PVZC); 536888ae5a3SPo Liu 537888ae5a3SPo Liu return 0; 53879e49982SPo Liu } 53979e49982SPo Liu 540888ae5a3SPo Liu static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv) 54179e49982SPo Liu { 542888ae5a3SPo Liu struct enetc_hw *hw = &priv->si->hw; 543888ae5a3SPo Liu int err; 544888ae5a3SPo Liu 545888ae5a3SPo Liu err = enetc_psfp_clean(priv); 546888ae5a3SPo Liu if (err) 547888ae5a3SPo Liu return err; 548888ae5a3SPo Liu 54979e49982SPo Liu enetc_wr(hw, ENETC_PPSFPMR, enetc_rd(hw, ENETC_PPSFPMR) & 55079e49982SPo Liu ~ENETC_PPSFPMR_PSFPEN & ~ENETC_PPSFPMR_VS & 55179e49982SPo Liu ~ENETC_PPSFPMR_PVC & ~ENETC_PPSFPMR_PVZC); 552888ae5a3SPo Liu 553888ae5a3SPo Liu memset(&priv->psfp_cap, 0, sizeof(struct psfp_cap)); 554888ae5a3SPo Liu 555888ae5a3SPo Liu return 0; 55679e49982SPo Liu } 557888ae5a3SPo Liu 55834c6adf1SPo Liu #else 559dfc7175dSVladimir Oltean #define enetc_qos_query_caps(ndev, type_data) -EOPNOTSUPP 56034c6adf1SPo Liu #define enetc_setup_tc_taprio(ndev, type_data) -EOPNOTSUPP 56171b77a7aSClaudiu Manoil #define enetc_sched_speed_set(priv, speed) (void)0 562c431047cSPo Liu #define enetc_setup_tc_cbs(ndev, type_data) -EOPNOTSUPP 5630d08c9ecSPo Liu #define enetc_setup_tc_txtime(ndev, type_data) -EOPNOTSUPP 564888ae5a3SPo Liu #define enetc_setup_tc_psfp(ndev, type_data) -EOPNOTSUPP 565888ae5a3SPo Liu #define enetc_setup_tc_block_cb NULL 566888ae5a3SPo Liu 56779e49982SPo Liu #define enetc_get_max_cap(p) \ 56879e49982SPo Liu memset(&((p)->psfp_cap), 0, sizeof(struct psfp_cap)) 56979e49982SPo Liu 570888ae5a3SPo Liu static inline int enetc_psfp_enable(struct enetc_ndev_priv *priv) 571888ae5a3SPo Liu { 572888ae5a3SPo Liu return 0; 573888ae5a3SPo Liu } 574888ae5a3SPo Liu 575888ae5a3SPo Liu static inline int enetc_psfp_disable(struct enetc_ndev_priv *priv) 576888ae5a3SPo Liu { 577888ae5a3SPo Liu return 0; 578888ae5a3SPo Liu } 579fed38e64SVladimir Oltean 580fed38e64SVladimir Oltean static inline int enetc_set_psfp(struct net_device *ndev, bool en) 581fed38e64SVladimir Oltean { 582fed38e64SVladimir Oltean return 0; 583fed38e64SVladimir Oltean } 58434c6adf1SPo Liu #endif 585