1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Linux network driver for QLogic BR-series Converged Network Adapter. 4 */ 5 /* 6 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. 7 * Copyright (c) 2014-2015 QLogic Corporation 8 * All rights reserved 9 * www.qlogic.com 10 */ 11 #include <linux/bitops.h> 12 #include <linux/netdevice.h> 13 #include <linux/skbuff.h> 14 #include <linux/etherdevice.h> 15 #include <linux/in.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_vlan.h> 18 #include <linux/if_ether.h> 19 #include <linux/ip.h> 20 #include <linux/prefetch.h> 21 #include <linux/module.h> 22 #include <net/gro.h> 23 24 #include "bnad.h" 25 #include "bna.h" 26 #include "cna.h" 27 28 static DEFINE_MUTEX(bnad_fwimg_mutex); 29 30 /* 31 * Module params 32 */ 33 static uint bnad_msix_disable; 34 module_param(bnad_msix_disable, uint, 0444); 35 MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode"); 36 37 static uint bnad_ioc_auto_recover = 1; 38 module_param(bnad_ioc_auto_recover, uint, 0444); 39 MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery"); 40 41 static uint bna_debugfs_enable = 1; 42 module_param(bna_debugfs_enable, uint, 0644); 43 MODULE_PARM_DESC(bna_debugfs_enable, "Enables debugfs feature, default=1," 44 " Range[false:0|true:1]"); 45 46 /* 47 * Global variables 48 */ 49 static u32 bnad_rxqs_per_cq = 2; 50 static atomic_t bna_id; 51 static const u8 bnad_bcast_addr[] __aligned(2) = 52 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 53 54 /* 55 * Local MACROS 56 */ 57 #define BNAD_GET_MBOX_IRQ(_bnad) \ 58 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \ 59 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \ 60 ((_bnad)->pcidev->irq)) 61 62 #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _size) \ 63 do { \ 64 (_res_info)->res_type = BNA_RES_T_MEM; \ 65 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \ 66 (_res_info)->res_u.mem_info.num = (_num); \ 67 (_res_info)->res_u.mem_info.len = (_size); \ 68 } while (0) 69 70 /* 71 * Reinitialize completions in CQ, once Rx is taken down 72 */ 73 static void 74 bnad_cq_cleanup(struct bnad *bnad, struct bna_ccb *ccb) 75 { 76 struct bna_cq_entry *cmpl; 77 int i; 78 79 for (i = 0; i < ccb->q_depth; i++) { 80 cmpl = &((struct bna_cq_entry *)ccb->sw_q)[i]; 81 cmpl->valid = 0; 82 } 83 } 84 85 /* Tx Datapath functions */ 86 87 88 /* Caller should ensure that the entry at unmap_q[index] is valid */ 89 static u32 90 bnad_tx_buff_unmap(struct bnad *bnad, 91 struct bnad_tx_unmap *unmap_q, 92 u32 q_depth, u32 index) 93 { 94 struct bnad_tx_unmap *unmap; 95 struct sk_buff *skb; 96 int vector, nvecs; 97 98 unmap = &unmap_q[index]; 99 nvecs = unmap->nvecs; 100 101 skb = unmap->skb; 102 unmap->skb = NULL; 103 unmap->nvecs = 0; 104 dma_unmap_single(&bnad->pcidev->dev, 105 dma_unmap_addr(&unmap->vectors[0], dma_addr), 106 skb_headlen(skb), DMA_TO_DEVICE); 107 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, 0); 108 nvecs--; 109 110 vector = 0; 111 while (nvecs) { 112 vector++; 113 if (vector == BFI_TX_MAX_VECTORS_PER_WI) { 114 vector = 0; 115 BNA_QE_INDX_INC(index, q_depth); 116 unmap = &unmap_q[index]; 117 } 118 119 dma_unmap_page(&bnad->pcidev->dev, 120 dma_unmap_addr(&unmap->vectors[vector], dma_addr), 121 dma_unmap_len(&unmap->vectors[vector], dma_len), 122 DMA_TO_DEVICE); 123 dma_unmap_addr_set(&unmap->vectors[vector], dma_addr, 0); 124 nvecs--; 125 } 126 127 BNA_QE_INDX_INC(index, q_depth); 128 129 return index; 130 } 131 132 /* 133 * Frees all pending Tx Bufs 134 * At this point no activity is expected on the Q, 135 * so DMA unmap & freeing is fine. 136 */ 137 static void 138 bnad_txq_cleanup(struct bnad *bnad, struct bna_tcb *tcb) 139 { 140 struct bnad_tx_unmap *unmap_q = tcb->unmap_q; 141 struct sk_buff *skb; 142 int i; 143 144 for (i = 0; i < tcb->q_depth; i++) { 145 skb = unmap_q[i].skb; 146 if (!skb) 147 continue; 148 bnad_tx_buff_unmap(bnad, unmap_q, tcb->q_depth, i); 149 150 dev_kfree_skb_any(skb); 151 } 152 } 153 154 /* 155 * bnad_txcmpl_process : Frees the Tx bufs on Tx completion 156 * Can be called in a) Interrupt context 157 * b) Sending context 158 */ 159 static u32 160 bnad_txcmpl_process(struct bnad *bnad, struct bna_tcb *tcb) 161 { 162 u32 sent_packets = 0, sent_bytes = 0; 163 u32 wis, unmap_wis, hw_cons, cons, q_depth; 164 struct bnad_tx_unmap *unmap_q = tcb->unmap_q; 165 struct bnad_tx_unmap *unmap; 166 struct sk_buff *skb; 167 168 /* Just return if TX is stopped */ 169 if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) 170 return 0; 171 172 hw_cons = *(tcb->hw_consumer_index); 173 rmb(); 174 cons = tcb->consumer_index; 175 q_depth = tcb->q_depth; 176 177 wis = BNA_Q_INDEX_CHANGE(cons, hw_cons, q_depth); 178 BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth))); 179 180 while (wis) { 181 unmap = &unmap_q[cons]; 182 183 skb = unmap->skb; 184 185 sent_packets++; 186 sent_bytes += skb->len; 187 188 unmap_wis = BNA_TXQ_WI_NEEDED(unmap->nvecs); 189 wis -= unmap_wis; 190 191 cons = bnad_tx_buff_unmap(bnad, unmap_q, q_depth, cons); 192 dev_kfree_skb_any(skb); 193 } 194 195 /* Update consumer pointers. */ 196 tcb->consumer_index = hw_cons; 197 198 tcb->txq->tx_packets += sent_packets; 199 tcb->txq->tx_bytes += sent_bytes; 200 201 return sent_packets; 202 } 203 204 static u32 205 bnad_tx_complete(struct bnad *bnad, struct bna_tcb *tcb) 206 { 207 struct net_device *netdev = bnad->netdev; 208 u32 sent = 0; 209 210 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) 211 return 0; 212 213 sent = bnad_txcmpl_process(bnad, tcb); 214 if (sent) { 215 if (netif_queue_stopped(netdev) && 216 netif_carrier_ok(netdev) && 217 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >= 218 BNAD_NETIF_WAKE_THRESHOLD) { 219 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) { 220 netif_wake_queue(netdev); 221 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); 222 } 223 } 224 } 225 226 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) 227 bna_ib_ack(tcb->i_dbell, sent); 228 229 smp_mb__before_atomic(); 230 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); 231 232 return sent; 233 } 234 235 /* MSIX Tx Completion Handler */ 236 static irqreturn_t 237 bnad_msix_tx(int irq, void *data) 238 { 239 struct bna_tcb *tcb = (struct bna_tcb *)data; 240 struct bnad *bnad = tcb->bnad; 241 242 bnad_tx_complete(bnad, tcb); 243 244 return IRQ_HANDLED; 245 } 246 247 static inline void 248 bnad_rxq_alloc_uninit(struct bnad *bnad, struct bna_rcb *rcb) 249 { 250 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 251 252 unmap_q->reuse_pi = -1; 253 unmap_q->alloc_order = -1; 254 unmap_q->map_size = 0; 255 unmap_q->type = BNAD_RXBUF_NONE; 256 } 257 258 /* Default is page-based allocation. Multi-buffer support - TBD */ 259 static int 260 bnad_rxq_alloc_init(struct bnad *bnad, struct bna_rcb *rcb) 261 { 262 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 263 int order; 264 265 bnad_rxq_alloc_uninit(bnad, rcb); 266 267 order = get_order(rcb->rxq->buffer_size); 268 269 unmap_q->type = BNAD_RXBUF_PAGE; 270 271 if (bna_is_small_rxq(rcb->id)) { 272 unmap_q->alloc_order = 0; 273 unmap_q->map_size = rcb->rxq->buffer_size; 274 } else { 275 if (rcb->rxq->multi_buffer) { 276 unmap_q->alloc_order = 0; 277 unmap_q->map_size = rcb->rxq->buffer_size; 278 unmap_q->type = BNAD_RXBUF_MULTI_BUFF; 279 } else { 280 unmap_q->alloc_order = order; 281 unmap_q->map_size = 282 (rcb->rxq->buffer_size > 2048) ? 283 PAGE_SIZE << order : 2048; 284 } 285 } 286 287 BUG_ON((PAGE_SIZE << order) % unmap_q->map_size); 288 289 return 0; 290 } 291 292 static inline void 293 bnad_rxq_cleanup_page(struct bnad *bnad, struct bnad_rx_unmap *unmap) 294 { 295 if (!unmap->page) 296 return; 297 298 dma_unmap_page(&bnad->pcidev->dev, 299 dma_unmap_addr(&unmap->vector, dma_addr), 300 unmap->vector.len, DMA_FROM_DEVICE); 301 put_page(unmap->page); 302 unmap->page = NULL; 303 dma_unmap_addr_set(&unmap->vector, dma_addr, 0); 304 unmap->vector.len = 0; 305 } 306 307 static inline void 308 bnad_rxq_cleanup_skb(struct bnad *bnad, struct bnad_rx_unmap *unmap) 309 { 310 if (!unmap->skb) 311 return; 312 313 dma_unmap_single(&bnad->pcidev->dev, 314 dma_unmap_addr(&unmap->vector, dma_addr), 315 unmap->vector.len, DMA_FROM_DEVICE); 316 dev_kfree_skb_any(unmap->skb); 317 unmap->skb = NULL; 318 dma_unmap_addr_set(&unmap->vector, dma_addr, 0); 319 unmap->vector.len = 0; 320 } 321 322 static void 323 bnad_rxq_cleanup(struct bnad *bnad, struct bna_rcb *rcb) 324 { 325 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 326 int i; 327 328 for (i = 0; i < rcb->q_depth; i++) { 329 struct bnad_rx_unmap *unmap = &unmap_q->unmap[i]; 330 331 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) 332 bnad_rxq_cleanup_skb(bnad, unmap); 333 else 334 bnad_rxq_cleanup_page(bnad, unmap); 335 } 336 bnad_rxq_alloc_uninit(bnad, rcb); 337 } 338 339 static u32 340 bnad_rxq_refill_page(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc) 341 { 342 u32 alloced, prod, q_depth; 343 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 344 struct bnad_rx_unmap *unmap, *prev; 345 struct bna_rxq_entry *rxent; 346 struct page *page; 347 u32 page_offset, alloc_size; 348 dma_addr_t dma_addr; 349 350 prod = rcb->producer_index; 351 q_depth = rcb->q_depth; 352 353 alloc_size = PAGE_SIZE << unmap_q->alloc_order; 354 alloced = 0; 355 356 while (nalloc--) { 357 unmap = &unmap_q->unmap[prod]; 358 359 if (unmap_q->reuse_pi < 0) { 360 page = alloc_pages(GFP_ATOMIC | __GFP_COMP, 361 unmap_q->alloc_order); 362 page_offset = 0; 363 } else { 364 prev = &unmap_q->unmap[unmap_q->reuse_pi]; 365 page = prev->page; 366 page_offset = prev->page_offset + unmap_q->map_size; 367 get_page(page); 368 } 369 370 if (unlikely(!page)) { 371 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed); 372 rcb->rxq->rxbuf_alloc_failed++; 373 goto finishing; 374 } 375 376 dma_addr = dma_map_page(&bnad->pcidev->dev, page, page_offset, 377 unmap_q->map_size, DMA_FROM_DEVICE); 378 if (dma_mapping_error(&bnad->pcidev->dev, dma_addr)) { 379 put_page(page); 380 BNAD_UPDATE_CTR(bnad, rxbuf_map_failed); 381 rcb->rxq->rxbuf_map_failed++; 382 goto finishing; 383 } 384 385 unmap->page = page; 386 unmap->page_offset = page_offset; 387 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr); 388 unmap->vector.len = unmap_q->map_size; 389 page_offset += unmap_q->map_size; 390 391 if (page_offset < alloc_size) 392 unmap_q->reuse_pi = prod; 393 else 394 unmap_q->reuse_pi = -1; 395 396 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod]; 397 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr); 398 BNA_QE_INDX_INC(prod, q_depth); 399 alloced++; 400 } 401 402 finishing: 403 if (likely(alloced)) { 404 rcb->producer_index = prod; 405 smp_mb(); 406 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags))) 407 bna_rxq_prod_indx_doorbell(rcb); 408 } 409 410 return alloced; 411 } 412 413 static u32 414 bnad_rxq_refill_skb(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc) 415 { 416 u32 alloced, prod, q_depth, buff_sz; 417 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 418 struct bnad_rx_unmap *unmap; 419 struct bna_rxq_entry *rxent; 420 struct sk_buff *skb; 421 dma_addr_t dma_addr; 422 423 buff_sz = rcb->rxq->buffer_size; 424 prod = rcb->producer_index; 425 q_depth = rcb->q_depth; 426 427 alloced = 0; 428 while (nalloc--) { 429 unmap = &unmap_q->unmap[prod]; 430 431 skb = netdev_alloc_skb_ip_align(bnad->netdev, buff_sz); 432 433 if (unlikely(!skb)) { 434 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed); 435 rcb->rxq->rxbuf_alloc_failed++; 436 goto finishing; 437 } 438 439 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data, 440 buff_sz, DMA_FROM_DEVICE); 441 if (dma_mapping_error(&bnad->pcidev->dev, dma_addr)) { 442 dev_kfree_skb_any(skb); 443 BNAD_UPDATE_CTR(bnad, rxbuf_map_failed); 444 rcb->rxq->rxbuf_map_failed++; 445 goto finishing; 446 } 447 448 unmap->skb = skb; 449 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr); 450 unmap->vector.len = buff_sz; 451 452 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod]; 453 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr); 454 BNA_QE_INDX_INC(prod, q_depth); 455 alloced++; 456 } 457 458 finishing: 459 if (likely(alloced)) { 460 rcb->producer_index = prod; 461 smp_mb(); 462 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags))) 463 bna_rxq_prod_indx_doorbell(rcb); 464 } 465 466 return alloced; 467 } 468 469 static inline void 470 bnad_rxq_post(struct bnad *bnad, struct bna_rcb *rcb) 471 { 472 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 473 u32 to_alloc; 474 475 to_alloc = BNA_QE_FREE_CNT(rcb, rcb->q_depth); 476 if (!(to_alloc >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)) 477 return; 478 479 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) 480 bnad_rxq_refill_skb(bnad, rcb, to_alloc); 481 else 482 bnad_rxq_refill_page(bnad, rcb, to_alloc); 483 } 484 485 #define flags_cksum_prot_mask (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \ 486 BNA_CQ_EF_IPV6 | \ 487 BNA_CQ_EF_TCP | BNA_CQ_EF_UDP | \ 488 BNA_CQ_EF_L4_CKSUM_OK) 489 490 #define flags_tcp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \ 491 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK) 492 #define flags_tcp6 (BNA_CQ_EF_IPV6 | \ 493 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK) 494 #define flags_udp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \ 495 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK) 496 #define flags_udp6 (BNA_CQ_EF_IPV6 | \ 497 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK) 498 499 static void 500 bnad_cq_drop_packet(struct bnad *bnad, struct bna_rcb *rcb, 501 u32 sop_ci, u32 nvecs) 502 { 503 struct bnad_rx_unmap_q *unmap_q; 504 struct bnad_rx_unmap *unmap; 505 u32 ci, vec; 506 507 unmap_q = rcb->unmap_q; 508 for (vec = 0, ci = sop_ci; vec < nvecs; vec++) { 509 unmap = &unmap_q->unmap[ci]; 510 BNA_QE_INDX_INC(ci, rcb->q_depth); 511 512 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) 513 bnad_rxq_cleanup_skb(bnad, unmap); 514 else 515 bnad_rxq_cleanup_page(bnad, unmap); 516 } 517 } 518 519 static void 520 bnad_cq_setup_skb_frags(struct bna_ccb *ccb, struct sk_buff *skb, u32 nvecs) 521 { 522 struct bna_rcb *rcb; 523 struct bnad *bnad; 524 struct bnad_rx_unmap_q *unmap_q; 525 struct bna_cq_entry *cq, *cmpl; 526 u32 ci, pi, totlen = 0; 527 528 cq = ccb->sw_q; 529 pi = ccb->producer_index; 530 cmpl = &cq[pi]; 531 532 rcb = bna_is_small_rxq(cmpl->rxq_id) ? ccb->rcb[1] : ccb->rcb[0]; 533 unmap_q = rcb->unmap_q; 534 bnad = rcb->bnad; 535 ci = rcb->consumer_index; 536 537 /* prefetch header */ 538 prefetch(page_address(unmap_q->unmap[ci].page) + 539 unmap_q->unmap[ci].page_offset); 540 541 while (nvecs--) { 542 struct bnad_rx_unmap *unmap; 543 u32 len; 544 545 unmap = &unmap_q->unmap[ci]; 546 BNA_QE_INDX_INC(ci, rcb->q_depth); 547 548 dma_unmap_page(&bnad->pcidev->dev, 549 dma_unmap_addr(&unmap->vector, dma_addr), 550 unmap->vector.len, DMA_FROM_DEVICE); 551 552 len = ntohs(cmpl->length); 553 skb->truesize += unmap->vector.len; 554 totlen += len; 555 556 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, 557 unmap->page, unmap->page_offset, len); 558 559 unmap->page = NULL; 560 unmap->vector.len = 0; 561 562 BNA_QE_INDX_INC(pi, ccb->q_depth); 563 cmpl = &cq[pi]; 564 } 565 566 skb->len += totlen; 567 skb->data_len += totlen; 568 } 569 570 static inline void 571 bnad_cq_setup_skb(struct bnad *bnad, struct sk_buff *skb, 572 struct bnad_rx_unmap *unmap, u32 len) 573 { 574 prefetch(skb->data); 575 576 dma_unmap_single(&bnad->pcidev->dev, 577 dma_unmap_addr(&unmap->vector, dma_addr), 578 unmap->vector.len, DMA_FROM_DEVICE); 579 580 skb_put(skb, len); 581 skb->protocol = eth_type_trans(skb, bnad->netdev); 582 583 unmap->skb = NULL; 584 unmap->vector.len = 0; 585 } 586 587 static u32 588 bnad_cq_process(struct bnad *bnad, struct bna_ccb *ccb, int budget) 589 { 590 struct bna_cq_entry *cq, *cmpl, *next_cmpl; 591 struct bna_rcb *rcb = NULL; 592 struct bnad_rx_unmap_q *unmap_q; 593 struct bnad_rx_unmap *unmap = NULL; 594 struct sk_buff *skb = NULL; 595 struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate; 596 struct bnad_rx_ctrl *rx_ctrl = ccb->ctrl; 597 u32 packets = 0, len = 0, totlen = 0; 598 u32 pi, vec, sop_ci = 0, nvecs = 0; 599 u32 flags, masked_flags; 600 601 prefetch(bnad->netdev); 602 603 cq = ccb->sw_q; 604 605 while (packets < budget) { 606 cmpl = &cq[ccb->producer_index]; 607 if (!cmpl->valid) 608 break; 609 /* The 'valid' field is set by the adapter, only after writing 610 * the other fields of completion entry. Hence, do not load 611 * other fields of completion entry *before* the 'valid' is 612 * loaded. Adding the rmb() here prevents the compiler and/or 613 * CPU from reordering the reads which would potentially result 614 * in reading stale values in completion entry. 615 */ 616 rmb(); 617 618 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length)); 619 620 if (bna_is_small_rxq(cmpl->rxq_id)) 621 rcb = ccb->rcb[1]; 622 else 623 rcb = ccb->rcb[0]; 624 625 unmap_q = rcb->unmap_q; 626 627 /* start of packet ci */ 628 sop_ci = rcb->consumer_index; 629 630 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) { 631 unmap = &unmap_q->unmap[sop_ci]; 632 skb = unmap->skb; 633 } else { 634 skb = napi_get_frags(&rx_ctrl->napi); 635 if (unlikely(!skb)) 636 break; 637 } 638 prefetch(skb); 639 640 flags = ntohl(cmpl->flags); 641 len = ntohs(cmpl->length); 642 totlen = len; 643 nvecs = 1; 644 645 /* Check all the completions for this frame. 646 * busy-wait doesn't help much, break here. 647 */ 648 if (BNAD_RXBUF_IS_MULTI_BUFF(unmap_q->type) && 649 (flags & BNA_CQ_EF_EOP) == 0) { 650 pi = ccb->producer_index; 651 do { 652 BNA_QE_INDX_INC(pi, ccb->q_depth); 653 next_cmpl = &cq[pi]; 654 655 if (!next_cmpl->valid) 656 break; 657 /* The 'valid' field is set by the adapter, only 658 * after writing the other fields of completion 659 * entry. Hence, do not load other fields of 660 * completion entry *before* the 'valid' is 661 * loaded. Adding the rmb() here prevents the 662 * compiler and/or CPU from reordering the reads 663 * which would potentially result in reading 664 * stale values in completion entry. 665 */ 666 rmb(); 667 668 len = ntohs(next_cmpl->length); 669 flags = ntohl(next_cmpl->flags); 670 671 nvecs++; 672 totlen += len; 673 } while ((flags & BNA_CQ_EF_EOP) == 0); 674 675 if (!next_cmpl->valid) 676 break; 677 } 678 packets++; 679 680 /* TODO: BNA_CQ_EF_LOCAL ? */ 681 if (unlikely(flags & (BNA_CQ_EF_MAC_ERROR | 682 BNA_CQ_EF_FCS_ERROR | 683 BNA_CQ_EF_TOO_LONG))) { 684 bnad_cq_drop_packet(bnad, rcb, sop_ci, nvecs); 685 rcb->rxq->rx_packets_with_error++; 686 687 goto next; 688 } 689 690 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) 691 bnad_cq_setup_skb(bnad, skb, unmap, len); 692 else 693 bnad_cq_setup_skb_frags(ccb, skb, nvecs); 694 695 rcb->rxq->rx_packets++; 696 rcb->rxq->rx_bytes += totlen; 697 ccb->bytes_per_intr += totlen; 698 699 masked_flags = flags & flags_cksum_prot_mask; 700 701 if (likely 702 ((bnad->netdev->features & NETIF_F_RXCSUM) && 703 ((masked_flags == flags_tcp4) || 704 (masked_flags == flags_udp4) || 705 (masked_flags == flags_tcp6) || 706 (masked_flags == flags_udp6)))) 707 skb->ip_summed = CHECKSUM_UNNECESSARY; 708 else 709 skb_checksum_none_assert(skb); 710 711 if ((flags & BNA_CQ_EF_VLAN) && 712 (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) 713 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(cmpl->vlan_tag)); 714 715 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) 716 netif_receive_skb(skb); 717 else 718 napi_gro_frags(&rx_ctrl->napi); 719 720 next: 721 BNA_QE_INDX_ADD(rcb->consumer_index, nvecs, rcb->q_depth); 722 for (vec = 0; vec < nvecs; vec++) { 723 cmpl = &cq[ccb->producer_index]; 724 cmpl->valid = 0; 725 BNA_QE_INDX_INC(ccb->producer_index, ccb->q_depth); 726 } 727 } 728 729 napi_gro_flush(&rx_ctrl->napi, false); 730 if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags))) 731 bna_ib_ack_disable_irq(ccb->i_dbell, packets); 732 733 bnad_rxq_post(bnad, ccb->rcb[0]); 734 if (ccb->rcb[1]) 735 bnad_rxq_post(bnad, ccb->rcb[1]); 736 737 return packets; 738 } 739 740 static void 741 bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb) 742 { 743 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl); 744 struct napi_struct *napi = &rx_ctrl->napi; 745 746 if (likely(napi_schedule_prep(napi))) { 747 __napi_schedule(napi); 748 rx_ctrl->rx_schedule++; 749 } 750 } 751 752 /* MSIX Rx Path Handler */ 753 static irqreturn_t 754 bnad_msix_rx(int irq, void *data) 755 { 756 struct bna_ccb *ccb = (struct bna_ccb *)data; 757 758 if (ccb) { 759 ((struct bnad_rx_ctrl *)ccb->ctrl)->rx_intr_ctr++; 760 bnad_netif_rx_schedule_poll(ccb->bnad, ccb); 761 } 762 763 return IRQ_HANDLED; 764 } 765 766 /* Interrupt handlers */ 767 768 /* Mbox Interrupt Handlers */ 769 static irqreturn_t 770 bnad_msix_mbox_handler(int irq, void *data) 771 { 772 u32 intr_status; 773 unsigned long flags; 774 struct bnad *bnad = (struct bnad *)data; 775 776 spin_lock_irqsave(&bnad->bna_lock, flags); 777 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) { 778 spin_unlock_irqrestore(&bnad->bna_lock, flags); 779 return IRQ_HANDLED; 780 } 781 782 bna_intr_status_get(&bnad->bna, intr_status); 783 784 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status)) 785 bna_mbox_handler(&bnad->bna, intr_status); 786 787 spin_unlock_irqrestore(&bnad->bna_lock, flags); 788 789 return IRQ_HANDLED; 790 } 791 792 static irqreturn_t 793 bnad_isr(int irq, void *data) 794 { 795 int i, j; 796 u32 intr_status; 797 unsigned long flags; 798 struct bnad *bnad = (struct bnad *)data; 799 struct bnad_rx_info *rx_info; 800 struct bnad_rx_ctrl *rx_ctrl; 801 struct bna_tcb *tcb = NULL; 802 803 spin_lock_irqsave(&bnad->bna_lock, flags); 804 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) { 805 spin_unlock_irqrestore(&bnad->bna_lock, flags); 806 return IRQ_NONE; 807 } 808 809 bna_intr_status_get(&bnad->bna, intr_status); 810 811 if (unlikely(!intr_status)) { 812 spin_unlock_irqrestore(&bnad->bna_lock, flags); 813 return IRQ_NONE; 814 } 815 816 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status)) 817 bna_mbox_handler(&bnad->bna, intr_status); 818 819 spin_unlock_irqrestore(&bnad->bna_lock, flags); 820 821 if (!BNA_IS_INTX_DATA_INTR(intr_status)) 822 return IRQ_HANDLED; 823 824 /* Process data interrupts */ 825 /* Tx processing */ 826 for (i = 0; i < bnad->num_tx; i++) { 827 for (j = 0; j < bnad->num_txq_per_tx; j++) { 828 tcb = bnad->tx_info[i].tcb[j]; 829 if (tcb && test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) 830 bnad_tx_complete(bnad, bnad->tx_info[i].tcb[j]); 831 } 832 } 833 /* Rx processing */ 834 for (i = 0; i < bnad->num_rx; i++) { 835 rx_info = &bnad->rx_info[i]; 836 if (!rx_info->rx) 837 continue; 838 for (j = 0; j < bnad->num_rxp_per_rx; j++) { 839 rx_ctrl = &rx_info->rx_ctrl[j]; 840 if (rx_ctrl->ccb) 841 bnad_netif_rx_schedule_poll(bnad, 842 rx_ctrl->ccb); 843 } 844 } 845 return IRQ_HANDLED; 846 } 847 848 /* 849 * Called in interrupt / callback context 850 * with bna_lock held, so cfg_flags access is OK 851 */ 852 static void 853 bnad_enable_mbox_irq(struct bnad *bnad) 854 { 855 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags); 856 857 BNAD_UPDATE_CTR(bnad, mbox_intr_enabled); 858 } 859 860 /* 861 * Called with bnad->bna_lock held b'cos of 862 * bnad->cfg_flags access. 863 */ 864 static void 865 bnad_disable_mbox_irq(struct bnad *bnad) 866 { 867 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags); 868 869 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled); 870 } 871 872 static void 873 bnad_set_netdev_perm_addr(struct bnad *bnad) 874 { 875 struct net_device *netdev = bnad->netdev; 876 877 ether_addr_copy(netdev->perm_addr, bnad->perm_addr); 878 if (is_zero_ether_addr(netdev->dev_addr)) 879 eth_hw_addr_set(netdev, bnad->perm_addr); 880 } 881 882 /* Control Path Handlers */ 883 884 /* Callbacks */ 885 void 886 bnad_cb_mbox_intr_enable(struct bnad *bnad) 887 { 888 bnad_enable_mbox_irq(bnad); 889 } 890 891 void 892 bnad_cb_mbox_intr_disable(struct bnad *bnad) 893 { 894 bnad_disable_mbox_irq(bnad); 895 } 896 897 void 898 bnad_cb_ioceth_ready(struct bnad *bnad) 899 { 900 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS; 901 complete(&bnad->bnad_completions.ioc_comp); 902 } 903 904 void 905 bnad_cb_ioceth_failed(struct bnad *bnad) 906 { 907 bnad->bnad_completions.ioc_comp_status = BNA_CB_FAIL; 908 complete(&bnad->bnad_completions.ioc_comp); 909 } 910 911 void 912 bnad_cb_ioceth_disabled(struct bnad *bnad) 913 { 914 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS; 915 complete(&bnad->bnad_completions.ioc_comp); 916 } 917 918 static void 919 bnad_cb_enet_disabled(void *arg) 920 { 921 struct bnad *bnad = (struct bnad *)arg; 922 923 netif_carrier_off(bnad->netdev); 924 complete(&bnad->bnad_completions.enet_comp); 925 } 926 927 void 928 bnad_cb_ethport_link_status(struct bnad *bnad, 929 enum bna_link_status link_status) 930 { 931 bool link_up = false; 932 933 link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP); 934 935 if (link_status == BNA_CEE_UP) { 936 if (!test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) 937 BNAD_UPDATE_CTR(bnad, cee_toggle); 938 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags); 939 } else { 940 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) 941 BNAD_UPDATE_CTR(bnad, cee_toggle); 942 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags); 943 } 944 945 if (link_up) { 946 if (!netif_carrier_ok(bnad->netdev)) { 947 uint tx_id, tcb_id; 948 netdev_info(bnad->netdev, "link up\n"); 949 netif_carrier_on(bnad->netdev); 950 BNAD_UPDATE_CTR(bnad, link_toggle); 951 for (tx_id = 0; tx_id < bnad->num_tx; tx_id++) { 952 for (tcb_id = 0; tcb_id < bnad->num_txq_per_tx; 953 tcb_id++) { 954 struct bna_tcb *tcb = 955 bnad->tx_info[tx_id].tcb[tcb_id]; 956 u32 txq_id; 957 if (!tcb) 958 continue; 959 960 txq_id = tcb->id; 961 962 if (test_bit(BNAD_TXQ_TX_STARTED, 963 &tcb->flags)) { 964 /* 965 * Force an immediate 966 * Transmit Schedule */ 967 netif_wake_subqueue( 968 bnad->netdev, 969 txq_id); 970 BNAD_UPDATE_CTR(bnad, 971 netif_queue_wakeup); 972 } else { 973 netif_stop_subqueue( 974 bnad->netdev, 975 txq_id); 976 BNAD_UPDATE_CTR(bnad, 977 netif_queue_stop); 978 } 979 } 980 } 981 } 982 } else { 983 if (netif_carrier_ok(bnad->netdev)) { 984 netdev_info(bnad->netdev, "link down\n"); 985 netif_carrier_off(bnad->netdev); 986 BNAD_UPDATE_CTR(bnad, link_toggle); 987 } 988 } 989 } 990 991 static void 992 bnad_cb_tx_disabled(void *arg, struct bna_tx *tx) 993 { 994 struct bnad *bnad = (struct bnad *)arg; 995 996 complete(&bnad->bnad_completions.tx_comp); 997 } 998 999 static void 1000 bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb) 1001 { 1002 struct bnad_tx_info *tx_info = 1003 (struct bnad_tx_info *)tcb->txq->tx->priv; 1004 1005 tcb->priv = tcb; 1006 tx_info->tcb[tcb->id] = tcb; 1007 } 1008 1009 static void 1010 bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb) 1011 { 1012 struct bnad_tx_info *tx_info = 1013 (struct bnad_tx_info *)tcb->txq->tx->priv; 1014 1015 tx_info->tcb[tcb->id] = NULL; 1016 tcb->priv = NULL; 1017 } 1018 1019 static void 1020 bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb) 1021 { 1022 struct bnad_rx_info *rx_info = 1023 (struct bnad_rx_info *)ccb->cq->rx->priv; 1024 1025 rx_info->rx_ctrl[ccb->id].ccb = ccb; 1026 ccb->ctrl = &rx_info->rx_ctrl[ccb->id]; 1027 } 1028 1029 static void 1030 bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb) 1031 { 1032 struct bnad_rx_info *rx_info = 1033 (struct bnad_rx_info *)ccb->cq->rx->priv; 1034 1035 rx_info->rx_ctrl[ccb->id].ccb = NULL; 1036 } 1037 1038 static void 1039 bnad_cb_tx_stall(struct bnad *bnad, struct bna_tx *tx) 1040 { 1041 struct bnad_tx_info *tx_info = tx->priv; 1042 struct bna_tcb *tcb; 1043 u32 txq_id; 1044 int i; 1045 1046 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { 1047 tcb = tx_info->tcb[i]; 1048 if (!tcb) 1049 continue; 1050 txq_id = tcb->id; 1051 clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags); 1052 netif_stop_subqueue(bnad->netdev, txq_id); 1053 } 1054 } 1055 1056 static void 1057 bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx) 1058 { 1059 struct bnad_tx_info *tx_info = tx->priv; 1060 struct bna_tcb *tcb; 1061 u32 txq_id; 1062 int i; 1063 1064 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { 1065 tcb = tx_info->tcb[i]; 1066 if (!tcb) 1067 continue; 1068 txq_id = tcb->id; 1069 1070 BUG_ON(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)); 1071 set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags); 1072 BUG_ON(*(tcb->hw_consumer_index) != 0); 1073 1074 if (netif_carrier_ok(bnad->netdev)) { 1075 netif_wake_subqueue(bnad->netdev, txq_id); 1076 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); 1077 } 1078 } 1079 1080 /* 1081 * Workaround for first ioceth enable failure & we 1082 * get a 0 MAC address. We try to get the MAC address 1083 * again here. 1084 */ 1085 if (is_zero_ether_addr(bnad->perm_addr)) { 1086 bna_enet_perm_mac_get(&bnad->bna.enet, bnad->perm_addr); 1087 bnad_set_netdev_perm_addr(bnad); 1088 } 1089 } 1090 1091 /* 1092 * Free all TxQs buffers and then notify TX_E_CLEANUP_DONE to Tx fsm. 1093 */ 1094 static void 1095 bnad_tx_cleanup(struct work_struct *work) 1096 { 1097 struct bnad_tx_info *tx_info = 1098 container_of(work, struct bnad_tx_info, tx_cleanup_work.work); 1099 struct bnad *bnad = NULL; 1100 struct bna_tcb *tcb; 1101 unsigned long flags; 1102 u32 i, pending = 0; 1103 1104 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { 1105 tcb = tx_info->tcb[i]; 1106 if (!tcb) 1107 continue; 1108 1109 bnad = tcb->bnad; 1110 1111 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) { 1112 pending++; 1113 continue; 1114 } 1115 1116 bnad_txq_cleanup(bnad, tcb); 1117 1118 smp_mb__before_atomic(); 1119 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); 1120 } 1121 1122 if (pending) { 1123 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 1124 msecs_to_jiffies(1)); 1125 return; 1126 } 1127 1128 spin_lock_irqsave(&bnad->bna_lock, flags); 1129 bna_tx_cleanup_complete(tx_info->tx); 1130 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1131 } 1132 1133 static void 1134 bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tx *tx) 1135 { 1136 struct bnad_tx_info *tx_info = tx->priv; 1137 struct bna_tcb *tcb; 1138 int i; 1139 1140 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { 1141 tcb = tx_info->tcb[i]; 1142 if (!tcb) 1143 continue; 1144 } 1145 1146 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 0); 1147 } 1148 1149 static void 1150 bnad_cb_rx_stall(struct bnad *bnad, struct bna_rx *rx) 1151 { 1152 struct bnad_rx_info *rx_info = rx->priv; 1153 struct bna_ccb *ccb; 1154 struct bnad_rx_ctrl *rx_ctrl; 1155 int i; 1156 1157 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { 1158 rx_ctrl = &rx_info->rx_ctrl[i]; 1159 ccb = rx_ctrl->ccb; 1160 if (!ccb) 1161 continue; 1162 1163 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[0]->flags); 1164 1165 if (ccb->rcb[1]) 1166 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[1]->flags); 1167 } 1168 } 1169 1170 /* 1171 * Free all RxQs buffers and then notify RX_E_CLEANUP_DONE to Rx fsm. 1172 */ 1173 static void 1174 bnad_rx_cleanup(struct work_struct *work) 1175 { 1176 struct bnad_rx_info *rx_info = 1177 container_of(work, struct bnad_rx_info, rx_cleanup_work); 1178 struct bnad_rx_ctrl *rx_ctrl; 1179 struct bnad *bnad = NULL; 1180 unsigned long flags; 1181 u32 i; 1182 1183 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { 1184 rx_ctrl = &rx_info->rx_ctrl[i]; 1185 1186 if (!rx_ctrl->ccb) 1187 continue; 1188 1189 bnad = rx_ctrl->ccb->bnad; 1190 1191 /* 1192 * Wait till the poll handler has exited 1193 * and nothing can be scheduled anymore 1194 */ 1195 napi_disable(&rx_ctrl->napi); 1196 1197 bnad_cq_cleanup(bnad, rx_ctrl->ccb); 1198 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[0]); 1199 if (rx_ctrl->ccb->rcb[1]) 1200 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[1]); 1201 } 1202 1203 spin_lock_irqsave(&bnad->bna_lock, flags); 1204 bna_rx_cleanup_complete(rx_info->rx); 1205 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1206 } 1207 1208 static void 1209 bnad_cb_rx_cleanup(struct bnad *bnad, struct bna_rx *rx) 1210 { 1211 struct bnad_rx_info *rx_info = rx->priv; 1212 struct bna_ccb *ccb; 1213 struct bnad_rx_ctrl *rx_ctrl; 1214 int i; 1215 1216 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { 1217 rx_ctrl = &rx_info->rx_ctrl[i]; 1218 ccb = rx_ctrl->ccb; 1219 if (!ccb) 1220 continue; 1221 1222 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags); 1223 1224 if (ccb->rcb[1]) 1225 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags); 1226 } 1227 1228 queue_work(bnad->work_q, &rx_info->rx_cleanup_work); 1229 } 1230 1231 static void 1232 bnad_cb_rx_post(struct bnad *bnad, struct bna_rx *rx) 1233 { 1234 struct bnad_rx_info *rx_info = rx->priv; 1235 struct bna_ccb *ccb; 1236 struct bna_rcb *rcb; 1237 struct bnad_rx_ctrl *rx_ctrl; 1238 int i, j; 1239 1240 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { 1241 rx_ctrl = &rx_info->rx_ctrl[i]; 1242 ccb = rx_ctrl->ccb; 1243 if (!ccb) 1244 continue; 1245 1246 napi_enable(&rx_ctrl->napi); 1247 1248 for (j = 0; j < BNAD_MAX_RXQ_PER_RXP; j++) { 1249 rcb = ccb->rcb[j]; 1250 if (!rcb) 1251 continue; 1252 1253 bnad_rxq_alloc_init(bnad, rcb); 1254 set_bit(BNAD_RXQ_STARTED, &rcb->flags); 1255 set_bit(BNAD_RXQ_POST_OK, &rcb->flags); 1256 bnad_rxq_post(bnad, rcb); 1257 } 1258 } 1259 } 1260 1261 static void 1262 bnad_cb_rx_disabled(void *arg, struct bna_rx *rx) 1263 { 1264 struct bnad *bnad = (struct bnad *)arg; 1265 1266 complete(&bnad->bnad_completions.rx_comp); 1267 } 1268 1269 static void 1270 bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx) 1271 { 1272 bnad->bnad_completions.mcast_comp_status = BNA_CB_SUCCESS; 1273 complete(&bnad->bnad_completions.mcast_comp); 1274 } 1275 1276 void 1277 bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status, 1278 struct bna_stats *stats) 1279 { 1280 if (status == BNA_CB_SUCCESS) 1281 BNAD_UPDATE_CTR(bnad, hw_stats_updates); 1282 1283 if (!netif_running(bnad->netdev) || 1284 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) 1285 return; 1286 1287 mod_timer(&bnad->stats_timer, 1288 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ)); 1289 } 1290 1291 static void 1292 bnad_cb_enet_mtu_set(struct bnad *bnad) 1293 { 1294 bnad->bnad_completions.mtu_comp_status = BNA_CB_SUCCESS; 1295 complete(&bnad->bnad_completions.mtu_comp); 1296 } 1297 1298 void 1299 bnad_cb_completion(void *arg, enum bfa_status status) 1300 { 1301 struct bnad_iocmd_comp *iocmd_comp = 1302 (struct bnad_iocmd_comp *)arg; 1303 1304 iocmd_comp->comp_status = (u32) status; 1305 complete(&iocmd_comp->comp); 1306 } 1307 1308 /* Resource allocation, free functions */ 1309 1310 static void 1311 bnad_mem_free(struct bnad *bnad, 1312 struct bna_mem_info *mem_info) 1313 { 1314 int i; 1315 dma_addr_t dma_pa; 1316 1317 if (mem_info->mdl == NULL) 1318 return; 1319 1320 for (i = 0; i < mem_info->num; i++) { 1321 if (mem_info->mdl[i].kva != NULL) { 1322 if (mem_info->mem_type == BNA_MEM_T_DMA) { 1323 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma), 1324 dma_pa); 1325 dma_free_coherent(&bnad->pcidev->dev, 1326 mem_info->mdl[i].len, 1327 mem_info->mdl[i].kva, dma_pa); 1328 } else 1329 kfree(mem_info->mdl[i].kva); 1330 } 1331 } 1332 kfree(mem_info->mdl); 1333 mem_info->mdl = NULL; 1334 } 1335 1336 static int 1337 bnad_mem_alloc(struct bnad *bnad, 1338 struct bna_mem_info *mem_info) 1339 { 1340 int i; 1341 dma_addr_t dma_pa; 1342 1343 if ((mem_info->num == 0) || (mem_info->len == 0)) { 1344 mem_info->mdl = NULL; 1345 return 0; 1346 } 1347 1348 mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr), 1349 GFP_KERNEL); 1350 if (mem_info->mdl == NULL) 1351 return -ENOMEM; 1352 1353 if (mem_info->mem_type == BNA_MEM_T_DMA) { 1354 for (i = 0; i < mem_info->num; i++) { 1355 mem_info->mdl[i].len = mem_info->len; 1356 mem_info->mdl[i].kva = 1357 dma_alloc_coherent(&bnad->pcidev->dev, 1358 mem_info->len, &dma_pa, 1359 GFP_KERNEL); 1360 if (mem_info->mdl[i].kva == NULL) 1361 goto err_return; 1362 1363 BNA_SET_DMA_ADDR(dma_pa, 1364 &(mem_info->mdl[i].dma)); 1365 } 1366 } else { 1367 for (i = 0; i < mem_info->num; i++) { 1368 mem_info->mdl[i].len = mem_info->len; 1369 mem_info->mdl[i].kva = kzalloc(mem_info->len, 1370 GFP_KERNEL); 1371 if (mem_info->mdl[i].kva == NULL) 1372 goto err_return; 1373 } 1374 } 1375 1376 return 0; 1377 1378 err_return: 1379 bnad_mem_free(bnad, mem_info); 1380 return -ENOMEM; 1381 } 1382 1383 /* Free IRQ for Mailbox */ 1384 static void 1385 bnad_mbox_irq_free(struct bnad *bnad) 1386 { 1387 int irq; 1388 unsigned long flags; 1389 1390 spin_lock_irqsave(&bnad->bna_lock, flags); 1391 bnad_disable_mbox_irq(bnad); 1392 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1393 1394 irq = BNAD_GET_MBOX_IRQ(bnad); 1395 free_irq(irq, bnad); 1396 } 1397 1398 /* 1399 * Allocates IRQ for Mailbox, but keep it disabled 1400 * This will be enabled once we get the mbox enable callback 1401 * from bna 1402 */ 1403 static int 1404 bnad_mbox_irq_alloc(struct bnad *bnad) 1405 { 1406 int err = 0; 1407 unsigned long irq_flags, flags; 1408 u32 irq; 1409 irq_handler_t irq_handler; 1410 1411 spin_lock_irqsave(&bnad->bna_lock, flags); 1412 if (bnad->cfg_flags & BNAD_CF_MSIX) { 1413 irq_handler = (irq_handler_t)bnad_msix_mbox_handler; 1414 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector; 1415 irq_flags = 0; 1416 } else { 1417 irq_handler = (irq_handler_t)bnad_isr; 1418 irq = bnad->pcidev->irq; 1419 irq_flags = IRQF_SHARED; 1420 } 1421 1422 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1423 sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME); 1424 1425 /* 1426 * Set the Mbox IRQ disable flag, so that the IRQ handler 1427 * called from request_irq() for SHARED IRQs do not execute 1428 */ 1429 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags); 1430 1431 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled); 1432 1433 err = request_irq(irq, irq_handler, irq_flags, 1434 bnad->mbox_irq_name, bnad); 1435 1436 return err; 1437 } 1438 1439 static void 1440 bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info) 1441 { 1442 kfree(intr_info->idl); 1443 intr_info->idl = NULL; 1444 } 1445 1446 /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */ 1447 static int 1448 bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src, 1449 u32 txrx_id, struct bna_intr_info *intr_info) 1450 { 1451 int i, vector_start = 0; 1452 u32 cfg_flags; 1453 unsigned long flags; 1454 1455 spin_lock_irqsave(&bnad->bna_lock, flags); 1456 cfg_flags = bnad->cfg_flags; 1457 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1458 1459 if (cfg_flags & BNAD_CF_MSIX) { 1460 intr_info->intr_type = BNA_INTR_T_MSIX; 1461 intr_info->idl = kcalloc(intr_info->num, 1462 sizeof(struct bna_intr_descr), 1463 GFP_KERNEL); 1464 if (!intr_info->idl) 1465 return -ENOMEM; 1466 1467 switch (src) { 1468 case BNAD_INTR_TX: 1469 vector_start = BNAD_MAILBOX_MSIX_VECTORS + txrx_id; 1470 break; 1471 1472 case BNAD_INTR_RX: 1473 vector_start = BNAD_MAILBOX_MSIX_VECTORS + 1474 (bnad->num_tx * bnad->num_txq_per_tx) + 1475 txrx_id; 1476 break; 1477 1478 default: 1479 BUG(); 1480 } 1481 1482 for (i = 0; i < intr_info->num; i++) 1483 intr_info->idl[i].vector = vector_start + i; 1484 } else { 1485 intr_info->intr_type = BNA_INTR_T_INTX; 1486 intr_info->num = 1; 1487 intr_info->idl = kcalloc(intr_info->num, 1488 sizeof(struct bna_intr_descr), 1489 GFP_KERNEL); 1490 if (!intr_info->idl) 1491 return -ENOMEM; 1492 1493 switch (src) { 1494 case BNAD_INTR_TX: 1495 intr_info->idl[0].vector = BNAD_INTX_TX_IB_BITMASK; 1496 break; 1497 1498 case BNAD_INTR_RX: 1499 intr_info->idl[0].vector = BNAD_INTX_RX_IB_BITMASK; 1500 break; 1501 } 1502 } 1503 return 0; 1504 } 1505 1506 /* NOTE: Should be called for MSIX only 1507 * Unregisters Tx MSIX vector(s) from the kernel 1508 */ 1509 static void 1510 bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info, 1511 int num_txqs) 1512 { 1513 int i; 1514 int vector_num; 1515 1516 for (i = 0; i < num_txqs; i++) { 1517 if (tx_info->tcb[i] == NULL) 1518 continue; 1519 1520 vector_num = tx_info->tcb[i]->intr_vector; 1521 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]); 1522 } 1523 } 1524 1525 /* NOTE: Should be called for MSIX only 1526 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel 1527 */ 1528 static int 1529 bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info, 1530 u32 tx_id, int num_txqs) 1531 { 1532 int i; 1533 int err; 1534 int vector_num; 1535 1536 for (i = 0; i < num_txqs; i++) { 1537 vector_num = tx_info->tcb[i]->intr_vector; 1538 snprintf(tx_info->tcb[i]->name, BNA_Q_NAME_SIZE, "%s TXQ %d", 1539 bnad->netdev->name, 1540 tx_id + tx_info->tcb[i]->id); 1541 err = request_irq(bnad->msix_table[vector_num].vector, 1542 (irq_handler_t)bnad_msix_tx, 0, 1543 tx_info->tcb[i]->name, 1544 tx_info->tcb[i]); 1545 if (err) 1546 goto err_return; 1547 } 1548 1549 return 0; 1550 1551 err_return: 1552 if (i > 0) 1553 bnad_tx_msix_unregister(bnad, tx_info, (i - 1)); 1554 return -1; 1555 } 1556 1557 /* NOTE: Should be called for MSIX only 1558 * Unregisters Rx MSIX vector(s) from the kernel 1559 */ 1560 static void 1561 bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info, 1562 int num_rxps) 1563 { 1564 int i; 1565 int vector_num; 1566 1567 for (i = 0; i < num_rxps; i++) { 1568 if (rx_info->rx_ctrl[i].ccb == NULL) 1569 continue; 1570 1571 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector; 1572 free_irq(bnad->msix_table[vector_num].vector, 1573 rx_info->rx_ctrl[i].ccb); 1574 } 1575 } 1576 1577 /* NOTE: Should be called for MSIX only 1578 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel 1579 */ 1580 static int 1581 bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info, 1582 u32 rx_id, int num_rxps) 1583 { 1584 int i; 1585 int err; 1586 int vector_num; 1587 1588 for (i = 0; i < num_rxps; i++) { 1589 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector; 1590 snprintf(rx_info->rx_ctrl[i].ccb->name, BNA_Q_NAME_SIZE, 1591 "%s CQ %d", bnad->netdev->name, 1592 rx_id + rx_info->rx_ctrl[i].ccb->id); 1593 err = request_irq(bnad->msix_table[vector_num].vector, 1594 (irq_handler_t)bnad_msix_rx, 0, 1595 rx_info->rx_ctrl[i].ccb->name, 1596 rx_info->rx_ctrl[i].ccb); 1597 if (err) 1598 goto err_return; 1599 } 1600 1601 return 0; 1602 1603 err_return: 1604 if (i > 0) 1605 bnad_rx_msix_unregister(bnad, rx_info, (i - 1)); 1606 return -1; 1607 } 1608 1609 /* Free Tx object Resources */ 1610 static void 1611 bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info) 1612 { 1613 int i; 1614 1615 for (i = 0; i < BNA_TX_RES_T_MAX; i++) { 1616 if (res_info[i].res_type == BNA_RES_T_MEM) 1617 bnad_mem_free(bnad, &res_info[i].res_u.mem_info); 1618 else if (res_info[i].res_type == BNA_RES_T_INTR) 1619 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info); 1620 } 1621 } 1622 1623 /* Allocates memory and interrupt resources for Tx object */ 1624 static int 1625 bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info, 1626 u32 tx_id) 1627 { 1628 int i, err = 0; 1629 1630 for (i = 0; i < BNA_TX_RES_T_MAX; i++) { 1631 if (res_info[i].res_type == BNA_RES_T_MEM) 1632 err = bnad_mem_alloc(bnad, 1633 &res_info[i].res_u.mem_info); 1634 else if (res_info[i].res_type == BNA_RES_T_INTR) 1635 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id, 1636 &res_info[i].res_u.intr_info); 1637 if (err) 1638 goto err_return; 1639 } 1640 return 0; 1641 1642 err_return: 1643 bnad_tx_res_free(bnad, res_info); 1644 return err; 1645 } 1646 1647 /* Free Rx object Resources */ 1648 static void 1649 bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info) 1650 { 1651 int i; 1652 1653 for (i = 0; i < BNA_RX_RES_T_MAX; i++) { 1654 if (res_info[i].res_type == BNA_RES_T_MEM) 1655 bnad_mem_free(bnad, &res_info[i].res_u.mem_info); 1656 else if (res_info[i].res_type == BNA_RES_T_INTR) 1657 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info); 1658 } 1659 } 1660 1661 /* Allocates memory and interrupt resources for Rx object */ 1662 static int 1663 bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info, 1664 uint rx_id) 1665 { 1666 int i, err = 0; 1667 1668 /* All memory needs to be allocated before setup_ccbs */ 1669 for (i = 0; i < BNA_RX_RES_T_MAX; i++) { 1670 if (res_info[i].res_type == BNA_RES_T_MEM) 1671 err = bnad_mem_alloc(bnad, 1672 &res_info[i].res_u.mem_info); 1673 else if (res_info[i].res_type == BNA_RES_T_INTR) 1674 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id, 1675 &res_info[i].res_u.intr_info); 1676 if (err) 1677 goto err_return; 1678 } 1679 return 0; 1680 1681 err_return: 1682 bnad_rx_res_free(bnad, res_info); 1683 return err; 1684 } 1685 1686 /* Timer callbacks */ 1687 /* a) IOC timer */ 1688 static void 1689 bnad_ioc_timeout(struct timer_list *t) 1690 { 1691 struct bnad *bnad = from_timer(bnad, t, bna.ioceth.ioc.ioc_timer); 1692 unsigned long flags; 1693 1694 spin_lock_irqsave(&bnad->bna_lock, flags); 1695 bfa_nw_ioc_timeout(&bnad->bna.ioceth.ioc); 1696 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1697 } 1698 1699 static void 1700 bnad_ioc_hb_check(struct timer_list *t) 1701 { 1702 struct bnad *bnad = from_timer(bnad, t, bna.ioceth.ioc.hb_timer); 1703 unsigned long flags; 1704 1705 spin_lock_irqsave(&bnad->bna_lock, flags); 1706 bfa_nw_ioc_hb_check(&bnad->bna.ioceth.ioc); 1707 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1708 } 1709 1710 static void 1711 bnad_iocpf_timeout(struct timer_list *t) 1712 { 1713 struct bnad *bnad = from_timer(bnad, t, bna.ioceth.ioc.iocpf_timer); 1714 unsigned long flags; 1715 1716 spin_lock_irqsave(&bnad->bna_lock, flags); 1717 bfa_nw_iocpf_timeout(&bnad->bna.ioceth.ioc); 1718 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1719 } 1720 1721 static void 1722 bnad_iocpf_sem_timeout(struct timer_list *t) 1723 { 1724 struct bnad *bnad = from_timer(bnad, t, bna.ioceth.ioc.sem_timer); 1725 unsigned long flags; 1726 1727 spin_lock_irqsave(&bnad->bna_lock, flags); 1728 bfa_nw_iocpf_sem_timeout(&bnad->bna.ioceth.ioc); 1729 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1730 } 1731 1732 /* 1733 * All timer routines use bnad->bna_lock to protect against 1734 * the following race, which may occur in case of no locking: 1735 * Time CPU m CPU n 1736 * 0 1 = test_bit 1737 * 1 clear_bit 1738 * 2 timer_delete_sync 1739 * 3 mod_timer 1740 */ 1741 1742 /* b) Dynamic Interrupt Moderation Timer */ 1743 static void 1744 bnad_dim_timeout(struct timer_list *t) 1745 { 1746 struct bnad *bnad = from_timer(bnad, t, dim_timer); 1747 struct bnad_rx_info *rx_info; 1748 struct bnad_rx_ctrl *rx_ctrl; 1749 int i, j; 1750 unsigned long flags; 1751 1752 if (!netif_carrier_ok(bnad->netdev)) 1753 return; 1754 1755 spin_lock_irqsave(&bnad->bna_lock, flags); 1756 for (i = 0; i < bnad->num_rx; i++) { 1757 rx_info = &bnad->rx_info[i]; 1758 if (!rx_info->rx) 1759 continue; 1760 for (j = 0; j < bnad->num_rxp_per_rx; j++) { 1761 rx_ctrl = &rx_info->rx_ctrl[j]; 1762 if (!rx_ctrl->ccb) 1763 continue; 1764 bna_rx_dim_update(rx_ctrl->ccb); 1765 } 1766 } 1767 1768 /* Check for BNAD_CF_DIM_ENABLED, does not eliminate a race */ 1769 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) 1770 mod_timer(&bnad->dim_timer, 1771 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ)); 1772 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1773 } 1774 1775 /* c) Statistics Timer */ 1776 static void 1777 bnad_stats_timeout(struct timer_list *t) 1778 { 1779 struct bnad *bnad = from_timer(bnad, t, stats_timer); 1780 unsigned long flags; 1781 1782 if (!netif_running(bnad->netdev) || 1783 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) 1784 return; 1785 1786 spin_lock_irqsave(&bnad->bna_lock, flags); 1787 bna_hw_stats_get(&bnad->bna); 1788 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1789 } 1790 1791 /* 1792 * Set up timer for DIM 1793 * Called with bnad->bna_lock held 1794 */ 1795 void 1796 bnad_dim_timer_start(struct bnad *bnad) 1797 { 1798 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED && 1799 !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) { 1800 timer_setup(&bnad->dim_timer, bnad_dim_timeout, 0); 1801 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags); 1802 mod_timer(&bnad->dim_timer, 1803 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ)); 1804 } 1805 } 1806 1807 /* 1808 * Set up timer for statistics 1809 * Called with mutex_lock(&bnad->conf_mutex) held 1810 */ 1811 static void 1812 bnad_stats_timer_start(struct bnad *bnad) 1813 { 1814 unsigned long flags; 1815 1816 spin_lock_irqsave(&bnad->bna_lock, flags); 1817 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) { 1818 timer_setup(&bnad->stats_timer, bnad_stats_timeout, 0); 1819 mod_timer(&bnad->stats_timer, 1820 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ)); 1821 } 1822 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1823 } 1824 1825 /* 1826 * Stops the stats timer 1827 * Called with mutex_lock(&bnad->conf_mutex) held 1828 */ 1829 static void 1830 bnad_stats_timer_stop(struct bnad *bnad) 1831 { 1832 int to_del = 0; 1833 unsigned long flags; 1834 1835 spin_lock_irqsave(&bnad->bna_lock, flags); 1836 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) 1837 to_del = 1; 1838 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1839 if (to_del) 1840 timer_delete_sync(&bnad->stats_timer); 1841 } 1842 1843 /* Utilities */ 1844 1845 static void 1846 bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list) 1847 { 1848 int i = 1; /* Index 0 has broadcast address */ 1849 struct netdev_hw_addr *mc_addr; 1850 1851 netdev_for_each_mc_addr(mc_addr, netdev) { 1852 ether_addr_copy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0]); 1853 i++; 1854 } 1855 } 1856 1857 static int 1858 bnad_napi_poll_rx(struct napi_struct *napi, int budget) 1859 { 1860 struct bnad_rx_ctrl *rx_ctrl = 1861 container_of(napi, struct bnad_rx_ctrl, napi); 1862 struct bnad *bnad = rx_ctrl->bnad; 1863 int rcvd = 0; 1864 1865 rx_ctrl->rx_poll_ctr++; 1866 1867 if (!netif_carrier_ok(bnad->netdev)) 1868 goto poll_exit; 1869 1870 rcvd = bnad_cq_process(bnad, rx_ctrl->ccb, budget); 1871 if (rcvd >= budget) 1872 return rcvd; 1873 1874 poll_exit: 1875 napi_complete_done(napi, rcvd); 1876 1877 rx_ctrl->rx_complete++; 1878 1879 if (rx_ctrl->ccb) 1880 bnad_enable_rx_irq_unsafe(rx_ctrl->ccb); 1881 1882 return rcvd; 1883 } 1884 1885 static void 1886 bnad_napi_add(struct bnad *bnad, u32 rx_id) 1887 { 1888 struct bnad_rx_ctrl *rx_ctrl; 1889 int i; 1890 1891 /* Initialize & enable NAPI */ 1892 for (i = 0; i < bnad->num_rxp_per_rx; i++) { 1893 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i]; 1894 netif_napi_add(bnad->netdev, &rx_ctrl->napi, 1895 bnad_napi_poll_rx); 1896 } 1897 } 1898 1899 static void 1900 bnad_napi_delete(struct bnad *bnad, u32 rx_id) 1901 { 1902 int i; 1903 1904 /* First disable and then clean up */ 1905 for (i = 0; i < bnad->num_rxp_per_rx; i++) 1906 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi); 1907 } 1908 1909 /* Should be held with conf_lock held */ 1910 void 1911 bnad_destroy_tx(struct bnad *bnad, u32 tx_id) 1912 { 1913 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id]; 1914 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0]; 1915 unsigned long flags; 1916 1917 if (!tx_info->tx) 1918 return; 1919 1920 init_completion(&bnad->bnad_completions.tx_comp); 1921 spin_lock_irqsave(&bnad->bna_lock, flags); 1922 bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled); 1923 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1924 wait_for_completion(&bnad->bnad_completions.tx_comp); 1925 1926 if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX) 1927 bnad_tx_msix_unregister(bnad, tx_info, 1928 bnad->num_txq_per_tx); 1929 1930 spin_lock_irqsave(&bnad->bna_lock, flags); 1931 bna_tx_destroy(tx_info->tx); 1932 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1933 1934 tx_info->tx = NULL; 1935 tx_info->tx_id = 0; 1936 1937 bnad_tx_res_free(bnad, res_info); 1938 } 1939 1940 /* Should be held with conf_lock held */ 1941 int 1942 bnad_setup_tx(struct bnad *bnad, u32 tx_id) 1943 { 1944 int err; 1945 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id]; 1946 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0]; 1947 struct bna_intr_info *intr_info = 1948 &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info; 1949 struct bna_tx_config *tx_config = &bnad->tx_config[tx_id]; 1950 static const struct bna_tx_event_cbfn tx_cbfn = { 1951 .tcb_setup_cbfn = bnad_cb_tcb_setup, 1952 .tcb_destroy_cbfn = bnad_cb_tcb_destroy, 1953 .tx_stall_cbfn = bnad_cb_tx_stall, 1954 .tx_resume_cbfn = bnad_cb_tx_resume, 1955 .tx_cleanup_cbfn = bnad_cb_tx_cleanup, 1956 }; 1957 1958 struct bna_tx *tx; 1959 unsigned long flags; 1960 1961 tx_info->tx_id = tx_id; 1962 1963 /* Initialize the Tx object configuration */ 1964 tx_config->num_txq = bnad->num_txq_per_tx; 1965 tx_config->txq_depth = bnad->txq_depth; 1966 tx_config->tx_type = BNA_TX_T_REGULAR; 1967 tx_config->coalescing_timeo = bnad->tx_coalescing_timeo; 1968 1969 /* Get BNA's resource requirement for one tx object */ 1970 spin_lock_irqsave(&bnad->bna_lock, flags); 1971 bna_tx_res_req(bnad->num_txq_per_tx, 1972 bnad->txq_depth, res_info); 1973 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1974 1975 /* Fill Unmap Q memory requirements */ 1976 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_TX_RES_MEM_T_UNMAPQ], 1977 bnad->num_txq_per_tx, (sizeof(struct bnad_tx_unmap) * 1978 bnad->txq_depth)); 1979 1980 /* Allocate resources */ 1981 err = bnad_tx_res_alloc(bnad, res_info, tx_id); 1982 if (err) 1983 return err; 1984 1985 /* Ask BNA to create one Tx object, supplying required resources */ 1986 spin_lock_irqsave(&bnad->bna_lock, flags); 1987 tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info, 1988 tx_info); 1989 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1990 if (!tx) { 1991 err = -ENOMEM; 1992 goto err_return; 1993 } 1994 tx_info->tx = tx; 1995 1996 INIT_DELAYED_WORK(&tx_info->tx_cleanup_work, bnad_tx_cleanup); 1997 1998 /* Register ISR for the Tx object */ 1999 if (intr_info->intr_type == BNA_INTR_T_MSIX) { 2000 err = bnad_tx_msix_register(bnad, tx_info, 2001 tx_id, bnad->num_txq_per_tx); 2002 if (err) 2003 goto cleanup_tx; 2004 } 2005 2006 spin_lock_irqsave(&bnad->bna_lock, flags); 2007 bna_tx_enable(tx); 2008 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2009 2010 return 0; 2011 2012 cleanup_tx: 2013 spin_lock_irqsave(&bnad->bna_lock, flags); 2014 bna_tx_destroy(tx_info->tx); 2015 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2016 tx_info->tx = NULL; 2017 tx_info->tx_id = 0; 2018 err_return: 2019 bnad_tx_res_free(bnad, res_info); 2020 return err; 2021 } 2022 2023 /* Setup the rx config for bna_rx_create */ 2024 /* bnad decides the configuration */ 2025 static void 2026 bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config) 2027 { 2028 memset(rx_config, 0, sizeof(*rx_config)); 2029 rx_config->rx_type = BNA_RX_T_REGULAR; 2030 rx_config->num_paths = bnad->num_rxp_per_rx; 2031 rx_config->coalescing_timeo = bnad->rx_coalescing_timeo; 2032 2033 if (bnad->num_rxp_per_rx > 1) { 2034 rx_config->rss_status = BNA_STATUS_T_ENABLED; 2035 rx_config->rss_config.hash_type = 2036 (BFI_ENET_RSS_IPV6 | 2037 BFI_ENET_RSS_IPV6_TCP | 2038 BFI_ENET_RSS_IPV4 | 2039 BFI_ENET_RSS_IPV4_TCP); 2040 rx_config->rss_config.hash_mask = 2041 bnad->num_rxp_per_rx - 1; 2042 netdev_rss_key_fill(rx_config->rss_config.toeplitz_hash_key, 2043 sizeof(rx_config->rss_config.toeplitz_hash_key)); 2044 } else { 2045 rx_config->rss_status = BNA_STATUS_T_DISABLED; 2046 memset(&rx_config->rss_config, 0, 2047 sizeof(rx_config->rss_config)); 2048 } 2049 2050 rx_config->frame_size = BNAD_FRAME_SIZE(bnad->netdev->mtu); 2051 rx_config->q0_multi_buf = BNA_STATUS_T_DISABLED; 2052 2053 /* BNA_RXP_SINGLE - one data-buffer queue 2054 * BNA_RXP_SLR - one small-buffer and one large-buffer queues 2055 * BNA_RXP_HDS - one header-buffer and one data-buffer queues 2056 */ 2057 /* TODO: configurable param for queue type */ 2058 rx_config->rxp_type = BNA_RXP_SLR; 2059 2060 if (BNAD_PCI_DEV_IS_CAT2(bnad) && 2061 rx_config->frame_size > 4096) { 2062 /* though size_routing_enable is set in SLR, 2063 * small packets may get routed to same rxq. 2064 * set buf_size to 2048 instead of PAGE_SIZE. 2065 */ 2066 rx_config->q0_buf_size = 2048; 2067 /* this should be in multiples of 2 */ 2068 rx_config->q0_num_vecs = 4; 2069 rx_config->q0_depth = bnad->rxq_depth * rx_config->q0_num_vecs; 2070 rx_config->q0_multi_buf = BNA_STATUS_T_ENABLED; 2071 } else { 2072 rx_config->q0_buf_size = rx_config->frame_size; 2073 rx_config->q0_num_vecs = 1; 2074 rx_config->q0_depth = bnad->rxq_depth; 2075 } 2076 2077 /* initialize for q1 for BNA_RXP_SLR/BNA_RXP_HDS */ 2078 if (rx_config->rxp_type == BNA_RXP_SLR) { 2079 rx_config->q1_depth = bnad->rxq_depth; 2080 rx_config->q1_buf_size = BFI_SMALL_RXBUF_SIZE; 2081 } 2082 2083 rx_config->vlan_strip_status = 2084 (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) ? 2085 BNA_STATUS_T_ENABLED : BNA_STATUS_T_DISABLED; 2086 } 2087 2088 static void 2089 bnad_rx_ctrl_init(struct bnad *bnad, u32 rx_id) 2090 { 2091 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id]; 2092 int i; 2093 2094 for (i = 0; i < bnad->num_rxp_per_rx; i++) 2095 rx_info->rx_ctrl[i].bnad = bnad; 2096 } 2097 2098 /* Called with mutex_lock(&bnad->conf_mutex) held */ 2099 static u32 2100 bnad_reinit_rx(struct bnad *bnad) 2101 { 2102 struct net_device *netdev = bnad->netdev; 2103 u32 err = 0, current_err = 0; 2104 u32 rx_id = 0, count = 0; 2105 unsigned long flags; 2106 2107 /* destroy and create new rx objects */ 2108 for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) { 2109 if (!bnad->rx_info[rx_id].rx) 2110 continue; 2111 bnad_destroy_rx(bnad, rx_id); 2112 } 2113 2114 spin_lock_irqsave(&bnad->bna_lock, flags); 2115 bna_enet_mtu_set(&bnad->bna.enet, 2116 BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL); 2117 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2118 2119 for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) { 2120 count++; 2121 current_err = bnad_setup_rx(bnad, rx_id); 2122 if (current_err && !err) { 2123 err = current_err; 2124 netdev_err(netdev, "RXQ:%u setup failed\n", rx_id); 2125 } 2126 } 2127 2128 /* restore rx configuration */ 2129 if (bnad->rx_info[0].rx && !err) { 2130 bnad_restore_vlans(bnad, 0); 2131 bnad_enable_default_bcast(bnad); 2132 spin_lock_irqsave(&bnad->bna_lock, flags); 2133 bnad_mac_addr_set_locked(bnad, netdev->dev_addr); 2134 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2135 bnad_set_rx_mode(netdev); 2136 } 2137 2138 return count; 2139 } 2140 2141 /* Called with bnad_conf_lock() held */ 2142 void 2143 bnad_destroy_rx(struct bnad *bnad, u32 rx_id) 2144 { 2145 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id]; 2146 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id]; 2147 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0]; 2148 unsigned long flags; 2149 int to_del = 0; 2150 2151 if (!rx_info->rx) 2152 return; 2153 2154 if (0 == rx_id) { 2155 spin_lock_irqsave(&bnad->bna_lock, flags); 2156 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED && 2157 test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) { 2158 clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags); 2159 to_del = 1; 2160 } 2161 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2162 if (to_del) 2163 timer_delete_sync(&bnad->dim_timer); 2164 } 2165 2166 init_completion(&bnad->bnad_completions.rx_comp); 2167 spin_lock_irqsave(&bnad->bna_lock, flags); 2168 bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled); 2169 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2170 wait_for_completion(&bnad->bnad_completions.rx_comp); 2171 2172 if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX) 2173 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths); 2174 2175 bnad_napi_delete(bnad, rx_id); 2176 2177 spin_lock_irqsave(&bnad->bna_lock, flags); 2178 bna_rx_destroy(rx_info->rx); 2179 2180 rx_info->rx = NULL; 2181 rx_info->rx_id = 0; 2182 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2183 2184 bnad_rx_res_free(bnad, res_info); 2185 } 2186 2187 /* Called with mutex_lock(&bnad->conf_mutex) held */ 2188 int 2189 bnad_setup_rx(struct bnad *bnad, u32 rx_id) 2190 { 2191 int err; 2192 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id]; 2193 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0]; 2194 struct bna_intr_info *intr_info = 2195 &res_info[BNA_RX_RES_T_INTR].res_u.intr_info; 2196 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id]; 2197 static const struct bna_rx_event_cbfn rx_cbfn = { 2198 .rcb_setup_cbfn = NULL, 2199 .rcb_destroy_cbfn = NULL, 2200 .ccb_setup_cbfn = bnad_cb_ccb_setup, 2201 .ccb_destroy_cbfn = bnad_cb_ccb_destroy, 2202 .rx_stall_cbfn = bnad_cb_rx_stall, 2203 .rx_cleanup_cbfn = bnad_cb_rx_cleanup, 2204 .rx_post_cbfn = bnad_cb_rx_post, 2205 }; 2206 struct bna_rx *rx; 2207 unsigned long flags; 2208 2209 rx_info->rx_id = rx_id; 2210 2211 /* Initialize the Rx object configuration */ 2212 bnad_init_rx_config(bnad, rx_config); 2213 2214 /* Get BNA's resource requirement for one Rx object */ 2215 spin_lock_irqsave(&bnad->bna_lock, flags); 2216 bna_rx_res_req(rx_config, res_info); 2217 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2218 2219 /* Fill Unmap Q memory requirements */ 2220 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPDQ], 2221 rx_config->num_paths, 2222 (rx_config->q0_depth * 2223 sizeof(struct bnad_rx_unmap)) + 2224 sizeof(struct bnad_rx_unmap_q)); 2225 2226 if (rx_config->rxp_type != BNA_RXP_SINGLE) { 2227 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPHQ], 2228 rx_config->num_paths, 2229 (rx_config->q1_depth * 2230 sizeof(struct bnad_rx_unmap) + 2231 sizeof(struct bnad_rx_unmap_q))); 2232 } 2233 /* Allocate resource */ 2234 err = bnad_rx_res_alloc(bnad, res_info, rx_id); 2235 if (err) 2236 return err; 2237 2238 bnad_rx_ctrl_init(bnad, rx_id); 2239 2240 /* Ask BNA to create one Rx object, supplying required resources */ 2241 spin_lock_irqsave(&bnad->bna_lock, flags); 2242 rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info, 2243 rx_info); 2244 if (!rx) { 2245 err = -ENOMEM; 2246 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2247 goto err_return; 2248 } 2249 rx_info->rx = rx; 2250 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2251 2252 INIT_WORK(&rx_info->rx_cleanup_work, bnad_rx_cleanup); 2253 2254 /* 2255 * Init NAPI, so that state is set to NAPI_STATE_SCHED, 2256 * so that IRQ handler cannot schedule NAPI at this point. 2257 */ 2258 bnad_napi_add(bnad, rx_id); 2259 2260 /* Register ISR for the Rx object */ 2261 if (intr_info->intr_type == BNA_INTR_T_MSIX) { 2262 err = bnad_rx_msix_register(bnad, rx_info, rx_id, 2263 rx_config->num_paths); 2264 if (err) 2265 goto err_return; 2266 } 2267 2268 spin_lock_irqsave(&bnad->bna_lock, flags); 2269 if (0 == rx_id) { 2270 /* Set up Dynamic Interrupt Moderation Vector */ 2271 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED) 2272 bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector); 2273 2274 /* Enable VLAN filtering only on the default Rx */ 2275 bna_rx_vlanfilter_enable(rx); 2276 2277 /* Start the DIM timer */ 2278 bnad_dim_timer_start(bnad); 2279 } 2280 2281 bna_rx_enable(rx); 2282 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2283 2284 return 0; 2285 2286 err_return: 2287 bnad_destroy_rx(bnad, rx_id); 2288 return err; 2289 } 2290 2291 /* Called with conf_lock & bnad->bna_lock held */ 2292 void 2293 bnad_tx_coalescing_timeo_set(struct bnad *bnad) 2294 { 2295 struct bnad_tx_info *tx_info; 2296 2297 tx_info = &bnad->tx_info[0]; 2298 if (!tx_info->tx) 2299 return; 2300 2301 bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo); 2302 } 2303 2304 /* Called with conf_lock & bnad->bna_lock held */ 2305 void 2306 bnad_rx_coalescing_timeo_set(struct bnad *bnad) 2307 { 2308 struct bnad_rx_info *rx_info; 2309 int i; 2310 2311 for (i = 0; i < bnad->num_rx; i++) { 2312 rx_info = &bnad->rx_info[i]; 2313 if (!rx_info->rx) 2314 continue; 2315 bna_rx_coalescing_timeo_set(rx_info->rx, 2316 bnad->rx_coalescing_timeo); 2317 } 2318 } 2319 2320 /* 2321 * Called with bnad->bna_lock held 2322 */ 2323 int 2324 bnad_mac_addr_set_locked(struct bnad *bnad, const u8 *mac_addr) 2325 { 2326 int ret; 2327 2328 if (!is_valid_ether_addr(mac_addr)) 2329 return -EADDRNOTAVAIL; 2330 2331 /* If datapath is down, pretend everything went through */ 2332 if (!bnad->rx_info[0].rx) 2333 return 0; 2334 2335 ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr); 2336 if (ret != BNA_CB_SUCCESS) 2337 return -EADDRNOTAVAIL; 2338 2339 return 0; 2340 } 2341 2342 /* Should be called with conf_lock held */ 2343 int 2344 bnad_enable_default_bcast(struct bnad *bnad) 2345 { 2346 struct bnad_rx_info *rx_info = &bnad->rx_info[0]; 2347 int ret; 2348 unsigned long flags; 2349 2350 init_completion(&bnad->bnad_completions.mcast_comp); 2351 2352 spin_lock_irqsave(&bnad->bna_lock, flags); 2353 ret = bna_rx_mcast_add(rx_info->rx, bnad_bcast_addr, 2354 bnad_cb_rx_mcast_add); 2355 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2356 2357 if (ret == BNA_CB_SUCCESS) 2358 wait_for_completion(&bnad->bnad_completions.mcast_comp); 2359 else 2360 return -ENODEV; 2361 2362 if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS) 2363 return -ENODEV; 2364 2365 return 0; 2366 } 2367 2368 /* Called with mutex_lock(&bnad->conf_mutex) held */ 2369 void 2370 bnad_restore_vlans(struct bnad *bnad, u32 rx_id) 2371 { 2372 u16 vid; 2373 unsigned long flags; 2374 2375 for_each_set_bit(vid, bnad->active_vlans, VLAN_N_VID) { 2376 spin_lock_irqsave(&bnad->bna_lock, flags); 2377 bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vid); 2378 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2379 } 2380 } 2381 2382 /* Statistics utilities */ 2383 void 2384 bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats) 2385 { 2386 int i, j; 2387 2388 for (i = 0; i < bnad->num_rx; i++) { 2389 for (j = 0; j < bnad->num_rxp_per_rx; j++) { 2390 if (bnad->rx_info[i].rx_ctrl[j].ccb) { 2391 stats->rx_packets += bnad->rx_info[i]. 2392 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets; 2393 stats->rx_bytes += bnad->rx_info[i]. 2394 rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes; 2395 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] && 2396 bnad->rx_info[i].rx_ctrl[j].ccb-> 2397 rcb[1]->rxq) { 2398 stats->rx_packets += 2399 bnad->rx_info[i].rx_ctrl[j]. 2400 ccb->rcb[1]->rxq->rx_packets; 2401 stats->rx_bytes += 2402 bnad->rx_info[i].rx_ctrl[j]. 2403 ccb->rcb[1]->rxq->rx_bytes; 2404 } 2405 } 2406 } 2407 } 2408 for (i = 0; i < bnad->num_tx; i++) { 2409 for (j = 0; j < bnad->num_txq_per_tx; j++) { 2410 if (bnad->tx_info[i].tcb[j]) { 2411 stats->tx_packets += 2412 bnad->tx_info[i].tcb[j]->txq->tx_packets; 2413 stats->tx_bytes += 2414 bnad->tx_info[i].tcb[j]->txq->tx_bytes; 2415 } 2416 } 2417 } 2418 } 2419 2420 /* 2421 * Must be called with the bna_lock held. 2422 */ 2423 void 2424 bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats) 2425 { 2426 struct bfi_enet_stats_mac *mac_stats; 2427 u32 bmap; 2428 int i; 2429 2430 mac_stats = &bnad->stats.bna_stats->hw_stats.mac_stats; 2431 stats->rx_errors = 2432 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error + 2433 mac_stats->rx_frame_length_error + mac_stats->rx_code_error + 2434 mac_stats->rx_undersize; 2435 stats->tx_errors = mac_stats->tx_fcs_error + 2436 mac_stats->tx_undersize; 2437 stats->rx_dropped = mac_stats->rx_drop; 2438 stats->tx_dropped = mac_stats->tx_drop; 2439 stats->multicast = mac_stats->rx_multicast; 2440 stats->collisions = mac_stats->tx_total_collision; 2441 2442 stats->rx_length_errors = mac_stats->rx_frame_length_error; 2443 2444 /* receive ring buffer overflow ?? */ 2445 2446 stats->rx_crc_errors = mac_stats->rx_fcs_error; 2447 stats->rx_frame_errors = mac_stats->rx_alignment_error; 2448 /* recv'r fifo overrun */ 2449 bmap = bna_rx_rid_mask(&bnad->bna); 2450 for (i = 0; bmap; i++) { 2451 if (bmap & 1) { 2452 stats->rx_fifo_errors += 2453 bnad->stats.bna_stats-> 2454 hw_stats.rxf_stats[i].frame_drops; 2455 break; 2456 } 2457 bmap >>= 1; 2458 } 2459 } 2460 2461 static void 2462 bnad_mbox_irq_sync(struct bnad *bnad) 2463 { 2464 u32 irq; 2465 unsigned long flags; 2466 2467 spin_lock_irqsave(&bnad->bna_lock, flags); 2468 if (bnad->cfg_flags & BNAD_CF_MSIX) 2469 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector; 2470 else 2471 irq = bnad->pcidev->irq; 2472 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2473 2474 synchronize_irq(irq); 2475 } 2476 2477 /* Utility used by bnad_start_xmit, for doing TSO */ 2478 static int 2479 bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb) 2480 { 2481 int err; 2482 2483 err = skb_cow_head(skb, 0); 2484 if (err < 0) { 2485 BNAD_UPDATE_CTR(bnad, tso_err); 2486 return err; 2487 } 2488 2489 /* 2490 * For TSO, the TCP checksum field is seeded with pseudo-header sum 2491 * excluding the length field. 2492 */ 2493 if (vlan_get_protocol(skb) == htons(ETH_P_IP)) { 2494 struct iphdr *iph = ip_hdr(skb); 2495 2496 /* Do we really need these? */ 2497 iph->tot_len = 0; 2498 iph->check = 0; 2499 2500 tcp_hdr(skb)->check = 2501 ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, 2502 IPPROTO_TCP, 0); 2503 BNAD_UPDATE_CTR(bnad, tso4); 2504 } else { 2505 tcp_v6_gso_csum_prep(skb); 2506 BNAD_UPDATE_CTR(bnad, tso6); 2507 } 2508 2509 return 0; 2510 } 2511 2512 /* 2513 * Initialize Q numbers depending on Rx Paths 2514 * Called with bnad->bna_lock held, because of cfg_flags 2515 * access. 2516 */ 2517 static void 2518 bnad_q_num_init(struct bnad *bnad) 2519 { 2520 int rxps; 2521 2522 rxps = min((uint)num_online_cpus(), 2523 (uint)(BNAD_MAX_RX * BNAD_MAX_RXP_PER_RX)); 2524 2525 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) 2526 rxps = 1; /* INTx */ 2527 2528 bnad->num_rx = 1; 2529 bnad->num_tx = 1; 2530 bnad->num_rxp_per_rx = rxps; 2531 bnad->num_txq_per_tx = BNAD_TXQ_NUM; 2532 } 2533 2534 /* 2535 * Adjusts the Q numbers, given a number of msix vectors 2536 * Give preference to RSS as opposed to Tx priority Queues, 2537 * in such a case, just use 1 Tx Q 2538 * Called with bnad->bna_lock held b'cos of cfg_flags access 2539 */ 2540 static void 2541 bnad_q_num_adjust(struct bnad *bnad, int msix_vectors, int temp) 2542 { 2543 bnad->num_txq_per_tx = 1; 2544 if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) + 2545 bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) && 2546 (bnad->cfg_flags & BNAD_CF_MSIX)) { 2547 bnad->num_rxp_per_rx = msix_vectors - 2548 (bnad->num_tx * bnad->num_txq_per_tx) - 2549 BNAD_MAILBOX_MSIX_VECTORS; 2550 } else 2551 bnad->num_rxp_per_rx = 1; 2552 } 2553 2554 /* Enable / disable ioceth */ 2555 static int 2556 bnad_ioceth_disable(struct bnad *bnad) 2557 { 2558 unsigned long flags; 2559 int err = 0; 2560 2561 spin_lock_irqsave(&bnad->bna_lock, flags); 2562 init_completion(&bnad->bnad_completions.ioc_comp); 2563 bna_ioceth_disable(&bnad->bna.ioceth, BNA_HARD_CLEANUP); 2564 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2565 2566 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp, 2567 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT)); 2568 2569 err = bnad->bnad_completions.ioc_comp_status; 2570 return err; 2571 } 2572 2573 static int 2574 bnad_ioceth_enable(struct bnad *bnad) 2575 { 2576 int err = 0; 2577 unsigned long flags; 2578 2579 spin_lock_irqsave(&bnad->bna_lock, flags); 2580 init_completion(&bnad->bnad_completions.ioc_comp); 2581 bnad->bnad_completions.ioc_comp_status = BNA_CB_WAITING; 2582 bna_ioceth_enable(&bnad->bna.ioceth); 2583 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2584 2585 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp, 2586 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT)); 2587 2588 err = bnad->bnad_completions.ioc_comp_status; 2589 2590 return err; 2591 } 2592 2593 /* Free BNA resources */ 2594 static void 2595 bnad_res_free(struct bnad *bnad, struct bna_res_info *res_info, 2596 u32 res_val_max) 2597 { 2598 int i; 2599 2600 for (i = 0; i < res_val_max; i++) 2601 bnad_mem_free(bnad, &res_info[i].res_u.mem_info); 2602 } 2603 2604 /* Allocates memory and interrupt resources for BNA */ 2605 static int 2606 bnad_res_alloc(struct bnad *bnad, struct bna_res_info *res_info, 2607 u32 res_val_max) 2608 { 2609 int i, err; 2610 2611 for (i = 0; i < res_val_max; i++) { 2612 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info); 2613 if (err) 2614 goto err_return; 2615 } 2616 return 0; 2617 2618 err_return: 2619 bnad_res_free(bnad, res_info, res_val_max); 2620 return err; 2621 } 2622 2623 /* Interrupt enable / disable */ 2624 static void 2625 bnad_enable_msix(struct bnad *bnad) 2626 { 2627 int i, ret; 2628 unsigned long flags; 2629 2630 spin_lock_irqsave(&bnad->bna_lock, flags); 2631 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) { 2632 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2633 return; 2634 } 2635 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2636 2637 if (bnad->msix_table) 2638 return; 2639 2640 bnad->msix_table = 2641 kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL); 2642 2643 if (!bnad->msix_table) 2644 goto intx_mode; 2645 2646 for (i = 0; i < bnad->msix_num; i++) 2647 bnad->msix_table[i].entry = i; 2648 2649 ret = pci_enable_msix_range(bnad->pcidev, bnad->msix_table, 2650 1, bnad->msix_num); 2651 if (ret < 0) { 2652 goto intx_mode; 2653 } else if (ret < bnad->msix_num) { 2654 dev_warn(&bnad->pcidev->dev, 2655 "%d MSI-X vectors allocated < %d requested\n", 2656 ret, bnad->msix_num); 2657 2658 spin_lock_irqsave(&bnad->bna_lock, flags); 2659 /* ret = #of vectors that we got */ 2660 bnad_q_num_adjust(bnad, (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2, 2661 (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2); 2662 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2663 2664 bnad->msix_num = BNAD_NUM_TXQ + BNAD_NUM_RXP + 2665 BNAD_MAILBOX_MSIX_VECTORS; 2666 2667 if (bnad->msix_num > ret) { 2668 pci_disable_msix(bnad->pcidev); 2669 goto intx_mode; 2670 } 2671 } 2672 2673 pci_intx(bnad->pcidev, 0); 2674 2675 return; 2676 2677 intx_mode: 2678 dev_warn(&bnad->pcidev->dev, 2679 "MSI-X enable failed - operating in INTx mode\n"); 2680 2681 kfree(bnad->msix_table); 2682 bnad->msix_table = NULL; 2683 bnad->msix_num = 0; 2684 spin_lock_irqsave(&bnad->bna_lock, flags); 2685 bnad->cfg_flags &= ~BNAD_CF_MSIX; 2686 bnad_q_num_init(bnad); 2687 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2688 } 2689 2690 static void 2691 bnad_disable_msix(struct bnad *bnad) 2692 { 2693 u32 cfg_flags; 2694 unsigned long flags; 2695 2696 spin_lock_irqsave(&bnad->bna_lock, flags); 2697 cfg_flags = bnad->cfg_flags; 2698 if (bnad->cfg_flags & BNAD_CF_MSIX) 2699 bnad->cfg_flags &= ~BNAD_CF_MSIX; 2700 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2701 2702 if (cfg_flags & BNAD_CF_MSIX) { 2703 pci_disable_msix(bnad->pcidev); 2704 kfree(bnad->msix_table); 2705 bnad->msix_table = NULL; 2706 } 2707 } 2708 2709 /* Netdev entry points */ 2710 static int 2711 bnad_open(struct net_device *netdev) 2712 { 2713 int err; 2714 struct bnad *bnad = netdev_priv(netdev); 2715 struct bna_pause_config pause_config; 2716 unsigned long flags; 2717 2718 mutex_lock(&bnad->conf_mutex); 2719 2720 /* Tx */ 2721 err = bnad_setup_tx(bnad, 0); 2722 if (err) 2723 goto err_return; 2724 2725 /* Rx */ 2726 err = bnad_setup_rx(bnad, 0); 2727 if (err) 2728 goto cleanup_tx; 2729 2730 /* Port */ 2731 pause_config.tx_pause = 0; 2732 pause_config.rx_pause = 0; 2733 2734 spin_lock_irqsave(&bnad->bna_lock, flags); 2735 bna_enet_mtu_set(&bnad->bna.enet, 2736 BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL); 2737 bna_enet_pause_config(&bnad->bna.enet, &pause_config); 2738 bna_enet_enable(&bnad->bna.enet); 2739 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2740 2741 /* Enable broadcast */ 2742 bnad_enable_default_bcast(bnad); 2743 2744 /* Restore VLANs, if any */ 2745 bnad_restore_vlans(bnad, 0); 2746 2747 /* Set the UCAST address */ 2748 spin_lock_irqsave(&bnad->bna_lock, flags); 2749 bnad_mac_addr_set_locked(bnad, netdev->dev_addr); 2750 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2751 2752 /* Start the stats timer */ 2753 bnad_stats_timer_start(bnad); 2754 2755 mutex_unlock(&bnad->conf_mutex); 2756 2757 return 0; 2758 2759 cleanup_tx: 2760 bnad_destroy_tx(bnad, 0); 2761 2762 err_return: 2763 mutex_unlock(&bnad->conf_mutex); 2764 return err; 2765 } 2766 2767 static int 2768 bnad_stop(struct net_device *netdev) 2769 { 2770 struct bnad *bnad = netdev_priv(netdev); 2771 unsigned long flags; 2772 2773 mutex_lock(&bnad->conf_mutex); 2774 2775 /* Stop the stats timer */ 2776 bnad_stats_timer_stop(bnad); 2777 2778 init_completion(&bnad->bnad_completions.enet_comp); 2779 2780 spin_lock_irqsave(&bnad->bna_lock, flags); 2781 bna_enet_disable(&bnad->bna.enet, BNA_HARD_CLEANUP, 2782 bnad_cb_enet_disabled); 2783 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2784 2785 wait_for_completion(&bnad->bnad_completions.enet_comp); 2786 2787 bnad_destroy_tx(bnad, 0); 2788 bnad_destroy_rx(bnad, 0); 2789 2790 /* Synchronize mailbox IRQ */ 2791 bnad_mbox_irq_sync(bnad); 2792 2793 mutex_unlock(&bnad->conf_mutex); 2794 2795 return 0; 2796 } 2797 2798 /* TX */ 2799 /* Returns 0 for success */ 2800 static int 2801 bnad_txq_wi_prepare(struct bnad *bnad, struct bna_tcb *tcb, 2802 struct sk_buff *skb, struct bna_txq_entry *txqent) 2803 { 2804 u16 flags = 0; 2805 u32 gso_size; 2806 u16 vlan_tag = 0; 2807 2808 if (skb_vlan_tag_present(skb)) { 2809 vlan_tag = (u16)skb_vlan_tag_get(skb); 2810 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN); 2811 } 2812 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) { 2813 vlan_tag = ((tcb->priority & 0x7) << VLAN_PRIO_SHIFT) 2814 | (vlan_tag & 0x1fff); 2815 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN); 2816 } 2817 txqent->hdr.wi.vlan_tag = htons(vlan_tag); 2818 2819 if (skb_is_gso(skb)) { 2820 gso_size = skb_shinfo(skb)->gso_size; 2821 if (unlikely(gso_size > bnad->netdev->mtu)) { 2822 BNAD_UPDATE_CTR(bnad, tx_skb_mss_too_long); 2823 return -EINVAL; 2824 } 2825 if (unlikely((gso_size + skb_tcp_all_headers(skb)) >= skb->len)) { 2826 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND); 2827 txqent->hdr.wi.lso_mss = 0; 2828 BNAD_UPDATE_CTR(bnad, tx_skb_tso_too_short); 2829 } else { 2830 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND_LSO); 2831 txqent->hdr.wi.lso_mss = htons(gso_size); 2832 } 2833 2834 if (bnad_tso_prepare(bnad, skb)) { 2835 BNAD_UPDATE_CTR(bnad, tx_skb_tso_prepare); 2836 return -EINVAL; 2837 } 2838 2839 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM); 2840 txqent->hdr.wi.l4_hdr_size_n_offset = 2841 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET( 2842 tcp_hdrlen(skb) >> 2, skb_transport_offset(skb))); 2843 } else { 2844 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND); 2845 txqent->hdr.wi.lso_mss = 0; 2846 2847 if (unlikely(skb->len > (bnad->netdev->mtu + VLAN_ETH_HLEN))) { 2848 BNAD_UPDATE_CTR(bnad, tx_skb_non_tso_too_long); 2849 return -EINVAL; 2850 } 2851 2852 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2853 __be16 net_proto = vlan_get_protocol(skb); 2854 u8 proto = 0; 2855 2856 if (net_proto == htons(ETH_P_IP)) 2857 proto = ip_hdr(skb)->protocol; 2858 #ifdef NETIF_F_IPV6_CSUM 2859 else if (net_proto == htons(ETH_P_IPV6)) { 2860 /* nexthdr may not be TCP immediately. */ 2861 proto = ipv6_hdr(skb)->nexthdr; 2862 } 2863 #endif 2864 if (proto == IPPROTO_TCP) { 2865 flags |= BNA_TXQ_WI_CF_TCP_CKSUM; 2866 txqent->hdr.wi.l4_hdr_size_n_offset = 2867 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET 2868 (0, skb_transport_offset(skb))); 2869 2870 BNAD_UPDATE_CTR(bnad, tcpcsum_offload); 2871 2872 if (unlikely(skb_headlen(skb) < 2873 skb_tcp_all_headers(skb))) { 2874 BNAD_UPDATE_CTR(bnad, tx_skb_tcp_hdr); 2875 return -EINVAL; 2876 } 2877 } else if (proto == IPPROTO_UDP) { 2878 flags |= BNA_TXQ_WI_CF_UDP_CKSUM; 2879 txqent->hdr.wi.l4_hdr_size_n_offset = 2880 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET 2881 (0, skb_transport_offset(skb))); 2882 2883 BNAD_UPDATE_CTR(bnad, udpcsum_offload); 2884 if (unlikely(skb_headlen(skb) < 2885 skb_transport_offset(skb) + 2886 sizeof(struct udphdr))) { 2887 BNAD_UPDATE_CTR(bnad, tx_skb_udp_hdr); 2888 return -EINVAL; 2889 } 2890 } else { 2891 2892 BNAD_UPDATE_CTR(bnad, tx_skb_csum_err); 2893 return -EINVAL; 2894 } 2895 } else 2896 txqent->hdr.wi.l4_hdr_size_n_offset = 0; 2897 } 2898 2899 txqent->hdr.wi.flags = htons(flags); 2900 txqent->hdr.wi.frame_length = htonl(skb->len); 2901 2902 return 0; 2903 } 2904 2905 /* 2906 * bnad_start_xmit : Netdev entry point for Transmit 2907 * Called under lock held by net_device 2908 */ 2909 static netdev_tx_t 2910 bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev) 2911 { 2912 struct bnad *bnad = netdev_priv(netdev); 2913 u32 txq_id = 0; 2914 struct bna_tcb *tcb = NULL; 2915 struct bnad_tx_unmap *unmap_q, *unmap, *head_unmap; 2916 u32 prod, q_depth, vect_id; 2917 u32 wis, vectors, len; 2918 int i; 2919 dma_addr_t dma_addr; 2920 struct bna_txq_entry *txqent; 2921 2922 len = skb_headlen(skb); 2923 2924 /* Sanity checks for the skb */ 2925 2926 if (unlikely(skb->len <= ETH_HLEN)) { 2927 dev_kfree_skb_any(skb); 2928 BNAD_UPDATE_CTR(bnad, tx_skb_too_short); 2929 return NETDEV_TX_OK; 2930 } 2931 if (unlikely(len > BFI_TX_MAX_DATA_PER_VECTOR)) { 2932 dev_kfree_skb_any(skb); 2933 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero); 2934 return NETDEV_TX_OK; 2935 } 2936 if (unlikely(len == 0)) { 2937 dev_kfree_skb_any(skb); 2938 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero); 2939 return NETDEV_TX_OK; 2940 } 2941 2942 tcb = bnad->tx_info[0].tcb[txq_id]; 2943 2944 /* 2945 * Takes care of the Tx that is scheduled between clearing the flag 2946 * and the netif_tx_stop_all_queues() call. 2947 */ 2948 if (unlikely(!tcb || !test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) { 2949 dev_kfree_skb_any(skb); 2950 BNAD_UPDATE_CTR(bnad, tx_skb_stopping); 2951 return NETDEV_TX_OK; 2952 } 2953 2954 q_depth = tcb->q_depth; 2955 prod = tcb->producer_index; 2956 unmap_q = tcb->unmap_q; 2957 2958 vectors = 1 + skb_shinfo(skb)->nr_frags; 2959 wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */ 2960 2961 if (unlikely(vectors > BFI_TX_MAX_VECTORS_PER_PKT)) { 2962 dev_kfree_skb_any(skb); 2963 BNAD_UPDATE_CTR(bnad, tx_skb_max_vectors); 2964 return NETDEV_TX_OK; 2965 } 2966 2967 /* Check for available TxQ resources */ 2968 if (unlikely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) { 2969 if ((*tcb->hw_consumer_index != tcb->consumer_index) && 2970 !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) { 2971 u32 sent; 2972 sent = bnad_txcmpl_process(bnad, tcb); 2973 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) 2974 bna_ib_ack(tcb->i_dbell, sent); 2975 smp_mb__before_atomic(); 2976 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); 2977 } else { 2978 netif_stop_queue(netdev); 2979 BNAD_UPDATE_CTR(bnad, netif_queue_stop); 2980 } 2981 2982 smp_mb(); 2983 /* 2984 * Check again to deal with race condition between 2985 * netif_stop_queue here, and netif_wake_queue in 2986 * interrupt handler which is not inside netif tx lock. 2987 */ 2988 if (likely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) { 2989 BNAD_UPDATE_CTR(bnad, netif_queue_stop); 2990 return NETDEV_TX_BUSY; 2991 } else { 2992 netif_wake_queue(netdev); 2993 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); 2994 } 2995 } 2996 2997 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod]; 2998 head_unmap = &unmap_q[prod]; 2999 3000 /* Program the opcode, flags, frame_len, num_vectors in WI */ 3001 if (bnad_txq_wi_prepare(bnad, tcb, skb, txqent)) { 3002 dev_kfree_skb_any(skb); 3003 return NETDEV_TX_OK; 3004 } 3005 txqent->hdr.wi.reserved = 0; 3006 txqent->hdr.wi.num_vectors = vectors; 3007 3008 head_unmap->skb = skb; 3009 head_unmap->nvecs = 0; 3010 3011 /* Program the vectors */ 3012 unmap = head_unmap; 3013 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data, 3014 len, DMA_TO_DEVICE); 3015 if (dma_mapping_error(&bnad->pcidev->dev, dma_addr)) { 3016 dev_kfree_skb_any(skb); 3017 BNAD_UPDATE_CTR(bnad, tx_skb_map_failed); 3018 return NETDEV_TX_OK; 3019 } 3020 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[0].host_addr); 3021 txqent->vector[0].length = htons(len); 3022 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, dma_addr); 3023 head_unmap->nvecs++; 3024 3025 for (i = 0, vect_id = 0; i < vectors - 1; i++) { 3026 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3027 u32 size = skb_frag_size(frag); 3028 3029 if (unlikely(size == 0)) { 3030 /* Undo the changes starting at tcb->producer_index */ 3031 bnad_tx_buff_unmap(bnad, unmap_q, q_depth, 3032 tcb->producer_index); 3033 dev_kfree_skb_any(skb); 3034 BNAD_UPDATE_CTR(bnad, tx_skb_frag_zero); 3035 return NETDEV_TX_OK; 3036 } 3037 3038 len += size; 3039 3040 vect_id++; 3041 if (vect_id == BFI_TX_MAX_VECTORS_PER_WI) { 3042 vect_id = 0; 3043 BNA_QE_INDX_INC(prod, q_depth); 3044 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod]; 3045 txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION); 3046 unmap = &unmap_q[prod]; 3047 } 3048 3049 dma_addr = skb_frag_dma_map(&bnad->pcidev->dev, frag, 3050 0, size, DMA_TO_DEVICE); 3051 if (dma_mapping_error(&bnad->pcidev->dev, dma_addr)) { 3052 /* Undo the changes starting at tcb->producer_index */ 3053 bnad_tx_buff_unmap(bnad, unmap_q, q_depth, 3054 tcb->producer_index); 3055 dev_kfree_skb_any(skb); 3056 BNAD_UPDATE_CTR(bnad, tx_skb_map_failed); 3057 return NETDEV_TX_OK; 3058 } 3059 3060 dma_unmap_len_set(&unmap->vectors[vect_id], dma_len, size); 3061 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr); 3062 txqent->vector[vect_id].length = htons(size); 3063 dma_unmap_addr_set(&unmap->vectors[vect_id], dma_addr, 3064 dma_addr); 3065 head_unmap->nvecs++; 3066 } 3067 3068 if (unlikely(len != skb->len)) { 3069 /* Undo the changes starting at tcb->producer_index */ 3070 bnad_tx_buff_unmap(bnad, unmap_q, q_depth, tcb->producer_index); 3071 dev_kfree_skb_any(skb); 3072 BNAD_UPDATE_CTR(bnad, tx_skb_len_mismatch); 3073 return NETDEV_TX_OK; 3074 } 3075 3076 BNA_QE_INDX_INC(prod, q_depth); 3077 tcb->producer_index = prod; 3078 3079 wmb(); 3080 3081 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) 3082 return NETDEV_TX_OK; 3083 3084 skb_tx_timestamp(skb); 3085 3086 bna_txq_prod_indx_doorbell(tcb); 3087 3088 return NETDEV_TX_OK; 3089 } 3090 3091 /* 3092 * Used spin_lock to synchronize reading of stats structures, which 3093 * is written by BNA under the same lock. 3094 */ 3095 static void 3096 bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats) 3097 { 3098 struct bnad *bnad = netdev_priv(netdev); 3099 unsigned long flags; 3100 3101 spin_lock_irqsave(&bnad->bna_lock, flags); 3102 3103 bnad_netdev_qstats_fill(bnad, stats); 3104 bnad_netdev_hwstats_fill(bnad, stats); 3105 3106 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3107 } 3108 3109 static void 3110 bnad_set_rx_ucast_fltr(struct bnad *bnad) 3111 { 3112 struct net_device *netdev = bnad->netdev; 3113 int uc_count = netdev_uc_count(netdev); 3114 enum bna_cb_status ret; 3115 u8 *mac_list; 3116 struct netdev_hw_addr *ha; 3117 int entry; 3118 3119 if (netdev_uc_empty(bnad->netdev)) { 3120 bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL); 3121 return; 3122 } 3123 3124 if (uc_count > bna_attr(&bnad->bna)->num_ucmac) 3125 goto mode_default; 3126 3127 mac_list = kcalloc(ETH_ALEN, uc_count, GFP_ATOMIC); 3128 if (mac_list == NULL) 3129 goto mode_default; 3130 3131 entry = 0; 3132 netdev_for_each_uc_addr(ha, netdev) { 3133 ether_addr_copy(&mac_list[entry * ETH_ALEN], &ha->addr[0]); 3134 entry++; 3135 } 3136 3137 ret = bna_rx_ucast_listset(bnad->rx_info[0].rx, entry, mac_list); 3138 kfree(mac_list); 3139 3140 if (ret != BNA_CB_SUCCESS) 3141 goto mode_default; 3142 3143 return; 3144 3145 /* ucast packets not in UCAM are routed to default function */ 3146 mode_default: 3147 bnad->cfg_flags |= BNAD_CF_DEFAULT; 3148 bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL); 3149 } 3150 3151 static void 3152 bnad_set_rx_mcast_fltr(struct bnad *bnad) 3153 { 3154 struct net_device *netdev = bnad->netdev; 3155 int mc_count = netdev_mc_count(netdev); 3156 enum bna_cb_status ret; 3157 u8 *mac_list; 3158 3159 if (netdev->flags & IFF_ALLMULTI) 3160 goto mode_allmulti; 3161 3162 if (netdev_mc_empty(netdev)) 3163 return; 3164 3165 if (mc_count > bna_attr(&bnad->bna)->num_mcmac) 3166 goto mode_allmulti; 3167 3168 mac_list = kcalloc(mc_count + 1, ETH_ALEN, GFP_ATOMIC); 3169 3170 if (mac_list == NULL) 3171 goto mode_allmulti; 3172 3173 ether_addr_copy(&mac_list[0], &bnad_bcast_addr[0]); 3174 3175 /* copy rest of the MCAST addresses */ 3176 bnad_netdev_mc_list_get(netdev, mac_list); 3177 ret = bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1, mac_list); 3178 kfree(mac_list); 3179 3180 if (ret != BNA_CB_SUCCESS) 3181 goto mode_allmulti; 3182 3183 return; 3184 3185 mode_allmulti: 3186 bnad->cfg_flags |= BNAD_CF_ALLMULTI; 3187 bna_rx_mcast_delall(bnad->rx_info[0].rx); 3188 } 3189 3190 void 3191 bnad_set_rx_mode(struct net_device *netdev) 3192 { 3193 struct bnad *bnad = netdev_priv(netdev); 3194 enum bna_rxmode new_mode, mode_mask; 3195 unsigned long flags; 3196 3197 spin_lock_irqsave(&bnad->bna_lock, flags); 3198 3199 if (bnad->rx_info[0].rx == NULL) { 3200 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3201 return; 3202 } 3203 3204 /* clear bnad flags to update it with new settings */ 3205 bnad->cfg_flags &= ~(BNAD_CF_PROMISC | BNAD_CF_DEFAULT | 3206 BNAD_CF_ALLMULTI); 3207 3208 new_mode = 0; 3209 if (netdev->flags & IFF_PROMISC) { 3210 new_mode |= BNAD_RXMODE_PROMISC_DEFAULT; 3211 bnad->cfg_flags |= BNAD_CF_PROMISC; 3212 } else { 3213 bnad_set_rx_mcast_fltr(bnad); 3214 3215 if (bnad->cfg_flags & BNAD_CF_ALLMULTI) 3216 new_mode |= BNA_RXMODE_ALLMULTI; 3217 3218 bnad_set_rx_ucast_fltr(bnad); 3219 3220 if (bnad->cfg_flags & BNAD_CF_DEFAULT) 3221 new_mode |= BNA_RXMODE_DEFAULT; 3222 } 3223 3224 mode_mask = BNA_RXMODE_PROMISC | BNA_RXMODE_DEFAULT | 3225 BNA_RXMODE_ALLMULTI; 3226 bna_rx_mode_set(bnad->rx_info[0].rx, new_mode, mode_mask); 3227 3228 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3229 } 3230 3231 /* 3232 * bna_lock is used to sync writes to netdev->addr 3233 * conf_lock cannot be used since this call may be made 3234 * in a non-blocking context. 3235 */ 3236 static int 3237 bnad_set_mac_address(struct net_device *netdev, void *addr) 3238 { 3239 int err; 3240 struct bnad *bnad = netdev_priv(netdev); 3241 struct sockaddr *sa = (struct sockaddr *)addr; 3242 unsigned long flags; 3243 3244 spin_lock_irqsave(&bnad->bna_lock, flags); 3245 3246 err = bnad_mac_addr_set_locked(bnad, sa->sa_data); 3247 if (!err) 3248 eth_hw_addr_set(netdev, sa->sa_data); 3249 3250 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3251 3252 return err; 3253 } 3254 3255 static int 3256 bnad_mtu_set(struct bnad *bnad, int frame_size) 3257 { 3258 unsigned long flags; 3259 3260 init_completion(&bnad->bnad_completions.mtu_comp); 3261 3262 spin_lock_irqsave(&bnad->bna_lock, flags); 3263 bna_enet_mtu_set(&bnad->bna.enet, frame_size, bnad_cb_enet_mtu_set); 3264 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3265 3266 wait_for_completion(&bnad->bnad_completions.mtu_comp); 3267 3268 return bnad->bnad_completions.mtu_comp_status; 3269 } 3270 3271 static int 3272 bnad_change_mtu(struct net_device *netdev, int new_mtu) 3273 { 3274 int err, mtu; 3275 struct bnad *bnad = netdev_priv(netdev); 3276 u32 frame, new_frame; 3277 3278 mutex_lock(&bnad->conf_mutex); 3279 3280 mtu = netdev->mtu; 3281 WRITE_ONCE(netdev->mtu, new_mtu); 3282 3283 frame = BNAD_FRAME_SIZE(mtu); 3284 new_frame = BNAD_FRAME_SIZE(new_mtu); 3285 3286 /* check if multi-buffer needs to be enabled */ 3287 if (BNAD_PCI_DEV_IS_CAT2(bnad) && 3288 netif_running(bnad->netdev)) { 3289 /* only when transition is over 4K */ 3290 if ((frame <= 4096 && new_frame > 4096) || 3291 (frame > 4096 && new_frame <= 4096)) 3292 bnad_reinit_rx(bnad); 3293 } 3294 3295 err = bnad_mtu_set(bnad, new_frame); 3296 if (err) 3297 err = -EBUSY; 3298 3299 mutex_unlock(&bnad->conf_mutex); 3300 return err; 3301 } 3302 3303 static int 3304 bnad_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid) 3305 { 3306 struct bnad *bnad = netdev_priv(netdev); 3307 unsigned long flags; 3308 3309 if (!bnad->rx_info[0].rx) 3310 return 0; 3311 3312 mutex_lock(&bnad->conf_mutex); 3313 3314 spin_lock_irqsave(&bnad->bna_lock, flags); 3315 bna_rx_vlan_add(bnad->rx_info[0].rx, vid); 3316 set_bit(vid, bnad->active_vlans); 3317 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3318 3319 mutex_unlock(&bnad->conf_mutex); 3320 3321 return 0; 3322 } 3323 3324 static int 3325 bnad_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid) 3326 { 3327 struct bnad *bnad = netdev_priv(netdev); 3328 unsigned long flags; 3329 3330 if (!bnad->rx_info[0].rx) 3331 return 0; 3332 3333 mutex_lock(&bnad->conf_mutex); 3334 3335 spin_lock_irqsave(&bnad->bna_lock, flags); 3336 clear_bit(vid, bnad->active_vlans); 3337 bna_rx_vlan_del(bnad->rx_info[0].rx, vid); 3338 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3339 3340 mutex_unlock(&bnad->conf_mutex); 3341 3342 return 0; 3343 } 3344 3345 static int bnad_set_features(struct net_device *dev, netdev_features_t features) 3346 { 3347 struct bnad *bnad = netdev_priv(dev); 3348 netdev_features_t changed = features ^ dev->features; 3349 3350 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(dev)) { 3351 unsigned long flags; 3352 3353 spin_lock_irqsave(&bnad->bna_lock, flags); 3354 3355 if (features & NETIF_F_HW_VLAN_CTAG_RX) 3356 bna_rx_vlan_strip_enable(bnad->rx_info[0].rx); 3357 else 3358 bna_rx_vlan_strip_disable(bnad->rx_info[0].rx); 3359 3360 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3361 } 3362 3363 return 0; 3364 } 3365 3366 #ifdef CONFIG_NET_POLL_CONTROLLER 3367 static void 3368 bnad_netpoll(struct net_device *netdev) 3369 { 3370 struct bnad *bnad = netdev_priv(netdev); 3371 struct bnad_rx_info *rx_info; 3372 struct bnad_rx_ctrl *rx_ctrl; 3373 u32 curr_mask; 3374 int i, j; 3375 3376 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) { 3377 bna_intx_disable(&bnad->bna, curr_mask); 3378 bnad_isr(bnad->pcidev->irq, netdev); 3379 bna_intx_enable(&bnad->bna, curr_mask); 3380 } else { 3381 /* 3382 * Tx processing may happen in sending context, so no need 3383 * to explicitly process completions here 3384 */ 3385 3386 /* Rx processing */ 3387 for (i = 0; i < bnad->num_rx; i++) { 3388 rx_info = &bnad->rx_info[i]; 3389 if (!rx_info->rx) 3390 continue; 3391 for (j = 0; j < bnad->num_rxp_per_rx; j++) { 3392 rx_ctrl = &rx_info->rx_ctrl[j]; 3393 if (rx_ctrl->ccb) 3394 bnad_netif_rx_schedule_poll(bnad, 3395 rx_ctrl->ccb); 3396 } 3397 } 3398 } 3399 } 3400 #endif 3401 3402 static const struct net_device_ops bnad_netdev_ops = { 3403 .ndo_open = bnad_open, 3404 .ndo_stop = bnad_stop, 3405 .ndo_start_xmit = bnad_start_xmit, 3406 .ndo_get_stats64 = bnad_get_stats64, 3407 .ndo_set_rx_mode = bnad_set_rx_mode, 3408 .ndo_validate_addr = eth_validate_addr, 3409 .ndo_set_mac_address = bnad_set_mac_address, 3410 .ndo_change_mtu = bnad_change_mtu, 3411 .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid, 3412 .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid, 3413 .ndo_set_features = bnad_set_features, 3414 #ifdef CONFIG_NET_POLL_CONTROLLER 3415 .ndo_poll_controller = bnad_netpoll 3416 #endif 3417 }; 3418 3419 static void 3420 bnad_netdev_init(struct bnad *bnad) 3421 { 3422 struct net_device *netdev = bnad->netdev; 3423 3424 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | 3425 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 3426 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_TX | 3427 NETIF_F_HW_VLAN_CTAG_RX; 3428 3429 netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA | 3430 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 3431 NETIF_F_TSO | NETIF_F_TSO6; 3432 3433 netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER | 3434 NETIF_F_HIGHDMA; 3435 3436 netdev->mem_start = bnad->mmio_start; 3437 netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1; 3438 3439 /* MTU range: 46 - 9000 */ 3440 netdev->min_mtu = ETH_ZLEN - ETH_HLEN; 3441 netdev->max_mtu = BNAD_JUMBO_MTU; 3442 3443 netdev->netdev_ops = &bnad_netdev_ops; 3444 bnad_set_ethtool_ops(netdev); 3445 } 3446 3447 /* 3448 * 1. Initialize the bnad structure 3449 * 2. Setup netdev pointer in pci_dev 3450 * 3. Initialize no. of TxQ & CQs & MSIX vectors 3451 * 4. Initialize work queue. 3452 */ 3453 static int 3454 bnad_init(struct bnad *bnad, 3455 struct pci_dev *pdev, struct net_device *netdev) 3456 { 3457 unsigned long flags; 3458 3459 SET_NETDEV_DEV(netdev, &pdev->dev); 3460 pci_set_drvdata(pdev, netdev); 3461 3462 bnad->netdev = netdev; 3463 bnad->pcidev = pdev; 3464 bnad->mmio_start = pci_resource_start(pdev, 0); 3465 bnad->mmio_len = pci_resource_len(pdev, 0); 3466 bnad->bar0 = ioremap(bnad->mmio_start, bnad->mmio_len); 3467 if (!bnad->bar0) { 3468 dev_err(&pdev->dev, "ioremap for bar0 failed\n"); 3469 return -ENOMEM; 3470 } 3471 dev_info(&pdev->dev, "bar0 mapped to %p, len %llu\n", bnad->bar0, 3472 (unsigned long long) bnad->mmio_len); 3473 3474 spin_lock_irqsave(&bnad->bna_lock, flags); 3475 if (!bnad_msix_disable) 3476 bnad->cfg_flags = BNAD_CF_MSIX; 3477 3478 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED; 3479 3480 bnad_q_num_init(bnad); 3481 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3482 3483 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) + 3484 (bnad->num_rx * bnad->num_rxp_per_rx) + 3485 BNAD_MAILBOX_MSIX_VECTORS; 3486 3487 bnad->txq_depth = BNAD_TXQ_DEPTH; 3488 bnad->rxq_depth = BNAD_RXQ_DEPTH; 3489 3490 bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO; 3491 bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO; 3492 3493 sprintf(bnad->wq_name, "%s_wq_%d", BNAD_NAME, bnad->id); 3494 bnad->work_q = create_singlethread_workqueue(bnad->wq_name); 3495 if (!bnad->work_q) { 3496 iounmap(bnad->bar0); 3497 return -ENOMEM; 3498 } 3499 3500 return 0; 3501 } 3502 3503 /* 3504 * Must be called after bnad_pci_uninit() 3505 * so that iounmap() and pci_set_drvdata(NULL) 3506 * happens only after PCI uninitialization. 3507 */ 3508 static void 3509 bnad_uninit(struct bnad *bnad) 3510 { 3511 if (bnad->work_q) { 3512 destroy_workqueue(bnad->work_q); 3513 bnad->work_q = NULL; 3514 } 3515 3516 if (bnad->bar0) 3517 iounmap(bnad->bar0); 3518 } 3519 3520 /* 3521 * Initialize locks 3522 a) Per ioceth mutes used for serializing configuration 3523 changes from OS interface 3524 b) spin lock used to protect bna state machine 3525 */ 3526 static void 3527 bnad_lock_init(struct bnad *bnad) 3528 { 3529 spin_lock_init(&bnad->bna_lock); 3530 mutex_init(&bnad->conf_mutex); 3531 } 3532 3533 static void 3534 bnad_lock_uninit(struct bnad *bnad) 3535 { 3536 mutex_destroy(&bnad->conf_mutex); 3537 } 3538 3539 /* PCI Initialization */ 3540 static int 3541 bnad_pci_init(struct bnad *bnad, struct pci_dev *pdev) 3542 { 3543 int err; 3544 3545 err = pci_enable_device(pdev); 3546 if (err) 3547 return err; 3548 err = pci_request_regions(pdev, BNAD_NAME); 3549 if (err) 3550 goto disable_device; 3551 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3552 if (err) 3553 goto release_regions; 3554 pci_set_master(pdev); 3555 return 0; 3556 3557 release_regions: 3558 pci_release_regions(pdev); 3559 disable_device: 3560 pci_disable_device(pdev); 3561 3562 return err; 3563 } 3564 3565 static void 3566 bnad_pci_uninit(struct pci_dev *pdev) 3567 { 3568 pci_release_regions(pdev); 3569 pci_disable_device(pdev); 3570 } 3571 3572 static int 3573 bnad_pci_probe(struct pci_dev *pdev, 3574 const struct pci_device_id *pcidev_id) 3575 { 3576 int err; 3577 struct bnad *bnad; 3578 struct bna *bna; 3579 struct net_device *netdev; 3580 struct bfa_pcidev pcidev_info; 3581 unsigned long flags; 3582 3583 mutex_lock(&bnad_fwimg_mutex); 3584 if (!cna_get_firmware_buf(pdev)) { 3585 mutex_unlock(&bnad_fwimg_mutex); 3586 dev_err(&pdev->dev, "failed to load firmware image!\n"); 3587 return -ENODEV; 3588 } 3589 mutex_unlock(&bnad_fwimg_mutex); 3590 3591 /* 3592 * Allocates sizeof(struct net_device + struct bnad) 3593 * bnad = netdev->priv 3594 */ 3595 netdev = alloc_etherdev(sizeof(struct bnad)); 3596 if (!netdev) { 3597 err = -ENOMEM; 3598 return err; 3599 } 3600 bnad = netdev_priv(netdev); 3601 bnad_lock_init(bnad); 3602 bnad->id = atomic_inc_return(&bna_id) - 1; 3603 3604 mutex_lock(&bnad->conf_mutex); 3605 /* PCI initialization */ 3606 err = bnad_pci_init(bnad, pdev); 3607 if (err) 3608 goto unlock_mutex; 3609 3610 /* 3611 * Initialize bnad structure 3612 * Setup relation between pci_dev & netdev 3613 */ 3614 err = bnad_init(bnad, pdev, netdev); 3615 if (err) 3616 goto pci_uninit; 3617 3618 /* Initialize netdev structure, set up ethtool ops */ 3619 bnad_netdev_init(bnad); 3620 3621 /* Set link to down state */ 3622 netif_carrier_off(netdev); 3623 3624 /* Setup the debugfs node for this bfad */ 3625 if (bna_debugfs_enable) 3626 bnad_debugfs_init(bnad); 3627 3628 /* Get resource requirement form bna */ 3629 spin_lock_irqsave(&bnad->bna_lock, flags); 3630 bna_res_req(&bnad->res_info[0]); 3631 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3632 3633 /* Allocate resources from bna */ 3634 err = bnad_res_alloc(bnad, &bnad->res_info[0], BNA_RES_T_MAX); 3635 if (err) 3636 goto drv_uninit; 3637 3638 bna = &bnad->bna; 3639 3640 /* Setup pcidev_info for bna_init() */ 3641 pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn); 3642 pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn); 3643 pcidev_info.device_id = bnad->pcidev->device; 3644 pcidev_info.pci_bar_kva = bnad->bar0; 3645 3646 spin_lock_irqsave(&bnad->bna_lock, flags); 3647 bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]); 3648 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3649 3650 bnad->stats.bna_stats = &bna->stats; 3651 3652 bnad_enable_msix(bnad); 3653 err = bnad_mbox_irq_alloc(bnad); 3654 if (err) 3655 goto res_free; 3656 3657 /* Set up timers */ 3658 timer_setup(&bnad->bna.ioceth.ioc.ioc_timer, bnad_ioc_timeout, 0); 3659 timer_setup(&bnad->bna.ioceth.ioc.hb_timer, bnad_ioc_hb_check, 0); 3660 timer_setup(&bnad->bna.ioceth.ioc.iocpf_timer, bnad_iocpf_timeout, 0); 3661 timer_setup(&bnad->bna.ioceth.ioc.sem_timer, bnad_iocpf_sem_timeout, 3662 0); 3663 3664 /* 3665 * Start the chip 3666 * If the call back comes with error, we bail out. 3667 * This is a catastrophic error. 3668 */ 3669 err = bnad_ioceth_enable(bnad); 3670 if (err) { 3671 dev_err(&pdev->dev, "initialization failed err=%d\n", err); 3672 goto probe_success; 3673 } 3674 3675 spin_lock_irqsave(&bnad->bna_lock, flags); 3676 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) || 3677 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) { 3678 bnad_q_num_adjust(bnad, bna_attr(bna)->num_txq - 1, 3679 bna_attr(bna)->num_rxp - 1); 3680 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) || 3681 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) 3682 err = -EIO; 3683 } 3684 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3685 if (err) 3686 goto disable_ioceth; 3687 3688 spin_lock_irqsave(&bnad->bna_lock, flags); 3689 bna_mod_res_req(&bnad->bna, &bnad->mod_res_info[0]); 3690 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3691 3692 err = bnad_res_alloc(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX); 3693 if (err) { 3694 err = -EIO; 3695 goto disable_ioceth; 3696 } 3697 3698 spin_lock_irqsave(&bnad->bna_lock, flags); 3699 bna_mod_init(&bnad->bna, &bnad->mod_res_info[0]); 3700 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3701 3702 /* Get the burnt-in mac */ 3703 spin_lock_irqsave(&bnad->bna_lock, flags); 3704 bna_enet_perm_mac_get(&bna->enet, bnad->perm_addr); 3705 bnad_set_netdev_perm_addr(bnad); 3706 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3707 3708 mutex_unlock(&bnad->conf_mutex); 3709 3710 /* Finally, reguister with net_device layer */ 3711 err = register_netdev(netdev); 3712 if (err) { 3713 dev_err(&pdev->dev, "registering net device failed\n"); 3714 goto probe_uninit; 3715 } 3716 set_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags); 3717 3718 return 0; 3719 3720 probe_success: 3721 mutex_unlock(&bnad->conf_mutex); 3722 return 0; 3723 3724 probe_uninit: 3725 mutex_lock(&bnad->conf_mutex); 3726 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX); 3727 disable_ioceth: 3728 bnad_ioceth_disable(bnad); 3729 timer_delete_sync(&bnad->bna.ioceth.ioc.ioc_timer); 3730 timer_delete_sync(&bnad->bna.ioceth.ioc.sem_timer); 3731 timer_delete_sync(&bnad->bna.ioceth.ioc.hb_timer); 3732 spin_lock_irqsave(&bnad->bna_lock, flags); 3733 bna_uninit(bna); 3734 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3735 bnad_mbox_irq_free(bnad); 3736 bnad_disable_msix(bnad); 3737 res_free: 3738 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX); 3739 drv_uninit: 3740 /* Remove the debugfs node for this bnad */ 3741 kfree(bnad->regdata); 3742 bnad_debugfs_uninit(bnad); 3743 bnad_uninit(bnad); 3744 pci_uninit: 3745 bnad_pci_uninit(pdev); 3746 unlock_mutex: 3747 mutex_unlock(&bnad->conf_mutex); 3748 bnad_lock_uninit(bnad); 3749 free_netdev(netdev); 3750 return err; 3751 } 3752 3753 static void 3754 bnad_pci_remove(struct pci_dev *pdev) 3755 { 3756 struct net_device *netdev = pci_get_drvdata(pdev); 3757 struct bnad *bnad; 3758 struct bna *bna; 3759 unsigned long flags; 3760 3761 if (!netdev) 3762 return; 3763 3764 bnad = netdev_priv(netdev); 3765 bna = &bnad->bna; 3766 3767 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags)) 3768 unregister_netdev(netdev); 3769 3770 mutex_lock(&bnad->conf_mutex); 3771 bnad_ioceth_disable(bnad); 3772 timer_delete_sync(&bnad->bna.ioceth.ioc.ioc_timer); 3773 timer_delete_sync(&bnad->bna.ioceth.ioc.sem_timer); 3774 timer_delete_sync(&bnad->bna.ioceth.ioc.hb_timer); 3775 spin_lock_irqsave(&bnad->bna_lock, flags); 3776 bna_uninit(bna); 3777 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3778 3779 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX); 3780 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX); 3781 bnad_mbox_irq_free(bnad); 3782 bnad_disable_msix(bnad); 3783 bnad_pci_uninit(pdev); 3784 mutex_unlock(&bnad->conf_mutex); 3785 bnad_lock_uninit(bnad); 3786 /* Remove the debugfs node for this bnad */ 3787 kfree(bnad->regdata); 3788 bnad_debugfs_uninit(bnad); 3789 bnad_uninit(bnad); 3790 free_netdev(netdev); 3791 } 3792 3793 static const struct pci_device_id bnad_pci_id_table[] = { 3794 { 3795 PCI_DEVICE(PCI_VENDOR_ID_BROCADE, 3796 PCI_DEVICE_ID_BROCADE_CT), 3797 .class = PCI_CLASS_NETWORK_ETHERNET << 8, 3798 .class_mask = 0xffff00 3799 }, 3800 { 3801 PCI_DEVICE(PCI_VENDOR_ID_BROCADE, 3802 BFA_PCI_DEVICE_ID_CT2), 3803 .class = PCI_CLASS_NETWORK_ETHERNET << 8, 3804 .class_mask = 0xffff00 3805 }, 3806 {0, }, 3807 }; 3808 3809 MODULE_DEVICE_TABLE(pci, bnad_pci_id_table); 3810 3811 static struct pci_driver bnad_pci_driver = { 3812 .name = BNAD_NAME, 3813 .id_table = bnad_pci_id_table, 3814 .probe = bnad_pci_probe, 3815 .remove = bnad_pci_remove, 3816 }; 3817 3818 static int __init 3819 bnad_module_init(void) 3820 { 3821 int err; 3822 3823 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover); 3824 3825 err = pci_register_driver(&bnad_pci_driver); 3826 if (err < 0) { 3827 pr_err("bna: PCI driver registration failed err=%d\n", err); 3828 return err; 3829 } 3830 3831 return 0; 3832 } 3833 3834 static void __exit 3835 bnad_module_exit(void) 3836 { 3837 pci_unregister_driver(&bnad_pci_driver); 3838 release_firmware(bfi_fw); 3839 } 3840 3841 module_init(bnad_module_init); 3842 module_exit(bnad_module_exit); 3843 3844 MODULE_AUTHOR("Brocade"); 3845 MODULE_LICENSE("GPL"); 3846 MODULE_DESCRIPTION("QLogic BR-series 10G PCIe Ethernet driver"); 3847 MODULE_FIRMWARE(CNA_FW_FILE_CT); 3848 MODULE_FIRMWARE(CNA_FW_FILE_CT2); 3849