1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014-2025 Broadcom 4 */ 5 6 #ifndef __BCMGENET_H__ 7 #define __BCMGENET_H__ 8 9 #include <linux/skbuff.h> 10 #include <linux/netdevice.h> 11 #include <linux/spinlock.h> 12 #include <linux/clk.h> 13 #include <linux/mii.h> 14 #include <linux/if_vlan.h> 15 #include <linux/phy.h> 16 #include <linux/dim.h> 17 #include <linux/ethtool.h> 18 19 #include "../unimac.h" 20 21 /* Maximum number of hardware queues, downsized if needed */ 22 #define GENET_MAX_MQ_CNT 4 23 24 /* total number of Buffer Descriptors, same for Rx/Tx */ 25 #define TOTAL_DESC 256 26 27 /* which ring is descriptor based */ 28 #define DESC_INDEX 16 29 30 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. 31 * 1536 is multiple of 256 bytes 32 */ 33 #define ENET_BRCM_TAG_LEN 6 34 #define ENET_PAD 8 35 #define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ 36 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) 37 #define DMA_MAX_BURST_LENGTH 0x10 38 39 /* misc. configuration */ 40 #define MAX_NUM_OF_FS_RULES 16 41 #define CLEAR_ALL_HFB 0xFF 42 #define DMA_FC_THRESH_HI (TOTAL_DESC >> 4) 43 #define DMA_FC_THRESH_LO 5 44 45 /* 64B receive/transmit status block */ 46 struct status_64 { 47 u32 length_status; /* length and peripheral status */ 48 u32 ext_status; /* Extended status*/ 49 u32 rx_csum; /* partial rx checksum */ 50 u32 unused1[9]; /* unused */ 51 u32 tx_csum_info; /* Tx checksum info. */ 52 u32 unused2[3]; /* unused */ 53 }; 54 55 /* Rx status bits */ 56 #define STATUS_RX_EXT_MASK 0x1FFFFF 57 #define STATUS_RX_CSUM_MASK 0xFFFF 58 #define STATUS_RX_CSUM_OK 0x10000 59 #define STATUS_RX_CSUM_FR 0x20000 60 #define STATUS_RX_PROTO_TCP 0 61 #define STATUS_RX_PROTO_UDP 1 62 #define STATUS_RX_PROTO_ICMP 2 63 #define STATUS_RX_PROTO_OTHER 3 64 #define STATUS_RX_PROTO_MASK 3 65 #define STATUS_RX_PROTO_SHIFT 18 66 #define STATUS_FILTER_INDEX_MASK 0xFFFF 67 /* Tx status bits */ 68 #define STATUS_TX_CSUM_START_MASK 0X7FFF 69 #define STATUS_TX_CSUM_START_SHIFT 16 70 #define STATUS_TX_CSUM_PROTO_UDP 0x8000 71 #define STATUS_TX_CSUM_OFFSET_MASK 0x7FFF 72 #define STATUS_TX_CSUM_LV 0x80000000 73 74 /* DMA Descriptor */ 75 #define DMA_DESC_LENGTH_STATUS 0x00 /* in bytes of data in buffer */ 76 #define DMA_DESC_ADDRESS_LO 0x04 /* lower bits of PA */ 77 #define DMA_DESC_ADDRESS_HI 0x08 /* upper 32 bits of PA, GENETv4+ */ 78 79 /* Rx/Tx common counter group */ 80 struct bcmgenet_pkt_counters { 81 u32 cnt_64; /* RO Received/Transmited 64 bytes packet */ 82 u32 cnt_127; /* RO Rx/Tx 127 bytes packet */ 83 u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */ 84 u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */ 85 u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */ 86 u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */ 87 u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */ 88 u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/ 89 u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/ 90 u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/ 91 }; 92 93 /* RSV, Receive Status Vector */ 94 struct bcmgenet_rx_counters { 95 struct bcmgenet_pkt_counters pkt_cnt; 96 u32 pkt; /* RO (0x428) Received pkt count*/ 97 u32 bytes; /* RO Received byte count */ 98 u32 mca; /* RO # of Received multicast pkt */ 99 u32 bca; /* RO # of Receive broadcast pkt */ 100 u32 fcs; /* RO # of Received FCS error */ 101 u32 cf; /* RO # of Received control frame pkt*/ 102 u32 pf; /* RO # of Received pause frame pkt */ 103 u32 uo; /* RO # of unknown op code pkt */ 104 u32 aln; /* RO # of alignment error count */ 105 u32 flr; /* RO # of frame length out of range count */ 106 u32 cde; /* RO # of code error pkt */ 107 u32 fcr; /* RO # of carrier sense error pkt */ 108 u32 ovr; /* RO # of oversize pkt*/ 109 u32 jbr; /* RO # of jabber count */ 110 u32 mtue; /* RO # of MTU error pkt*/ 111 u32 pok; /* RO # of Received good pkt */ 112 u32 uc; /* RO # of unicast pkt */ 113 u32 ppp; /* RO # of PPP pkt */ 114 u32 rcrc; /* RO (0x470),# of CRC match pkt */ 115 }; 116 117 /* TSV, Transmit Status Vector */ 118 struct bcmgenet_tx_counters { 119 struct bcmgenet_pkt_counters pkt_cnt; 120 u32 pkts; /* RO (0x4a8) Transmited pkt */ 121 u32 mca; /* RO # of xmited multicast pkt */ 122 u32 bca; /* RO # of xmited broadcast pkt */ 123 u32 pf; /* RO # of xmited pause frame count */ 124 u32 cf; /* RO # of xmited control frame count */ 125 u32 fcs; /* RO # of xmited FCS error count */ 126 u32 ovr; /* RO # of xmited oversize pkt */ 127 u32 drf; /* RO # of xmited deferral pkt */ 128 u32 edf; /* RO # of xmited Excessive deferral pkt*/ 129 u32 scl; /* RO # of xmited single collision pkt */ 130 u32 mcl; /* RO # of xmited multiple collision pkt*/ 131 u32 lcl; /* RO # of xmited late collision pkt */ 132 u32 ecl; /* RO # of xmited excessive collision pkt*/ 133 u32 frg; /* RO # of xmited fragments pkt*/ 134 u32 ncl; /* RO # of xmited total collision count */ 135 u32 jbr; /* RO # of xmited jabber count*/ 136 u32 bytes; /* RO # of xmited byte count */ 137 u32 pok; /* RO # of xmited good pkt */ 138 u32 uc; /* RO (0x0x4f0)# of xmited unitcast pkt */ 139 }; 140 141 struct bcmgenet_mib_counters { 142 struct bcmgenet_rx_counters rx; 143 struct bcmgenet_tx_counters tx; 144 u32 rx_runt_cnt; 145 u32 rx_runt_fcs; 146 u32 rx_runt_fcs_align; 147 u32 rx_runt_bytes; 148 u32 rbuf_ovflow_cnt; 149 u32 rbuf_err_cnt; 150 u32 mdf_err_cnt; 151 u32 alloc_rx_buff_failed; 152 u32 rx_dma_failed; 153 u32 tx_dma_failed; 154 u32 tx_realloc_tsb; 155 u32 tx_realloc_tsb_failed; 156 }; 157 158 #define UMAC_MIB_START 0x400 159 160 #define UMAC_MDIO_CMD 0x614 161 #define MDIO_START_BUSY (1 << 29) 162 #define MDIO_READ_FAIL (1 << 28) 163 #define MDIO_RD (2 << 26) 164 #define MDIO_WR (1 << 26) 165 #define MDIO_PMD_SHIFT 21 166 #define MDIO_PMD_MASK 0x1F 167 #define MDIO_REG_SHIFT 16 168 #define MDIO_REG_MASK 0x1F 169 170 #define UMAC_RBUF_OVFL_CNT_V1 0x61C 171 #define RBUF_OVFL_CNT_V2 0x80 172 #define RBUF_OVFL_CNT_V3PLUS 0x94 173 174 #define UMAC_MPD_CTRL 0x620 175 #define MPD_EN (1 << 0) 176 #define MPD_PW_EN (1 << 27) 177 #define MPD_MSEQ_LEN_SHIFT 16 178 #define MPD_MSEQ_LEN_MASK 0xFF 179 180 #define UMAC_MPD_PW_MS 0x624 181 #define UMAC_MPD_PW_LS 0x628 182 #define UMAC_RBUF_ERR_CNT_V1 0x634 183 #define RBUF_ERR_CNT_V2 0x84 184 #define RBUF_ERR_CNT_V3PLUS 0x98 185 #define UMAC_MDF_ERR_CNT 0x638 186 #define UMAC_MDF_CTRL 0x650 187 #define UMAC_MDF_ADDR 0x654 188 #define UMAC_MIB_CTRL 0x580 189 #define MIB_RESET_RX (1 << 0) 190 #define MIB_RESET_RUNT (1 << 1) 191 #define MIB_RESET_TX (1 << 2) 192 193 #define RBUF_CTRL 0x00 194 #define RBUF_64B_EN (1 << 0) 195 #define RBUF_ALIGN_2B (1 << 1) 196 #define RBUF_BAD_DIS (1 << 2) 197 198 #define RBUF_STATUS 0x0C 199 #define RBUF_STATUS_WOL (1 << 0) 200 #define RBUF_STATUS_MPD_INTR_ACTIVE (1 << 1) 201 #define RBUF_STATUS_ACPI_INTR_ACTIVE (1 << 2) 202 203 #define RBUF_CHK_CTRL 0x14 204 #define RBUF_RXCHK_EN (1 << 0) 205 #define RBUF_SKIP_FCS (1 << 4) 206 #define RBUF_L3_PARSE_DIS (1 << 5) 207 208 #define RBUF_ENERGY_CTRL 0x9c 209 #define RBUF_EEE_EN (1 << 0) 210 #define RBUF_PM_EN (1 << 1) 211 212 #define RBUF_TBUF_SIZE_CTRL 0xb4 213 214 #define RBUF_HFB_CTRL_V1 0x38 215 #define RBUF_HFB_FILTER_EN_SHIFT 16 216 #define RBUF_HFB_FILTER_EN_MASK 0xffff0000 217 #define RBUF_HFB_EN (1 << 0) 218 #define RBUF_HFB_256B (1 << 1) 219 #define RBUF_ACPI_EN (1 << 2) 220 221 #define RBUF_HFB_LEN_V1 0x3C 222 #define RBUF_FLTR_LEN_MASK 0xFF 223 #define RBUF_FLTR_LEN_SHIFT 8 224 225 #define TBUF_CTRL 0x00 226 #define TBUF_64B_EN (1 << 0) 227 #define TBUF_BP_MC 0x0C 228 #define TBUF_ENERGY_CTRL 0x14 229 #define TBUF_EEE_EN (1 << 0) 230 #define TBUF_PM_EN (1 << 1) 231 232 #define TBUF_CTRL_V1 0x80 233 #define TBUF_BP_MC_V1 0xA0 234 235 #define HFB_CTRL 0x00 236 #define HFB_FLT_ENABLE_V3PLUS 0x04 237 #define HFB_FLT_LEN_V2 0x04 238 #define HFB_FLT_LEN_V3PLUS 0x1C 239 240 /* uniMac intrl2 registers */ 241 #define INTRL2_CPU_STAT 0x00 242 #define INTRL2_CPU_SET 0x04 243 #define INTRL2_CPU_CLEAR 0x08 244 #define INTRL2_CPU_MASK_STATUS 0x0C 245 #define INTRL2_CPU_MASK_SET 0x10 246 #define INTRL2_CPU_MASK_CLEAR 0x14 247 248 /* INTRL2 instance 0 definitions */ 249 #define UMAC_IRQ_SCB (1 << 0) 250 #define UMAC_IRQ_EPHY (1 << 1) 251 #define UMAC_IRQ_PHY_DET_R (1 << 2) 252 #define UMAC_IRQ_PHY_DET_F (1 << 3) 253 #define UMAC_IRQ_LINK_UP (1 << 4) 254 #define UMAC_IRQ_LINK_DOWN (1 << 5) 255 #define UMAC_IRQ_LINK_EVENT (UMAC_IRQ_LINK_UP | UMAC_IRQ_LINK_DOWN) 256 #define UMAC_IRQ_UMAC (1 << 6) 257 #define UMAC_IRQ_UMAC_TSV (1 << 7) 258 #define UMAC_IRQ_TBUF_UNDERRUN (1 << 8) 259 #define UMAC_IRQ_RBUF_OVERFLOW (1 << 9) 260 #define UMAC_IRQ_HFB_SM (1 << 10) 261 #define UMAC_IRQ_HFB_MM (1 << 11) 262 #define UMAC_IRQ_MPD_R (1 << 12) 263 #define UMAC_IRQ_WAKE_EVENT (UMAC_IRQ_HFB_SM | UMAC_IRQ_HFB_MM | \ 264 UMAC_IRQ_MPD_R) 265 #define UMAC_IRQ_RXDMA_MBDONE (1 << 13) 266 #define UMAC_IRQ_RXDMA_PDONE (1 << 14) 267 #define UMAC_IRQ_RXDMA_BDONE (1 << 15) 268 #define UMAC_IRQ_RXDMA_DONE UMAC_IRQ_RXDMA_MBDONE 269 #define UMAC_IRQ_TXDMA_MBDONE (1 << 16) 270 #define UMAC_IRQ_TXDMA_PDONE (1 << 17) 271 #define UMAC_IRQ_TXDMA_BDONE (1 << 18) 272 #define UMAC_IRQ_TXDMA_DONE UMAC_IRQ_TXDMA_MBDONE 273 274 /* Only valid for GENETv3+ */ 275 #define UMAC_IRQ_MDIO_DONE (1 << 23) 276 #define UMAC_IRQ_MDIO_ERROR (1 << 24) 277 #define UMAC_IRQ_MDIO_EVENT (UMAC_IRQ_MDIO_DONE | \ 278 UMAC_IRQ_MDIO_ERROR) 279 280 /* INTRL2 instance 1 definitions */ 281 #define UMAC_IRQ1_TX_INTR_MASK 0xFFFF 282 #define UMAC_IRQ1_RX_INTR_MASK 0xFFFF 283 #define UMAC_IRQ1_RX_INTR_SHIFT 16 284 285 /* Register block offsets */ 286 #define GENET_SYS_OFF 0x0000 287 #define GENET_GR_BRIDGE_OFF 0x0040 288 #define GENET_EXT_OFF 0x0080 289 #define GENET_INTRL2_0_OFF 0x0200 290 #define GENET_INTRL2_1_OFF 0x0240 291 #define GENET_RBUF_OFF 0x0300 292 #define GENET_UMAC_OFF 0x0800 293 294 /* SYS block offsets and register definitions */ 295 #define SYS_REV_CTRL 0x00 296 #define SYS_PORT_CTRL 0x04 297 #define PORT_MODE_INT_EPHY 0 298 #define PORT_MODE_INT_GPHY 1 299 #define PORT_MODE_EXT_EPHY 2 300 #define PORT_MODE_EXT_GPHY 3 301 #define PORT_MODE_EXT_RVMII_25 (4 | BIT(4)) 302 #define PORT_MODE_EXT_RVMII_50 4 303 #define LED_ACT_SOURCE_MAC (1 << 9) 304 305 #define SYS_RBUF_FLUSH_CTRL 0x08 306 #define SYS_TBUF_FLUSH_CTRL 0x0C 307 #define RBUF_FLUSH_CTRL_V1 0x04 308 309 /* Ext block register offsets and definitions */ 310 #define EXT_EXT_PWR_MGMT 0x00 311 #define EXT_PWR_DOWN_BIAS (1 << 0) 312 #define EXT_PWR_DOWN_DLL (1 << 1) 313 #define EXT_PWR_DOWN_PHY (1 << 2) 314 #define EXT_PWR_DN_EN_LD (1 << 3) 315 #define EXT_ENERGY_DET (1 << 4) 316 #define EXT_IDDQ_FROM_PHY (1 << 5) 317 #define EXT_IDDQ_GLBL_PWR (1 << 7) 318 #define EXT_PHY_RESET (1 << 8) 319 #define EXT_ENERGY_DET_MASK (1 << 12) 320 #define EXT_PWR_DOWN_PHY_TX (1 << 16) 321 #define EXT_PWR_DOWN_PHY_RX (1 << 17) 322 #define EXT_PWR_DOWN_PHY_SD (1 << 18) 323 #define EXT_PWR_DOWN_PHY_RD (1 << 19) 324 #define EXT_PWR_DOWN_PHY_EN (1 << 20) 325 326 #define EXT_RGMII_OOB_CTRL 0x0C 327 #define RGMII_MODE_EN_V123 (1 << 0) 328 #define RGMII_LINK (1 << 4) 329 #define OOB_DISABLE (1 << 5) 330 #define RGMII_MODE_EN (1 << 6) 331 #define ID_MODE_DIS (1 << 16) 332 333 #define EXT_GPHY_CTRL 0x1C 334 #define EXT_CFG_IDDQ_BIAS (1 << 0) 335 #define EXT_CFG_PWR_DOWN (1 << 1) 336 #define EXT_CK25_DIS (1 << 4) 337 #define EXT_CFG_IDDQ_GLOBAL_PWR (1 << 3) 338 #define EXT_GPHY_RESET (1 << 5) 339 340 /* DMA rings size */ 341 #define DMA_RING_SIZE (0x40) 342 #define DMA_RINGS_SIZE (DMA_RING_SIZE * (DESC_INDEX + 1)) 343 344 /* DMA registers common definitions */ 345 #define DMA_RW_POINTER_MASK 0x1FF 346 #define DMA_P_INDEX_DISCARD_CNT_MASK 0xFFFF 347 #define DMA_P_INDEX_DISCARD_CNT_SHIFT 16 348 #define DMA_BUFFER_DONE_CNT_MASK 0xFFFF 349 #define DMA_BUFFER_DONE_CNT_SHIFT 16 350 #define DMA_P_INDEX_MASK 0xFFFF 351 #define DMA_C_INDEX_MASK 0xFFFF 352 353 /* DMA ring size register */ 354 #define DMA_RING_SIZE_MASK 0xFFFF 355 #define DMA_RING_SIZE_SHIFT 16 356 #define DMA_RING_BUFFER_SIZE_MASK 0xFFFF 357 358 /* DMA interrupt threshold register */ 359 #define DMA_INTR_THRESHOLD_MASK 0x01FF 360 361 /* DMA XON/XOFF register */ 362 #define DMA_XON_THREHOLD_MASK 0xFFFF 363 #define DMA_XOFF_THRESHOLD_MASK 0xFFFF 364 #define DMA_XOFF_THRESHOLD_SHIFT 16 365 366 /* DMA flow period register */ 367 #define DMA_FLOW_PERIOD_MASK 0xFFFF 368 #define DMA_MAX_PKT_SIZE_MASK 0xFFFF 369 #define DMA_MAX_PKT_SIZE_SHIFT 16 370 371 372 /* DMA control register */ 373 #define DMA_EN (1 << 0) 374 #define DMA_RING_BUF_EN_SHIFT 0x01 375 #define DMA_RING_BUF_EN_MASK 0xFFFF 376 #define DMA_TSB_SWAP_EN (1 << 20) 377 378 /* DMA status register */ 379 #define DMA_DISABLED (1 << 0) 380 #define DMA_DESC_RAM_INIT_BUSY (1 << 1) 381 382 /* DMA SCB burst size register */ 383 #define DMA_SCB_BURST_SIZE_MASK 0x1F 384 385 /* DMA activity vector register */ 386 #define DMA_ACTIVITY_VECTOR_MASK 0x1FFFF 387 388 /* DMA backpressure mask register */ 389 #define DMA_BACKPRESSURE_MASK 0x1FFFF 390 #define DMA_PFC_ENABLE (1 << 31) 391 392 /* DMA backpressure status register */ 393 #define DMA_BACKPRESSURE_STATUS_MASK 0x1FFFF 394 395 /* DMA override register */ 396 #define DMA_LITTLE_ENDIAN_MODE (1 << 0) 397 #define DMA_REGISTER_MODE (1 << 1) 398 399 /* DMA timeout register */ 400 #define DMA_TIMEOUT_MASK 0xFFFF 401 #define DMA_TIMEOUT_VAL 5000 /* micro seconds */ 402 403 /* TDMA rate limiting control register */ 404 #define DMA_RATE_LIMIT_EN_MASK 0xFFFF 405 406 /* TDMA arbitration control register */ 407 #define DMA_ARBITER_MODE_MASK 0x03 408 #define DMA_RING_BUF_PRIORITY_MASK 0x1F 409 #define DMA_RING_BUF_PRIORITY_SHIFT 5 410 #define DMA_PRIO_REG_INDEX(q) ((q) / 6) 411 #define DMA_PRIO_REG_SHIFT(q) (((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT) 412 #define DMA_RATE_ADJ_MASK 0xFF 413 414 /* Tx/Rx Dma Descriptor common bits*/ 415 #define DMA_BUFLENGTH_MASK 0x0fff 416 #define DMA_BUFLENGTH_SHIFT 16 417 #define DMA_OWN 0x8000 418 #define DMA_EOP 0x4000 419 #define DMA_SOP 0x2000 420 #define DMA_WRAP 0x1000 421 /* Tx specific Dma descriptor bits */ 422 #define DMA_TX_UNDERRUN 0x0200 423 #define DMA_TX_APPEND_CRC 0x0040 424 #define DMA_TX_OW_CRC 0x0020 425 #define DMA_TX_DO_CSUM 0x0010 426 #define DMA_TX_QTAG_SHIFT 7 427 428 /* Rx Specific Dma descriptor bits */ 429 #define DMA_RX_CHK_V3PLUS 0x8000 430 #define DMA_RX_CHK_V12 0x1000 431 #define DMA_RX_BRDCAST 0x0040 432 #define DMA_RX_MULT 0x0020 433 #define DMA_RX_LG 0x0010 434 #define DMA_RX_NO 0x0008 435 #define DMA_RX_RXER 0x0004 436 #define DMA_RX_CRC_ERROR 0x0002 437 #define DMA_RX_OV 0x0001 438 #define DMA_RX_FI_MASK 0x001F 439 #define DMA_RX_FI_SHIFT 0x0007 440 #define DMA_DESC_ALLOC_MASK 0x00FF 441 442 #define DMA_ARBITER_RR 0x00 443 #define DMA_ARBITER_WRR 0x01 444 #define DMA_ARBITER_SP 0x02 445 446 struct enet_cb { 447 struct sk_buff *skb; 448 void __iomem *bd_addr; 449 DEFINE_DMA_UNMAP_ADDR(dma_addr); 450 DEFINE_DMA_UNMAP_LEN(dma_len); 451 }; 452 453 /* power management mode */ 454 enum bcmgenet_power_mode { 455 GENET_POWER_CABLE_SENSE = 0, 456 GENET_POWER_PASSIVE, 457 GENET_POWER_WOL_MAGIC, 458 }; 459 460 struct bcmgenet_priv; 461 462 /* We support both runtime GENET detection and compile-time 463 * to optimize code-paths for a given hardware 464 */ 465 enum bcmgenet_version { 466 GENET_V1 = 1, 467 GENET_V2, 468 GENET_V3, 469 GENET_V4, 470 GENET_V5 471 }; 472 473 #define GENET_IS_V1(p) ((p)->version == GENET_V1) 474 #define GENET_IS_V2(p) ((p)->version == GENET_V2) 475 #define GENET_IS_V3(p) ((p)->version == GENET_V3) 476 #define GENET_IS_V4(p) ((p)->version == GENET_V4) 477 #define GENET_IS_V5(p) ((p)->version == GENET_V5) 478 479 /* Hardware flags */ 480 #define GENET_HAS_40BITS (1 << 0) 481 #define GENET_HAS_EXT (1 << 1) 482 #define GENET_HAS_MDIO_INTR (1 << 2) 483 #define GENET_HAS_MOCA_LINK_DET (1 << 3) 484 #define GENET_HAS_EPHY_16NM (1 << 4) 485 486 /* BCMGENET hardware parameters, keep this structure nicely aligned 487 * since it is going to be used in hot paths 488 */ 489 struct bcmgenet_hw_params { 490 u8 tx_queues; 491 u8 tx_bds_per_q; 492 u8 rx_queues; 493 u8 rx_bds_per_q; 494 u8 bp_in_en_shift; 495 u32 bp_in_mask; 496 u8 hfb_filter_cnt; 497 u8 hfb_filter_size; 498 u8 qtag_mask; 499 u16 tbuf_offset; 500 u32 hfb_offset; 501 u32 hfb_reg_offset; 502 u32 rdma_offset; 503 u32 tdma_offset; 504 u32 words_per_bd; 505 }; 506 507 struct bcmgenet_skb_cb { 508 struct enet_cb *first_cb; /* First control block of SKB */ 509 struct enet_cb *last_cb; /* Last control block of SKB */ 510 unsigned int bytes_sent; /* bytes on the wire (no TSB) */ 511 }; 512 513 #define GENET_CB(skb) ((struct bcmgenet_skb_cb *)((skb)->cb)) 514 515 struct bcmgenet_tx_ring { 516 spinlock_t lock; /* ring lock */ 517 struct napi_struct napi; /* NAPI per tx queue */ 518 unsigned long packets; 519 unsigned long bytes; 520 unsigned int index; /* ring index */ 521 struct enet_cb *cbs; /* tx ring buffer control block*/ 522 unsigned int size; /* size of each tx ring */ 523 unsigned int clean_ptr; /* Tx ring clean pointer */ 524 unsigned int c_index; /* last consumer index of each ring*/ 525 unsigned int free_bds; /* # of free bds for each ring */ 526 unsigned int write_ptr; /* Tx ring write pointer SW copy */ 527 unsigned int prod_index; /* Tx ring producer index SW copy */ 528 unsigned int cb_ptr; /* Tx ring initial CB ptr */ 529 unsigned int end_ptr; /* Tx ring end CB ptr */ 530 struct bcmgenet_priv *priv; 531 }; 532 533 struct bcmgenet_net_dim { 534 u16 use_dim; 535 u16 event_ctr; 536 unsigned long packets; 537 unsigned long bytes; 538 struct dim dim; 539 }; 540 541 struct bcmgenet_rx_ring { 542 struct napi_struct napi; /* Rx NAPI struct */ 543 unsigned long bytes; 544 unsigned long packets; 545 unsigned long errors; 546 unsigned long dropped; 547 unsigned int index; /* Rx ring index */ 548 struct enet_cb *cbs; /* Rx ring buffer control block */ 549 unsigned int size; /* Rx ring size */ 550 unsigned int c_index; /* Rx last consumer index */ 551 unsigned int read_ptr; /* Rx ring read pointer */ 552 unsigned int cb_ptr; /* Rx ring initial CB ptr */ 553 unsigned int end_ptr; /* Rx ring end CB ptr */ 554 unsigned int old_discards; 555 struct bcmgenet_net_dim dim; 556 u32 rx_max_coalesced_frames; 557 u32 rx_coalesce_usecs; 558 struct bcmgenet_priv *priv; 559 }; 560 561 enum bcmgenet_rxnfc_state { 562 BCMGENET_RXNFC_STATE_UNUSED = 0, 563 BCMGENET_RXNFC_STATE_DISABLED, 564 BCMGENET_RXNFC_STATE_ENABLED 565 }; 566 567 struct bcmgenet_rxnfc_rule { 568 struct list_head list; 569 struct ethtool_rx_flow_spec fs; 570 enum bcmgenet_rxnfc_state state; 571 }; 572 573 /* device context */ 574 struct bcmgenet_priv { 575 void __iomem *base; 576 /* reg_lock: lock to serialize access to shared registers */ 577 spinlock_t reg_lock; 578 enum bcmgenet_version version; 579 struct net_device *dev; 580 581 /* transmit variables */ 582 void __iomem *tx_bds; 583 struct enet_cb *tx_cbs; 584 unsigned int num_tx_bds; 585 586 struct bcmgenet_tx_ring tx_rings[GENET_MAX_MQ_CNT + 1]; 587 588 /* receive variables */ 589 void __iomem *rx_bds; 590 struct enet_cb *rx_cbs; 591 unsigned int num_rx_bds; 592 unsigned int rx_buf_len; 593 struct bcmgenet_rxnfc_rule rxnfc_rules[MAX_NUM_OF_FS_RULES]; 594 struct list_head rxnfc_list; 595 596 struct bcmgenet_rx_ring rx_rings[GENET_MAX_MQ_CNT + 1]; 597 598 /* other misc variables */ 599 const struct bcmgenet_hw_params *hw_params; 600 u32 flags; 601 unsigned autoneg_pause:1; 602 unsigned tx_pause:1; 603 unsigned rx_pause:1; 604 605 /* MDIO bus variables */ 606 wait_queue_head_t wq; 607 bool internal_phy; 608 struct device_node *phy_dn; 609 struct device_node *mdio_dn; 610 struct mii_bus *mii_bus; 611 u16 gphy_rev; 612 struct clk *clk_eee; 613 bool clk_eee_enabled; 614 615 /* PHY device variables */ 616 phy_interface_t phy_interface; 617 int phy_addr; 618 int ext_phy; 619 620 /* Interrupt variables */ 621 struct work_struct bcmgenet_irq_work; 622 int irq0; 623 int irq1; 624 int wol_irq; 625 bool wol_irq_disabled; 626 627 /* shared status */ 628 spinlock_t lock; 629 unsigned int irq0_stat; 630 631 /* HW descriptors/checksum variables */ 632 bool crc_fwd_en; 633 634 u32 dma_max_burst_length; 635 636 u32 msg_enable; 637 638 struct clk *clk; 639 struct platform_device *pdev; 640 struct platform_device *mii_pdev; 641 642 /* WOL */ 643 struct clk *clk_wol; 644 u32 wolopts; 645 u8 sopass[SOPASS_MAX]; 646 647 struct bcmgenet_mib_counters mib; 648 649 struct ethtool_keee eee; 650 }; 651 652 static inline bool bcmgenet_has_40bits(struct bcmgenet_priv *priv) 653 { 654 return !!(priv->flags & GENET_HAS_40BITS); 655 } 656 657 static inline bool bcmgenet_has_ext(struct bcmgenet_priv *priv) 658 { 659 return !!(priv->flags & GENET_HAS_EXT); 660 } 661 662 static inline bool bcmgenet_has_mdio_intr(struct bcmgenet_priv *priv) 663 { 664 return !!(priv->flags & GENET_HAS_MDIO_INTR); 665 } 666 667 static inline bool bcmgenet_has_moca_link_det(struct bcmgenet_priv *priv) 668 { 669 return !!(priv->flags & GENET_HAS_MOCA_LINK_DET); 670 } 671 672 static inline bool bcmgenet_has_ephy_16nm(struct bcmgenet_priv *priv) 673 { 674 return !!(priv->flags & GENET_HAS_EPHY_16NM); 675 } 676 677 #define GENET_IO_MACRO(name, offset) \ 678 static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv, \ 679 u32 off) \ 680 { \ 681 /* MIPS chips strapped for BE will automagically configure the \ 682 * peripheral registers for CPU-native byte order. \ 683 */ \ 684 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \ 685 return __raw_readl(priv->base + offset + off); \ 686 else \ 687 return readl_relaxed(priv->base + offset + off); \ 688 } \ 689 static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv, \ 690 u32 val, u32 off) \ 691 { \ 692 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \ 693 __raw_writel(val, priv->base + offset + off); \ 694 else \ 695 writel_relaxed(val, priv->base + offset + off); \ 696 } 697 698 GENET_IO_MACRO(ext, GENET_EXT_OFF); 699 GENET_IO_MACRO(umac, GENET_UMAC_OFF); 700 GENET_IO_MACRO(sys, GENET_SYS_OFF); 701 702 /* interrupt l2 registers accessors */ 703 GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF); 704 GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF); 705 706 /* HFB register accessors */ 707 GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset); 708 709 /* GENET v2+ HFB control and filter len helpers */ 710 GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset); 711 712 /* RBUF register accessors */ 713 GENET_IO_MACRO(rbuf, GENET_RBUF_OFF); 714 715 /* MDIO routines */ 716 int bcmgenet_mii_init(struct net_device *dev); 717 int bcmgenet_mii_config(struct net_device *dev, bool init); 718 int bcmgenet_mii_probe(struct net_device *dev); 719 void bcmgenet_mii_exit(struct net_device *dev); 720 void bcmgenet_phy_pause_set(struct net_device *dev, bool rx, bool tx); 721 void bcmgenet_phy_power_set(struct net_device *dev, bool enable); 722 void bcmgenet_mii_setup(struct net_device *dev); 723 724 /* Wake-on-LAN routines */ 725 void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol); 726 int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol); 727 int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv, 728 enum bcmgenet_power_mode mode); 729 int bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv, 730 enum bcmgenet_power_mode mode); 731 732 void bcmgenet_eee_enable_set(struct net_device *dev, bool enable, 733 bool tx_lpi_enabled); 734 735 #endif /* __BCMGENET_H__ */ 736