1e6ad7673SIyappan Subramanian /* Applied Micro X-Gene SoC Ethernet Driver 2e6ad7673SIyappan Subramanian * 3e6ad7673SIyappan Subramanian * Copyright (c) 2014, Applied Micro Circuits Corporation 4e6ad7673SIyappan Subramanian * Authors: Iyappan Subramanian <isubramanian@apm.com> 5e6ad7673SIyappan Subramanian * Ravi Patel <rapatel@apm.com> 6e6ad7673SIyappan Subramanian * Keyur Chudgar <kchudgar@apm.com> 7e6ad7673SIyappan Subramanian * 8e6ad7673SIyappan Subramanian * This program is free software; you can redistribute it and/or modify it 9e6ad7673SIyappan Subramanian * under the terms of the GNU General Public License as published by the 10e6ad7673SIyappan Subramanian * Free Software Foundation; either version 2 of the License, or (at your 11e6ad7673SIyappan Subramanian * option) any later version. 12e6ad7673SIyappan Subramanian * 13e6ad7673SIyappan Subramanian * This program is distributed in the hope that it will be useful, 14e6ad7673SIyappan Subramanian * but WITHOUT ANY WARRANTY; without even the implied warranty of 15e6ad7673SIyappan Subramanian * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16e6ad7673SIyappan Subramanian * GNU General Public License for more details. 17e6ad7673SIyappan Subramanian * 18e6ad7673SIyappan Subramanian * You should have received a copy of the GNU General Public License 19e6ad7673SIyappan Subramanian * along with this program. If not, see <http://www.gnu.org/licenses/>. 20e6ad7673SIyappan Subramanian */ 21e6ad7673SIyappan Subramanian 22e6ad7673SIyappan Subramanian #ifndef __XGENE_ENET_HW_H__ 23e6ad7673SIyappan Subramanian #define __XGENE_ENET_HW_H__ 24e6ad7673SIyappan Subramanian 25e6ad7673SIyappan Subramanian #include "xgene_enet_main.h" 26e6ad7673SIyappan Subramanian 27e6ad7673SIyappan Subramanian struct xgene_enet_pdata; 28e6ad7673SIyappan Subramanian struct xgene_enet_stats; 2981cefb81SIyappan Subramanian struct xgene_enet_desc_ring; 30e6ad7673SIyappan Subramanian 31e6ad7673SIyappan Subramanian /* clears and then set bits */ 32e6ad7673SIyappan Subramanian static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len) 33e6ad7673SIyappan Subramanian { 34e6ad7673SIyappan Subramanian u32 end = start + len - 1; 35e6ad7673SIyappan Subramanian u32 mask = GENMASK(end, start); 36e6ad7673SIyappan Subramanian 37e6ad7673SIyappan Subramanian *dst &= ~mask; 38e6ad7673SIyappan Subramanian *dst |= (val << start) & mask; 39e6ad7673SIyappan Subramanian } 40e6ad7673SIyappan Subramanian 41e6ad7673SIyappan Subramanian static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) 42e6ad7673SIyappan Subramanian { 43e6ad7673SIyappan Subramanian return (val & GENMASK(end, start)) >> start; 44e6ad7673SIyappan Subramanian } 45e6ad7673SIyappan Subramanian 460148d38dSIyappan Subramanian enum xgene_enet_rm { 470148d38dSIyappan Subramanian RM0, 4832f784b5SIyappan Subramanian RM1, 490148d38dSIyappan Subramanian RM3 = 3 500148d38dSIyappan Subramanian }; 510148d38dSIyappan Subramanian 52e6ad7673SIyappan Subramanian #define CSR_RING_ID 0x0008 53e6ad7673SIyappan Subramanian #define OVERWRITE BIT(31) 54e6ad7673SIyappan Subramanian #define IS_BUFFER_POOL BIT(20) 55e6ad7673SIyappan Subramanian #define PREFETCH_BUF_EN BIT(21) 56e6ad7673SIyappan Subramanian #define CSR_RING_ID_BUF 0x000c 57107dec27SIyappan Subramanian #define CSR_PBM_COAL 0x0014 58f126df85SIyappan Subramanian #define CSR_PBM_CTICK0 0x0018 59107dec27SIyappan Subramanian #define CSR_PBM_CTICK1 0x001c 60107dec27SIyappan Subramanian #define CSR_PBM_CTICK2 0x0020 61f126df85SIyappan Subramanian #define CSR_PBM_CTICK3 0x0024 62107dec27SIyappan Subramanian #define CSR_THRESHOLD0_SET1 0x0030 63107dec27SIyappan Subramanian #define CSR_THRESHOLD1_SET1 0x0034 64e6ad7673SIyappan Subramanian #define CSR_RING_NE_INT_MODE 0x017c 65e6ad7673SIyappan Subramanian #define CSR_RING_CONFIG 0x006c 66e6ad7673SIyappan Subramanian #define CSR_RING_WR_BASE 0x0070 67e6ad7673SIyappan Subramanian #define NUM_RING_CONFIG 5 68e6ad7673SIyappan Subramanian #define BUFPOOL_MODE 3 69e6ad7673SIyappan Subramanian #define INC_DEC_CMD_ADDR 0x002c 70e6ad7673SIyappan Subramanian #define UDP_HDR_SIZE 2 71e6ad7673SIyappan Subramanian #define BUF_LEN_CODE_2K 0x5000 72e6ad7673SIyappan Subramanian 73e6ad7673SIyappan Subramanian #define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos)) 74e6ad7673SIyappan Subramanian #define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos)) 75e6ad7673SIyappan Subramanian 76e6ad7673SIyappan Subramanian /* Empty slot soft signature */ 77e6ad7673SIyappan Subramanian #define EMPTY_SLOT_INDEX 1 78e6ad7673SIyappan Subramanian #define EMPTY_SLOT ~0ULL 79e6ad7673SIyappan Subramanian 80e6ad7673SIyappan Subramanian #define WORK_DESC_SIZE 32 81e6ad7673SIyappan Subramanian #define BUFPOOL_DESC_SIZE 16 82e6ad7673SIyappan Subramanian 83e6ad7673SIyappan Subramanian #define RING_OWNER_MASK GENMASK(9, 6) 84e6ad7673SIyappan Subramanian #define RING_BUFNUM_MASK GENMASK(5, 0) 85e6ad7673SIyappan Subramanian 86e6ad7673SIyappan Subramanian #define SELTHRSH_POS 3 87e6ad7673SIyappan Subramanian #define SELTHRSH_LEN 3 88e6ad7673SIyappan Subramanian #define RINGADDRL_POS 5 89e6ad7673SIyappan Subramanian #define RINGADDRL_LEN 27 90e6ad7673SIyappan Subramanian #define RINGADDRH_POS 0 91e2f2d9a7SIyappan Subramanian #define RINGADDRH_LEN 7 92e6ad7673SIyappan Subramanian #define RINGSIZE_POS 23 93e6ad7673SIyappan Subramanian #define RINGSIZE_LEN 3 94e6ad7673SIyappan Subramanian #define RINGTYPE_POS 19 95e6ad7673SIyappan Subramanian #define RINGTYPE_LEN 2 96e6ad7673SIyappan Subramanian #define RINGMODE_POS 20 97e6ad7673SIyappan Subramanian #define RINGMODE_LEN 3 98e6ad7673SIyappan Subramanian #define RECOMTIMEOUTL_POS 28 99e2f2d9a7SIyappan Subramanian #define RECOMTIMEOUTL_LEN 4 100e6ad7673SIyappan Subramanian #define RECOMTIMEOUTH_POS 0 101e2f2d9a7SIyappan Subramanian #define RECOMTIMEOUTH_LEN 3 102e6ad7673SIyappan Subramanian #define NUMMSGSINQ_POS 1 103e6ad7673SIyappan Subramanian #define NUMMSGSINQ_LEN 16 104e6ad7673SIyappan Subramanian #define ACCEPTLERR BIT(19) 105e6ad7673SIyappan Subramanian #define QCOHERENT BIT(4) 106e6ad7673SIyappan Subramanian #define RECOMBBUF BIT(27) 107e6ad7673SIyappan Subramanian 108ca626454SKeyur Chudgar #define MAC_OFFSET 0x30 1099a8c5ddeSIyappan Subramanian #define OFFSET_4 0x04 1109a8c5ddeSIyappan Subramanian #define OFFSET_8 0x08 111ca626454SKeyur Chudgar 112e6ad7673SIyappan Subramanian #define BLOCK_ETH_CSR_OFFSET 0x2000 11376f94a9cSIyappan Subramanian #define BLOCK_ETH_CLE_CSR_OFFSET 0x6000 114e6ad7673SIyappan Subramanian #define BLOCK_ETH_RING_IF_OFFSET 0x9000 115bc1b7c13SIyappan Subramanian #define BLOCK_ETH_CLKRST_CSR_OFFSET 0xc000 116e6ad7673SIyappan Subramanian #define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000 117e6ad7673SIyappan Subramanian #define BLOCK_ETH_MAC_OFFSET 0x0000 1182d07d8e4SQuan Nguyen #define BLOCK_ETH_STATS_OFFSET 0x0000 119e6ad7673SIyappan Subramanian #define BLOCK_ETH_MAC_CSR_OFFSET 0x2800 120e6ad7673SIyappan Subramanian 121c3f4465dSIyappan Subramanian #define CLKEN_ADDR 0xc208 122c3f4465dSIyappan Subramanian #define SRST_ADDR 0xc200 123c3f4465dSIyappan Subramanian 124e6ad7673SIyappan Subramanian #define MAC_ADDR_REG_OFFSET 0x00 125e6ad7673SIyappan Subramanian #define MAC_COMMAND_REG_OFFSET 0x04 126e6ad7673SIyappan Subramanian #define MAC_WRITE_REG_OFFSET 0x08 127e6ad7673SIyappan Subramanian #define MAC_READ_REG_OFFSET 0x0c 128e6ad7673SIyappan Subramanian #define MAC_COMMAND_DONE_REG_OFFSET 0x10 129e6ad7673SIyappan Subramanian 1302d07d8e4SQuan Nguyen #define STAT_ADDR_REG_OFFSET 0x14 1312d07d8e4SQuan Nguyen #define STAT_COMMAND_REG_OFFSET 0x18 1322d07d8e4SQuan Nguyen #define STAT_WRITE_REG_OFFSET 0x1c 1332d07d8e4SQuan Nguyen #define STAT_READ_REG_OFFSET 0x20 1342d07d8e4SQuan Nguyen #define STAT_COMMAND_DONE_REG_OFFSET 0x24 1352d07d8e4SQuan Nguyen 1363eb7cb9dSIyappan Subramanian #define PCS_ADDR_REG_OFFSET 0x00 1373eb7cb9dSIyappan Subramanian #define PCS_COMMAND_REG_OFFSET 0x04 1383eb7cb9dSIyappan Subramanian #define PCS_WRITE_REG_OFFSET 0x08 1393eb7cb9dSIyappan Subramanian #define PCS_READ_REG_OFFSET 0x0c 1403eb7cb9dSIyappan Subramanian #define PCS_COMMAND_DONE_REG_OFFSET 0x10 1413eb7cb9dSIyappan Subramanian 142e6ad7673SIyappan Subramanian #define MII_MGMT_CONFIG_ADDR 0x20 143e6ad7673SIyappan Subramanian #define MII_MGMT_COMMAND_ADDR 0x24 144e6ad7673SIyappan Subramanian #define MII_MGMT_ADDRESS_ADDR 0x28 145e6ad7673SIyappan Subramanian #define MII_MGMT_CONTROL_ADDR 0x2c 146e6ad7673SIyappan Subramanian #define MII_MGMT_STATUS_ADDR 0x30 147e6ad7673SIyappan Subramanian #define MII_MGMT_INDICATORS_ADDR 0x34 148e6ad7673SIyappan Subramanian 149e6ad7673SIyappan Subramanian #define BUSY_MASK BIT(0) 150e6ad7673SIyappan Subramanian #define READ_CYCLE_MASK BIT(0) 151e6ad7673SIyappan Subramanian #define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16) 152e6ad7673SIyappan Subramanian 153e6ad7673SIyappan Subramanian #define ENET_SPARE_CFG_REG_ADDR 0x0750 154e6ad7673SIyappan Subramanian #define RSIF_CONFIG_REG_ADDR 0x0010 155e6ad7673SIyappan Subramanian #define RSIF_RAM_DBG_REG0_ADDR 0x0048 156e6ad7673SIyappan Subramanian #define RGMII_REG_0_ADDR 0x07e0 157e6ad7673SIyappan Subramanian #define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8 158e6ad7673SIyappan Subramanian #define DEBUG_REG_ADDR 0x0700 159e6ad7673SIyappan Subramanian #define CFG_BYPASS_ADDR 0x0294 160e6ad7673SIyappan Subramanian #define CLE_BYPASS_REG0_0_ADDR 0x0490 161e6ad7673SIyappan Subramanian #define CLE_BYPASS_REG1_0_ADDR 0x0494 162e6ad7673SIyappan Subramanian #define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31) 163e6ad7673SIyappan Subramanian #define RESUME_TX BIT(0) 164e6ad7673SIyappan Subramanian #define CFG_SPEED_1250 BIT(24) 165e6ad7673SIyappan Subramanian #define TX_PORT0 BIT(0) 166e6ad7673SIyappan Subramanian #define CFG_BYPASS_UNISEC_TX BIT(2) 167e6ad7673SIyappan Subramanian #define CFG_BYPASS_UNISEC_RX BIT(1) 168e6ad7673SIyappan Subramanian #define CFG_CLE_BYPASS_EN0 BIT(31) 169e6ad7673SIyappan Subramanian #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3) 17016615a4cSIyappan Subramanian #define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3) 171e6ad7673SIyappan Subramanian 172e6ad7673SIyappan Subramanian #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2) 173e026e700SQuan Nguyen #define CFG_CLE_IP_HDR_LEN_SET(dst, val) xgene_set_bits(dst, val, 8, 5) 174e6ad7673SIyappan Subramanian #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12) 175e6ad7673SIyappan Subramanian #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4) 176d6d48969SIyappan Subramanian #define CFG_CLE_NXTFPSEL0_SET(dst, val) xgene_set_bits(dst, val, 20, 4) 177e6ad7673SIyappan Subramanian #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2) 178e6ad7673SIyappan Subramanian #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16) 179d6d48969SIyappan Subramanian #define CFG_CLE_DSTQID0(val) ((val) & GENMASK(11, 0)) 180d6d48969SIyappan Subramanian #define CFG_CLE_FPSEL0(val) (((val) << 16) & GENMASK(19, 16)) 181bb64fa09SIyappan Subramanian #define CSR_ECM_CFG_0_ADDR 0x0220 182bb64fa09SIyappan Subramanian #define CSR_ECM_CFG_1_ADDR 0x0224 18356090b12SIyappan Subramanian #define CSR_MULTI_DPF0_ADDR 0x0230 18456090b12SIyappan Subramanian #define RXBUF_PAUSE_THRESH 0x0534 18556090b12SIyappan Subramanian #define RXBUF_PAUSE_OFF_THRESH 0x0540 18656090b12SIyappan Subramanian #define DEF_PAUSE_THRES 0x7d 18756090b12SIyappan Subramanian #define DEF_PAUSE_OFF_THRES 0x6d 18856090b12SIyappan Subramanian #define DEF_QUANTA 0x8000 18956090b12SIyappan Subramanian #define NORM_PAUSE_OPCODE 0x0001 190bb64fa09SIyappan Subramanian #define PAUSE_XON_EN BIT(30) 191bb64fa09SIyappan Subramanian #define MULTI_DPF_AUTOCTRL BIT(28) 192d6d48969SIyappan Subramanian #define CFG_CLE_NXTFPSEL0(val) (((val) << 20) & GENMASK(23, 20)) 193e6ad7673SIyappan Subramanian #define ICM_CONFIG0_REG_0_ADDR 0x0400 194e6ad7673SIyappan Subramanian #define ICM_CONFIG2_REG_0_ADDR 0x0410 195*ca6d550cSIyappan Subramanian #define ECM_CONFIG0_REG_0_ADDR 0x0500 196*ca6d550cSIyappan Subramanian #define ECM_CONFIG0_REG_1_ADDR 0x0504 197*ca6d550cSIyappan Subramanian #define ICM_ECM_DROP_COUNT_REG0_ADDR 0x0508 198*ca6d550cSIyappan Subramanian #define ICM_ECM_DROP_COUNT_REG1_ADDR 0x050c 199e6ad7673SIyappan Subramanian #define RX_DV_GATE_REG_0_ADDR 0x05fc 200e6ad7673SIyappan Subramanian #define TX_DV_GATE_EN0 BIT(2) 201e6ad7673SIyappan Subramanian #define RX_DV_GATE_EN0 BIT(1) 202e6ad7673SIyappan Subramanian #define RESUME_RX0 BIT(0) 203cb11c062SIyappan Subramanian #define ENET_CFGSSQMIFPRESET_ADDR 0x14 204cb11c062SIyappan Subramanian #define ENET_CFGSSQMIWQRESET_ADDR 0x1c 205e6ad7673SIyappan Subramanian #define ENET_CFGSSQMIWQASSOC_ADDR 0xe0 206e6ad7673SIyappan Subramanian #define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc 207e6ad7673SIyappan Subramanian #define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0 208e6ad7673SIyappan Subramanian #define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4 209e6ad7673SIyappan Subramanian #define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70 210e6ad7673SIyappan Subramanian #define ENET_BLOCK_MEM_RDY_ADDR 0x74 211e6ad7673SIyappan Subramanian #define MAC_CONFIG_1_ADDR 0x00 212e6ad7673SIyappan Subramanian #define MAC_CONFIG_2_ADDR 0x04 213e6ad7673SIyappan Subramanian #define MAX_FRAME_LEN_ADDR 0x10 214e6ad7673SIyappan Subramanian #define INTERFACE_CONTROL_ADDR 0x38 215e6ad7673SIyappan Subramanian #define STATION_ADDR0_ADDR 0x40 216e6ad7673SIyappan Subramanian #define STATION_ADDR1_ADDR 0x44 217e6ad7673SIyappan Subramanian #define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5) 218e6ad7673SIyappan Subramanian #define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5) 219e6ad7673SIyappan Subramanian #define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2) 220e6ad7673SIyappan Subramanian #define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3) 221e6ad7673SIyappan Subramanian #define SOFT_RESET1 BIT(31) 222e6ad7673SIyappan Subramanian #define TX_EN BIT(0) 223e6ad7673SIyappan Subramanian #define RX_EN BIT(2) 224bb64fa09SIyappan Subramanian #define TX_FLOW_EN BIT(4) 225bb64fa09SIyappan Subramanian #define RX_FLOW_EN BIT(5) 226e6ad7673SIyappan Subramanian #define ENET_LHD_MODE BIT(25) 227e6ad7673SIyappan Subramanian #define ENET_GHD_MODE BIT(26) 228e6ad7673SIyappan Subramanian #define FULL_DUPLEX2 BIT(0) 229761d4be5SIyappan Subramanian #define PAD_CRC BIT(2) 2304902a922SIyappan Subramanian #define LENGTH_CHK BIT(4) 231e6ad7673SIyappan Subramanian 2322d07d8e4SQuan Nguyen #define TR64_ADDR 0x20 2332d07d8e4SQuan Nguyen #define TR127_ADDR 0x21 2342d07d8e4SQuan Nguyen #define TR255_ADDR 0x22 2352d07d8e4SQuan Nguyen #define TR511_ADDR 0x23 2362d07d8e4SQuan Nguyen #define TR1K_ADDR 0x24 2372d07d8e4SQuan Nguyen #define TRMAX_ADDR 0x25 2382d07d8e4SQuan Nguyen #define TRMGV_ADDR 0x26 2392d07d8e4SQuan Nguyen 2402d07d8e4SQuan Nguyen #define RFCS_ADDR 0x29 2412d07d8e4SQuan Nguyen #define RMCA_ADDR 0x2a 2422d07d8e4SQuan Nguyen #define RBCA_ADDR 0x2b 2432d07d8e4SQuan Nguyen #define RXCF_ADDR 0x2c 2442d07d8e4SQuan Nguyen #define RXPF_ADDR 0x2d 2452d07d8e4SQuan Nguyen #define RXUO_ADDR 0x2e 2462d07d8e4SQuan Nguyen #define RALN_ADDR 0x2f 2472d07d8e4SQuan Nguyen #define RFLR_ADDR 0x30 2482d07d8e4SQuan Nguyen #define RCDE_ADDR 0x31 2492d07d8e4SQuan Nguyen #define RCSE_ADDR 0x32 2502d07d8e4SQuan Nguyen #define RUND_ADDR 0x33 2512d07d8e4SQuan Nguyen #define ROVR_ADDR 0x34 2522d07d8e4SQuan Nguyen #define RFRG_ADDR 0x35 2532d07d8e4SQuan Nguyen #define RJBR_ADDR 0x36 2542d07d8e4SQuan Nguyen #define RDRP_ADDR 0x37 2552d07d8e4SQuan Nguyen 2562d07d8e4SQuan Nguyen #define TMCA_ADDR 0x3a 2572d07d8e4SQuan Nguyen #define TBCA_ADDR 0x3b 2582d07d8e4SQuan Nguyen #define TXPF_ADDR 0x3c 2592d07d8e4SQuan Nguyen #define TDFR_ADDR 0x3d 2602d07d8e4SQuan Nguyen #define TEDF_ADDR 0x3e 2612d07d8e4SQuan Nguyen #define TSCL_ADDR 0x3f 2622d07d8e4SQuan Nguyen #define TMCL_ADDR 0x40 2632d07d8e4SQuan Nguyen #define TLCL_ADDR 0x41 2642d07d8e4SQuan Nguyen #define TXCL_ADDR 0x42 2652d07d8e4SQuan Nguyen #define TNCL_ADDR 0x43 2662d07d8e4SQuan Nguyen #define TPFH_ADDR 0x44 2672d07d8e4SQuan Nguyen #define TDRP_ADDR 0x45 2682d07d8e4SQuan Nguyen #define TJBR_ADDR 0x46 2692d07d8e4SQuan Nguyen #define TFCS_ADDR 0x47 2702d07d8e4SQuan Nguyen #define TXCF_ADDR 0x48 2712d07d8e4SQuan Nguyen #define TOVR_ADDR 0x49 2722d07d8e4SQuan Nguyen #define TUND_ADDR 0x4a 2732d07d8e4SQuan Nguyen #define TFRG_ADDR 0x4b 274*ca6d550cSIyappan Subramanian #define DUMP_ADDR 0x27 275*ca6d550cSIyappan Subramanian 276*ca6d550cSIyappan Subramanian #define ECM_DROP_COUNT(src) xgene_get_bits(src, 0, 15) 277*ca6d550cSIyappan Subramanian #define ICM_DROP_COUNT(src) xgene_get_bits(src, 16, 31) 2782d07d8e4SQuan Nguyen 279e6ad7673SIyappan Subramanian #define TSO_IPPROTO_TCP 1 280e6ad7673SIyappan Subramanian 281e6ad7673SIyappan Subramanian #define USERINFO_POS 0 282e6ad7673SIyappan Subramanian #define USERINFO_LEN 32 283e6ad7673SIyappan Subramanian #define FPQNUM_POS 32 284e6ad7673SIyappan Subramanian #define FPQNUM_LEN 12 2853bb502f8SIyappan Subramanian #define ELERR_POS 46 2863bb502f8SIyappan Subramanian #define ELERR_LEN 2 2879b00eb49SIyappan Subramanian #define NV_POS 50 2889b00eb49SIyappan Subramanian #define NV_LEN 1 2899b00eb49SIyappan Subramanian #define LL_POS 51 2909b00eb49SIyappan Subramanian #define LL_LEN 1 291e6ad7673SIyappan Subramanian #define LERR_POS 60 292e6ad7673SIyappan Subramanian #define LERR_LEN 3 293e6ad7673SIyappan Subramanian #define STASH_POS 52 294e6ad7673SIyappan Subramanian #define STASH_LEN 2 295e6ad7673SIyappan Subramanian #define BUFDATALEN_POS 48 2969b00eb49SIyappan Subramanian #define BUFDATALEN_LEN 15 297e6ad7673SIyappan Subramanian #define DATAADDR_POS 0 298e6ad7673SIyappan Subramanian #define DATAADDR_LEN 42 299e6ad7673SIyappan Subramanian #define COHERENT_POS 63 300e6ad7673SIyappan Subramanian #define HENQNUM_POS 48 301e6ad7673SIyappan Subramanian #define HENQNUM_LEN 12 302e6ad7673SIyappan Subramanian #define TYPESEL_POS 44 303e6ad7673SIyappan Subramanian #define TYPESEL_LEN 4 304e6ad7673SIyappan Subramanian #define ETHHDR_POS 12 305e6ad7673SIyappan Subramanian #define ETHHDR_LEN 8 306e6ad7673SIyappan Subramanian #define IC_POS 35 /* Insert CRC */ 307e6ad7673SIyappan Subramanian #define TCPHDR_POS 0 308e6ad7673SIyappan Subramanian #define TCPHDR_LEN 6 309e6ad7673SIyappan Subramanian #define IPHDR_POS 6 310e6ad7673SIyappan Subramanian #define IPHDR_LEN 6 311e3978673SIyappan Subramanian #define MSS_POS 20 312e3978673SIyappan Subramanian #define MSS_LEN 2 313e6ad7673SIyappan Subramanian #define EC_POS 22 /* Enable checksum */ 314e6ad7673SIyappan Subramanian #define EC_LEN 1 3159b00eb49SIyappan Subramanian #define ET_POS 23 /* Enable TSO */ 316e6ad7673SIyappan Subramanian #define IS_POS 24 /* IP protocol select */ 317e6ad7673SIyappan Subramanian #define IS_LEN 1 318e6ad7673SIyappan Subramanian #define TYPE_ETH_WORK_MESSAGE_POS 44 3199b00eb49SIyappan Subramanian #define LL_BYTES_MSB_POS 56 3209b00eb49SIyappan Subramanian #define LL_BYTES_MSB_LEN 8 3219b00eb49SIyappan Subramanian #define LL_BYTES_LSB_POS 48 3229b00eb49SIyappan Subramanian #define LL_BYTES_LSB_LEN 12 3239b00eb49SIyappan Subramanian #define LL_LEN_POS 48 3249b00eb49SIyappan Subramanian #define LL_LEN_LEN 8 3259b00eb49SIyappan Subramanian #define DATALEN_MASK GENMASK(11, 0) 3269b00eb49SIyappan Subramanian 3279b00eb49SIyappan Subramanian #define LAST_BUFFER (0x7800ULL << BUFDATALEN_POS) 328e6ad7673SIyappan Subramanian 329e3978673SIyappan Subramanian #define TSO_MSS0_POS 0 330e3978673SIyappan Subramanian #define TSO_MSS0_LEN 14 331e3978673SIyappan Subramanian #define TSO_MSS1_POS 16 332e3978673SIyappan Subramanian #define TSO_MSS1_LEN 14 333e3978673SIyappan Subramanian 334e6ad7673SIyappan Subramanian struct xgene_enet_raw_desc { 335e6ad7673SIyappan Subramanian __le64 m0; 336e6ad7673SIyappan Subramanian __le64 m1; 337e6ad7673SIyappan Subramanian __le64 m2; 338e6ad7673SIyappan Subramanian __le64 m3; 339e6ad7673SIyappan Subramanian }; 340e6ad7673SIyappan Subramanian 341e6ad7673SIyappan Subramanian struct xgene_enet_raw_desc16 { 342e6ad7673SIyappan Subramanian __le64 m0; 343e6ad7673SIyappan Subramanian __le64 m1; 344e6ad7673SIyappan Subramanian }; 345e6ad7673SIyappan Subramanian 346e6ad7673SIyappan Subramanian static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr) 347e6ad7673SIyappan Subramanian { 348e6ad7673SIyappan Subramanian __le64 *desc_slot = desc_slot_ptr; 349e6ad7673SIyappan Subramanian 350e6ad7673SIyappan Subramanian desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT); 351e6ad7673SIyappan Subramanian } 352e6ad7673SIyappan Subramanian 353e6ad7673SIyappan Subramanian static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr) 354e6ad7673SIyappan Subramanian { 355e6ad7673SIyappan Subramanian __le64 *desc_slot = desc_slot_ptr; 356e6ad7673SIyappan Subramanian 357e6ad7673SIyappan Subramanian return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT)); 358e6ad7673SIyappan Subramanian } 359e6ad7673SIyappan Subramanian 360e6ad7673SIyappan Subramanian enum xgene_enet_ring_cfgsize { 361e6ad7673SIyappan Subramanian RING_CFGSIZE_512B, 362e6ad7673SIyappan Subramanian RING_CFGSIZE_2KB, 363e6ad7673SIyappan Subramanian RING_CFGSIZE_16KB, 364e6ad7673SIyappan Subramanian RING_CFGSIZE_64KB, 365e6ad7673SIyappan Subramanian RING_CFGSIZE_512KB, 366e6ad7673SIyappan Subramanian RING_CFGSIZE_INVALID 367e6ad7673SIyappan Subramanian }; 368e6ad7673SIyappan Subramanian 369e6ad7673SIyappan Subramanian enum xgene_enet_ring_type { 370e6ad7673SIyappan Subramanian RING_DISABLED, 371e6ad7673SIyappan Subramanian RING_REGULAR, 372e6ad7673SIyappan Subramanian RING_BUFPOOL 373e6ad7673SIyappan Subramanian }; 374e6ad7673SIyappan Subramanian 375e6ad7673SIyappan Subramanian enum xgene_ring_owner { 376e6ad7673SIyappan Subramanian RING_OWNER_ETH0, 377ed9b7da0SIyappan Subramanian RING_OWNER_ETH1, 378e6ad7673SIyappan Subramanian RING_OWNER_CPU = 15, 379e6ad7673SIyappan Subramanian RING_OWNER_INVALID 380e6ad7673SIyappan Subramanian }; 381e6ad7673SIyappan Subramanian 382e6ad7673SIyappan Subramanian enum xgene_enet_ring_bufnum { 383e6ad7673SIyappan Subramanian RING_BUFNUM_REGULAR = 0x0, 384e6ad7673SIyappan Subramanian RING_BUFNUM_BUFPOOL = 0x20, 385e6ad7673SIyappan Subramanian RING_BUFNUM_INVALID 386e6ad7673SIyappan Subramanian }; 387e6ad7673SIyappan Subramanian 388e6ad7673SIyappan Subramanian enum xgene_enet_err_code { 389e6ad7673SIyappan Subramanian HBF_READ_DATA = 3, 390e6ad7673SIyappan Subramanian HBF_LL_READ = 4, 391e6ad7673SIyappan Subramanian BAD_WORK_MSG = 6, 392e6ad7673SIyappan Subramanian BUFPOOL_TIMEOUT = 15, 393e6ad7673SIyappan Subramanian INGRESS_CRC = 16, 394e6ad7673SIyappan Subramanian INGRESS_CHECKSUM = 17, 395e6ad7673SIyappan Subramanian INGRESS_TRUNC_FRAME = 18, 396e6ad7673SIyappan Subramanian INGRESS_PKT_LEN = 19, 397e6ad7673SIyappan Subramanian INGRESS_PKT_UNDER = 20, 398e6ad7673SIyappan Subramanian INGRESS_FIFO_OVERRUN = 21, 399e6ad7673SIyappan Subramanian INGRESS_CHECKSUM_COMPUTE = 26, 400e6ad7673SIyappan Subramanian ERR_CODE_INVALID 401e6ad7673SIyappan Subramanian }; 402e6ad7673SIyappan Subramanian 403e6ad7673SIyappan Subramanian static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id) 404e6ad7673SIyappan Subramanian { 405e6ad7673SIyappan Subramanian return (id & RING_OWNER_MASK) >> 6; 406e6ad7673SIyappan Subramanian } 407e6ad7673SIyappan Subramanian 408e6ad7673SIyappan Subramanian static inline u8 xgene_enet_ring_bufnum(u16 id) 409e6ad7673SIyappan Subramanian { 410e6ad7673SIyappan Subramanian return id & RING_BUFNUM_MASK; 411e6ad7673SIyappan Subramanian } 412e6ad7673SIyappan Subramanian 413e6ad7673SIyappan Subramanian static inline bool xgene_enet_is_bufpool(u16 id) 414e6ad7673SIyappan Subramanian { 415e6ad7673SIyappan Subramanian return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false; 416e6ad7673SIyappan Subramanian } 417e6ad7673SIyappan Subramanian 4182c839337SIyappan Subramanian static inline u8 xgene_enet_get_fpsel(u16 id) 4192c839337SIyappan Subramanian { 4202c839337SIyappan Subramanian if (xgene_enet_is_bufpool(id)) 4212c839337SIyappan Subramanian return xgene_enet_ring_bufnum(id) - RING_BUFNUM_BUFPOOL; 4222c839337SIyappan Subramanian 4232c839337SIyappan Subramanian return 0; 4242c839337SIyappan Subramanian } 4252c839337SIyappan Subramanian 426e6ad7673SIyappan Subramanian static inline u16 xgene_enet_get_numslots(u16 id, u32 size) 427e6ad7673SIyappan Subramanian { 428e6ad7673SIyappan Subramanian bool is_bufpool = xgene_enet_is_bufpool(id); 429e6ad7673SIyappan Subramanian 430e6ad7673SIyappan Subramanian return (is_bufpool) ? size / BUFPOOL_DESC_SIZE : 431e6ad7673SIyappan Subramanian size / WORK_DESC_SIZE; 432e6ad7673SIyappan Subramanian } 433e6ad7673SIyappan Subramanian 434e6ad7673SIyappan Subramanian void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring, 435e6ad7673SIyappan Subramanian enum xgene_enet_err_code status); 436e6ad7673SIyappan Subramanian int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata); 437e6ad7673SIyappan Subramanian void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata); 438c3f4465dSIyappan Subramanian bool xgene_ring_mgr_init(struct xgene_enet_pdata *p); 4398089a96fSIyappan Subramanian int xgene_enet_phy_connect(struct net_device *ndev); 4408089a96fSIyappan Subramanian void xgene_enet_phy_disconnect(struct xgene_enet_pdata *pdata); 441ae1aed95SIyappan Subramanian u32 xgene_enet_rd_mac(struct xgene_enet_pdata *pdata, u32 rd_addr); 442ae1aed95SIyappan Subramanian void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, u32 wr_addr, 443ae1aed95SIyappan Subramanian u32 wr_data); 4442d07d8e4SQuan Nguyen u32 xgene_enet_rd_stat(struct xgene_enet_pdata *pdata, u32 rd_addr); 445e6ad7673SIyappan Subramanian 4463cdb7309SJulia Lawall extern const struct xgene_mac_ops xgene_gmac_ops; 4473cdb7309SJulia Lawall extern const struct xgene_port_ops xgene_gport_ops; 44881cefb81SIyappan Subramanian extern struct xgene_ring_ops xgene_ring1_ops; 449d0eb7458SIyappan Subramanian 450e6ad7673SIyappan Subramanian #endif /* __XGENE_ENET_HW_H__ */ 451