1*1ccea77eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
2384fe7a4SIyappan Subramanian /*
3384fe7a4SIyappan Subramanian * Applied Micro X-Gene SoC Ethernet v2 Driver
4384fe7a4SIyappan Subramanian *
5384fe7a4SIyappan Subramanian * Copyright (c) 2017, Applied Micro Circuits Corporation
6384fe7a4SIyappan Subramanian * Author(s): Iyappan Subramanian <isubramanian@apm.com>
7384fe7a4SIyappan Subramanian * Keyur Chudgar <kchudgar@apm.com>
8384fe7a4SIyappan Subramanian */
9384fe7a4SIyappan Subramanian
10384fe7a4SIyappan Subramanian #ifndef __XGENE_ENET_V2_RING_H__
11384fe7a4SIyappan Subramanian #define __XGENE_ENET_V2_RING_H__
12384fe7a4SIyappan Subramanian
13384fe7a4SIyappan Subramanian #define XGENE_ENET_DESC_SIZE 64
14384fe7a4SIyappan Subramanian #define XGENE_ENET_NUM_DESC 256
15384fe7a4SIyappan Subramanian #define NUM_BUFS 8
16384fe7a4SIyappan Subramanian #define SLOT_EMPTY 0xfff
17384fe7a4SIyappan Subramanian
18384fe7a4SIyappan Subramanian #define DMATXCTRL 0xa180
19384fe7a4SIyappan Subramanian #define DMATXDESCL 0xa184
20384fe7a4SIyappan Subramanian #define DMATXDESCH 0xa1a0
21384fe7a4SIyappan Subramanian #define DMATXSTATUS 0xa188
22384fe7a4SIyappan Subramanian #define DMARXCTRL 0xa18c
23384fe7a4SIyappan Subramanian #define DMARXDESCL 0xa190
24384fe7a4SIyappan Subramanian #define DMARXDESCH 0xa1a4
25384fe7a4SIyappan Subramanian #define DMARXSTATUS 0xa194
26384fe7a4SIyappan Subramanian #define DMAINTRMASK 0xa198
27384fe7a4SIyappan Subramanian #define DMAINTERRUPT 0xa19c
28384fe7a4SIyappan Subramanian
29384fe7a4SIyappan Subramanian #define D_POS 62
30384fe7a4SIyappan Subramanian #define D_LEN 2
31384fe7a4SIyappan Subramanian #define E_POS 63
32384fe7a4SIyappan Subramanian #define E_LEN 1
33384fe7a4SIyappan Subramanian #define PKT_ADDRL_POS 0
34384fe7a4SIyappan Subramanian #define PKT_ADDRL_LEN 32
35384fe7a4SIyappan Subramanian #define PKT_ADDRH_POS 32
36384fe7a4SIyappan Subramanian #define PKT_ADDRH_LEN 10
37384fe7a4SIyappan Subramanian #define PKT_SIZE_POS 32
38384fe7a4SIyappan Subramanian #define PKT_SIZE_LEN 12
39384fe7a4SIyappan Subramanian #define NEXT_DESC_ADDRL_POS 0
40384fe7a4SIyappan Subramanian #define NEXT_DESC_ADDRL_LEN 32
41384fe7a4SIyappan Subramanian #define NEXT_DESC_ADDRH_POS 48
42384fe7a4SIyappan Subramanian #define NEXT_DESC_ADDRH_LEN 10
43384fe7a4SIyappan Subramanian
44384fe7a4SIyappan Subramanian #define TXPKTCOUNT_POS 16
45384fe7a4SIyappan Subramanian #define TXPKTCOUNT_LEN 8
46384fe7a4SIyappan Subramanian #define RXPKTCOUNT_POS 16
47384fe7a4SIyappan Subramanian #define RXPKTCOUNT_LEN 8
48384fe7a4SIyappan Subramanian
49384fe7a4SIyappan Subramanian #define TX_PKT_SENT BIT(0)
50384fe7a4SIyappan Subramanian #define TX_BUS_ERROR BIT(3)
51384fe7a4SIyappan Subramanian #define RX_PKT_RCVD BIT(4)
52384fe7a4SIyappan Subramanian #define RX_BUS_ERROR BIT(7)
53384fe7a4SIyappan Subramanian #define RXSTATUS_RXPKTRCVD BIT(0)
54384fe7a4SIyappan Subramanian
55384fe7a4SIyappan Subramanian struct xge_raw_desc {
56384fe7a4SIyappan Subramanian __le64 m0;
57384fe7a4SIyappan Subramanian __le64 m1;
58384fe7a4SIyappan Subramanian __le64 m2;
59384fe7a4SIyappan Subramanian __le64 m3;
60384fe7a4SIyappan Subramanian __le64 m4;
61384fe7a4SIyappan Subramanian __le64 m5;
62384fe7a4SIyappan Subramanian __le64 m6;
63384fe7a4SIyappan Subramanian __le64 m7;
64384fe7a4SIyappan Subramanian };
65384fe7a4SIyappan Subramanian
66384fe7a4SIyappan Subramanian struct pkt_info {
67384fe7a4SIyappan Subramanian struct sk_buff *skb;
68384fe7a4SIyappan Subramanian dma_addr_t dma_addr;
69384fe7a4SIyappan Subramanian void *pkt_buf;
70384fe7a4SIyappan Subramanian };
71384fe7a4SIyappan Subramanian
72384fe7a4SIyappan Subramanian /* software context of a descriptor ring */
73384fe7a4SIyappan Subramanian struct xge_desc_ring {
74384fe7a4SIyappan Subramanian struct net_device *ndev;
75384fe7a4SIyappan Subramanian dma_addr_t dma_addr;
76384fe7a4SIyappan Subramanian u8 head;
77384fe7a4SIyappan Subramanian u8 tail;
78384fe7a4SIyappan Subramanian union {
79384fe7a4SIyappan Subramanian void *desc_addr;
80384fe7a4SIyappan Subramanian struct xge_raw_desc *raw_desc;
81384fe7a4SIyappan Subramanian };
82384fe7a4SIyappan Subramanian struct pkt_info (*pkt_info);
83384fe7a4SIyappan Subramanian };
84384fe7a4SIyappan Subramanian
xge_set_desc_bits(int pos,int len,u64 val)85384fe7a4SIyappan Subramanian static inline u64 xge_set_desc_bits(int pos, int len, u64 val)
86384fe7a4SIyappan Subramanian {
87384fe7a4SIyappan Subramanian return (val & ((1ULL << len) - 1)) << pos;
88384fe7a4SIyappan Subramanian }
89384fe7a4SIyappan Subramanian
xge_get_desc_bits(int pos,int len,u64 src)90384fe7a4SIyappan Subramanian static inline u64 xge_get_desc_bits(int pos, int len, u64 src)
91384fe7a4SIyappan Subramanian {
92384fe7a4SIyappan Subramanian return (src >> pos) & ((1ULL << len) - 1);
93384fe7a4SIyappan Subramanian }
94384fe7a4SIyappan Subramanian
95384fe7a4SIyappan Subramanian #define SET_BITS(field, val) \
96384fe7a4SIyappan Subramanian xge_set_desc_bits(field ## _POS, field ## _LEN, val)
97384fe7a4SIyappan Subramanian
98384fe7a4SIyappan Subramanian #define GET_BITS(field, src) \
99384fe7a4SIyappan Subramanian xge_get_desc_bits(field ## _POS, field ## _LEN, src)
100384fe7a4SIyappan Subramanian
101384fe7a4SIyappan Subramanian void xge_setup_desc(struct xge_desc_ring *ring);
102384fe7a4SIyappan Subramanian void xge_update_tx_desc_addr(struct xge_pdata *pdata);
103384fe7a4SIyappan Subramanian void xge_update_rx_desc_addr(struct xge_pdata *pdata);
104384fe7a4SIyappan Subramanian void xge_intr_enable(struct xge_pdata *pdata);
105384fe7a4SIyappan Subramanian void xge_intr_disable(struct xge_pdata *pdata);
106384fe7a4SIyappan Subramanian
107384fe7a4SIyappan Subramanian #endif /* __XGENE_ENET_V2_RING_H__ */
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